CN115037129A - Control circuit based on parallel current sharing of SiC MOSFET - Google Patents
Control circuit based on parallel current sharing of SiC MOSFET Download PDFInfo
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- CN115037129A CN115037129A CN202210692643.1A CN202210692643A CN115037129A CN 115037129 A CN115037129 A CN 115037129A CN 202210692643 A CN202210692643 A CN 202210692643A CN 115037129 A CN115037129 A CN 115037129A
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- 239000003990 capacitor Substances 0.000 claims description 82
- 239000004065 semiconductor Substances 0.000 claims description 74
- 230000005669 field effect Effects 0.000 claims description 72
- 229910044991 metal oxide Inorganic materials 0.000 claims description 72
- 150000004706 metal oxides Chemical class 0.000 claims description 69
- 238000002955 isolation Methods 0.000 claims description 48
- 239000003381 stabilizer Substances 0.000 claims description 11
- 102100039435 C-X-C motif chemokine 17 Human genes 0.000 claims description 4
- 101000889048 Homo sapiens C-X-C motif chemokine 17 Proteins 0.000 claims description 4
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 claims description 4
- 230000007935 neutral effect Effects 0.000 claims description 4
- 238000013461 design Methods 0.000 abstract description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 33
- 229910010271 silicon carbide Inorganic materials 0.000 description 33
- 238000002474 experimental method Methods 0.000 description 12
- 238000012360 testing method Methods 0.000 description 8
- 230000010355 oscillation Effects 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005284 excitation Effects 0.000 description 4
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a control circuit based on parallel current sharing of SiC MOSFETs, which comprises: the power circuit comprises a direct current bus side circuit and a SiC MOSFET parallel device circuit; the driving circuit is divided into a branch circuit A driving circuit and a branch circuit B driving circuit which are completely the same in two parts; the driving circuit consists of a signal input side, an isolated gate driver and an output side; the driving power supply circuit consists of a power Vd generating circuit and a driving power supply main circuit. The invention can make the switching speed of the parallel device faster, reduce the imbalance degree of the drain current and expand the current capacity to meet the design requirement.
Description
Technical Field
The invention relates to the technical field of performance test of power semiconductor devices, in particular to a control circuit based on parallel current sharing of SiC MOSFETs.
Background
The SiC MOSFET device, which is one of novel wide bandgap semiconductor representative devices, has the advantages of low conduction loss, high switching speed, strong high-temperature tolerance and the like, can reduce converter loss and improve power density when applied to a power electronic converter, and has great application advantages in occasions of high temperature, high voltage and the like. In order to meet the application requirements of the SiC MOSFET in medium and high power occasions, the SiC MOSFET needs to be connected in parallel to improve the current capability. However, the silicon carbide MOSFET chip electrical parameter dispersion and the asymmetric distribution of module package parasitic parameters cause the chips in parallel connection inside the silicon carbide power module to bear larger voltage overshoot and unbalanced current during the high-speed switching process. The gate source of the insulated gate device (IGBT, MOSFET) is a capacitive structure, and the parasitic inductance of the gate loop is inevitable, so that the gate loop can generate strong oscillation under the excitation of the drive pulse of the driver.
Disclosure of Invention
The invention aims to solve the defects of the prior art and provides a control circuit based on parallel current sharing of SiC MOSFETs, so that the current imbalance phenomenon between parallel devices can be reduced, strong oscillation of a grid circuit under the excitation of a driver driving pulse can be improved, and the current capacity can be enlarged to meet the design requirement.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention relates to a control circuit based on parallel current sharing of SiC MOSFETs, which is characterized by comprising the following steps: the device comprises a power circuit, 2 driving circuits and 2 driving power supply circuits;
the power circuit consists of a direct current bus side circuit and a SiC MOSFET parallel device circuit;
the direct current bus side circuit includes: the device comprises a direct-current power supply interface, a supporting capacitor and a decoupling capacitor;
the support capacitor and the decoupling capacitor are connected in parallel between the positive pole DC + and the negative pole DC-of the direct-current power supply interface; the support capacitor is formed by connecting N1 capacitors in parallel, and the decoupling capacitor is formed by connecting N2 capacitors in parallel;
the SiC MOSFET parallel device circuit is a half-bridge circuit formed by connecting two mutually symmetrical branches A and B in series and is connected with the direct current bus side circuit in parallel;
the branch circuit A and the branch circuit B are formed by connecting 4 metal-oxide semiconductor field effect transistors in parallel;
the drains of the metal-oxide semiconductor field effect transistor MOSFET1, the metal-oxide semiconductor field effect transistor MOSFET2, the metal-oxide semiconductor field effect transistor MOSFET3 and the metal-oxide semiconductor field effect transistor MOSFET4 in the branch A are connected in parallel and then connected with the positive electrode DC +;
the sources of the metal-oxide semiconductor field effect transistor MOSFET5, the metal-oxide semiconductor field effect transistor MOSFET6, the metal-oxide semiconductor field effect transistor MOSFET7 and the metal-oxide semiconductor field effect transistor MOSFET8 in the branch B are connected in parallel and then are connected with the negative pole DC-;
a node a formed by connecting the sources of the metal-oxide semiconductor field effect transistor MOSFET1, the metal-oxide semiconductor field effect transistor MOSFET2, the metal-oxide semiconductor field effect transistor MOSFET3 and the metal-oxide semiconductor field effect transistor MOSFET4 in the branch A in parallel is connected with a node B formed by connecting the drains of the metal-oxide semiconductor field effect transistor MOSFET5, the metal-oxide semiconductor field effect transistor MOSFET6, the metal-oxide semiconductor field effect transistor MOSFET7 and the metal-oxide semiconductor field effect transistor MOSFET8 in parallel in the branch B, and a neutral point Mid is led out from between the node a and the node B;
the gate and the source of the metal-oxide semiconductor field effect transistors MOSFET 1-MOFET 8 are respectively connected with the cathode of the driving circuit;
the gates of the metal-oxide semiconductor field effect transistors MOSFET 1-MOFET 4 of the branch A are respectively connected with resistors R1-R4;
the gates of the metal-oxide semiconductor field effect transistors MOSFET 5-MOFET 8 of the branch B are respectively connected with resistors R5-R8;
the source of the metal-oxide semiconductor field effect transistor MOSFET 5-metal-oxide semiconductor field effect transistor MOFET8 is led out of a compensation branch, the source compensation branch is connected with resistors R9-R12, the upper end parts of the resistors R9-R12 are connected with the source compensation branch, and the lower end parts of the resistors R9-R12 are connected with the negative electrode of the driving circuit;
the 2 driving circuits respectively provide driving signals for a branch circuit A and a branch circuit B in the power circuit, and are used for correspondingly driving the on and off of 8 metal-oxide semiconductor field effect transistors in the power circuit;
the driving circuit of any branch circuit is composed of three parts, which are respectively: the signal input side, the isolated gate driver and the output side are powered by the driving power supply circuit;
the signal input side is used for receiving an externally input PWM signal;
the isolated gate driver is composed of an isolated gate driving chip U1 d;
a VCC1 pin of the isolation type gate driving chip U1d is connected with an external power supply Vd, and a capacitor C5 is connected in parallel between the external power supply Vd and a ground end GND of the control circuit;
a VCC2 pin of the isolation type gate driving chip U1d is connected with an external power supply VCC _ TOP, and capacitors C6 and C7 are connected in parallel between the external power supply VCC _ TOP and an upper isolation grounding end GND _ TOP of the control circuit;
a GND2 pin of the isolation type gate driving chip U1d is connected with an external power supply VCC _ BOM, and capacitors C8 and C9 are connected in parallel between the external power supply VCC _ BOM and a lower isolation grounding end GND _ BOM of the control circuit;
the output side is connected with N3 driving resistors in parallel; the N3 driving resistors are evenly divided into two parts of resistors and then are respectively connected with an OUT + pin and an OUT-pin of the isolation type gate driving chip U1 d;
the driving power supply circuit consists of a power Vd generating circuit and a driving power supply main circuit;
the power supply Vd generation circuit is formed by connecting a voltage stabilizer chip L1, an input side capacitor C10 and an output side capacitor C11 in parallel;
the input side capacitor C11 is connected with an external direct-current power supply Vin and then connected with an IN pin of the voltage stabilizer chip L1;
the output side capacitor C12 is connected with an external power supply Vd and then connected with an OUT pin of the voltage stabilizer chip L1; the IN pin and the OUT pin are connected IN parallel and then are connected with a GND3 pin of the voltage stabilizer chip L1, and are connected to the ground end GND;
the main driving power supply circuit consists of a main circuit input side, an isolation gate driving power supply U2d and a main circuit output side; the output side of the main circuit is used for supplying power to the driving circuit;
an IN1 pin of the isolation gate driving power supply U2d is connected with an external direct-current power supply Vin; the IN2 pin of the isolation gate driving power supply U2d is connected to the ground terminal GND; a capacitor C12 at the input side of the main circuit is connected between the external direct-current power supply Vin and a ground end GND;
the + VOUT pin of the isolation gate driving power supply U2d is connected with an external power supply VCC _ TOP;
a GND4 pin of the isolation gate driving power supply U2d is connected with a lower isolation ground terminal GND _ BOM;
a-VOUT pin of the isolation gate driving power supply U2d is connected with an external power supply VCC-BOM;
a capacitor C13, a capacitor C14 and a capacitor C15 on the output side of the main circuit are connected in parallel between a + VOUT pin and a GND4 pin of the isolation gate driving power supply U2 d;
a capacitor C16, a capacitor C17 and a capacitor C18 on the output side of the main circuit are connected in parallel between a-VOUT pin and a GND4 pin of the isolation gate driving power supply U2 d.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention solves the problem of non-uniform current flow in dynamic and static states caused by the difference of internal parameters such as threshold voltage, on-resistance, interelectrode capacitance, transconductance and the like of the SiC MOSFET through a completely symmetrical circuit design, and reduces the influence of current distribution caused by stray inductance of a circuit layout, different circuit positions and small length change of leads, main grid decoupling resistance of external circuit parameters, grid lead inductance, source lead inductance, drain lead inductance and the like, thereby reducing the phenomenon of unbalance of current among parallel devices and having great significance for improving current uniform distribution.
2. In the power circuit, the resistors are connected in front of the MOSFET gates of the metal-oxide semiconductor field effect transistors to eliminate gate oscillation, so that the problem of strong oscillation generated by a gate loop under the excitation of a driver driving pulse is solved, the oscillation is quickly attenuated, and the power circuit is easier to replace when an influence experiment of different gate resistors is carried out.
3. In the power circuit, a line is additionally led out from the source electrode of each SiC MOSFET to form a grid circuit, and the auxiliary source electrode lead wire design can make the switching speed faster and the imbalance degree of the drain current smaller.
4. In the design, the SiC MOSFET parallel double-pulse experiment and the SiC MOSFET parallel short-circuit experiment are considered, the multipurpose effect is achieved, the current equalizing effect can be seen after the SiC MOSFET parallel double-pulse experiment is carried out, and the experimental foundation is laid for the SiC MOSFET short-circuit experiment.
Drawings
FIG. 1 is a power circuit diagram of an embodiment of the present invention;
fig. 2 is a driving circuit diagram in an embodiment of the present invention;
FIG. 3 is a diagram of a driving power supply circuit in an embodiment of the present invention;
FIG. 4 is a system circuit connection diagram in an embodiment of the invention;
the reference numbers in the figures: 1, a direct-current power supply interface; 2, supporting a capacitor; 3 decoupling capacitor; 4 drive the resistance.
Detailed Description
The technical scheme of the invention is clearly and completely described below with reference to the accompanying drawings.
In this embodiment, a control circuit based on parallel current sharing of SiC MOSFETs is used to solve the problems that, due to the fact that characteristic parameters among SiC MOSFET devices are dispersive, parasitic parameters of a power circuit and a driving circuit are not consistent, junction temperatures are different, and when a plurality of SiC MOSFETs are connected in parallel, current imbalance inevitably occurs, including dynamic current imbalance at the moment of switching on and static current imbalance during the switching on. Specifically, as shown in fig. 4, the control circuit includes: the device comprises a power circuit, 2 driving circuits and 2 driving power supply circuits;
as shown in fig. 1, the power circuit is composed of a direct current bus side circuit and a SiC MOSFET parallel device circuit;
the direct current bus side circuit includes: the device comprises a direct-current power supply interface 1, a supporting capacitor 2 and a decoupling capacitor 3;
a support capacitor 2 and a decoupling capacitor 3 are connected in parallel between the positive pole DC + and the negative pole DC-of the direct-current power supply interface 1; the support capacitor 2 and the decoupling capacitor 3 are respectively formed by connecting N1 capacitors and N2 capacitors in parallel;
the measuring device circuit is a half-bridge circuit formed by connecting two mutually symmetrical branches A and B in series and is connected with a direct current bus side circuit in parallel;
as shown in fig. 1, N1 supporting capacitors are connected in parallel, and different supporting capacitor capacitance values, withstand voltage grades and numbers are selected according to actual experiment requirements; the N2 decoupling capacitors are mutually connected in parallel, the model of the decoupling capacitors is selected as the model of low parasitic inductance, and when the parallel SiC MOSFET double-pulse test is carried out, the patch type ceramic capacitor can be selected to play a role in voltage stabilization; when a short circuit test of the parallel SiC MOSFET is carried out, the decoupling capacitor can be removed, so that the purpose of testing and using a plurality of plates is achieved, and the requirements of different experiments are met.
The branch A and the branch B are formed by connecting 4 metal-oxide semiconductor field effect transistors in parallel;
the drains of the metal-oxide semiconductor field effect transistor MOSFET1, the metal-oxide semiconductor field effect transistor MOSFET2, the metal-oxide semiconductor field effect transistor MOSFET3 and the metal-oxide semiconductor field effect transistor MOSFET4 in the branch A are connected in parallel and then connected with the positive electrode DC +;
the sources of the metal-oxide semiconductor field effect transistor MOSFET5, the metal-oxide semiconductor field effect transistor MOSFET6, the metal-oxide semiconductor field effect transistor MOSFET7 and the metal-oxide semiconductor field effect transistor MOSFET8 in the branch B are connected in parallel and then are connected with the negative pole DC-;
a node a formed by connecting the sources of the metal-oxide semiconductor field effect transistor MOSFET1, the metal-oxide semiconductor field effect transistor MOSFET2, the metal-oxide semiconductor field effect transistor MOSFET3 and the metal-oxide semiconductor field effect transistor MOSFET4 in the branch A in parallel is connected with a node B formed by connecting the drains of the metal-oxide semiconductor field effect transistor MOSFET5, the metal-oxide semiconductor field effect transistor MOSFET6, the metal-oxide semiconductor field effect transistor MOSFET7 and the metal-oxide semiconductor field effect transistor MOSFET8 in parallel in the branch B, and a neutral point Mid is led out from the position between the node a and the node B;
when designing the layout of the circuit board of the circuit PCB, the layout of the branches A and B must be strictly ensured to be strictly symmetrical, so that the parasitic parameters in each branch are consistent. The neutral point interface Mid is led out and can be used for connecting a large inductor when a parallel SiC MOSFET double-pulse test experiment is carried out; when the short circuit test experiment is carried out, the short circuit test experiment of the parallel SiC MOSFET can be carried out only by carrying out short circuit on the drain and the source of the metal-oxide semiconductor field effect transistors (MOSFET 1-4) in the branch circuit A. Different experiments were performed by adapting the decoupling capacitors.
The gates and the sources of the metal-oxide semiconductor field effect transistors MOSFET 1-MOFET 8 are respectively connected with the cathode of the drive circuit;
the gates of the metal-oxide semiconductor field effect transistor MOSFET 1-the metal-oxide semiconductor field effect transistor MOFET4 of the branch A are respectively connected with resistors R1-R4;
the gates of the metal-oxide semiconductor field effect transistor MOSFET 5-the metal-oxide semiconductor field effect transistor MOFET8 of the branch B are respectively connected with resistors R5-R8;
the gate resistors R1-R8 can play a role in eliminating gate oscillation in the circuit, a capacitive structure is arranged between the insulated gate device IGBT and the gate source electrode of the MOSFET, and parasitic inductance of a gate loop is inevitable, so that if the gate resistors are not arranged, the gate loop can generate strong oscillation under the excitation of a drive pulse of a driver, and the series gate resistors can be quickly attenuated; the gate resistors R1-R8 can also play a role in transferring power loss of the driver in the circuit, the capacitor inductors are passive elements, and if the gate resistors are not arranged, most of driving power is consumed on an output tube in the driver, so that the temperature of the output tube is greatly increased, and the gate resistors R1-R8 are necessary.
The source of the metal-oxide semiconductor field effect transistor MOSFET 5-metal-oxide semiconductor field effect transistor MOFET8 is led out of a compensation branch, resistors R9-R12 are connected to the source compensation branch, the upper end parts of the resistors R9-R12 are connected with the source compensation branch, and the lower end parts of the resistors R9-R12 are connected with the negative electrode of the driving circuit;
and a compensation branch is additionally led out from the source electrode of each SiC MOSFET to form a grid loop. The current imbalance of the design with the auxiliary source lead can be reduced, and the reduction amplitude of the current imbalance is larger as the number of the parallel SiC MOSFETs is increased. The design method of the auxiliary source lead can be used for a parallel SiC MOSFET double-pulse test and a parallel SiC MOSFET short circuit test experiment.
Fig. 2 is a diagram of driving circuits in an embodiment of the present invention, in which 2 driving circuits respectively provide driving signals for a branch a and a branch B in a power circuit to correspondingly drive 8 mosfets in the power circuit to be turned on and off, wherein the branch a and the branch B of the power circuit are respectively driven by two identical driving circuits to drive the mosfets in the branch a or the branch B of the power circuit; in specific implementation, when 8 SiC MOSFETs are arranged, the parasitic parameters of the SiC MOSFETs are ensured to be the same according to strict vertical uniform trend.
Any branch driving circuit is composed of three parts, which are respectively: a signal input side, an isolated gate driver and an output side;
the signal input side is used for receiving an externally input PWM signal;
the isolated gate driver is composed of an isolated gate driving chip U1d, and the model of the driving chip is 1ED3123MC12 HUMA 1. Pins on the left side of the isolation type gate driving chip U1d from top to bottom are VCC1, IN +, IN-, and GND1 IN sequence; pins on the right side of the isolation type gate driving chip U1d from top to bottom are VCC2, OUT +, OUT-, and GND2 in sequence;
a VCC1 pin of the isolation type gate driving chip U1d is connected with an external power supply Vd, and a capacitor C5 is connected in parallel between the external power supply Vd and a ground end GND of the control circuit;
a VCC2 pin of the isolation type gate driving chip U1d is connected with an external power supply VCC _ TOP, and capacitors C6 and C7 are connected in parallel between the external power supply VCC _ TOP and an upper isolation grounding end GND _ TOP of the control circuit;
a GND2 pin of the isolation type gate driving chip U1d is connected with an external power supply VCC _ BOM, and capacitors C8 and C9 are connected in parallel between the external power supply VCC _ BOM and a lower isolation grounding end GND _ BOM of the control circuit;
in the isolation type gate driving chip U1d, according to the voltage generated by the driving power supply circuit, an external power supply Vd is connected with +5V, an external power supply VCC _ TOP is connected with +15V, and an external power supply VCC _ BOM is connected with-3V.
The output side is connected with N3 driving resistors 4 in parallel; the N3 driving resistors 4 are equally divided into two parts of resistors and then are respectively connected with an OUT + pin and an OUT-pin of the U1d of the isolated gate driving chip; in this embodiment, two driving resistors 4 are adopted, the driving circuit provides driving signals for 8 MOSFETs in the power circuit, the output end of the driving resistor 4 is connected to G _ HS of the power circuit branches a and B, GND _ BOM is connected to S _ HS of the power circuit branches a and B, and meanwhile, the switching speed of the SiC MOSFET can be changed by changing the size of the driving resistor.
FIG. 3 is a diagram of a driving power supply circuit in an embodiment of the present invention, the driving power supply circuit is composed of a power Vd generation circuit and a driving power supply main circuit;
the power supply Vd generation circuit is formed by connecting a voltage stabilizer chip L1, an input side capacitor C10 and an output side capacitor C11 in parallel;
the left pin and the right pin of the voltage stabilizer chip L1 are IN and OUT respectively, and the bottom pin is GND 3;
an input side capacitor C11 is connected with an external direct-current power supply Vin and then connected with an IN pin of a voltage stabilizer chip L1;
the output side capacitor C12 is connected with an external power supply Vd and then connected with an OUT pin of a voltage stabilizer chip L1; the IN pin and the OUT pin are connected IN parallel and then are connected with a GND3 pin of a voltage regulator chip L1 and are connected to a ground end GND;
the main driving power supply circuit consists of a main circuit input side, an isolation gate driving power supply U2d and a main circuit output side; the output side of the main circuit is used for supplying power to the driving circuit;
pins from top to bottom on the left side of the isolation gate driving power supply U2d are IN1 and IN2 respectively; the pins from top to bottom on the right side are OUT +, GND4 and OUT-; the model number selected by the isolating door driving power supply U2D is MGJ2D121505 SC;
the input side of the main circuit consists of an external direct-current power supply Vin and a capacitor C12;
an IN1 pin of the isolation gate driving power supply U2d is connected with an external direct current power supply Vin; the IN2 pin of the isolation gate driving power supply U2d is connected to the ground GND; a capacitor C12 at the input side of the main circuit is connected between an external direct current power Vin and a ground end GND;
the output side of the main circuit is composed of a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17 and a capacitor C18; the + VOUT pin of the isolation gate driving power supply U2d is connected with an external power supply VCC _ TOP;
a GND4 pin of the isolation gate driving power supply U2d is connected with a lower isolation ground terminal GND _ BOM;
a-VOUT pin of the isolation gate driving power supply U2d is connected with an external power supply VCC _ BOM;
a capacitor C13, a capacitor C14 and a capacitor C15 on the output side of the main circuit are connected in parallel between a + VOUT pin and a GND4 pin of the isolation gate driving power supply U2 d;
a capacitor C16, a capacitor C17 and a capacitor C18 on the output side of the main circuit are connected in parallel between a-VOUT pin and a GND4 pin of the isolation gate driving power supply U2 d. According to the isolation gate driving power supply U2d, the external power supply VCC _ TOP is +15V, and the external power supply VCC _ BOM is-3V;
through the embodiment, the circuit can play a certain role in equalizing the current of the parallel SiC MOSFETs.
Claims (1)
1. A control circuit based on parallel current sharing of SiC MOSFETs is characterized by comprising: the device comprises a power circuit, 2 driving circuits and 2 driving power supply circuits;
the power circuit consists of a direct current bus side circuit and a SiC MOSFET parallel device circuit;
the direct current bus side circuit includes: the device comprises a direct-current power interface (1), a supporting capacitor (2) and a decoupling capacitor (3);
the support capacitor (2) and the decoupling capacitor (3) are connected in parallel between the positive pole DC + and the negative pole DC-of the direct-current power supply interface (1); the support capacitor (2) is formed by connecting N1 capacitors in parallel, and the decoupling capacitor (3) is formed by connecting N2 capacitors in parallel;
the SiC MOSFET parallel device circuit is a half-bridge circuit formed by connecting two mutually symmetrical branches A and B in series and is connected with the direct-current bus side circuit in parallel;
the branch circuit A and the branch circuit B are formed by connecting 4 metal-oxide semiconductor field effect transistors in parallel;
the drains of the metal-oxide semiconductor field effect transistor MOSFET1, the metal-oxide semiconductor field effect transistor MOSFET2, the metal-oxide semiconductor field effect transistor MOSFET3 and the metal-oxide semiconductor field effect transistor MOSFET4 in the branch A are connected in parallel and then connected with the positive electrode DC +;
the sources of the metal-oxide semiconductor field effect transistor MOSFET5, the metal-oxide semiconductor field effect transistor MOSFET6, the metal-oxide semiconductor field effect transistor MOSFET7 and the metal-oxide semiconductor field effect transistor MOSFET8 in the branch B are connected in parallel and then are connected with the negative pole DC-;
a node a formed by connecting the sources of the metal-oxide semiconductor field effect transistor MOSFET1, the metal-oxide semiconductor field effect transistor MOSFET2, the metal-oxide semiconductor field effect transistor MOSFET3 and the metal-oxide semiconductor field effect transistor MOSFET4 in the branch A in parallel is connected with a node B formed by connecting the drains of the metal-oxide semiconductor field effect transistor MOSFET5, the metal-oxide semiconductor field effect transistor MOSFET6, the metal-oxide semiconductor field effect transistor MOSFET7 and the metal-oxide semiconductor field effect transistor MOSFET8 in parallel in the branch B, and a neutral point Mid is led out from between the node a and the node B;
the gate and the source of the metal-oxide semiconductor field effect transistors MOSFET 1-MOFET 8 are respectively connected with the cathode of the driving circuit;
the gates of the metal-oxide semiconductor field effect transistors MOSFET 1-MOFET 4 of the branch A are respectively connected with resistors R1-R4;
the gates of the metal-oxide semiconductor field effect transistors MOSFET 5-MOFET 8 of the branch B are respectively connected with resistors R5-R8;
the source of the metal-oxide semiconductor field effect transistor MOSFET 5-metal-oxide semiconductor field effect transistor MOFET8 is led out of a compensation branch, the source compensation branch is connected with resistors R9-R12, the upper end parts of the resistors R9-R12 are connected with the source compensation branch, and the lower end parts of the resistors R9-R12 are connected with the negative electrode of the driving circuit;
the 2 driving circuits respectively provide driving signals for a branch circuit A and a branch circuit B in the power circuit, and are used for correspondingly driving the on and off of 8 metal-oxide semiconductor field effect transistors in the power circuit;
the driving circuit of any branch circuit is composed of three parts, which are respectively: the signal input side, the isolated gate driver and the output side are powered by the driving power supply circuit;
the signal input side is used for receiving an externally input PWM signal;
the isolated gate driver is composed of an isolated gate driving chip U1 d;
a VCC1 pin of the isolation type gate driving chip U1d is connected with an external power supply Vd, and a capacitor C5 is connected in parallel between the external power supply Vd and a ground terminal GND of the control circuit;
a VCC2 pin of the isolation type gate driving chip U1d is connected with an external power supply VCC _ TOP, and capacitors C6 and C7 are connected in parallel between the external power supply VCC _ TOP and an upper isolation grounding end GND _ TOP of the control circuit;
a GND2 pin of the isolation type gate driving chip U1d is connected with an external power supply VCC _ BOM, and capacitors C8 and C9 are connected in parallel between the external power supply VCC _ BOM and a lower isolation grounding end GND _ BOM of the control circuit;
the output side is connected with N3 driving resistors (4) in parallel; the N3 driving resistors (4) are equally divided into two parts of resistors and then are respectively connected with the OUT + pin and the OUT-pin of the U1d of the isolated gate driving chip;
the driving power supply circuit consists of a power Vd generating circuit and a driving power supply main circuit;
the power supply Vd generation circuit is formed by connecting a voltage stabilizer chip L1, an input side capacitor C10 and an output side capacitor C11 in parallel;
the input side capacitor C11 is connected with an external direct-current power supply Vin and then connected with an IN pin of the voltage stabilizer chip L1;
the output side capacitor C12 is connected with an external power supply Vd and then connected with an OUT pin of the voltage stabilizer chip L1; the IN pin and the OUT pin are connected IN parallel and then are connected with a GND3 pin of the L1 of the voltage regulator chip and are connected to the ground end GND;
the main drive power supply circuit consists of a main circuit input side, an isolation door drive power supply U2d and a main circuit output side; the output side of the main circuit is used for supplying power to the driving circuit;
an IN1 pin of the isolation gate driving power supply U2d is connected with an external direct-current power supply Vin; the IN2 pin of the isolation gate driving power supply U2d is connected to the ground terminal GND; a capacitor C12 at the input side of the main circuit is connected between the external direct-current power supply Vin and a ground end GND;
the + VOUT pin of the isolation gate driving power supply U2d is connected with an external power supply VCC _ TOP;
a GND4 pin of the isolation gate driving power supply U2d is connected with a lower isolation ground terminal GND _ BOM;
a-VOUT pin of the isolation gate driving power supply U2d is connected with an external power supply VCC-BOM;
a capacitor C13, a capacitor C14 and a capacitor C15 on the output side of the main circuit are connected in parallel between a + VOUT pin and a GND4 pin of the isolation gate driving power supply U2 d;
a capacitor C16, a capacitor C17 and a capacitor C18 on the output side of the main circuit are connected in parallel between a-VOUT pin of the isolation gate driving power supply U2d and a GND4 pin.
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Inventor after: Li Helong Inventor after: Han Liangliang Inventor after: Zhang Man Inventor after: Yu Langlang Inventor after: Wang Ao Inventor after: Zhao Shuang Inventor after: Yang Zhiqing Inventor after: Ding Lijian Inventor before: Li Helong Inventor before: Han Liangliang Inventor before: Zhang Man Inventor before: Yu Langlang Inventor before: Wang Ao Inventor before: Zhao Shuang Inventor before: Yang Zhiqing Inventor before: Ding Lijian |