JP2016134882A - Device and method for load drive control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a load drive control device and a load drive control method, enabling improved reliability at the drive of a power semiconductor device while restraining the deterioration of the device at the drive.SOLUTION: An IGBT device 2ud includes a plurality of cells 8, 9 mutually electrically connected to a gate input terminal 10. Each time constant of the gate capacitance of a charge and discharge path of the plurality of cells 8, 9 is different between the two cells 8, 9. A drive control unit 15 performs control to drive a load according to the drive of the IGBT device 2ud. An acquisition unit 16 acquires a value corresponding to a load current which flows through the IGBT device 2ud. A drive control unit 15 drives the IGBT device 2ud by reducing a switching-off speed as a load conduction current, which is detected corresponding to the acquisition value of the acquisition unit 16, becomes higher.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a load drive control device and a load drive control method.

  As this type of load drive control device, there is an IGBT (Insulated Gate Bipolar Transistor), and a device that drives a load by connecting a power semiconductor element typified by a power MOS transistor. Such a power semiconductor element is configured by connecting a plurality of cells in parallel when the semiconductor structure is observed microscopically (see, for example, Patent Document 1). The configuration described in Patent Document 1 includes a first gate voltage driven semiconductor element, a first gate pattern connected to the gate of the first gate voltage driven semiconductor element, a second gate voltage driven semiconductor element, and a second gate voltage driven semiconductor element. It consists of a second gate pattern connected to the gate of the gate voltage driven semiconductor element, and causes a difference in the gate impedance between the cells. Thereby, the behavior of each cell at the time of turn-off is made uneven, the surge voltage at the time of turn-off of the power semiconductor element can be reduced, and the trade-off between Eoff loss and surge voltage can be improved.

JP 2004-319624 A

  When the configuration described in Patent Document 1 is adopted, it is found that when the power semiconductor element is turned off, current tends to concentrate on a specific structure of a plurality of cells (or / and a plurality of devices), and element deterioration is likely to be induced. ing.

  An object of the present invention is to provide a load drive control device and a load drive control method capable of improving reliability during driving of a power semiconductor element while suppressing element deterioration during driving.

  According to the invention described in claim 1 or 3, the power semiconductor element has a plurality of structures including a plurality of cells or / and a plurality of devices electrically connected to the gate input terminal. The time constant of the charge / discharge path of the gate capacitance of the structure is different between at least two structures. The drive control unit drives and controls the load in response to driving the power semiconductor element. The acquisition unit acquires a value corresponding to the load current flowing through the power semiconductor element, and the drive control unit decreases the switching-off speed as the load energization current detected corresponding to the acquired value of the acquisition unit increases. Then, the power semiconductor element is driven. Thereby, it becomes difficult for current to concentrate on a specific structure among the plurality of structures, and it is possible to improve reliability during driving of the power semiconductor element while suppressing element deterioration during driving.

1 is an electrical configuration diagram schematically illustrating a drive control device according to a first embodiment. Electrical configuration diagram schematically showing an overall configuration example of a vehicle inverter device (A) Electrical configuration diagram schematically showing an example of an internal configuration of a power semiconductor element, (b) Timing chart schematically showing a current flowing through each node when switching off. The figure which shows roughly the load current change characteristic according to the difference in the current between each structure Correlation diagram between load current and current flowing through each structure in comparative example Timing chart schematically showing signal changes at each node Correlation diagram between improved load current and current flowing through each structure The electrical block diagram which shows roughly the principal part of the drive control apparatus in 2nd Embodiment. Correlation diagram between improved load current and current flowing through each structure Electrical configuration diagram schematically showing the structure of a plurality of cells in the third embodiment Electrical configuration diagram schematically showing the structure of a plurality of cells in the fourth embodiment Electrical configuration diagram schematically showing the structure of a plurality of devices in the fifth embodiment Electrical block diagram which shows schematically the principal part of the drive control apparatus in 6th Embodiment Correlation diagram between improved load current and current flowing through each structure

  Hereinafter, some embodiments of a load drive control device and a load drive control method will be described with reference to the drawings. In the following description, components having the same or similar functions as those described in each embodiment are denoted by the same reference numerals or similar symbols, and description thereof will be omitted as necessary in the second and subsequent embodiments.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a diagram schematically showing an electrical configuration block of the vehicle inverter device according to the present embodiment. In the present embodiment, a description will be given of a mode in which the load of a vehicle motor as an inductive load is used as a load, and the drive control unit drives and controls the load by turning on and off the power semiconductor element.

  The vehicle inverter device 1 shown in FIG. 2 includes an inverter unit 3 in which IGBT devices 2uu, 2ud, 2vu, 2vd, 2wu, and 2wd as power semiconductor elements are connected in, for example, a three-phase bridge, and each IGBT device 2uu of the inverter unit 3 2d, 2vu, 2vd, 2wu, and 2wd, load drive control devices 4u, 4ud, 4vu, 4vd, 4wu, and 4wd for controlling the gate signals at the gate input terminals of the vehicle motor (load equivalent) 5 are driven. The IGBT devices 2uu, 2ud, 2vu, 2vd, 2wu, and 2wd are constituted by multi-emitter type devices.

  The electronic control unit (ECU) 6 calculates a required torque for the motor from an accelerator opening detected by an unillustrated accelerator sensor provided in the vehicle, and each IGBT device 2uu of the inverter unit 3 so as to obtain the required torque. 2ud, 2vu, 2vd, 2wu, 2wd ON / OFF periods are set.

  When the electronic control device 6 outputs a command signal to the load drive control devices 4uu, 4ud, 4vu, 4vd, 4wu, 4wd, the load drive control devices 4uu, 4ud, 4vu, 4vd, 4wu, 4wd are inverters according to the command signal. The unit 3 is driven and controlled. The inverter unit 3 converts the DC power supplied from the motor drive power supply VB into three-phase AC power based on the drive control by the load drive control devices 4uu, 4ud, 4vu, 4vd, 4wu, 4wd, and is converted. The motor 5 is driven and controlled by three-phase AC power. A smoothing capacitor 7 is connected in parallel to the power supply VB. When the IGBT device 2ud is shown in detail, the IGBT device 2ud is constituted by a multiple cell structure (corresponding to multiple structures) as shown in FIGS. Here, one IGBT device 2ud on the lower arm side will be described as an example, but the other IGBT devices 2uu, 2vu, 2vd, 2wu, and 2wd are the same, and therefore other IGBT devices 2uu, 2vu, 2vd, Detailed description of the control for 2wu and 2wd will be omitted.

  In the present embodiment, as shown in FIG. 3A, the IGBT device 2 ud includes a first cell (structure) 8 and a second cell (structure) 9. The first cell 8 includes a first IGBT cell 8a having a gate, a collector, and an emitter, and a first diode cell 8b, and the second cell 9 has a gate, a collector, first and second emitters (E1 and E2). The second IGBT cell 9a and the second diode cell 9b are provided. The first IGBT cell 8a and the second IGBT cell 9a have the same gate width and gate length (including variations), and the input capacitance Ciss (= gate-drain capacitance Cgd + gate-source capacitance Cgs) is set to have the same characteristics. It is a device. Gate input terminals (corresponding to gate input nodes) 10 of the first cell 8 and the second cell 9 are commonly connected to each other. A gate resistor 11 is connected between the gate input terminal 10 and the gate of the first IGBT cell 8a. The gate input terminal 10 and the gate of the second IGBT cell 9a are directly connected. The collector of the first IGBT cell 8a and the collector of the second IGBT cell 9a are connected in common and connected to the collector terminal 12. The emitter of the first IGBT cell 8a and the first emitter E1 of the second IGBT cell 9a are connected in common and are connected to the emitter terminal 13. The first diode cell 8b has an anode connected to the emitter of the first IGBT cell 8a and a cathode connected to the collector of the first IGBT cell 8a. The second diode cell 9b has an anode connected to the first emitter E1 of the second IGBT cell 9a and a cathode connected to the collector of the second IGBT cell 9a.

  The second emitter E2 of the second IGBT cell 9a is output to the outside via the sense terminal 14 of the IGBT device 2ud, and is input to the load drive control device 4ud. Thereby, the IGBT device 2ud includes a plurality of first cells 8 and second cells 9 having different time constants of the charge / discharge path of the gate charge. In other words, in the present embodiment, the IGBT device 2ud includes a plurality of first cells 8 and second cells 9 having different impedance values (resistance values) in the energization path from the gate input terminal 10 to the emitter terminal 13, for example. .

<Explanation of technical idea>
Hereinafter, the technical idea of the characteristic part according to the present embodiment will be described. The above-described IGBT device 2ud intentionally changes the impedance value of the charge / discharge path of each of the first and second IGBT cells 8a and 9a. First, the reason will be described. Here, the behavior of the switching process of the first and second IGBT cells 8a and 9a will be described supplementarily. When the first cell 8 and the second cell 9 have a difference in impedance of the charge / discharge path (corresponding to the time constant of the charge / discharge path of the gate charge), each node when the IGBT cells 8a, 9a are switched off. The signal change characteristic is obtained as shown in FIG.

  For example, when the first cell 8 and the second cell 9 have the same characteristics, the same gate current originally flows through the first cell 8 and the second cell 9. However, when there is a difference between the impedance values of the charge / discharge paths of the first cell 8 and the second cell 9, the gate voltage is substantially constant over time (see T1 in FIG. 3B: so-called During the mirror period), a difference occurs in the mirror voltage of each of the cells 8 and 9 according to the difference in impedance. As a result, if the cells 8 and 9 have the same characteristics, the collector current Ic2 flowing during the mirror period flows more than the current Ic1. Therefore, the following equations (1-1) and (1-2) Is established. If the load current Ir is set, the formula (1-3) is established.

ここでサージ電圧Ｖｓｕについて検討する。サージ電圧Ｖｓｕは、コレクタ電流の合計値Ｉｃの時間変化量ｄＩｃ／ｄｔ、及び、モータ５の配線などのインダクタンス値Ｌを乗じた下記（２）式により決定される。

Here, the surge voltage Vsu is examined. The surge voltage Vsu is determined by the following equation (2) obtained by multiplying the time change amount dIc / dt of the total value Ic of the collector current and the inductance value L of the wiring of the motor 5 or the like.

一般に、コレクタ電流Ｉｃの時間変化量ｄＩｃ／ｄｔは、次の（３）式で決定される。

In general, the time variation dIc / dt of the collector current Ic is determined by the following equation (3).

第１セル８及び第２セル９の合計コレクタ電流Ｉｃの時間変化量ｄＩｃ／ｄｔは、第１セル８の電流値Ｉｃ１の時間変化量ｄＩｃ１／ｄｔと、第２セル９の電流値Ｉｃ２の時間変化量ｄＩｃ２／ｄｔとの和となるため、次の（４）式により決定される。

The time variation dIc / dt of the total collector current Ic of the first cell 8 and the second cell 9 is the time of the time variation dIc1 / dt of the current value Ic1 of the first cell 8 and the current value Ic2 of the second cell 9. Since it is the sum of the change amount dIc2 / dt, it is determined by the following equation (4).

ここで第１セル８及び第２セル９のゲート入力端子１０が共通接続されており、第１セル８及び第２セル９が互いに同一特性であるときにはＩｇ１＝Ｉｇ２と仮定できる。このため、次の（５）式のように展開できる。

Here, when the gate input terminals 10 of the first cell 8 and the second cell 9 are connected in common, and the first cell 8 and the second cell 9 have the same characteristics, it can be assumed that Ig1 = Ig2. For this reason, it can expand | deploy like following (5) Formula.

さて、Ｉｃ１＋Ｉｃ２＝所定値（例えば１０［ｍＡ］）とした条件下において、｜Ｉｃ１−Ｉｃ２｜を横軸とし、ｓｑｒｔ（Ｉｃ１）＋ｓｑｒｔ（Ｉｃ２）（ｓｑｒｔはルートを示す）を縦軸としたグラフを図４に示す。図４の縦軸、横軸共にリニアメモリである。電流Ｉｃ１と電流Ｉｃ２とで差があるほど、ｓｑｒｔ（Ｉｃ１）＋ｓｑｒｔ（Ｉｃ２）が小さくなることがわかる。つまり、コレクタ電流Ｉｃ１とＩｃ２とで差を生じさせるように、ゲート電荷の充放電経路のインピーダンスに差を生じさせると、コレクタ電流の合計値Ｉｃの時間変化量ｄＩｃ／ｄｔを小さくできる。

Now, under the condition of Ic1 + Ic2 = predetermined value (for example, 10 [mA]), a graph with | Ic1−Ic2 | Is shown in FIG. Both the vertical and horizontal axes in FIG. 4 are linear memories. It can be seen that sqrt (Ic1) + sqrt (Ic2) becomes smaller as there is a difference between the current Ic1 and the current Ic2. That is, if a difference is caused in the impedance of the charge / discharge path of the gate charge so as to cause a difference between the collector currents Ic1 and Ic2, the time change amount dIc / dt of the total value Ic of the collector current can be reduced.

  Since the surge voltage Vsu is proportional to the time change amount dIc / dt as shown in the equation (2), the surge voltage Vsu can be reduced by reducing the time change amount dIc / dt. As a result, since the surge voltage Vsu can be reduced without changing the time variation dVce / dt of the collector-emitter voltage Vce, the trade-off effect of both characteristics of the turn-off loss Eoff and the surge voltage Vsu can be improved. Further, the larger the collector current difference | Ic1-Ic2 | between the first cell 8 and the second cell 9, the higher the trade-off improvement effect of both characteristics of the turn-off loss Eoff and the surge voltage Vsu. Therefore, in the present embodiment, a structure is employed in which the impedance of the charge / discharge path of the gate charge is changed for each of the cells 8 and 9.

  FIG. 5 schematically shows the relationship between the current flowing through the cells 8 and 9 and the load current. A characteristic A1 indicates a current flowing through the first cell 8, and a characteristic A2 indicates a current flowing through the second cell 9. Characteristic B is shown as a reference example, and the impedance of the charge / discharge paths of the gate capacitances of the cells 8 and 9 is R = 0Ω (that is, the resistance value of the gate resistor 11 is 0). The characteristic is shown when there is almost no difference in impedance value of the discharge path other than variation. Here, as shown by these characteristics A 1, A 2, and B, the current characteristic A 1 flowing through the first cell 8 is larger than the characteristic B having a configuration in which there is no difference in impedance, and flows through the second cell 9. The current characteristic A2 is smaller than the characteristic B.

  Similar to the configuration in which there is no difference in impedance, when an allowable current value of the first cell 8 is designed, even if the current is concentrated in the first cell 8 in the operation region R1 in which the load current operates lower than the predetermined current Iw. The current allowable value Iwh is not exceeded. However, in the operation region R2 where the load current operates higher than the predetermined current Iw, the current allowable value Iwh is exceeded. In order to increase the allowable current value Iwh, the size of the first cell 8 must be increased, leading to an increase in the size of the power semiconductor element.

  As a result of investigations by the inventors, when low-speed driving is performed to reduce the switching speed of the power semiconductor element, current concentration in the specific first cell 8 is reduced as compared with the case of performing high-speed driving. It has been found. Focusing on this point, it is desirable to change the switching speed so that high-speed driving is performed when the load current is small and low-speed driving is performed when the load current is large. By performing this control, it is possible to improve the trade-off between the turn-off loss Eoff and the surge voltage Vsu resistance characteristics, and it is possible to suppress element deterioration due to current concentration in the specific first cell 8.

  That is, the collector currents Ic1 and Ic2 of the first cell 8 and the second cell 9 are determined by the equations (1-1) and (1-2), respectively. As a result, the value of the gate current is reduced, and the voltage drop due to the gate resistor 11 is reduced. Therefore, the influence of the third term Ig1 · R / 2 depending on the resistance R in the expression (1-1) is reduced, and as a result, the collector current difference | Ic1-Ic2 | between the first cell 8 and the second cell 9 Becomes smaller.

<Example>
Hereinafter, embodiments based on the above-described technical idea will be described. As shown in FIG. 1, the load drive control device 4ud is configured to drive the IGBT device 2ud when a power supply voltage Vcc is applied between the power supply terminal and the ground G, and is controlled by the gate input terminal 10 of the IGBT device 2ud. Input a signal. The load drive control device 4ud functionally includes a drive control unit 15, an acquisition unit 16, and a holding unit 17. The acquisition unit 16 includes, for example, a sense resistor 18, a comparator 19, and a threshold voltage generation unit 20. The sense resistor 18 is connected between the second emitter E2 of the second cell 9 and the ground G. A current corresponding to (for example, proportional to) a current flowing between the collector terminal 12 of the IGBT device 2ud and the first emitter E1 flows through the sense resistor 18 through the sense terminal 14 of the IGBT device 2ud. The comparator 19 compares the sense voltage Vs applied to the sense resistor 18 with the threshold voltage Vt generated by the threshold voltage generator 20, and outputs an H level when the sense voltage Vs becomes higher than the threshold voltage Vt, for example. When the sense voltage Vs becomes equal to or lower than the threshold voltage Vt, the comparison result of the comparator 19 is output to the holding unit 17 by outputting the L level. The holding unit 17 is configured by, for example, a D flip-flop, and holds the acquired value (comparison result of the comparator 19) of the acquiring unit 16 when the level of the command signal from the ECU 6 is switched to the “H” level.

  The drive control unit 15 adjusts and controls the gate signal input to the gate input terminal 10 of the IGBT device 2ud according to the acquired value of the acquiring unit 16 held in the holding unit 17. The drive control unit 15 is configured by combining, for example, an OR gate 21, a NAND gate 22, a NOR gate 23, an AND gate 24, and pre-inverters 25 and 26.

  The pre-inverter 25 includes a P-channel type MOS transistor (hereinafter referred to as PMOS transistor) 27 and an N-channel type MOS transistor (hereinafter referred to as NMOS transistor) 28, and a plurality of resistors 29 between the drains of these PMOS transistor 27 and NMOS transistor 28. , 30 in between.

  The pre-inverter 26 includes a P-channel type MOS transistor (hereinafter referred to as PMOS transistor) 31 and an N-channel type MOS transistor (hereinafter referred to as NMOS transistor) 32, and a plurality of resistors 33 between the drains of these PMOS transistor 31 and NMOS transistor 32. , 34 is sandwiched.

  A resistor 29 is connected between the drain of the PMOS transistor 27 and the gate input terminal 10, and a resistor 33 is connected between the drain of the PMOS transistor 31 and the gate input terminal 10. These resistors 29 and 33 are resistors for adjusting the switching-on speed when the IGBT device 2ud is turned on, and are set to different resistance values (for example, about 1 to several [kΩ]). Here, a case where the resistance value of the resistor 29 is smaller than the resistance value of the resistor 33 will be described as an example.

  A resistor 30 is connected between the drain of the NMOS transistor 28 and the gate input terminal 10, and a resistor 34 is connected between the drain of the NMOS transistor 32 and the gate input terminal 10. These resistors 30 and 34 are resistors for adjusting the switching-off speed when the IGBT device 2ud is turned off, and are set to different resistance values (for example, about 1 to several [kΩ]). Here, a case where the resistance value of the resistor 30 is smaller than the resistance value of the resistor 34 will be described as an example.

  When one of the PMOS transistor 27 and the NMOS transistor 28 is turned on, the other is turned off. When one of the PMOS transistor 31 and the NMOS transistor 32 is turned on, the other is turned off. The NMOS transistors 28 and 32 are also turned off when either one is turned on. The PMOS transistors 27 and 31 are also turned off when either one is turned on. Logic is set by the logic gates 21 to 24 so as to satisfy these conditions. A combination of the logic gates 21 to 24 as shown in FIG. 1 may be used, but it may be configured using other types of logic gate topologies.

  The operation of the above configuration will be described. FIG. 6 schematically shows a temporal change of the signal by a timing chart. Here, the operation when turning on / off the IGBT device 2ud on the lower arm side will be described, but the same is true when turning on / off the other IGBT devices 2uu, 2vu, 2vd, 2wu, 2wd, and the description thereof is omitted. The electronic control device 6 outputs an on command signal “L” or an off command signal “H” as a command signal to the load drive control device 4ud. The drive control unit 15 of the load drive control device 4ud turns on and off the IGBT device 2ud in accordance with the input command signal.

  For example, the normal operation will be described on the assumption that the IGBT device 2ud is in an off state. When the IGBT device 2ud is in the off state, no collector current flows through the IGBT device 2ud. Then, since no current flows through the sense resistor 18, the comparator 19 outputs an L level. Since the off command signal “H” is input to the input terminal of the load drive control device 4ud and the Q output of the holding unit 17 is “L”, the output of the OR gate 21 is “H”, and the NAND gate 22 Is “H”, the output of the NOR gate 23 is “H”, and the output of the AND gate 24 is “L”. Accordingly, since the MOS transistor 28 connected to the ground G side is turned on and the other MOS transistors 27, 31, 32 are turned off, the gate of the IGBT device 2ud is connected to the potential (0) of the ground G through the resistor 30 and the MOS transistor 28. ).

  For example, when the electronic control device 6 turns on the IGBT device 2ud that is in the off state, it outputs the on command signal “L” as the command signal. When the drive control unit 15 inputs the ON command signal “L”, the output of the NOR gate 23 changes from “H” to “L”, and the output of the OR gate 21 changes from “H” to “L”. Therefore, the MOS transistor 28 is turned off and the MOS transistor 27 is turned on. As a result, the gates of the cells 8 and 9 of the IGBT device 2ud can be charged through the gate input terminal 10 of the IGBT device 2ud. As a result, the IGBT device 2ud is turned on, the total value Ic of the collector current increases to a predetermined value, and the collector voltage Vc decreases to approximately 0.

  Conversely, when the electronic control unit 6 turns off the IGBT device 2ud that is in the on state, it outputs an off command signal “H” as a command signal. When the drive control unit 15 inputs the off command signal “H”, the gate charges accumulated in the cells 8 and 9 are discharged. At this time, the drive control unit 15 discharges the gate charge while changing the discharge rate of the gate charge, that is, the switching-off rate of the IGBT device 2ud, according to the magnitude of the energization current of the motor 5.

  For example, when the acquisition unit 16 acquires the energization current of the motor 5 as a predetermined current value or less, the drive control unit 15 sets the resistance value of the discharge resistor in the drive control unit 15 to be relatively small and performs discharge. Switch to When the energization current of the motor 5 is smaller than the predetermined current value, the emitter current of the IGBT device 2ud is also small. For this reason, since the sense voltage Vs of the sense resistor 18 does not exceed the output voltage of the threshold voltage generator 20, the output of the comparator 19 is maintained at "L". Therefore, as described above, the MOS transistor 28 on the ground G side is turned on and the other MOS transistors 27, 31, and 32 are turned off, so that the gate charge of the IGBT device 2 ud is discharged through the resistor 30. In this case, since the gate charge of the IGBT device 2ud is discharged through a path (resistor 30) having a relatively small resistance value, the IGBT device 2ud can be driven at high-speed switching off.

  On the other hand, for example, when the acquisition unit 16 acquires that the energization current of the motor 5 is larger than a predetermined current value, the drive control unit 15 increases the resistance value of the discharge resistor in the drive control unit 15 relatively large. And switch to discharge. When the energization current of the motor 5 is larger than the predetermined current value, the emitter current of the IGBT device 2ud also increases. For this reason, since the sense voltage Vs of the sense resistor 18 exceeds the output voltage of the threshold voltage generation unit 20, the output of the comparator 19 becomes “H”. Therefore, the holding unit 17 holds the output “H” of the comparator 19 at the timing when the OFF command signal “H” is input, and outputs this “H” level to each of the logic gates 21 to 24. As a result, the OR gate 21 outputs “H”, the NAND gate 22 outputs “H”, the NOR gate 23 outputs “L”, and the AND gate 24 outputs “H”. Since the MOS transistor 32 on the ground G side is turned on and the other MOS transistors 27, 28 and 31 are turned off, the gate charge accumulated in the IGBT device 2 ud is discharged through the resistor 34. In this case, since the gate charge of the IGBT device 2ud is discharged through a path (resistor 34) having a relatively large resistance value, the IGBT device 2ud can be driven off at a low speed.

  Thereafter, when the electronic control device 6 further turns on the IGBT device 2ud in the off state, it outputs an on command signal “L” as a command signal. When the drive control unit 15 inputs the ON command signal “L”, the drive control unit 15 changes the charge rate of the gate charge, that is, the switching on rate of the IGBT device 2 ud according to the magnitude of the energization current of the motor 5. The IGBT device 2ud is turned on.

  On the other hand, when the electronic control device 6 issues a turn-off command and the off command signal “H” is input to the load drive control device 4ud, the holding unit 17 inputs the “H” level to the clock input terminal of the DFF. Therefore, the output of the comparator 19 is held. For this reason, the acquisition result acquired by the acquisition unit 16 is held by the holding unit 17 even during the period in which the IGBT device 2ud is turned on (see period X in FIG. 6).

  When the off command signal “H” is input to the load drive control device 4ud, if the acquisition unit 16 acquires the load energization current to be equal to or less than a predetermined current value, the drive control unit 15 Even when the command signal “L” is input, switching is performed so that the resistance value of the charging resistor in the drive control unit 15 is relatively small. When the energization current of the load is smaller than the predetermined current value, the emitter current of the second cell 9 is also small. At this time, since the sense voltage Vs of the sense resistor 18 does not exceed the threshold voltage Vt of the threshold voltage generation unit 20, the output of the comparator 19 becomes “L”. In this case, the holding unit 17 holds the output “L” of the comparator 19 while the next ON command signal “L” is input after the OFF command signal “H” is input. Level is output to each logic gate 21-24. As a result, when the next ON command signal “L” is input, the OR gate 21 outputs “L”, the NAND gate 22 outputs “H”, the NOR gate 23 outputs “L”, The AND gate 24 outputs “L”. Since the MOS transistor 27 on the power supply side is turned on and the other MOS transistors 28, 31, and 32 are turned off, the gates of the first cell 8 and the second cell 9 of the IGBT device 2ud are charged through the resistor 29. In this case, the gate charge of the IGBT device 2ud is charged using a current-carrying path in which the gate resistance is small, so that the IGBT device 2ud can be driven on at high speed.

  On the other hand, when the obtaining unit 16 obtains that the energization current of the load is larger than the predetermined current value when the off command signal “H” is input, the drive control unit 15 determines that the next on command signal “ Even when “L” is input, the switching is performed so that the resistance value of the charging resistor in the drive control unit 15 becomes relatively large. When the energization current of the load is larger than a predetermined current value, the emitter current of the second cell 9 is also increased. For this reason, since the sense voltage Vs of the sense resistor 18 exceeds the threshold voltage Vt of the threshold voltage generation unit 20, the output of the comparator 19 becomes “H”. The holding unit 17 holds the output level “H” of the comparator 19 while the next ON command signal “L” is input after the OFF command signal “H” is input, and this “H” level. Is output to each of the logic gates 21-24.

  As a result, when the next ON command signal “L” is input, the OR gate 21 outputs “H”, the NAND gate 22 outputs “L”, the NOR gate 23 outputs “L”, The AND gate 24 outputs “L”. Since the MOS transistor 31 on the power supply side is turned on and the other MOS transistors 27, 28, and 32 are turned off, the gates of the first cell 8 and the second cell 9 of the IGBT device 2ud are charged through the resistor 33. In this case, since the gate charge of the IGBT device 2ud is charged using the energization path having a large gate resistance, the IGBT device 2ud can be driven at a low speed. The above is the description of the switching operation of the IGBT device 2ud. However, the switching speed can be changed so that high-speed driving is performed when the load current is small and low-speed driving is performed when the load current is large.

  FIG. 7 shows the improved characteristics A1a and A2a, and shows the current characteristics flowing in the first cell 8 and the second cell 9 according to the load current. In FIG. 7, the IGBT device 2ud is driven at a high speed when the load current becomes less than the predetermined threshold value Iw2, and the IGBT device 2ud is driven at a low speed when the load current becomes equal to or greater than the predetermined threshold value Iw2. For this reason, as shown in the characteristic A1a of FIG. 7, the current flows relatively easily in the first cell 8 having a large gate resistance, and in the second cell 9 having a low gate resistance as shown in the characteristic A2a of FIG. The flowing current is relatively small.

  When the load current exceeds the predetermined threshold value Iw2, the gate resistance of the drive control unit 15 is largely switched. Although the current flows relatively large in the first cell 8 having a large gate resistance and does not change in the relatively small flow in the second cell 9, the change amount of the current according to the load current can be lowered. As a result, the maximum amount of current flowing through the first cell 8 can be suppressed. Here, in the IGBT device 2ud, since the time constant of the charge / discharge path of the gate charge of the first cell 8 is set to be the largest, the current flowing through the first cell 8 is suppressed to be less than the maximum allowable current Iwh. It is desirable to switch the resistors 29, 30, 33, and 34 in the drive control unit 15 in accordance with the load current. Then, element degradation of the second cell 9 can be suppressed as much as possible.

  According to the present embodiment, the drive control unit 15 drives the IGBT device 2ud at a lower switching-off speed as the load energization current detected corresponding to the acquired value of the acquiring unit 16 increases. Thereby, it becomes difficult to concentrate current on the specific first cell 8, and it is possible to improve the reliability when driving the element while suppressing the deterioration of the element at the time of driving.

  The holding unit 17 holds the determination result of the comparator 19 for the next switching-on period at the turn-off timing of the IGBT device 2ud, and the drive control unit 15 responds to the determination result of the comparator 19 held by the holding unit 17 Thus, the switching-on speed of the IGBT device 2ud is changed. For this reason, according to the magnitude of the load current at the turn-off timing, the next switching on speed of the IGBT device 2ud can be switched to low speed driving or high speed driving.

(Second Embodiment)
8 and 9 show additional explanatory views of the second embodiment. FIG. 8 shows a circuit configuration when the switching speed is switched in three stages. As shown in FIG. 8, a load drive control device 104ud that replaces the load drive control device 4ud includes a drive control unit 115 that replaces the drive control unit 15, an acquisition unit 116 that replaces the acquisition unit 16, and a holding unit 117 that replaces the holding unit 17. Prepare. FIG. 8 shows the configuration of the logic gate for switching off as the drive control unit 115, but the logic gate for switching on driving is not shown in FIG.

  As illustrated in FIG. 8, the acquisition unit 116 includes a plurality of comparators 119 a and 119 b and a plurality of threshold voltage generation units 120 a and 120 b, and includes a plurality of DFFs 117 a and 117 b as the holding unit 117.

  The drive control unit 115 connects a plurality of MOS transistors 128 to 132, 131a, 132a, a NOR gate 123, AND gates 124, 124a, resistors 129, 130, 133, 134, 133a, 134a and the like in the illustrated form. The gate resistance connected to the gate input terminal 10 of the power semiconductor element 2ud can be switched according to the holding result of the holding unit 117 (DFF 117a, 117b). Note that the configuration of the logic gate that operates at the time of charging is omitted in FIG.

  The threshold voltage VT2 of the threshold voltage generator 120b input to the comparator 119b is set higher than the threshold voltage VT1 of the threshold voltage generator 120a input to the comparator 119a. The resistance values of the resistors 130, 134, and 134a are set to be different from each other, and the resistance values of the resistors 129, 133, and 133a are set to be different from each other. For example, the resistance value of the resistor 130 <the resistance value of the resistor 134 <the resistance value of the resistor 134a, for example, the resistance value of the resistor 129 <the resistance value of the resistor 133 <the resistance value of the resistor 133a is set. ing.

  Although a specific description of the logic gate signal processing is omitted, the value of the current flowing through the sense resistor 118 when the gate charge of the IGBT device 2ud is discharged is a first predetermined value (corresponding to the threshold voltage VT2 of the detection voltage of the sense resistor 118). If it is higher, the current value flowing through the resistor 130 and the MOS transistor 128 and flowing through the sense resistor 118 is a first predetermined value and a second predetermined value (<first predetermined value: equivalent to the threshold voltage VT1 of the detection voltage of the sense resistor 118). When the current value is lower than the second predetermined value, the resistor 134a and the MOS transistor 132a are discharged.

  FIG. 9 schematically shows the load current dependency of the current of the IGBT device 2ud when the switching speed is switched in three stages. A characteristic A11 indicates a current flowing through the first cell 8, and a characteristic A12 indicates a current flowing through the second cell 9. By setting the switching speed in multiple stages, the amount of current according to the load current can be finely adjusted. At this time, the current amount according to the load current can be adjusted to be less than the allowable current amount Iwh, the trade-off between the turn-off loss and the surge voltage resistance characteristic can be improved, and the element deterioration due to current concentration is suppressed. it can. As shown in FIG. 9, even when the load current is high, the amount of collector current flowing through the first cell 8 can be suppressed to less than the allowable current amount Iwh (see characteristic A11).

  When the switching speed is switched in multiple stages to three or more stages, the characteristics A11 and A12 are compared with the characteristics A1a and A2a in the case of switching in two stages. The collector current difference from the cell 9 increases. The larger the collector current difference, the better the trade-off between the loss at turn-off and the surge voltage withstand characteristics. Therefore, it is desirable to switch in three steps or more.

(Third embodiment)
FIG. 10 shows an additional explanatory diagram of the third embodiment. As shown in FIG. 10, the IGBT device 202 ud corresponding to the IGBT device 2 ud includes a plurality of parallel connection cells 208, 209, 219, 229, and 239 with the number of parallel connections of the internal cells being five. I have. The number of parallel connections may be other numbers such as 3, 4. The time constants of the charge / discharge paths between these cells 208, 209, 219, 229, and 239 (for example, the resistance values (impedance values) of the gate resistors 211, 221, 231, and 241) are different from each other. Has been. In such a case, different currents flow through the cells 208, 209, 219, 229, and 239 according to the load current, and the same or similar effects as the effects described in the above-described embodiment are achieved. Although the IGBT device 2ud shown in the first embodiment is provided with the sense terminal 14, the output corresponding to the sense terminal 14 in this embodiment is the output of any of the cells 208, 209, 219, 229, 239. The emitter may be output as a multi-emitter and is omitted in FIG.

(Fourth embodiment)
FIG. 11 shows an additional explanatory diagram of the fourth embodiment. As shown in FIG. 11, the IGBT device 302 ud corresponding to the IGBT device 2 ud is configured by including a first cell 308 and a second cell 309 and connecting a resistor 311 to the emitter of the first cell 308. ing.

  Even when the emitter resistor 311 is used instead of the gate resistor 11 described in the first embodiment, the charge / discharge path between the first and second cells 308 and 309 is different. The time constants (for example, impedance) are different from each other. Even in such a case, the same or similar effects as those described in the above embodiment can be obtained. Although the sense terminal 14 is provided in the IGBT device 2ud shown in the first embodiment, the output corresponding to the sense terminal 14 in this embodiment may be output by using the emitter of the cell 309 as a multi-emitter. Is omitted.

(Fifth embodiment)
FIG. 12 shows an additional explanatory diagram of the fifth embodiment. 5th Embodiment shows the form from which the time constant of the charging / discharging path | route of multiple structures by IGBT device 402uda, 402udb as a power semiconductor element mutually differs. As shown in FIG. 12, the drive control unit 15 connects a plurality (two) of IGBT devices 402uda and 402udb. Here, each of the IGBT devices 402uda and 402udb is configured by accommodating the IGBTs 409 and 408, respectively, in one semiconductor package. The IGBT 409 includes an IGBT cell 9a and a diode cell 9b, and the IGBT 408 includes an IGBT cell 8a and a diode cell 8b. And the time constant of the charging / discharging path | route of each IGBT device 402uda and 402udb is set so that it may mutually differ. For example, the gate resistance 411 is connected to the gate of the IGBT 408 of the IGBT device 402udb, and no gate resistance is provided to the gate of the cell 409 of the IGBT device 402uda. As a result, the IGBT devices 402uda and 402udb are set to have different resistance values for the charge / discharge paths through which the cells 409 and 408 are energized. The collectors of the IGBTs 409 and 408 are commonly connected outside the package, and the first emitter E1 of the IGBT 409 and the emitter of the IGBT 408 are commonly connected outside the package. Also in such an embodiment, since the electrical connection is the same as that of the above-described embodiment, the same effect as or similar to the effect described in the above-described embodiment is achieved.

(Sixth embodiment)
13 and 14 show additional explanatory views of the sixth embodiment. In the sixth embodiment, a mode in which control is performed substantially in a stepless manner is shown. As shown in FIG. 13, a load drive control device 504ud is connected to the IGBT device 2ud in place of the load drive control device 4ud. The load drive control device 504ud is configured to drive the IGBT device 2ud when a power supply voltage Vcc is applied between the power supply terminal and the ground G, and includes a drive control unit 515, an A / D converter 550, a selection unit 551, and a sense. A resistor 18 is provided. In addition to the PMOS transistor 27, the NMOS transistor 28, and the resistor 29, the drive control unit 515 includes switches 552a to 552m and resistors 530a to 530n connected in the illustrated form. An A / D converter 550 is connected to the sense resistor 18, and the A / D converter 550 A / D converts the detection voltage by the sense resistor 18. Between the gate input terminal 10 and the ground G, a plurality of resistors 530 a to 530 n and the drain-source of the N-channel MOS transistor 28 are connected in series. Switches 552a to 552m are formed between a common connection point between the plurality of resistors 530a to 530n and the drain of the MOS transistor 28, respectively. A selection unit 551 is connected to the control terminals of these switches 552a to 552m, and the selection unit 551 can switch the switches 552a to 552m on and off according to the A / D conversion result of the A / D converter 550. ing.

  For example, the selection unit 551 turns on the switch (for example, 552a) connected to the gate input terminal 10 in response to the detection voltage of the sense resistor 18 being detected to be high, and other switches (for example, 552b to 552m). Turn off. Further, the selection unit 551 turns on the switch (eg, 552m) connected to the ground G side and turns off the other switches (eg, 552a to 552l) in response to the detection voltage of the sense resistor 18 being detected low. To do. That is, the higher the detection voltage of the sense resistor 18 (the emitter current of the second cell 9) is, the higher the combined resistance value between the gate input terminal 10 and the ground G when the MOS transistor 28 is turned on is increased. Reduce the off speed.

  Conversely, if the emitter current of the second cell 9 is low, the combined resistance value between the gate input terminal 10 and the ground G when the MOS transistor 28 is turned on is reduced to increase the switching-off speed. As a result, the IGBT device 2ud can be driven at a lower switching-off speed as the load current increases.

  FIG. 14 shows the characteristics after the improvement, and shows the characteristics A51 and A52 of the current values flowing through the first cell 8 and the second cell 9 according to the load current. As shown in FIG. 14, when the load current is small, the IGBT device 2ud is driven at high speed, so that a relatively large current flows through the first cell 8 having a large gate resistance, and the second cell 9 having a small gate resistance. The current flowing in the is relatively small.

  When the load current exceeds a predetermined value, the selection unit 551 selectively switches on one of the switches 552a to 552m according to the conversion result of the A / D converter 550. In particular, since the selection unit 551 selectively switches the switches 552a to 552m so as to slow down the switching-off speed when the emitter current of the second cell 9 is high, as illustrated in FIG. The switching-off speed can be adjusted so as not to exceed the allowable current value Iwh. Even in such a case, the same or similar effects as those described in the above embodiment can be obtained, and the adjustment can be made almost steplessly.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and for example, the following modifications or expansions are possible. The above-described embodiments can be applied in combination.
The power semiconductor element is not limited to the IGBT devices 2uu, 2ud, 2vu, 2vd, 2wu, and 2wd, but may be a MOSFET device or the like. Although a constant voltage drive is shown, the same effect can be obtained by a constant current drive.

  The first cell 8 and the second cell 9 of the IGBT are shown as having the same size, but may be configured with different sizes. It is more desirable to configure the same size because it can be configured in an aligned arrangement form. A plurality of IGBT devices 402 uda and 402 udb may be connected, a plurality of cells 8 and 9 may be connected, or a combination of these may be applied. Although the embodiment in which the motor 5 is applied as the load has been described, other types of loads (for example, inductive loads) may be used.

  In the drawing, 2ud, 202ud, and 302ud are IGBT devices (power semiconductor elements), 4uu, 4ud, 4vu, 4vd, 4wu, 4wd, 104ud, and 504ud are load drive control devices, 5 is a motor (load), and 8 is a first cell. (Structure), 9 is a second cell (structure), 10 is a gate input terminal (gate input node), 15, 115 and 515 are drive control units, 16 and 116 are acquisition units, 17 and 117 are holding units, 208, Reference numerals 209, 219, 229, and 239 denote cells (structures), and 402uda and 402udb denote IGBT devices (structures and power semiconductor elements).

Claims (14)

A plurality of structures comprising a plurality of cells (8, 9; 208, 209, 219, 229, 239) or / and a plurality of devices (402 uda, 402 udb) electrically connected to a common gate input terminal (10). The drive (5) is driven and controlled in response to driving power semiconductor elements (2ud; 202ud; 302ud; 402uda, 402udb, etc.) having different time constants in the charge / discharge path of the gate charge between the structures. A drive control unit (15; 115; 515),
An acquisition unit (16; 116) for acquiring a value corresponding to a current flowing through the load through the power semiconductor element;
The drive control unit drives the power semiconductor element at a lower switching-off speed as the load energization current detected corresponding to the acquired value of the acquisition unit becomes higher. .   2. The load drive control according to claim 1, wherein the drive control unit changes a switching-off speed according to a current allowable amount of a structure having a largest time constant of a charge / discharge path of a gate charge among the plurality of structures. apparatus.   The load drive control device according to claim 1, wherein the drive control unit switches the switching-off speed in a stepwise manner in accordance with an acquired value of the acquisition unit. A holding unit (17; 117) for holding the acquired value acquired by the acquiring unit at the turn-off timing of the power semiconductor element for the next switching-on period of the power semiconductor element;
4. The load drive control according to claim 1, wherein the drive control unit changes a switching-on speed of the power semiconductor element in accordance with an acquired value held by the holding unit. 5. apparatus.   The load drive control device according to any one of claims 1 to 4, wherein the plurality of structures are configured to have the same size.   The load drive control device according to any one of claims 1 to 5, wherein the load is an inductive load.   The impedance of the charge / discharge path of the gate capacitance includes a gate resistance (11; 111; 211, 221, 231, 241; 411) or an emitter resistance (311). The load drive control device according to item. A power semiconductor element (2ud; 202ud; 302ud; 402uda, 402udb, etc.) has a plurality of cells (8, 9; 208, 209, 219, 229, 239) electrically connected to a common gate input node (10). Or / and having a plurality of structures composed of a plurality of devices (402uda, 402udb), the time constant of the charge / discharge path of the gate charge is different between at least two of the cells,
Obtaining a value corresponding to the current flowing through the load through the power semiconductor element;
A load drive, wherein the load is driven and controlled in response to driving the power semiconductor element at a low switching-off speed as the load current detected in accordance with the acquired value increases. Control method.   9. The load drive control method according to claim 8, wherein the switching-off speed is changed in accordance with a current allowable amount of a structure having the largest time constant of the charge / discharge path of the gate charge among the plurality of structures.   10. The load drive control method according to claim 8, wherein the switching-off speed is switched in a stepwise manner in accordance with an acquisition value of the acquisition unit. The acquired value obtained by acquiring the value corresponding to the current flowing through the load at the turn-off timing of the power semiconductor element is held for the next switching on period of the power semiconductor element,
The load drive control method according to any one of claims 8 to 10, wherein a switching-on speed of the power semiconductor element is changed in accordance with a held acquired value.   The load drive control method according to any one of claims 8 to 11, wherein the plurality of structures are configured to have the same size.   The load drive control method according to any one of claims 8 to 12, wherein the load is an inductive load.   The load drive control method according to any one of claims 8 to 13, wherein the impedance of the charge / discharge path of the gate capacitance includes a gate resistance or an emitter resistance.

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