JP2004319624A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing breakdown due to a surge current at a low production cost and changing the characteristics as required. <P>SOLUTION: The semiconductor device consists of a first gate voltage driving type semiconductor element 20, a first gate pattern 26 connected to the gate of the semiconductor element 20, a second gate voltage driving type semiconductor element 41 and a second gate pattern 33 connected to the gate of the semiconductor element 41. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a plurality of gate voltage driven semiconductor elements.
[0002]
[Prior art]
One of the gate voltage driven semiconductor devices is an insulated gate bipolar transistor (IGBT). For example, in an inverter, it is used as a switching element that controls a collector current flowing from a collector to an emitter by controlling a gate voltage and switches the direction of the current. If a large current flows from the collector to the emitter due to a load short circuit or the like, the IGBT may be destroyed. Therefore, the collector current is detected, and when an overcurrent flows, the gate voltage is controlled.
[0003]
For example, in a conventional semiconductor device (see Patent Document 1), as shown in FIG. 16, an emitter cell of a transistor Tr1 (IGBT) is separated into a first emitter cell E1 and a second emitter cell E2, and a current detection terminal S is provided for each of them. And the second emitter terminal E are connected. Both ends of the current detection resistor Rs and the base and the emitter of the protection transistor Tr2 are connected between the current detection terminal S and the second emitter terminal E. A gate resistor Rg is connected to the gate terminal of the transistor Tr1, and a split resistor Rd is connected between the collector of the protection transistor Tr2 and the gate of Tr1.
[0004]
When the collector current of the transistor Tr1 flows as a part of the short-circuit current due to the short-circuit of the load, a part of the short-circuit current also flows to the current detection resistor Rs via the current detection terminal S. When the voltage between both ends of the current detection resistor Rs exceeds the conduction voltage, the protection transistor Tr2 conducts, and the input voltage Vin applied to the gate terminal G is divided by the gate resistance Rg and the division resistance Rd. As a result, the gate voltage of the transistor Tr1 decreases, the current density decreases, and protection from latch-up breakdown occurs.
[0005]
[Patent Document 1]
Patent No. 2806503 [0006]
[Problems to be solved by the invention]
As described above, in the conventional semiconductor device, the protection transistor Tr2 is driven by using the voltage drop due to the current detection resistor Rs, and the gate voltage of the transistor Tr1 is controlled. However, when the gate voltage is rapidly lowered, the current flowing through the transistor Tr1 rapidly decreases, and a surge voltage proportional to the current / time is generated. Therefore, a split resistor Rd is added externally to prevent a sharp drop in the gate voltage.
[0007]
However, the dividing resistor Rd must be externally attached to the semiconductor device, and an attaching operation is required, which increases component costs and manufacturing costs. In addition, since the transistor Tr1 and the protection transistor Tr2 operate simultaneously, characteristics such as switching speed are determined in one way. In order to change this characteristic, it is necessary to change the resistance value of the split resistor Rd.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that can prevent destruction due to a surge voltage due to a short circuit of a load or the like at a low manufacturing cost, and can change characteristics as needed.
[0009]
[Means for Solving the Problems]
As the inventor of the present application has conducted research on overcurrent and surge voltage, the problem of the above-described conventional example is that a common (one) divided resistor Rd is externally connected to the transistor Tr1 and the protection transistor Tr2, and a common ( It has been found that this is caused by the collective control of the gate voltage through one (one) gate pad and gate pattern. Therefore, the present inventors have conceived of forming a semiconductor device with a plurality of gate voltage driving type semiconductor element groups and forming a plurality of gate patterns to be connected to each semiconductor element group correspondingly.
[0010]
According to a first aspect of the present invention, there is provided a semiconductor device including at least a first gate voltage driven semiconductor element and a first gate pattern connected to a gate of the first gate voltage driven semiconductor element. , A second gate voltage driven semiconductor device, and a second gate pattern connected to the gate of the second gate voltage driven semiconductor device.
[0011]
In this semiconductor device, a plurality of gate voltage driven semiconductor element groups can be selectively operated in different modes or any of them. Thus, for example, when an overcurrent occurs, only a part of the gate voltage driving type semiconductor element is operated, and then another gate voltage driving type semiconductor element is operated, so that the gate voltage gradually decreases.
[0012]
In addition, by inserting a resistor or the like into any of the gate patterns and changing the resistance value or the like, characteristics (on-resistance or switching speed) of the semiconductor device can be changed. In other words, a single semiconductor device can have a plurality of characteristics.
[0013]
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first gate voltage of the first gate voltage driven semiconductor element and the second gate voltage of the second gate voltage driven semiconductor element are turned off at different timings. You. According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the first gate pattern and / or the second gate pattern are turned off when the timing of turning off the first gate voltage and the timing of turning off the second gate voltage are shifted. Including change elements.
[0014]
According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the first gate voltage of the first gate voltage driving type semiconductor element and the second gate voltage of the second gate voltage driving type semiconductor element have different voltage values. According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, the first gate pattern and / or the second gate pattern have a voltage value change that causes the voltage value of the first gate voltage to be different from the voltage value of the second gate voltage. Contains elements.
[0015]
According to a sixth aspect of the present invention, in the semiconductor device according to the second or fourth aspect, the first gate pattern is connected to the first gate pad, and the second gate pattern is connected to the first gate pad. According to a seventh aspect of the present invention, in the semiconductor device according to the second or fourth aspect, the first gate pattern and the second gate pattern are connected to one common gate pad.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
<Gate voltage driven semiconductor device>
(1) The semiconductor device of the present invention includes at least two gate-voltage-driven semiconductor elements (hereinafter, abbreviated as “semiconductor elements” in the embodiments of the present invention). Therefore, two or three or more semiconductor elements constitute a semiconductor device. "One" semiconductor device means an aggregate of a large number of cells in contact with one gate pattern. Semiconductor devices include IGBTs and MOSFETs, and in each case, the current flowing from the collector to the emitter is controlled by controlling the gate voltage.
(2) Semiconductor devices can be roughly classified into two types. In the A type, gate voltages of a plurality of semiconductor element groups are turned off at different timings. The shift amount (time difference) of the turning-off timing is determined so that the surge voltage generated due to the current change amount does not exceed the withstand voltage of the semiconductor device. For example, if the first semiconductor element is turned off first and then the second semiconductor element is turned off, the surge voltage associated with the current change when the first semiconductor element is turned off and the surge voltage associated with the current change when the second semiconductor element is turned off Is halved compared to the amount of voltage drop when both are dropped at the same time.
[0017]
For example, three (first, second, and third) semiconductor elements may have their gate voltages turned off at different timings, or two of them may be turned off at the same time, and the remaining one may be different from these. It may be turned off at the timing. The same applies to the case of four or more. The plurality of gate voltage values may be the same or different.
(3) In the B type, the voltage values of the gate voltages of the plurality of semiconductor element groups are different. Each gate voltage value is determined in consideration of the collector current density with respect to the gate voltage of the semiconductor device. In this case, the timing of turning off the first gate voltage of the first semiconductor element and the timing of turning off the second gate voltage of the second semiconductor element may be the same or different.
{Circle around (4)} If necessary, both the A type and the B type can be adopted.
<Gate pad, gate pattern>
{Circle around (1)} One or two or more gate pads are formed at corners or corners of the surface of the semiconductor device, serving as entrances of control signals from a control circuit (control IC). A plurality (for example, two) of gate pads may be formed, and a gate pattern (gate wiring) may extend from each of the gate pads. Further, a plurality of (for example, two) gate patterns may be branched from one gate pad. The gate pattern can be formed by a general-purpose material and method such as evaporation of aluminum.
{Circle over (2)} When the semiconductor device is of the A type, a plurality of gate patterns (for example, the first gate pattern and / or the second gate pattern) are provided between a plurality of semiconductor elements (for example, the (Off), an off-time changing element for shifting the timing of turning off the gate voltage can be included. For example, when a resistor, a capacitor, or a coil is inserted into any of the gate patterns, the off time is shifted (C type). In addition, the off-time can be shifted by giving a difference in shading between the surface concentration of a certain gate electrode and the surface concentration of another gate electrode (D type).
[0018]
If necessary, both the C type and the D type can be adopted.
{Circle around (3)} When the semiconductor device is of the B type, the plurality of gate patterns (for example, the first gate pattern and / or the second gate pattern) can include a voltage value changing element that varies a voltage value. Specifically, a divided resistor may be inserted into any of the gate patterns, a diode may be arranged bidirectionally, or a Zener diode may be inserted (E type). Further, voltage values applied from the control circuit to the plurality of gate pads may be different (F type).
[0019]
If necessary, both E type and F type can be adopted.
{Circle around (4)} When the A type and the B type are adopted, both the C type and the D type and the E type and the F type can be adopted.
[0020]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<First embodiment>
In the first embodiment, the timing for turning off the gate voltage is made different. This is the same in the second, third and fourth embodiments described below.
(Constitution)
1, 2 and 3 show a semiconductor device (semiconductor chip) according to a first embodiment. 1 is a circuit diagram, FIG. 2 is a plan view showing a gate pattern formed on the surface of the semiconductor device, and FIG. 3 is a cross-sectional view of a part (first IGBT) of the semiconductor device.
[0021]
As shown in FIGS. 1 and 2, the semiconductor device 10 includes a first IGBT 20, a second IGBT 40, a first gate pad 25 and a first gate pattern 26, and a second gate pad 32 and a second gate pattern 33. .
[0022]
More specifically, as shown in FIG. 3, an n-type layer 12 is stacked on a p-type layer 11, and a p-type layer 13 is stacked on the n-type layer 12. On the front surface side of the semiconductor device 10, a plurality of gate buried electrodes 16 having a predetermined width and depth are buried from the p-type layer 13 to the n-type layer 12 via the insulating layer 17, and extend long (see FIG. 2). . In the p-type layer 13, n-type regions 14 are formed on both sides of the gate buried electrode 16. In a region other than the gate G, the p-type layer 13 and the n-type layer 14 form an emitter E (not shown in FIG. 2). On the other hand, a collector C is formed on the back surface side.
[0023]
Thus, the first IGBT 20 is configured by the IGBT cells 21 connected in parallel (see FIG. 1). Similarly, the second IGBT 40 includes a number of IGBT cells 41 connected in parallel.
[0024]
As is clear from FIG. 2, a first gate pad 25 is formed at a first corner 18a at one end 18 of the surface of the semiconductor device 10, and a first gate pattern 26 extends from this. The first gate pattern 26 extends inward from one side 27a and the other side 27b, one end 28a and the other end 28b, and a plurality (three in FIG. 2) extending inward from the one side 27a and the other side 27b, respectively. ) Extensions 29a and 29b.
[0025]
The second gate pattern 33 extending from the second gate pad 32 at the second corner 18 b of the semiconductor device 10 is located entirely inside the first gate pattern 26. That is, one side portion 34a and the other side portion 34b located inside the one side portion 27a and the other side portion 27b, and one end portion 35a and the other end portion 35b located inside the one end portion 28a and the other end portion 28b. And a plurality (three in FIG. 2) of U-shaped extensions 36a and 36b extending from the one side 34a and the other side 34b, respectively, and surrounding the extensions 29a and 29b.
[0026]
As partially shown in FIG. 2, the gate buried electrode 16 of each cell 21 of the first IGBT 20 extends between adjacent extensions 29b of the first gate pattern 26 and is joined to the extensions 29b at both ends. (See x mark). It is not joined to the extension 36b of the second gate pattern 33.
[0027]
The gate buried electrode 43 of each cell 41 of the second IGBT 40 extends between the adjacent extension portions 36b of the second gate pattern 33, and is joined to the extension portions 36b at both ends (see the mark ○). It is not joined to the extension 29b of the first gate pattern 26.
(Effect)
The operation and effect will be described with reference to FIGS. 1 to 3 and 4. FIGS. 4A and 4B are graphs showing the relationship between ON and OFF of the first gate voltage V1 applied to the first gate pad 25 and the second gate voltage V2 applied to the second gate pad 32, and the elapsed time. is there. FIG. 4C shows the relationship between the collector current and voltage and the elapsed time.
[0028]
4A and 4B, when the semiconductor device 10 is turned on, a first gate voltage V1 is applied to the first gate pad 25, and at the same time, a second voltage gate V2 (here, the first voltage gate V2) is applied to the second gate pad 32. (Equal to the voltage V1). Then, in FIG. 4C, the current value of the collector current flowing from the collector C to the emitter E increases, and the voltage value between the collector and the emitter decreases.
[0029]
On the other hand, when the semiconductor device 10 is turned off, as shown in FIGS. 4A and 4B, the control circuit first releases the application of the first gate voltage V1 to the first gate pad 25, and after a predetermined time Δt has elapsed. The application of the second gate voltage V2 to the second gate pad 32 is released. By releasing the application of the first gate voltage V1, the current value decreases by about half of the predetermined value as indicated by Ia in FIG. 4C, and the voltage value decreases by about half of the predetermined voltage Vcc between the collector and the emitter as indicated by Va. Go up. As a result, a surge voltage Vb is generated, but its value is reduced by about half as compared with the prior art.
[0030]
Subsequently, when the application of the second gate voltage V2 is released, the current value decreases to almost zero as indicated by Ib, and the voltage value increases to a predetermined value as indicated by Vc. Also at this time, a surge voltage Vd is generated, but its magnitude is about half of the conventional one.
[0031]
As described above, the application of the first gate voltage V1 and the second gate voltage V2 staggered the application release timing, so that the current value decreased in two steps and the voltage value increased in two steps. As a result, the surge voltage is divided into two when the first gate voltage V1 is released and when the second gate voltage V2 is released, and the individual surge voltages Vb and Vd are suppressed to a level that does not damage the semiconductor device 10.
[0032]
In addition, it is not necessary to externally attach a resistor or the like to the semiconductor device, which simplifies the manufacturing process and reduces the manufacturing cost.
<Second embodiment>
In this embodiment, only one gate pad is provided on the surface of the semiconductor device, and a resistor is provided on only one of the first gate pattern and the second gate pattern extending therefrom. More specifically, in FIGS. 5 and 6, the resistor 54 is arranged in the second gate pattern 53 extending from the gate pad 50, but the resistor is not arranged in the first gate pattern 51. Since there is only one gate pad 50, application and release of the gate voltage to the first IGBT 56 contacting the gate pattern 51 and the second IGBT contacting the second gate pattern 53 are performed simultaneously.
[0033]
According to this embodiment, even if the gate voltage is released at the same time, the resistor 54 is arranged only in the second gate pattern 53, so that the timing of the fall of the second current is slightly shorter than the timing of the fall of the first current. There is a specific effect that is delayed. As a result, similarly to the first embodiment, the current decreases in two stages, and the voltage value of the surge voltage distributed twice is reduced by half.
<Third embodiment>
The third embodiment shown in FIGS. 7 and 8 has both the advantages of the first embodiment and the advantages of the second embodiment. A first gate pattern 72 extends from the first gate pad 71 and is in contact with the gate of the first IGBT 78. A second gate pattern 74 extends from the second gate pad 73 and is in contact with the gate of the second IGBT 79.
[0034]
The timing of the release of the application of the second gate voltage to the first gate pad 71 and the release of the application of the second gate voltage to the second gate pad 73 are shifted. Further, a resistor 76 is arranged in the second gate pattern 74, but no resistor is arranged in the first gate pattern 72.
[0035]
As an effect peculiar to this embodiment, first, a two-step current drop, that is, a two-time dispersion of the surge voltage becomes more reliable. Second, it is not necessary to provide a resistor in the first IGBT.
[0036]
As an effect common to the second and third embodiments, when the resistances of the resistors 54 and 76 provided in the gate patterns 53 and 74 are changed, the on-resistance and the switching characteristics as well as the timing of turning off the gate voltage. Can also be changed.
<Mode of resistance>
The following various aspects can be adopted for the resistors 54 and 76 in the second and third embodiments.
{Circle around (1)} In the first mode, the sizes of the contact areas between the gate electrodes of the two IGBTs and the two gate patterns are made different. As shown in FIG. 9, the contact area S1 of the contact portion 83 between the gate electrode 81 of the first IGBT and the first gate pattern 82 is the contact area 87 of the contact portion 87 between the gate electrode 85 of the second IGBT and the second gate pattern 86. Wider than S2.
{Circle around (2)} In the second mode, the surface concentrations of the gate electrodes of the two IGBTs are different. As shown in FIG. 10, the surface concentration of the contact portion 93 of the first IGBT gate electrode 92 that contacts the first gate pattern 91 is reduced, and the contact portion 96 of the second IGBT gate electrode 95 that contacts the second gate pattern 94. Has a high surface concentration.
{Circle around (3)} In the third embodiment shown in FIG. 11, the resistor 103 is provided between the gate electrode 101 of the second IGBT and the second gate pattern 102. However, no resistance is provided between the gate electrode 105 of the first IGBT and the first gate pattern 106.
{Circle around (4)} In the fourth mode, resistors having different resistance values are arranged between the two gate pads and the two external terminals. As shown in FIG. 12, the resistance value of the first resistor 112 between the first gate pad 110 and the first external terminal 111 is the second resistance 116 between the second gate pad 114 and the second external terminal 115. Is larger than the resistance value.
<Fourth embodiment>
In the fourth embodiment, the heat radiation after turning off the IGBT is devised. As shown in FIG. 13, the first gate pattern 121 extending from the first gate pad 120 has one side 122a and the other side 122b, one end 123a and the other end 123b, and has a rectangular frame shape. On the other hand, the second gate pattern 126 extending from the second gate pad 125 is disposed inside the first gate pattern 121, has one side 127a and the other side 127b, one end 128a and the other end 128b, and has a square shape. It has a frame shape.
[0037]
Both ends of the plurality of gate electrodes 130 of the first IGBT are joined to one end 123a and the other end 123b of the first gate pattern 121 (see the crosses). The total width (for example, 100 μm) of the plurality of gate electrodes 130 is smaller than the thickness (for example, 200 μm) of the semiconductor device. The same applies to the connection (see the circle) between both ends of the plurality of gate electrodes 133 of the second IGBT and one end 128a and the other end 128b of the second gate pattern 126.
[0038]
According to this embodiment, generation of a surge voltage can be suppressed by providing a time difference between the turning off of the gate voltage to the first gate pad 120 and the turning off of the gate voltage to the second gate pad 125. In addition, heat radiation of the semiconductor element after the first IGBT is turned off is smooth. Since the sum of the widths of the plurality of gate electrodes 130 of the first IGBT is smaller than the thickness of the semiconductor device, the current flowing in the vertical direction of the semiconductor device flows while spreading over the entire surface of the semiconductor, and the heat is not localized but uniform. is there.
<Fifth embodiment>
In the fifth embodiment, the first IBGT and the second IGBT have different gate voltage values. This is the same in the sixth embodiment described below.
[0039]
More specifically, as shown in FIG. 14, a first dividing resistor 146 is inserted between the gate 141 of the first IBGT 140 and the gate 144 of the second IGBT 143, and a second dividing resistor is connected between the gate 144 of the second IGBT 143 and GND. The resistor 147 is inserted. For example, when the resistance values of the first divided resistor 146 and the second divided resistor 147 are equal, the gate voltage of the second IGBT 143 becomes V / 2 with respect to the gate voltage V of the first IBGT 140.
[0040]
As a result, it is possible to cope with a surge voltage by shifting the timing of opening and closing the application of the gate voltage between the first IBGT 140 and the second IGBT 143. In addition, different characteristics are obtained when both the first IBGT 140 and the second IGBT 143 are activated, when only the first IBGT 140 is activated, and when only the second IGBT 143 is activated. That is, a single semiconductor device can have three different characteristics.
<Sixth embodiment>
In the sixth embodiment, as shown in FIG. 15, a diode 156 is arranged bidirectionally between the gate 154 of the second IBGT 153 and a control circuit (not shown). However, no diode is arranged between the gate 151 of the IGBT 150 and the control circuit.
[0041]
As a result, first, it is possible to incorporate a circuit that can be driven with different gate voltages inside the semiconductor device. Second, an effect of incorporating a drive circuit capable of controlling input / output signal timing with a time difference can be obtained.
[0042]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, a plurality of gate voltage drive type semiconductor element groups can be operated in different modes or selectively. As a result, the surge voltage can be suppressed and the switching speed can be changed at a low manufacturing cost.
[0043]
According to the semiconductor device of the second and third aspects, when an overcurrent occurs, the gate voltage is increased by turning off some of the gate voltage driven semiconductor elements and the remaining gate voltage driven semiconductor elements with a time difference. And the surge voltage can be suppressed.
[0044]
According to the semiconductor device of the fourth and fifth aspects, a single semiconductor device can have a plurality of characteristics by changing the resistance value or the like of the resistor inserted into any one of the gate patterns. According to the semiconductor device of the sixth and seventh aspects, suppression of surge voltage can be realized without externally attaching a resistor or the like to the semiconductor element, and the manufacturing cost is reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment (semiconductor device) of the present invention.
FIG. 2 is a plan view showing the surface of the first embodiment.
FIG. 3 is a cross-sectional view illustrating a stacked structure of the IGBT.
FIGS. 4 (a), (b) and (c) are explanatory diagrams of the operation of the first embodiment.
FIG. 5 is a circuit diagram of a second embodiment (semiconductor device) of the present invention.
FIG. 6 is a plan view showing the surface of the second embodiment.
FIG. 7 is a circuit diagram of a third embodiment (semiconductor device) of the present invention.
FIG. 8 is a plan view showing the surface of the third embodiment.
FIG. 9 is a perspective view showing a first mode of the resistor.
FIG. 10 is a perspective view showing a second mode of the resistor.
FIG. 11 is a perspective view showing a third mode of the resistor.
FIG. 12 is an explanatory plan view showing a fourth mode of the resistor.
FIG. 13 is a plan view showing the surface of the fourth embodiment.
FIG. 14 is a circuit diagram showing the surface of the fifth embodiment.
FIG. 15 is a circuit diagram showing the surface of the sixth embodiment.
FIG. 16 is a circuit diagram showing a conventional example.
[Explanation of symbols]
11, 13: p-type layer 12: n-type layer 14: n-type region 16: buried gate electrode 20: first IGBT 21: cell 25: first gate pad 26: first gate pad 32: second gate pad 33: Second gate pad 40: second IGBT 41: cell

Claims (7)

At least a first gate voltage drive type semiconductor element;
A first gate pattern connected to a gate of the first gate voltage driven semiconductor device;
A second gate voltage drive type semiconductor device;
A second gate pattern connected to a gate of the second gate voltage drive type semiconductor device;
A semiconductor device having a plurality of gate patterns made of: 2. The semiconductor device according to claim 1, wherein the first gate voltage of the first gate voltage driven semiconductor element and the second gate voltage of the second gate voltage driven semiconductor element are turned off at different timings. 3. 3. The device according to claim 2, wherein the first gate pattern and / or the second gate pattern includes an off-time changing element that shifts a timing of turning off the first gate voltage and a timing of turning off the second gate voltage. 4. Semiconductor device. 2. The semiconductor device according to claim 1, wherein a first gate voltage of the first gate voltage driven semiconductor element and a second gate voltage of the second gate voltage driven semiconductor element have different voltage values. 3. 5. The semiconductor device according to claim 4, wherein the first gate pattern and / or the second gate pattern includes a voltage value changing element that makes a voltage value of the first gate voltage different from a voltage value of the second gate voltage. 6. . The semiconductor device according to claim 2, wherein the first gate pattern is connected to a first gate pad, and the second gate pattern is connected to a first gate pad. The semiconductor device according to claim 2, wherein the first gate pattern and the second gate pattern are connected to one common gate pad.

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