JP4547790B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4547790B2
JP4547790B2 JP2000306206A JP2000306206A JP4547790B2 JP 4547790 B2 JP4547790 B2 JP 4547790B2 JP 2000306206 A JP2000306206 A JP 2000306206A JP 2000306206 A JP2000306206 A JP 2000306206A JP 4547790 B2 JP4547790 B2 JP 4547790B2
Authority
JP
Japan
Prior art keywords
region
semiconductor
thin film
film layer
zener diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000306206A
Other languages
Japanese (ja)
Other versions
JP2002118230A (en
Inventor
順 齋藤
信一 神保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Systems Co Ltd filed Critical Fuji Electric Systems Co Ltd
Priority to JP2000306206A priority Critical patent/JP4547790B2/en
Publication of JP2002118230A publication Critical patent/JP2002118230A/en
Application granted granted Critical
Publication of JP4547790B2 publication Critical patent/JP4547790B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
この発明は、パワーデバイスの制御駆動用などに用いられる高耐圧ＩＣ（ＨＶＩＣ）などの半導体装置に関する。
【０００２】
【従来の技術】
図５は、Ｄｏｕｂｌｅ ＲＥＳＵＲＦ構造と抵抗性フィールドプレート構造を組み合わせた高耐圧接合終端構造であり、同図（ａ）は要部断面図、同図（ｂ）は電位分布図である。この高耐圧接合終端構造は、高耐圧ＩＣの代表的な耐圧構造である。
【０００３】
同図（ａ）において、ｐ基板３５ａの表面層にＮwell領域３４が設けられている。このＮwell領域３４の表面層に高電位領域３３、低電位領域３７およびＰoffset領域３９がそれぞれ形成されている。高電位領域３３上と低電位領域３７上には、高電位側電極３２と低電位側電極３８がそれぞれ形成され、ｐ基板３５上に形成される絶縁酸化膜４１上に高比抵抗の抵抗性フィールドプレートである薄膜抵抗層４０が形成され、この薄膜抵抗層４０により高電位側電極３２と低電位側電極３８とが電気的に接続されている。また、低電位側電極３８と裏面側電極３６は、ｐ基板３５の終端部で電気的に接続している。前記の薄膜抵抗層４０が高耐圧接合終端構造上部の表面構造である。尚、３５ａはｐ基板層である。
【０００４】
同図（ｂ）において、低電位側電極３８を基準（例えば、ＧＮＤ）として、高電位側電極３２に正電位ＶS を印加したとき、電位分布は抵抗性フィールドプレート４０の両端付近で歪みが大きく、電界が集中している。そのために、この個所で耐圧が低下する。
図６は、特開平９−５５４９８号公報に開示されているような高耐圧ＩＣの高耐圧接合終端構造（ＨＶＪＴ）の平面図である。この高耐圧接合終端構造（ＨＶＪＴ）は、その表面に、図５のような抵抗性フィールドプレート４０を適用した例である。
【０００５】
第１基準回路形成領域５１と第２基準回路形成領域５２は、それぞれ異なる電位を基準電位とする集積回路が形成される領域である。例えば、第１基準回路形成領域５１を、ＧＮＤを基準電位とする集積回路が形成される領域であり、第２基準回路形成領域５２は、０〜１２００Ｖまでの変動する電位を基準とする集積回路が集積形成される領域である。この第１基準回路形成領域５１と第２基準回路形成領域５２の間には、前記の抵抗性フィールドプレート５４（図５の４０に相当する）が設けられ、第１基準回路形成領域５１と第２基準回路形成領域５２が、電位的に分離されている。尚、図中の５３は高耐圧接合終端構造上部の表面構造であり、５５は高耐圧ＮＭＯＳであり、５６は高耐圧ＰＭＯＳである。
【０００６】
【発明が解決しようとする課題】
この抵抗性フィールドプレート５４の両端近傍（第１基準回路形成領域５１と第２基準回路形成領域５２に接続する箇所の近傍）での電位分布の歪みが大きく（図５（ｂ）のように）、電界が集中し、この箇所で耐圧が低下する。この電界集中を和らげるために、抵抗性フィールドプレート５４の幅を広くすると、チップサイズが増大し、チップコストが増加する。
【０００７】
この発明の目的は、前記の課題を解決して、高耐圧化が可能で、チップコストが抑制され、かつ、長期信頼性の確保が可能である高耐圧接合終端構造を有する高耐圧ＩＣなどの半導体装置を提供することにある。
【０００８】
【課題を解決するための手段】
前記の目的を達成するために、半導体基板内に形成された第１半導体領域に接続された第１電極と、第１半導体領域と異なる電位を基準電位とする前記第１半導体領域を囲む前記半導体基板内に形成された第２半導体領域と、該第２半導体領域に接続された第２電極とを有する半導体装置において、前記半導体基板上に両端が前記第１電極と前記第２電極にそれぞれ電気的に接続され、第１電極を囲む渦巻状の帯状の薄膜層が形成され、該薄膜層は、第１、第２半導体領域の端部に対して平行に形成される等距離領域と、第１、第２半導体領域の端部に対して傾斜して形成される傾斜領域とで構成され、該薄膜層の少なくとも傾斜領域にはツェナーダイオードが形成され、該傾斜領域のツェナーダイオードのｐｎ接合面が第１、第２半導体領域の端部に対して平行であるとする。
【０００９】
【００１０】
前記第１半導体領域が第１集積回路形成領域であり、前記第２半導体領域が第２集積回路形成領域であり、前記薄膜層が前記第１集積回路形成領域と第２集積回路形成領域を電位的に分離するための高耐圧接合終端構造上部の表面構造であるとよい。
前記薄膜層の等距離領域は、曲線部分または直線部分が形成されているとよい。
前記等距離領域の曲線部分または直線部分にはツェナーダイオードを形成しないとよい。
【００１１】
このように、高耐圧接合終端構造上部の表面構造を構成する薄膜層に、直列に複数個接続したツェナーダイオードを形成し、このツェナーダイオードの均等な分圧を利用することで、均一な電位分布が得られる。
【００１２】
【発明の実施の形態】
図１は、この発明の第１実施例の半導体装置の要部平面図である。この図は、高耐圧ＩＣの要部平面図である。この高耐圧ＩＣを形成する領域は、第１基準回路形成領域１と第２基準回路形成領域２と、これらの基準回路形成領域１、２を電位的に分離する複数のツェナーダイオード（図中のｐで表されるｐ型薄膜層と、ｎで表されるｎ型薄膜層で形成される）が形成された薄膜層４で構成される。この薄膜層４に形成されるツェナーダイオードは、高耐圧ＮＭＯＳ５、高耐圧ＰＭＯＳ６が設けられている箇所やコーナ箇所の曲線部分Ｂと、基準回路形成領域１、２端部と等距離になる直線部分Ｃとに形成されるが、傾斜部分Ａにも、ツェナーダイオードが形成されるが図が複雑になることから省いた。この薄膜層４が、高耐圧接合終端構造上部の表面構造３であり、また、第１、第２基準回路形成領域１、２には、それぞれ集積回路である第１、第２基準回路が形成される。
【００１３】
帯状の薄膜層４の両端間で、全体的に第１、第２基準回路形成領域に対して傾きを付け、ツェナーダイオードを薄膜層全体に形成しても勿論構わない。
この実施例は、薄膜層４の両端間で全体的に傾きを付けて形成するものに比べ設計を容易に行うことが可能となる。全体的に傾きを付けたものと比べると、直線部分において直線部分と直交する方向（第１基準回路形成領域と第２基準回路形成領域間）での電位分布が不十分となり、耐圧は小さい。しかしながら、傾斜部Ａの傾斜の角度を十分小さくし、傾斜部を長くすれば第１基準回路形成領域と第２基準回路形成領域間の電位変動が小さくなるので、全体に傾きを付けたものに耐圧を近づけることが可能となる。
【００１４】
この高耐圧ＩＣにおいて、例えば、第２基準回路形成領域２を高電位とすると、低電位側の第１基準回路形成領域１に形成された第１基準回路の低電位信号と、高電位側の第２基準回路の高電位信号が、高耐圧ＮＭＯＳ５（ｎチャネルＭＯＳＦＥＴ）および高耐圧ＰＭＯＳ６（ｐチャネルＭＯＳＦＥＴ）を介して、それぞれやり取りされる。
【００１５】
この高電位となる第２基準回路形成領域２の耐圧を確保するために、前記の高耐圧接合終端構造上部の表面構造３である薄膜層４を、第１基準回路形成領域１と第２基準回路形成領域２の間に設ける。この薄膜層４には、ツェナーダイオードが直列に複数個形成された、図５で示す抵抗性フィールドプレート５４に代わる高耐圧接合終端構造上部の表面構造４となる。
【００１６】
このツェナーダイオードで形成した薄膜層４においては、個々のツェナーダイオードの耐圧は等しいために、高耐圧接合終端構造上部の表面構造３の長手方向の電位分布は均等化され、それによって、長手方向と直交する方向の電位分布も均等化される。つまり、第１、第２基準回路領域間の電位分布が均等化される。また、第１、第２基準回路形成領域間１、２の電圧は、ツェナーダイオードの逆方向耐圧で保持するために、抵抗性フィールドプレートの場合に流れるような比較的大きな漏れ電流が流れることは防止される。
【００１７】
また、高耐圧接合終端構造上部の表面構造３の長手方向に対して、薄膜層４に傾きをつけた傾斜部分Ａを１箇所あるいは複数箇所設けることで、必要に応じた本数の薄膜層を容易に形成することができる。
図１では、従来の図６の構造と比べ、高耐圧接合終端構造の幅を狭くすることが可能となり、その結果チップサイズが小さくなり、チップコストが抑制できる。また、抵抗性窒化膜（抵抗性フィールドプレート）を使用しないため、抵抗性窒化膜の酸化による耐圧の低下が起こらず、長期間の信頼性を確保することができる。
【００１８】
図２は、この発明の第２実施例の半導体装置の要部平面図である。この構造の場合、ツェナーダイオードを配置するのは、傾斜部分Ａの薄膜層とし、第１、第２基準回路形成領域１、２端部と等距離となる直線箇所Ｃや、曲線部分Ｂにはツェナーダイオードを配置しない。
この場合、曲線部分Ｂに形成される高耐圧ＮＭＯＳ５近傍、高耐圧ＰＭＯＳ６近傍など、電界の集中しやすい曲率を持った部分には、ツェナーダイオードを形成せず、また、高耐圧接合終端構造上部の表面構造３と等距離となる箇所にもツェナーダイオードを形成しない構造である。そのため、ツェナーダイオードのない薄膜層４（ここではｎ型薄膜層である）では、電位降下が小さく、ほぼ等電位となり、これと直交する方向の電位分布は均一化される。その結果、第１実施例よりもさらに高耐圧接合終端構造の耐圧を高めることができる。
【００１９】
つぎに、前記の曲線部分Ｂにツェナーダイオードがある場合とない場合の電位分布について説明する。
図７は、曲線部分の等電位線を表した図であり、同図（ａ）は第１実施例の場合で、ツェナーダイオードがある場合の図、同図（ｂ）は第２実施例の場合でツェナーダイオードがない場合の図である。この曲線部分は図１および図２の右上端の曲線部分Ｂである。
【００２０】
同図（ａ）の曲線部分では、そもそも、電界が集中し易いが、さらにツェナーダイオードを形成することにより、電位分布がＦ部のように不均一となり、耐圧の低下を引き起こす。
一方、同図（ｂ）の曲線部分では、電界の集中しやすい曲線部分には、ツェナーダイオードを形成しないため、この箇所では、等電位線は均等に形成され、安定した耐圧を得ることが可能となる。
【００２１】
ところで、図１の傾斜部分Ａに形成されたツェナーダイオードのｐｎ接合面７が、図４のように、高耐圧接合終端構造上部の表面構造３に対して不等距離（表面構造３の長手方向に対して不平行）に形成されると、ツェナーダイオードに逆バイアスが印加された場合、等電位線１２が乱れ、この部分で耐圧の低下が生じてしまう。これを解決する方法をつぎに説明する。
【００２２】
図３は、この発明の第３実施例の半導体装置の要部平面図である。この図は、図２の傾斜部分Ａの薄膜層４を示し、図２との違いは、この箇所に形成されるツェナーダイオードのｐｎ接合面８を、第１、第２基準回路形成領域と等距離となるように形成する点である。つまり、長手方向に平行になるようにｐｎ接合面８を形成することで、等電位線１１が長手方向に平行に形成される。
【００２３】
このように、等電位線１１を高耐圧接合終端構造上部の表面構造３の長手方向に対して平行にすることにより、傾斜部分Ａの薄膜層４での耐圧低下を防止することができる。
【００２４】
【発明の効果】
この発明によれば、高耐圧ＩＣ（ＨＶＩＣ）の高耐圧接合終端構造（ＨＶＪＴ）上部の表面構造を、ツェナーダイオードを形成した帯状の薄膜層とすることで、従来構造よりも狭い高耐圧接合終端構造幅で高耐圧化が可能となり、チップコストを低減できる。さらに、傾斜領域のツェナーダイオードのｐｎ接合面が第１、第２半導体領域の端部に対して平行であることにより、等電位線が平行になり、傾斜部分での耐圧低下を防止することができる。また、抵抗性窒化膜を使用しないため、抵抗性窒化膜の酸化による耐圧の低下が起こらず、長期間の信頼性を確保することができる。
【図面の簡単な説明】
【図１】 この発明の第１実施例の半導体装置の要部平面図
【図２】 この発明の第２実施例の半導体装置の要部平面図
【図３】 この発明の第３実施例の半導体装置の要部平面図
【図４】 ツェナーダイオードを薄膜層の傾斜部分に形成した場合の等電位線図
【図５】 Ｄｏｕｂｌｅ ＲＥＳＵＲＦ構造と抵抗性フィールドプレート構造を組み合わせた高耐圧接合終端構造であり、（ａ）は要部断面図、（ｂ）は電位分布図
【図６】 従来の高耐圧ＩＣの高耐圧接合終端構造（ＨＶＪＴ）の平面図
【図７】 曲線部分の等電位線を表した図であり、（ａ）は第１実施例の場合で、ツェナーダイオードがある場合の図、（ｂ）は第２実施例の場合で、ツェナーダイオードがない場合の図
【符号の説明】
１ 第１基準回路形成領域
２ 第２基準回路形成領域
３ 高耐圧接合終端構造上部の表面構造
４ 薄膜層
５ 高耐圧ＮＭＯＳ
６ 高耐圧ＰＭＯＳ
７、８ ｐｎ接合面
１１、１２ 等電位線
Ａ 傾斜部分
Ｂ 曲線部分
Ｃ 直線部分
ｐ ｐ型薄膜層
ｎ ｎ型薄膜層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a high voltage IC (HVIC) used for control drive of a power device.
[0002]
[Prior art]
FIG. 5 shows a high voltage junction termination structure in which a double RESURF structure and a resistive field plate structure are combined. FIG. 5 (a) is a cross-sectional view of the main part and FIG. 5 (b) is a potential distribution diagram. This high withstand voltage junction termination structure is a typical withstand voltage structure of a high withstand voltage IC.
[0003]
In FIG. 5A, an N well region 34 is provided in the surface layer of a p substrate 35a. A high potential region 33, a low potential region 37, and a Poffset region 39 are formed on the surface layer of the N well region 34, respectively. A high potential side electrode 32 and a low potential side electrode 38 are formed on the high potential region 33 and the low potential region 37, respectively, and a high resistivity resistance is formed on the insulating oxide film 41 formed on the p substrate 35. A thin film resistance layer 40 which is a field plate is formed, and the high potential side electrode 32 and the low potential side electrode 38 are electrically connected by the thin film resistance layer 40. Further, the low potential side electrode 38 and the back surface side electrode 36 are electrically connected at the terminal portion of the p substrate 35. The thin-film resistance layer 40 has a surface structure above the high voltage junction termination structure. Reference numeral 35a denotes a p substrate layer.
[0004]
In FIG. 5B, when the positive potential VS is applied to the high potential side electrode 32 with the low potential side electrode 38 as a reference (for example, GND), the potential distribution is greatly distorted near both ends of the resistive field plate 40. The electric field is concentrated. For this reason, the withstand voltage decreases at this point.
FIG. 6 is a plan view of a high voltage junction termination structure (HVJT) of a high voltage IC as disclosed in JP-A-9-55498. This high voltage junction termination structure (HVJT) is an example in which a resistive field plate 40 as shown in FIG. 5 is applied to the surface.
[0005]
The first reference circuit formation region 51 and the second reference circuit formation region 52 are regions in which integrated circuits having different potentials as reference potentials are formed. For example, the first reference circuit formation region 51 is a region where an integrated circuit having GND as a reference potential is formed, and the second reference circuit formation region 52 is an integrated circuit having a potential varying from 0 to 1200V as a reference. Is a region in which they are integrated and formed. The resistive field plate 54 (corresponding to 40 in FIG. 5) is provided between the first reference circuit formation region 51 and the second reference circuit formation region 52, and the first reference circuit formation region 51 and the second reference circuit formation region 51 The two reference circuit formation regions 52 are separated in terms of potential. In the figure, reference numeral 53 denotes a surface structure above the high voltage junction termination structure, 55 denotes a high voltage NMOS, and 56 denotes a high voltage PMOS.
[0006]
[Problems to be solved by the invention]
The potential distribution is greatly distorted in the vicinity of both ends of this resistive field plate 54 (in the vicinity of the portion connected to the first reference circuit forming region 51 and the second reference circuit forming region 52) (as shown in FIG. 5B). The electric field concentrates and the withstand voltage decreases at this point. Increasing the width of the resistive field plate 54 to alleviate this electric field concentration increases the chip size and increases the chip cost.
[0007]
An object of the present invention is to solve the above-mentioned problems, such as a high breakdown voltage IC having a high breakdown voltage junction termination structure that can increase the breakdown voltage, suppress the chip cost, and ensure long-term reliability. It is to provide a semiconductor device.
[0008]
[Means for Solving the Problems]
To achieve the above object, a first electrode connected to a first semiconductor region formed in a semiconductor substrate, and the semiconductor surrounding the first semiconductor region having a potential different from that of the first semiconductor region as a reference potential In a semiconductor device having a second semiconductor region formed in a substrate and a second electrode connected to the second semiconductor region, both ends are electrically connected to the first electrode and the second electrode on the semiconductor substrate, respectively. And a spiral band-shaped thin film layer surrounding the first electrode is formed, and the thin film layer includes an equidistant region formed parallel to the end portions of the first and second semiconductor regions, 1 and an inclined region formed to be inclined with respect to an end portion of the second semiconductor region, a Zener diode is formed in at least the inclined region of the thin film layer, and a pn junction surface of the Zener diode in the inclined region Is the first and second semiconductor areas And it is parallel to the end.
[0009]
[0010]
The first semiconductor region is a first integrated circuit formation region, the second semiconductor region is a second integrated circuit formation region, and the thin film layer is a potential between the first integrated circuit formation region and the second integrated circuit formation region. The surface structure of the upper portion of the high-voltage junction termination structure for isolating them may be good.
The equidistant region of the thin film layer may have a curved portion or a straight portion .
The curved portion or linear portion of the equidistant regions have good if not form a Zener diode.
[0011]
As this, the thin film layer constituting the high voltage junction terminating structure top surface structure, to form a Zener diode in which a plurality of serially connected, by using a uniform partial pressure of the Zener diode, uniform potential Distribution is obtained.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a plan view of an essential part of a semiconductor device according to a first embodiment of the present invention. This figure is a plan view of the main part of the high voltage IC. The region where the high breakdown voltage IC is formed includes a first reference circuit formation region 1 and a second reference circuit formation region 2 and a plurality of Zener diodes (potentially separating the reference circuit formation regions 1 and 2). a thin film layer 4 formed with a p-type thin film layer represented by p and an n-type thin film layer represented by n). The Zener diode formed in the thin film layer 4 is a straight line portion that is equidistant from the curve portion B where the high breakdown voltage NMOS 5 and the high breakdown voltage PMOS 6 are provided or the corner portion, and the reference circuit formation regions 1 and 2. Although a Zener diode is also formed in the inclined portion A, it is omitted because the figure becomes complicated. This thin film layer 4 is the surface structure 3 above the high-voltage junction termination structure, and the first and second reference circuits, which are integrated circuits, are formed in the first and second reference circuit forming regions 1 and 2, respectively. Is done.
[0013]
Of course, a Zener diode may be formed over the entire thin film layer by providing an inclination with respect to the first and second reference circuit formation regions as a whole between both ends of the strip-shaped thin film layer 4.
This embodiment can be designed more easily than a case where the thin film layer 4 is formed with an overall inclination between both ends. Overall compared to that with a tilt, the potential distribution in the direction (between the first reference circuit forming region and the second reference circuit forming region) perpendicular to the straight line portion in the linear portion becomes insufficient, breakdown voltage is small. However, if the inclination angle of the inclined portion A is made sufficiently small and the inclined portion is lengthened , the potential fluctuation between the first reference circuit forming region and the second reference circuit forming region is reduced, so that the entire portion is inclined. It becomes possible to make the pressure resistance close.
[0014]
In this high voltage IC, for example, if the second reference circuit formation region 2 is set to a high potential, the low potential signal of the first reference circuit formed in the first reference circuit formation region 1 on the low potential side and the high potential side The high potential signal of the second reference circuit is exchanged via the high breakdown voltage NMOS 5 (n channel MOSFET) and the high breakdown voltage PMOS 6 (p channel MOSFET).
[0015]
In order to ensure the withstand voltage of the second reference circuit forming region 2 having a high potential, the thin film layer 4 which is the surface structure 3 above the high withstand voltage junction termination structure is connected to the first reference circuit forming region 1 and the second reference circuit. Provided between the circuit formation regions 2. The thin film layer 4 has a surface structure 4 on the upper portion of the high withstand voltage junction termination structure, in which a plurality of Zener diodes are formed in series, instead of the resistive field plate 54 shown in FIG.
[0016]
In the thin film layer 4 formed of this Zener diode, since the breakdown voltage of each Zener diode is equal, the potential distribution in the longitudinal direction of the surface structure 3 above the high-breakdown junction termination structure is equalized. The potential distribution in the orthogonal direction is also equalized. That is, the potential distribution between the first and second reference circuit regions is equalized. In addition, since the voltage between the first and second reference circuit forming regions 1 and 2 is maintained at the reverse breakdown voltage of the Zener diode, a relatively large leakage current that flows in the case of the resistive field plate does not flow. Is prevented.
[0017]
In addition, by providing one or a plurality of inclined portions A with the thin film layer 4 inclined with respect to the longitudinal direction of the surface structure 3 above the high-voltage junction termination structure, the required number of thin film layers can be easily provided. Can be formed.
In FIG. 1, compared with the conventional structure of FIG. 6, the width of the high voltage junction termination structure can be narrowed. As a result, the chip size is reduced and the chip cost can be suppressed. In addition, since a resistive nitride film (resistive field plate) is not used, the breakdown voltage does not decrease due to oxidation of the resistive nitride film, and long-term reliability can be ensured.
[0018]
FIG. 2 is a plan view of an essential part of a semiconductor device according to a second embodiment of the present invention. In the case of this structure, the Zener diode is disposed in the thin film layer of the inclined portion A, and in the straight portion C that is equidistant from the first and second reference circuit forming regions 1 and 2 and the curved portion B, Do not arrange Zener diodes.
In this case, a Zener diode is not formed in a portion having a curvature that tends to concentrate an electric field, such as the vicinity of the high breakdown voltage NMOS 5 and the high breakdown voltage PMOS 6 formed in the curved portion B, and the upper portion of the high breakdown voltage junction termination structure is not formed. In this structure, a Zener diode is not formed at a location that is equidistant from the surface structure 3. For this reason, in the thin film layer 4 without the Zener diode (here, the n-type thin film layer), the potential drop is small and becomes almost equipotential, and the potential distribution in the direction orthogonal thereto is made uniform. As a result, the breakdown voltage of the high breakdown voltage junction termination structure can be further increased as compared with the first embodiment.
[0019]
Next, the potential distribution with and without the Zener diode in the curve portion B will be described.
7A and 7B are diagrams showing equipotential lines in a curved portion. FIG. 7A shows the case of the first embodiment, where there is a Zener diode, and FIG. 7B shows the second embodiment. It is a figure in case there is no Zener diode. This curved portion is a curved portion B at the upper right end of FIGS.
[0020]
In the curve portion of FIG. 5A, the electric field tends to concentrate in the first place. However, by forming a Zener diode, the potential distribution becomes non-uniform as in the F portion, and the breakdown voltage is lowered.
On the other hand, in the curved portion of FIG. 5B, the Zener diode is not formed in the curved portion where the electric field is likely to concentrate. Therefore, equipotential lines are formed uniformly in this portion, and a stable breakdown voltage can be obtained. It becomes.
[0021]
Incidentally, the pn junction surface 7 of the Zener diode formed in the inclined portion A of FIG. 1 is unequal with respect to the surface structure 3 above the high-voltage junction termination structure as shown in FIG. 4 (the longitudinal direction of the surface structure 3). If the reverse bias is applied to the Zener diode, the equipotential line 12 is disturbed, and the breakdown voltage is lowered at this portion. A method for solving this will be described below.
[0022]
FIG. 3 is a plan view of an essential part of a semiconductor device according to a third embodiment of the present invention. This figure shows the thin film layer 4 of the inclined portion A of FIG. 2, and the difference from FIG. 2 is that the pn junction surface 8 of the Zener diode formed at this location is the first and second reference circuit formation regions, etc. It is a point formed so as to be a distance. That is, by forming the pn junction surface 8 so as to be parallel to the longitudinal direction, the equipotential lines 11 are formed parallel to the longitudinal direction.
[0023]
Thus, by making the equipotential line 11 parallel to the longitudinal direction of the surface structure 3 above the high-breakdown-voltage junction termination structure, it is possible to prevent a decrease in breakdown voltage in the thin film layer 4 in the inclined portion A.
[0024]
【The invention's effect】
According to the present invention, the surface structure above the high voltage junction termination structure (HVJT) of the high voltage IC (HVIC) is a band-shaped thin film layer in which a Zener diode is formed, thereby making the high voltage junction termination narrower than the conventional structure. With the structure width, a high breakdown voltage can be achieved, and the chip cost can be reduced. Furthermore, since the pn junction surface of the Zener diode in the inclined region is parallel to the end portions of the first and second semiconductor regions, the equipotential lines are parallel to prevent the breakdown voltage from decreasing in the inclined portion. it can. In addition, since a resistive nitride film is not used, the breakdown voltage is not reduced by oxidation of the resistive nitride film, and long-term reliability can be ensured.
[Brief description of the drawings]
FIG. 1 is a fragmentary plan view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a fragmentary plan view of a semiconductor device according to a second embodiment of the present invention. FIG. 4 is an equipotential diagram when a Zener diode is formed on an inclined portion of a thin film layer. FIG. 5 is a high voltage junction termination structure combining a Double RESURF structure and a resistive field plate structure. Yes, (a) is a cross-sectional view of the main part, (b) is a potential distribution diagram [Fig. 6] Plan view of a conventional high voltage IC high voltage junction termination structure (HVJT) [Fig. FIG. 7A is a diagram in the case of the first embodiment, where there is a Zener diode, and FIG. 9B is a diagram in the case of the second embodiment, where there is no Zener diode.
1 First reference circuit formation region
2 Second reference circuit formation region
3 Surface structure above the high voltage junction termination structure
4 Thin film layer
5 High voltage NMOS
6 High voltage PMOS
7, 8 pn junction surface 11, 12 equipotential lines
A Inclined part
B Curve part
C Straight line part
p p-type thin film layer
n n-type thin film layer

Claims (4)

半導体基板内に形成された第１半導体領域に接続された第１電極と、第１半導体領域と異なる電位を基準電位とする前記第１半導体領域を囲む前記半導体基板内に形成された第２半導体領域と、該第２半導体領域に接続された第２電極とを有する半導体装置において、前記半導体基板上に両端が前記第１電極と前記第２電極にそれぞれ電気的に接続され、第１電極を囲む渦巻状の帯状の薄膜層が形成され、該薄膜層は、第１、第２半導体領域の端部に対して平行に形成される等距離領域と、第１、第２半導体領域の端部に対して傾斜して形成される傾斜領域とで構成され、該薄膜層の少なくとも傾斜領域にはツェナーダイオードが形成され、該傾斜領域のツェナーダイオードのｐｎ接合面が第１、第２半導体領域の端部に対して平行であることを特徴とする半導体装置。A first electrode connected to the first semiconductor region formed in the semiconductor substrate and a second semiconductor formed in the semiconductor substrate surrounding the first semiconductor region having a potential different from the first semiconductor region as a reference potential In a semiconductor device having a region and a second electrode connected to the second semiconductor region, both ends on the semiconductor substrate are electrically connected to the first electrode and the second electrode, respectively. a spiral strip-like thin layer surrounding formation, thin film layer, first, the equidistant region formed parallel to the end portion of the second semiconductor region, a first end of the second semiconductor region is composed of an inclined region formed inclined with respect to the parts, a Zener diode is formed on at least the inclined region of the thin film layer, pn junction surface is first Zener diode of the inclined region, second semiconductor region this is parallel to the end Wherein a. 前記第１半導体領域が第１集積回路形成領域であり、前記第２半導体領域が第２集積回路形成領域であり、前記薄膜層が前記第１集積回路形成領域と第２集積回路形成領域を電位的に分離するための高耐圧接合終端構造上部の表面構造であることを特徴とする請求項１に記載の半導体装置。 The first semiconductor region is a first integrated circuit formation region, the second semiconductor region is a second integrated circuit formation region, and the thin film layer is a potential between the first integrated circuit formation region and the second integrated circuit formation region. The semiconductor device according to claim 1, wherein the semiconductor device has a surface structure on an upper portion of a high voltage junction termination structure for isolating . 前記薄膜層の等距離領域は、曲線部分または直線部分が形成されていることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1 , wherein the equidistant region of the thin film layer is formed with a curved portion or a straight portion . 前記等距離領域の曲線部分または直線部分にはツェナーダイオードを形成しないことを特徴とする請求項３に記載の半導体装置。4. The semiconductor device according to claim 3 , wherein a Zener diode is not formed in a curved portion or a straight portion of the equidistant region.
JP2000306206A 2000-10-05 2000-10-05 Semiconductor device Expired - Lifetime JP4547790B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000306206A JP4547790B2 (en) 2000-10-05 2000-10-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000306206A JP4547790B2 (en) 2000-10-05 2000-10-05 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2002118230A JP2002118230A (en) 2002-04-19
JP4547790B2 true JP4547790B2 (en) 2010-09-22

Family

ID=18786934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000306206A Expired - Lifetime JP4547790B2 (en) 2000-10-05 2000-10-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4547790B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7183626B2 (en) * 2004-11-17 2007-02-27 International Rectifier Corporation Passivation structure with voltage equalizing loops
DE102007045185A1 (en) * 2007-09-21 2009-04-02 Robert Bosch Gmbh Semiconductor device and method for its production
JP2017045969A (en) * 2015-08-28 2017-03-02 株式会社タムラ製作所 Schottky barrier diode
US11063116B2 (en) 2016-09-13 2021-07-13 Mitsubishi Electric Corporation Semiconductor device
US10734476B2 (en) 2017-11-14 2020-08-04 Stmicroelectronics S.R.L. Integrated electronic device including an edge termination structure with a plurality of diode chains

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677470A (en) * 1992-06-24 1994-03-18 Toshiba Corp Semiconductor device
EP1032046A1 (en) * 1999-02-01 2000-08-30 Fuji Electric Co., Ltd. Semiconductor device having a thin film field-shaping structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677470A (en) * 1992-06-24 1994-03-18 Toshiba Corp Semiconductor device
EP1032046A1 (en) * 1999-02-01 2000-08-30 Fuji Electric Co., Ltd. Semiconductor device having a thin film field-shaping structure

Also Published As

Publication number Publication date
JP2002118230A (en) 2002-04-19

Similar Documents

Publication Publication Date Title
JP5589052B2 (en) Semiconductor device
JP5655255B2 (en) Power integrated circuit device
JP5585593B2 (en) Semiconductor device
JP2000357796A (en) Edge termination of high-voltage semiconductor device by resistor-type voltage divider
US10438944B2 (en) Semiconductor device having ESD element
US9620595B2 (en) Semiconductor device
JP2009065026A (en) Switching device of electric circuit
TW201924174A (en) Low capacitance transient voltage suppressor
US7598587B2 (en) Semiconductor device
JP4971848B2 (en) Power MOS circuit that achieves both low switching loss and low noise
US10163890B2 (en) Semiconductor device
JP4839225B2 (en) SOI semiconductor device with high dielectric strength
JP2004356622A (en) Junction type electronic component and integrated electric power equipment comprising electronic component
US10396071B2 (en) Semiconductor device having a sense diode portion
US20100127259A1 (en) Semiconductor device
US11469316B2 (en) Semiconductor device
JP4547790B2 (en) Semiconductor device
US20040012052A1 (en) Semiconductor device
US6448587B1 (en) Circuit incorporated IGBT and power conversion device using the same
JP4645069B2 (en) Semiconductor device
JP5080056B2 (en) Semiconductor device for electrostatic protection
US10811529B2 (en) Transistor device with gate resistor
JP4815740B2 (en) Semiconductor device and level shift circuit using the same
JP2008270367A (en) Semiconductor device
US9500805B2 (en) Optical waveguide to be carried by a semiconductor material including a plurality of parallel strips of alternating conductivity types and related methods

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060703

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060704

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061115

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20081216

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090219

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100105

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100107

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100308

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100615

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100628

R150 Certificate of patent or registration of utility model

Ref document number: 4547790

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130716

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130716

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130716

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250