JP4815740B2 - Semiconductor device and level shift circuit using the same - Google Patents

Description

  According to the present invention, the first conductivity type semiconductor region and the second conductivity type semiconductor region are formed adjacent to each other, so that when the semiconductor device is turned off, the first conductivity type semiconductor region and the second conductivity type semiconductor region are formed. The present invention relates to a high withstand voltage semiconductor device that is substantially completely depleted to ensure a withstand voltage. The structure in which the first conductive type semiconductor region and the second conductive type semiconductor region are formed adjacent to each other can be seen in, for example, a double resurf structure or a super junction structure. The present invention aims to further improve the breakdown voltage by substantially suppressing the collapse of the charge balance due to the Kirk effect that occurs in this type of semiconductor device.

A semiconductor device is known in which a first conductive type semiconductor region and a second conductive type semiconductor region are formed adjacent to each other, and when the semiconductor device is turned off, these regions are substantially completely depleted to ensure a breakdown voltage. . For example, Patent Document 1 discloses a semiconductor device in which a double resurf structure is formed in a drift region to increase the breakdown voltage.
Japanese Patent Laid-Open No. 6-120510 (see FIG. 1 of that gazette)

The high breakdown voltage semiconductor device having a double resurf structure shown in FIG. 9 is formed in a p ⁻ type semiconductor substrate 222, an n type drift layer 224 formed on the semiconductor substrate 222, and the drift layer 224. A p-type body region 232, an n ⁺ -type source region 234 formed in the body region 232 and separated from the drift layer 224 by the body region 232, and the source region 234 and the drift layer 224 are separated from each other. A gate electrode 242 facing the body region 232 with a gate insulating film 244 interposed therebetween, a p ⁺ -type body contact region 236 formed in the body region 232, and an n ⁺ formed in the drift layer 224 A drain region 252 of a type, a source electrode 246 connected to the source region 234 and the body contact region 236, A drain electrode 253 connected to the drain region 252 is provided. A p-type top region 262 extending from the body region 232 toward the drain region 252 is formed on the surface of the semiconductor region. The p-type top region 262 can also be viewed as a part of the p-type body region 232. The source electrode 246 maintains the source region 234, the body contact region 236, and the body region 232 at the same potential. Part of body region 232 is connected to semiconductor substrate 222, and the potential of semiconductor substrate 222 is also maintained at the same potential as source region 234, body contact region 236, and body region 232. Incidentally, reference numeral 272 shown in the figure is a field oxide film.

When the semiconductor device is turned off, a depletion layer is formed from each of the pn junction interface between the p-type top region 262 and the n-type drift layer 224 and the pn junction interface between the p ⁻ -type semiconductor substrate 222 and the n-type drift layer 224. spread. When the film thickness (L2) of the drift layer 224 and the impurity concentration thereof are set to appropriate values with respect to the film thickness (L1) of the top region 262 and its impurity concentration, the semiconductor device is turned off in the top region 262 and the drift layer 224. Sometimes it is substantially fully depleted, and a high off breakdown voltage can be realized by the fully depleted layer.
FIG. 10 shows the relationship between the charge amount of the drift layer 224 and the breakdown voltage. The charge amount is a product of the thickness (L2) of the drift layer 224 and its impurity concentration. FIG. 15 shows the relationship between the charge amount of the drift layer 224 and the off breakdown voltage when the semiconductor device is turned off. When the charge amount of the drift layer 224 is set to NA, the off breakdown voltage shows the maximum value. When the charge amount is smaller than NA, the electric field concentrates on the drain region 252 side, so that the off breakdown voltage is reduced. When the charge amount is larger than NA, the electric field is concentrated on the source region 234 side, so that the off breakdown voltage is lowered.

In the case of a high breakdown voltage semiconductor device, an on breakdown voltage is important as well as an off breakdown voltage. The on breakdown voltage is a drain voltage at which the drain current increases rapidly when the semiconductor device is in an on state.
When a positive voltage is applied to the drain electrode 253 and the gate electrode 242 of the semiconductor device illustrated in FIG. 9 and the source electrode 246 is set to 0 V, an n-type inversion layer is formed in the body region 232 facing the gate electrode 242. Electrons flow from the source region 234 to the drift layer 224 via the inversion layer, and further flow to the drain region 252. This state is the on state of the semiconductor device. At this time, a phenomenon occurs in which charge balance in the drift layer 224 is lost due to electrons flowing in the drift layer 224. This is because the positive space charge held by the n-type drift layer 224 is canceled by the flowing negative electrons, and the charge amount of the drift layer 224 is apparently reduced (Kirk effect). .
Therefore, as shown in FIG. 16 in FIG. 10, the relationship between the charge amount of the semiconductor device and the ON breakdown voltage shifts to the right as compared to the OFF breakdown voltage. Considering only the ON breakdown voltage, the maximum value is obtained when the charge amount of the drift layer 224 is NC. However, in a high breakdown voltage semiconductor device, it is necessary to ensure both off breakdown voltage and ON breakdown voltage in a balanced manner.
For this reason, in this type of high breakdown voltage semiconductor device, the charge amount of the drift layer 224 is set to NB to ensure an off breakdown voltage and an on breakdown voltage equal to or higher than VB.

As apparent from FIG. 10, in this type of conventional high breakdown voltage semiconductor device, the charge amount of the drift layer 224 is set at the sacrifice of the highest values of the off breakdown voltage and the on breakdown voltage. That is, if only the off-breakdown voltage is considered, a higher off-breakdown voltage can be realized, but the VB off-breakdown voltage is lower than that. If only the on-breakdown voltage is considered, a higher on-breakdown voltage can be realized, but a compromise is made with a lower on-breakdown voltage of VB.
In the present invention, the charge amount NA of the drift layer 224 that achieves the highest off-breakdown voltage and the charge amount NC of the drift layer 224 that achieves the highest on-breakdown voltage are brought close to each other. Provide technology that can be easily approached. If the relationship illustrated in FIG. 15 illustrated in FIG. 10 and the relationship illustrated in FIG. 16 can be made closer, the charge amount that the drift layer 224 is charge balanced when the semiconductor device is in the off state and the drift layer 224 is charged when the semiconductor device is in the on state. The difference between the charge amount to be balanced can be reduced, and an off withstand voltage close to the maximum off withstand voltage and an on withstand voltage close to the maximum on withstand voltage can be realized. Off-breakdown voltage and maximum on-breakdown voltage can be obtained at the same time.The present invention pays attention to the fact that useful results can be obtained even if they are not matched as long as they can be made closer than before).

The semiconductor device of the present invention can be realized by improving a conventionally known so-called double resurf structure. By using the top region of the double RESURF structure as a carrier flow path, the semiconductor device of the present invention can be realized.
A semiconductor device of this type includes a second conductivity type drift layer, a first body type first body region formed in the drift layer, a first body region, and a drift layer. A first source region of a second conductivity type separated by a first body region, and a first body region that separates the first source region and the drift layer from each other with a first gate insulating film therebetween. A gate electrode; a first drain region of a second conductivity type formed in the drift layer; a second source region of a first conductivity type formed at a position away from the first body region in the drift layer; A second gate electrode facing the drift layer separating the second source region and the first body region via a second gate insulating film, and a first conductivity type formed in the first body region A second drain region and a first source A first electrode connected to the drain region, a second electrode connected to the first drain region, a third electrode connected to the second source region, and a second electrode connected to the second drain region. 4 electrodes.

The second drain region of the first conductivity type formed in the first body region can be used as a body contact region of the first body region.
It is preferable that a second body region of a second conductivity type surrounding the second source region is formed in the drift layer. The drift layer and the second body region have the same conductivity type, and the second body region that can be distinguished from the drift layer may not exist. The second body region is not essential. If the impurity concentration suitable for inversion when the ON potential is applied to the second gate electrode is different from the impurity concentration of the drift layer, the impurity concentration is different from that of the drift layer and suitable for inversion. It is preferable to form a second body region having an impurity concentration.
The drift region has preferably that the top region of the first conductivity type extending toward the second body region from the first body region along a surface of the drift region is formed. If top-region is formed, it is possible to adjust the breakdown voltage by adjusting the length of extension of the top region.

  In the semiconductor device having the above structure, a first MOSFET is formed by the first source region, the first body region, the drift layer, the first drain region, and the first gate electrode, and the second source region and the drift layer (second body region). The second MOSFET is formed by the second body region), the first body region (including the top region when the top region is present), the second drain region, and the second gate electrode. In the second MOSFET, the drift layer (the second body region if the second body region is present) functions as the body region, and the first body region (including the top region when the top region is present) is provided. Functions as a drift layer.

When the first MOSFET and the second MOSFET are turned on, carriers of the second conductivity type flow in the drift layer (the drift layer of the first MOSFET), and the first body region (the region including the top region when the top region exists) The first conductivity type carriers flow in the 2MOSFET drift layer). That is, the first body region (the top region when a top region is present) becomes the first conductivity type semiconductor region where the first conductivity type carriers flow, and the drift layer becomes the second conductivity type semiconductor region where the second conductivity type carriers flow. It becomes.
In the above semiconductor device, when a positive voltage is not applied to the first gate electrode and a positive voltage higher than the positive voltage applied to the second source electrode is applied to the second gate electrode, the semiconductor device is turned off. In this case, carriers do not flow in either the drift layer or the first body region (the top region when the top region is present). At this time, the depletion layer extends from the pn junction interface between the first body region (the top region when a top region is present) and the drift layer. As a result, the first body region (the top region when a top region is present) and the drift layer are substantially completely depleted, and a high breakdown voltage is secured by securing a potential in the depletion layer.

On the other hand, when a positive voltage is applied to the first gate electrode and a voltage equal to or lower than the positive voltage applied to the second source electrode is applied to the second gate electrode, the semiconductor device is turned on. An inversion layer is formed in the first body region facing the first gate electrode, and the inversion layer is also formed in the drift layer facing the second gate electrode (the second body region when the second body region is present). Is formed. Then, the second conductivity type carriers that flow from the drift layer to the first drain region via the inversion layer in the first body flow region from the first source region, and the drift layer (the second body region is formed from the second source region). If present, the first conductivity type carriers flowing from the first body region (the top region when the top region is present) to the second drain region via the inversion layer of the second body region simultaneously flow. Will do.
The second conductivity type carriers flowing in the drift layer cause a Kirk effect in the drift layer, which reduces the apparent charge amount of the drift layer. However, the first body region (the top region when the top region is present) is reduced. The Kirk effect is also generated in the first body region (top region) by the flowing first conductivity type conduction carrier, and the apparent charge amount of the first body region (top region when the top region is present) is reduced. . Since the apparent charge amount of both semiconductor regions is reduced, the charge balance is prevented from being lost. The on-breakdown voltage is prevented from decreasing when the semiconductor device is on.
In the high breakdown voltage semiconductor device described above, a part of the first conductivity type carrier that flows in the first conductivity type semiconductor region (which is the first body region and includes the top region when the top region is present). Is injected into the second conductivity type semiconductor region (drift layer) to cause conductivity modulation. The withstand voltage is improved and the on-resistance is also reduced.

All of the first electrode to the fourth electrode may be independent electrodes. In this case, the semiconductor device includes two pairs of source and drain electrodes.
The first electrode and the fourth electrode may be a common electrode. In this case, the second drain region formed in the first body region becomes a body contact region of the first body region.
Further, the second electrode and the third electrode may be a common electrode.

  The drift layer may be stacked on the first conductivity type semiconductor substrate, or may be stacked on an insulating substrate (for example, an SOI substrate). When the SOI substrate is used, in addition to the effects inherent in the present invention, it is possible to obtain effects such as reduction of parasitic capacitance, improvement of operating speed, suppression of leakage current when a surge voltage is generated, and the like. Even if the SOI substrate is used, a part of the first conductivity type carriers flowing in the first conductivity type semiconductor region is injected into the second conductivity type semiconductor region, and conductivity modulation occurs. The withstand voltage is improved and the on-resistance is also reduced.

Any of the semiconductor devices described above is preferably used for the level shift circuit.
In a semiconductor device used for a level shift circuit, a high voltage is easily applied between main electrodes in an on state. Therefore, in the on state of the semiconductor device, the charge balance in the drift region is lost and the on-breakdown voltage is liable to occur.
The semiconductor device of the present invention solves the above-described problems, and is extremely effective when applied to a level shift circuit.

  According to the present invention, when the semiconductor device is turned on, it is possible to suppress the charge balance from being lost in the drift region for ensuring the breakdown voltage. The breakdown voltage of the semiconductor device can be improved.

First, the main features of the embodiment are listed.
First Embodiment A first conductivity type semiconductor device (MOSFET) and a second conductivity type semiconductor device (MOSFET) are formed in parallel in the same element. Each drift region is adjacent. The body region (the top region when the top region is formed) of the second conductivity type semiconductor device functions as a drift region of the first conductivity type semiconductor device.

Example 1
FIG. 1 is a cross-sectional view of a main part of the semiconductor device of Example 1. This semiconductor device is a lateral high breakdown voltage semiconductor device having a so-called double resurf structure in a drift region.
In the semiconductor device shown in FIG. 1, an n-type silicon single crystal drift layer 24 is formed, for example, by epitaxial growth on a semiconductor substrate 22 made of p ⁻ type silicon single crystal. A p-type first body region 32 is formed in the drift layer 24 by, for example, an ion implantation method. An n ⁺ -type first source region 34 formed in the first body region 32 and separated from the drift layer 24 by the first body region 32 is formed by, for example, an ion implantation method.
A first gate electrode 42 is formed opposite to the first body region 32 that separates the first source region 34 and the drift layer 24 via a first gate insulating film 42. The first gate insulating film 42 is made of silicon oxide, and the gate electrode 42 is made of polysilicon. A p ⁺ -type body contact region 36 is formed in the first body region 32 by, for example, an ion implantation method. A source electrode 46 made of aluminum or the like is connected to the first source region 34 and the body contact region 36.
An n ⁺ -type drain region 52 is formed in the drift layer 24 at a position away from the first body region 32 by, for example, an ion implantation method. The drain region 52 is made of aluminum or the like. A drain electrode 53 is connected. An n ⁻ -type second body region 54 is formed so as to surround the drain region 52 by, for example, an ion implantation method. A p ⁺ -type second source region 56 is formed in the second body region 54 by, for example, an ion implantation method, and a second source electrode 57 made of aluminum or the like is connected to the second source region 56.
The second body region 54 is a region having the same conductivity type as the drift region 24 and the drain region 52 and a low impurity concentration. The second body region 54 relaxes the electric field concentrated in the vicinity of the drain region 52 and adjusts the threshold value of the second gate electrode 84 described later.

A p-type top region 62 extending along the surface of the drift layer 24 from the first body region 32 toward the second body region 54 is formed by, for example, an ion implantation method. A field oxide film 72 made of silicon oxide is formed on top region 62. The top region 62 may be in contact with the second body region 54 or may be separated. The top region 62 has the same conductivity type as that of the first body region 32, and a part of the first body region 32 can be seen if the way of viewing is changed.
A second gate electrode 84 is opposed to the drift layer 24 and the second body region 54 that separate the second source region 56 and the top region 62 with a second gate insulating film 82 interposed therebetween. The second gate insulating film 82 is made of silicon oxide, and the second gate electrode 84 is made of polysilicon.
FIG. 2 is a plan view corresponding to a section taken along line II-II in FIG. It can be seen that the top region 62 is formed over the drift layer 24. An n type drift layer 24 is formed adjacent to the p ⁻ type semiconductor substrate 22 and the p type top region 62. This region is called a drift region.
Note that the charge amount of the drift layer 24 and the top region 62 is preferably set to a charge amount that substantially completely depletes the drift region when the high breakdown voltage semiconductor device is turned off. In this embodiment, the thickness of the top region 62 is 4 μm and the impurity concentration thereof is 5 × 10 ¹⁵ cm ⁻³ , the thickness of the drift layer 24 is 28 μm and the impurity concentration thereof is 8 × 10 ¹⁴ cm ⁻³ . The impurity concentration of the semiconductor substrate 22 is 8 × 10 ¹³ cm ⁻³ .
By the first source electrode 46, the first source region 34, the body contact region 36, and the body region 32 are maintained at the same potential. A part of the body region 32 is connected to the semiconductor substrate 22, and the potential of the semiconductor substrate 22 is also maintained at the same potential as the first source region 34, the body contact region 36, and the body region 32.

First, the case where the high voltage semiconductor device is in an off state will be described.
The source electrode 46 and the first gate electrode 42 are at 0 V, and a positive voltage is applied to the drain electrode 53 and the second source electrode 57. At this time, a voltage equal to or higher than the positive voltage applied to the second source electrode 57 is applied to the second gate electrode 84. In this state, the inversion layer is not formed in the first body region 32 facing the first gate electrode 42, and the inversion layer is also formed in the drift layer 24 and the second body region 54 facing the second gate electrode 84. Not formed. Conductive carriers do not flow in the drift region. A depletion layer extends from the pn junction interface between the p ^- type top region 62 and the n-type drift layer 24 and from the pn junction interface between the p ⁻ -type semiconductor substrate 22 and the drift layer 24. This depletion layer substantially completely depletes the top region 62 and the drift layer 24 and holds the potential applied between the first source electrode 46 and the drain electrode 53.

Next, the case where this semiconductor device is in an on state will be described.
First, when a positive voltage is applied to the first gate electrode 42, the semiconductor device is turned on. As a result, an n-type inversion layer is formed in the first body region 32 facing the first gate electrode 42. Electrons are injected from the first source region 34 into the drift layer 24 through this inversion layer. The electrons flow from the drift layer 24 to the drain electrode 53 via the second body region 54 and the drain region 52.
The positive space charge held in the drift layer 24 is canceled by the electron flow. Therefore, the charge amount of the drift layer 24 is apparently reduced. When the charge amount of the drift layer 24 decreases, the charge balance is lost due to the relative relationship with the charge amount of the top region 62. When this charge balance is lost, the ON breakdown voltage of the semiconductor device is lowered.

In the semiconductor device shown in FIG. 1, when a potential that breaks the charge balance of the drift layer 24 is applied between the drain electrode 53 and the first source electrode 46, the second gate electrode 84 is more than the second source electrode 57. A small voltage (ON voltage) is applied. Alternatively, the second gate electrode 84 is turned on in synchronization with the turn-on of the first gate electrode 42 before a potential that causes the charge balance of the drift layer 24 to be lost is applied between the drain electrode 53 and the first source electrode 46. May be.
As a result, a p-type inversion layer is formed in the drift layer 24 and the second body region 54 facing the second gate electrode 84. Holes are injected from the second source region 56 into the top region 62 via the inversion layer. The holes flow from the top region 62 to the first source electrode 46 via the body contact region 36 in the first body region 32. Considering the flow of holes, the body contact region 36 can also be referred to as a second drain region.
The negative space charge held in the top region 62 is canceled by the flow of the holes. Therefore, the charge amount of the top region 62 is apparently reduced. As a result, the apparent charge amount of the top region 62 is reduced in response to the apparent charge amount of the drift layer 24, so that the charge balance between the drift layer 24 and the top region 62 is relatively lost. Is suppressed.

This can be understood as shown in FIG. Note that the difference between FIG. 3 and the conventional structure of FIG. 10 can be clearly understood.
FIG. 15 shown in FIG. 3 shows the relationship between the charge amount of the drift layer 24 and the off breakdown voltage when the semiconductor device is turned off. On the other hand, FIG. 12 shows the relationship between the charge amount of the drift layer 24 and the ON breakdown voltage when the semiconductor device of this embodiment is turned on.
As shown in FIG. 10, in the case of the conventional structure, since the apparent charge amount is reduced only in the drift layer 24, the illustration 16 showing the on-withstand voltage is greatly shifted to the right from the illustration 15 showing the off-withstand voltage. It was.
On the other hand, in the semiconductor device of the present embodiment, the apparent charge amount of the top region 62 is also reduced in response to the decrease in the apparent charge amount of the drift layer 24. Almost no shift from FIG. 15 shown. Therefore, when the charge amount of the drift layer 24 is set to ND, for example, the breakdown voltage of the semiconductor device is VD. It can be seen that the breakdown voltage is improved as compared with the VB of the conventional structure.
If the charge amount of the drift layer 24 is ND, it can be said that the drift region is substantially completely depleted when the semiconductor device is turned off.

In this embodiment, compared to the case of flowing only electrons as in the conventional structure, holes are also flowed in parallel, so the on-resistance is lowered.
A part of the holes flowing through the top region 62 is injected into the drift layer 24 and conductivity modulation occurs, so the on-resistance decreases.
It should be noted that the same effect can be obtained by forming an insulating layer on the bottom surface side of the drain layer 24 of this embodiment and using a so-called SOI substrate.
The first source electrode 46 is a common electrode for the first source region 34 and the body contact region 36, but different electrodes may be connected to the first source region 34 and the body contact region 36, respectively. . Further, the drain electrode 53 and the second source electrode 57 may be a common electrode.

Examples 2 to 4 will be described below. In addition, the same code | symbol may be attached | subjected to the component substantially the same as 1st Example, and description may be abbreviate | omitted.
(Second embodiment)
The semiconductor device according to the second embodiment includes a repetitive structure (so-called super junction structure) in which p-type semiconductor regions and n-type semiconductor regions are alternately formed in the drift region of the semiconductor device according to the first embodiment. It is.
FIG. 4 is a plan view of the main part of the high voltage semiconductor device of the second embodiment. In the first embodiment, the top region 62 is formed over the upper portion of the drift layer 24, but in this embodiment, the p-type p-type partial region 63 is alternately formed on the upper portion of the drift layer 24. ing. The repeating direction is a direction orthogonal to the direction between the main electrodes (in this example, the left-right direction on the paper).

The characteristics of this semiconductor device are easy to understand when viewed in cross-section in the film thickness direction of the semiconductor substrate. Along the repeated structure of the drift region, a cross-sectional view taken along arrow VV in the drawing corresponding to the drift layer 24 is shown in FIG. 5, and a cross-sectional view taken along arrow VI-VI in the drawing corresponding to the p-type partial region 63 is shown. As shown in FIG.
Comparing the cross-sectional views of FIGS. 5 and 6, the drift region of the semiconductor device of Example 2 is that the p-type partial region 63 and the n-type drift layer 24 are repeated in a multilayered manner along the repeating direction. I understand. 21 is a drain region, and 55 is a drain electrode. 58 is the second source region, and 59 is the second source electrode.
In this example, the p-type partial region 63 is not in contact with the semiconductor substrate 22. Unless the p-type partial region 63 is in contact with the semiconductor substrate 22, holes flowing in the p-type partial region 63 do not flow in the semiconductor substrate 22. Therefore, a so-called Kirk effect can be effectively generated in the p-type partial region 63.

  In the semiconductor device according to the second embodiment, the p-type partial region 63 and the drift layer 24 are repeated in a multilayer manner in the drift region. In addition, since the impurity concentration of the p-type partial region 63 and the drift layer 24 can be increased as the pitch width of the repetitive structure is narrowed, the on-resistance can be reduced.

The semiconductor device of the second embodiment is controlled to be turned on / off in the same procedure as the semiconductor device of the first embodiment. When the semiconductor device is on, electrons flow through the drift layer 24 and holes flow through the p-type partial region 63. Therefore, it is possible to suppress the charge balance from being lost in the on state of the semiconductor device.
Further, in this embodiment, compared to the case where only electrons are flowed as in the conventional structure, since the holes are also flowed in parallel, the on-resistance is lowered.
In the semiconductor device of this embodiment, a part of the holes flowing in the p-type partial region 63 is injected into the drift layer 24, and conductivity modulation can occur. On-resistance is reduced.
It should be noted that the same effect can be obtained by forming an insulating layer on the bottom surface side of the drain layer 24 of this embodiment and using a so-called SOI substrate. In this case, since the hole carriers flowing in the p-type partial region 63 can be prevented from flowing to the semiconductor substrate 22 by the insulating layer, the p-type partial region 63 is formed to extend to the bottom surface side of the drift layer 24. be able to. A higher breakdown voltage can be achieved in the drift region.

(Third embodiment)
FIG. 7 is a cross-sectional view of a main part of a vertical semiconductor device having a repeating structure in a drift region formed between main electrodes.
In the semiconductor device shown in FIG. 7, the n-type n-type partial region 124 and the p-type p-type partial region 122 in the drift region 126 are in a plane orthogonal to the direction between the main electrodes (in this example, the vertical direction in the drawing). It is formed repeatedly alternately. The n-type partial region 124 and the p-type partial region 122 of the drift region 126 are set with a charge amount that is substantially completely depleted when the semiconductor device is off.
A p-type first body region 132 is formed on the main surface side of drift region 126. An n ⁺ -type first source region 134 formed in the first body region 132 and separated from the n-type partial region 124 by the first body region 132 is formed. The first gate electrode 142 is opposed to the first body region 132 that separates the first source region 134 and the n-type partial region 132 with the first gate insulating film 144 interposed therebetween. A p ⁺ -type body contact region 136 is formed in the first body region 132, and the first source electrode 146 is connected to the body contact region 136 and the first source region 134.

An n ⁺ -type drain region 152 is formed in the n-type partial region 124 on the back surface side of the drift region 126, and the drain region 152 is connected to the drain electrode 153. An n ⁻ -type second body region 154 is formed so as to surround drain region 152. A p ⁺ -type second source region 156 is formed in the second body region 154, and the second source region 156 is connected to the second source electrode 157. A second gate electrode 184 faces the second body region 154 separating the second source region 156 and the p-type partial region 122 with the second gate insulating film 182 interposed therebetween.

First, the case where the semiconductor device is in an off state will be described.
The source electrode 146 and the first gate electrode 142 are 0 V, and a positive voltage is applied to the drain electrode 153 and the second source electrode 157. At this time, a voltage higher than the positive voltage applied to the second source electrode 157 is applied to the second gate electrode 184. In this state, the inversion layer is not formed in the first body region 132 facing the first gate electrode 142, and the inversion layer is not formed in the second body region 154 facing the second gate electrode 184. Conductive carriers do not flow through the drift region 126. A depletion layer spreads from the pn junction interface between the p-type partial region 122 and the n-type partial region 124. This depletion layer substantially completely depletes the p-type partial region 122 and the n-type partial region 124 and holds the potential applied between the first source electrode 146 and the drain electrode 153.

Next, the case where this semiconductor device is in an on state will be described.
First, when a positive voltage is applied to the first gate electrode 142, the semiconductor device is turned on. As a result, an n-type inversion layer is formed in the first body region 132 facing the first gate electrode 142. Electrons are injected from the first source region 134 into the n-type partial region 124 through this inversion layer. The electrons flow from the n-type partial region 124 to the drain electrode 153 via the second body region 154 and the drain region 152.
By this electron flow, the positive space charge held in the n-type partial region 124 is canceled out. Therefore, the charge amount of the n-type partial region 124 is apparently reduced. When the charge amount of the n-type partial region 124 decreases, the charge balance is lost due to the relative relationship with the charge amount of the p-type partial region 124. When this charge balance is lost, the ON breakdown voltage of the semiconductor device is lowered.

In the semiconductor device shown in FIG. 7, when a potential that breaks the charge balance of the n-type partial region 124 is applied between the drain electrode 153 and the source electrode 146, the second gate electrode 184 has a higher potential than the second source electrode 157. Apply a small voltage (ON voltage). Alternatively, the second gate electrode 184 is turned on in synchronization with the turn-on of the first gate electrode 142 before a potential that causes the charge balance of the n-type partial region 124 to be lost is applied between the drain electrode 153 and the source electrode 146. May be.
As a result, a p-type inversion layer is formed in the second body region 154 facing the second gate electrode 184. Holes are injected from the second source region 156 into the p-type partial region 122 via the inversion layer. The holes flow from the p-type partial region 122 to the source electrode S via the body contact region 136 in the first body region 132.
Due to the flow of the holes, the negative space charge held in the p-type partial region 122 is canceled. Therefore, the charge amount of the p-type partial region 122 is apparently reduced. As a result, a decrease in the apparent charge amount of the p-type partial region 124 occurs in response to a decrease in the apparent charge amount of the n-type partial region 124. The charge balance of the partial area 122 is not lost. Therefore, the difference between the charge amount that the drift region 125 charge balances when the semiconductor device is off and the charge amount that the drift region 126 charges balance when the semiconductor device is on is small. The breakdown voltage of the semiconductor device can be improved.

In this embodiment, compared to the case of flowing only electrons as in the conventional structure, holes are also flowed in parallel, so the on-resistance is lowered.
A part of hole carriers flowing in the p-type partial region 122 is injected into the n-type partial region 124 and conductivity modulation occurs, so that the on-resistance decreases.

(Fourth embodiment)
It is extremely effective to use the semiconductor device exemplified in the first to third embodiments for the level shift circuit. The level shift circuit is a circuit used for mounting a low voltage circuit and a high voltage circuit on one chip and transmitting signals between the circuits.
FIG. 8 shows an example of the level shift circuit. The power supply voltage of the low voltage circuit is 0-15V, and the power supply voltage of the high voltage circuit is 1000-1015V. A semiconductor device 100 illustrated in FIG. In this embodiment, a case where the semiconductor device of Embodiment 1 is applied will be described.
In the semiconductor device according to the first embodiment, the n-MOS 101 that controls the flow of electrons between the drain electrode 53 and the first source electrode 46 with the first gate electrode 42, and between the first source electrode 46 and the second source electrode 57 are used. Can be regarded as a parallel circuit with the p-MOS 102 in which the flow of the positive holes is controlled by the second gate electrode 84. The first source electrode 46 functions as a drain electrode in the p-MOS 102. Therefore, the semiconductor device can be replaced with a parallel circuit of an n-MOS 101 and a p-MOS 102 as shown in FIG.

A pull-up resistor 103 and a voltage clamping Zener diode 104 are formed between the drain electrode 53 side of the n-MOS 101 and the power supply voltage 1015V. A pull-up resistor 105 and a voltage clamping Zener diode 106 are formed between the second source electrode 57 side of the p-MOS 102 and the power supply voltage 1015V.
The potential on the drain electrode 53 side of the n-MOS 101 is input to the non-inverting terminal of the comparator 109. The power supply voltage 1015V of the high voltage circuit is transformed to 1012V using the voltage dividing resistors 107 and 108 and input to the inverting terminal of the comparator 109.
The output of the comparator 109 is fed back to the second gate electrode 84 of the p-MOS 102.

  First, consider the case where the power supply voltage of the low voltage circuit is applied to the first gate electrode 42 of the n-MOS 101. When a power supply voltage of 15 V is applied to the first gate electrode 42, the n-MOS 101 is turned on. At this time, the potential on the drain electrode 53 side of the n-MOS 101 is 1009V obtained by subtracting the potential 6V of the Zener diode 104 from the power supply voltage 1015V of the high voltage circuit. When this 1009V is input to the non-inverting terminal of the comparator 109, the comparator 109 outputs a 1000V signal. When this 1000 V output signal is fed back to the second gate electrode 84 of the p-MOS 102, a potential difference (1000 V-1009 V = −9 V) between the second gate electrode 84 and the second source electrode 57 is applied to the second gate electrode 84. Since the voltage is applied, the p-MOS 102 is also turned on. That is, the p-MOS 102 is turned on in synchronization with the n-MOS 101 being turned on.

On the other hand, when the n-MOS 101 is turned off, the potential on the drain electrode 53 side of the n-MOS 101 becomes 1015V. When this 1015V is input to the non-inverting terminal of the comparator 109, the comparator 109 outputs a 1015V signal. When this 1015 V output signal is fed back to the second gate electrode 84 of the p-MOS 102, no negative potential difference is generated between the second gate electrode 84 and the second source electrode 57, so that the p-MOS 102 is turned off. That is, the p-MOS 102 is turned off in synchronization with the n-MOS 101 being turned off.
In this way, the 0-15V signal on the low voltage circuit side is converted into a 1000-1015V signal on the high voltage circuit side.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

FIG. 3 is a cross-sectional view of main parts of the semiconductor device of Example 1; FIG. 3 is a plan view of a principal part of the semiconductor device according to the first embodiment. The relationship between the charge amount of the drift layer and the breakdown voltage of the semiconductor device of Example 1 is shown. The principal part top view of the semiconductor device of Example 2 is shown. Sectional drawing of the principal part of the semiconductor device of Example 2 is shown (1). Sectional drawing of the principal part of the semiconductor device of Example 2 is shown (2). FIG. 6 is a cross-sectional view of a principal part of a semiconductor device of Example 3. FIG. 6 shows a circuit diagram of a level shift circuit according to a fourth embodiment. The principal part sectional drawing of the semiconductor device of a conventional structure is shown. The relationship between the charge amount of the drift layer and the breakdown voltage of a semiconductor device having a conventional structure is shown.

Explanation of symbols

22: semiconductor substrate 24: drift layer 32: first body region 34: first source region 36: body contact region 42: first gate electrode 44: first gate insulating film 52: drain region 53: drain electrode 54: second Body region 56: second source region 57: second source electrode 62: top region 72: field oxide film 82: second gate insulating film 84: second gate electrode

Claims (6)

A second conductivity type drift layer;
A first body region of a first conductivity type formed in the drift layer;
A first source region of a second conductivity type formed in the first body region and separated from the drift layer by the first body region;
A first gate electrode facing the first body region separating the first source region and the drift layer via the first gate insulating film;
A first drain region of a second conductivity type formed in the drift layer;
A second source region of the first conductivity type formed at a position away from the first body region in the drift layer;
A second gate electrode facing the drift layer separating the second source region and the first body region via a second gate insulating film;
A second drain region of a first conductivity type formed in the first body region;
A first electrode connected to the first source region;
A second electrode connected to the first drain region;
A third electrode connected to the second source region;
A semiconductor device comprising a fourth electrode connected to the second drain region. A second body region of a second conductivity type surrounding the second source region is formed in the drift layer,
The drift region, the semiconductor device according to claim 1, characterized in that the top region of the first conductivity type extending from the first body region along a surface of the drift region towards the second body region is formed.   The semiconductor device according to claim 1, wherein the first electrode and the fourth electrode are common electrodes.   The semiconductor device according to claim 1, wherein the second electrode and the third electrode are common electrodes.   The semiconductor device according to claim 1, wherein the drift layer is stacked on the first conductivity type semiconductor substrate or the insulating substrate. A level shift circuit comprising the semiconductor device according to claim 1.

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