CN115020495A - 半导体器件结构及其形成方法 - Google Patents
半导体器件结构及其形成方法 Download PDFInfo
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- CN115020495A CN115020495A CN202210492122.1A CN202210492122A CN115020495A CN 115020495 A CN115020495 A CN 115020495A CN 202210492122 A CN202210492122 A CN 202210492122A CN 115020495 A CN115020495 A CN 115020495A
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Abstract
半导体器件结构包括形成在衬底上方的纳米结构。该结构还包括形成在纳米结构上方和周围的栅极结构。该结构还包括在纳米结构上方的栅极结构的侧壁上方形成的间隔件层。该结构还包括邻近间隔件层形成的源极/漏极外延结构。该结构还包括形成在源极/漏极外延结构上方的接触结构,以及形成在间隔件层和接触结构之间的空气间隔件。本申请的实施例还涉及用于形成半导体器件结构的方法。
Description
技术领域
本申请的实施例涉及半导体器件结构及其形成方法。
背景技术
半导体器件用于各种电子应用,诸如个人计算机、手机、数码相机和其他电子设备。半导体器件通常通过在半导体衬底上方依次沉积绝缘或ILD结构、导电层和半导体材料层,并使用光刻对各个材料层进行图案化以在其上形成电路组件和元件来制造。许多集成电路通常在单个半导体晶圆上制造,并且晶圆上的各个管芯通过沿划线在集成电路之间进行锯切而被切割。各个管芯通常被单独封装,例如以多芯片模块或以其他类型的封装形式。
最近,为了通过增加栅极-沟道耦合、减小截止状态电流并且减少短沟道效应(SCE)来努力改进栅极控制,已经引入了多栅极器件。已经引入的一种这样的多栅极器件是全环栅晶体管(GAA)。GAA器件得名于栅极结构,该栅极结构可以在沟道区域周围延伸,从两个或四个侧访问沟道。GAA器件与传统的互补金属氧化物半导体(CMOS)工艺兼容。
GAA器件不能免受可能会影响器件性能的寄生电容的影响。虽然现有的GAA结构和制造方法在许多方面都令人满意,但仍需要继续改进。
发明内容
本申请的一些实施例提供了一种半导体器件结构,包括:纳米结构,形成在衬底上方;栅极结构,形成在所述纳米结构上方和周围;间隔件层,形成在所述纳米结构上方的所述栅极结构的侧壁上方;源极/漏极外延结构,形成为邻近所述间隔件层;接触结构,形成在所述源极/漏极外延结构上方;以及空气间隔件,设置在所述间隔件层和所述接触结构之间。
本申请的另一些实施例提供了一种半导体器件结构,包括:鳍结构,形成在衬底上方;纳米结构,形成在所述鳍结构上方;栅极结构,包裹所述纳米结构;间隔件层,形成在所述纳米结构之上的所述栅极结构的相对侧上方;源极/漏极外延结构,形成在所述纳米结构的相对侧上方;接触结构,形成在所述源极/漏极外延结构上方;保护层,形成在所述接触结构的侧壁上方;以及空气间隔件,设置在所述间隔件层和所述保护层之间。
本申请的又一些实施例提供了一种用于形成半导体器件结构的方法,包括:在衬底上方形成纳米结构;在所述纳米结构周围和上方形成栅极结构;在所述纳米结构上方的所述栅极结构的相对侧上方形成间隔件层;在所述间隔件层的侧壁上方形成伪层;在所述栅极结构旁边形成接触结构;去除所述伪层以在所述间隔件层和所述接触结构之间形成空气间隔件;以及在所述栅极结构、所述接触结构和所述空气间隔件上方沉积密封衬垫层。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是根据本公开的一些实施例的半导体器件结构的立体图。
图2A-图2J是根据本公开的一些实施例的形成半导体器件结构的各个阶段的截面图。
图3A-图3C是根据本公开的一些实施例的形成半导体器件结构的各个阶段的截面图。
图4A-图4B是根据本公开的一些实施例的形成半导体器件结构的各个阶段的截面图。
图5A-图5C是根据本公开的一些实施例的形成半导体器件结构的各个阶段的截面图。
图6是根据本公开的一些实施例的半导体器件结构的截面图。
图7A-图7F是根据本公开的一些实施例的形成半导体器件结构的各个阶段的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
此外,当用“约”、“近似”等描述数值或数值范围时,该术语旨在涵盖在合理范围内的数值,该合理范围考虑了由本领域的普通技术人员所理解的在制造过程中固有地出现的变化。例如,基于与制造具有与该数值相关的特性的部件相关的已知制造公差,数值或数值范围涵盖包括所描述数值的合理范围,诸如在所描述数值的+/-10%内。例如,具有“约5nm”厚度的材料层可以涵盖从4.25nm到5.75nm的尺寸范围,其中与沉积材料层相关的制造公差由本领域普通技术人员已知为+/-15%。更进一步,本公开可以在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
描述了实施例的一些变形。贯穿各个视图和示例性实施例,相同的参考标号用于表示相同的元件。应当理解,可以在该方法之前、期间和之后提供额外的操作,并且对于该方法的其他实施例可以替换或消除所描述的一些操作。
下文描述的全环栅(GAA)晶体管结构中的各个部件可以通过任何合适的方法来图案化。例如,GAA晶体管的有源区和栅极结构可以使用一个或多个光刻工艺来图案化,一个或多个光刻工艺包括双图案化或多图案化工艺。通常,双图案或多图案工艺结合光刻和自对准工艺,从而允许创建具有例如比使用单个直接光刻工艺可获得的间距更小的间距的图案。例如,在一个实施例中,牺牲层形成在衬底上方并使用光刻工艺图案化。使用自对准工艺在图案化牺牲层旁边形成间隔件。然后去除牺牲层,并且然后可以使用剩余的间隔件来图案化GAA晶体管的有源区或栅极结构。
提供了用于形成半导体器件结构的实施例。用于形成半导体器件结构的方法可以包括在间隔件层和接触结构之间形成空气间隔件。空气间隔件可以通过密封衬垫层形成。使用空气间隔件,可以减少寄生电容。
图1是根据本公开的一些实施例的用于图2J所示的半导体器件结构10a的工件的立体图。半导体器件结构10a是全环栅(GAA)晶体管结构。图2A-图2J是根据本公开的一些实施例的形成半导体器件结构10a的各个阶段的截面图。图2A-图2J示出了沿图1中的线2-2截取的截面图。
根据一些实施例,如图1和图2A所示,提供了衬底102。衬底102可以是半导体晶圆,诸如硅晶圆。衬底102还可以包括其他元素半导体材料、化合物半导体材料和/或合金半导体材料。元素半导体材料的示例可以包括但不限于晶体硅、多晶硅、非晶硅、锗和/或金刚石。化合物半导体材料的示例可以包括但不限于碳化硅、氮化镓、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟。合金半导体材料的示例可以包括但不限于SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP。衬底102可以包括外延层。例如,衬底102可以是位于体半导体上面的外延层。此外,衬底102也可以是绝缘体上半导体(SOI)。SOI衬底可以通过晶圆接合工艺、硅膜转移工艺、注氧隔离(SIMOX)工艺、其他适用方法或它们的组合来制造。衬底102可以是N型衬底。衬底102可以是P型衬底。
接下来,根据一些实施例,如图1所示,第一半导体层104和第二半导体层106交替堆叠在衬底102上方。第一半导体层104和第二半导体层106可以包括Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb或InP。第一半导体层104和第二半导体层106可以由具有不同蚀刻速率的不同材料制成。在一些实施例中,第一半导体层104包括SiGe并且第二半导体层106包括Si。
第一半导体层104和第二半导体层106可以通过低压化学气相沉积(LPCVD)工艺、外延生长工艺、其他适用的方法或它们的组合来形成。外延生长工艺可以包括分子束外延(MBE)、金属有机化学气相沉积(MOCVD)或气相外延(VPE)。
应该注意,虽然图1示出了三层的第一半导体层104和三层的第二半导体层106,但是工件可以包括更少或更多的第一半导体层104和第二半导体层106,这取决于半导体器件结构10a的设计和形成该结构的工艺。
接下来,可以在第一半导体层104和第二半导体层106(未示出)上方形成硬掩模层并对其进行图案化。可以使用图案化的硬掩模层作为掩模层来图案化第一半导体层104和第二半导体层106以形成鳍结构108。图案化工艺可以包括光刻工艺和蚀刻工艺。光刻工艺可以包括光刻胶涂布(例如,旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、显影光刻胶、冲洗和干燥(例如,硬烘烤)。蚀刻工艺可以包括干蚀刻工艺或湿蚀刻工艺。
根据一些实施例,如图1所示,在形成鳍结构108之后,在鳍结构108之间的沟槽中形成衬垫层110。衬垫层110可以共形地形成在衬底102、鳍结构108和覆盖鳍结构的硬掩模层上方。衬垫层110可用于保护鳍结构108在后续工艺(诸如退火工艺或蚀刻工艺)中免受损坏。衬垫层110可以由氮化硅制成。衬垫层110可以通过使用CVD工艺、原子层沉积(ALD)工艺、LPCVD工艺、等离子体增强CVD(PECVD)工艺、HDPCVD工艺、其他适用工艺或它们的组合来形成。
接下来,然后可以在鳍结构108之间的沟槽中的衬垫层110上方沉积隔离结构材料112。隔离结构112可以由氧化硅、氮化硅、氮氧化硅、氟化物掺杂的硅酸盐玻璃(FSG)或其它低k介电材料制成。隔离结构112可以通过诸如化学气相沉积(CVD)工艺、旋涂玻璃工艺或其他适用工艺的沉积工艺来沉积。
接下来,可以对隔离结构112和衬垫层110执行蚀刻工艺。蚀刻工艺可以用于去除衬垫层110的顶部和隔离结构112的顶部。结果,第一半导体层104和第二半导体层106可以被暴露并且剩余的隔离结构112和衬垫层110可以围绕鳍结构108的基部。剩余的隔离结构112可以是围绕鳍结构108的基部的浅沟槽隔离(STI)结构。隔离结构112可以被配置为防止电干扰或串扰。因此,可以在鳍结构108之间形成沟槽。
接下来,根据一些实施例,如图1所示,在鳍结构108上方并横跨鳍结构108形成伪栅极结构114。伪栅极结构114可以包括伪栅极介电层116和伪栅电极层118。伪栅极介电层116和伪栅电极层118可以通过利用如图2A所示的高k介电层和金属栅电极层140的以下步骤来替换,以形成真实栅极结构。
伪栅极介电层116可以包括氧化硅。氧化硅可通过氧化工艺(例如,干氧化工艺或湿氧化工艺)、化学气相沉积工艺、其他适用工艺或它们的组合形成。可选地,栅极介电层116可以包括高k介电层(例如,介电常数大于3.9),诸如氧化铪(HfO2)。可选地,高k介电层可以包括其他高k电介质,诸如LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3、BaTiO3、BaZrO、HfZrO、HfLaO、HfTaO、HfSiO、HfSiON、HfTiO、LaSiO、AlSiO、(Ba,Sr)TiO3、Al2O3、其他适用的高k介电材料或它们的组合。可以通过化学气相沉积工艺(例如,等离子体增强化学气相沉积(PECVD)工艺,或金属有机化学气相沉积(MOCVD)工艺)、原子层沉积(ALD)工艺(例如,等离子体增强原子层沉积(PEALD)工艺)、物理气相沉积(PVD)工艺(例如,真空蒸发工艺或溅射工艺)、其他适用的工艺或它们的组合来形成高k介电层。
伪栅电极层118可以包括多晶硅(poly-Si)、多晶硅锗(poly-SiGe)、其他适用材料或它们的组合。可以通过化学气相沉积工艺(例如,低压化学气相沉积工艺,或等离子体增强化学气相沉积工艺)、物理气相沉积工艺(例如,真空蒸发工艺,或溅射工艺)、其他适用工艺或它们的组合来形成伪栅电极层118。
之后,可以使用图案化的光刻胶层作为掩模(未示出)对伪栅极介电层116和伪栅电极层118执行蚀刻工艺以形成伪栅极结构114。蚀刻工艺可以是干蚀刻工艺。伪栅极介电层116和伪栅电极层118可以通过干蚀刻工艺来蚀刻。干蚀刻工艺可以包括使用基于氟的蚀刻剂气体,诸如SF6、CxFy(其中x和y可以是正整数)、NF3或它们的组合。在蚀刻工艺之后,第一半导体层104和第二半导体层106可以暴露在伪栅极结构114的相对侧上。
接下来,根据一些实施例,如图1和图2A所示,在伪栅极结构114的相对侧壁上形成一对间隔件层120。间隔件层120可以由氧化硅、氮化硅、氮氧化硅和/或介电材料制成。间隔件层120可以通过化学气相沉积(CVD)工艺、ALD或其他适用工艺形成。
在如图2A所示的一些实施例中,每个间隔件层120均包括内部部分120a和外部部分120b。间隔件层120的内部部分120a覆盖伪栅极结构114的侧壁以及第二半导体层106和第一半导体层104的堆叠件的顶面。间隔件层120的外部部分120b形成在间隔件层120的内部部分120a的侧壁和顶面上方。间隔件层120的内部部分120a可以包括更多的碳和氮,以避免在后续蚀刻工艺中被消耗。间隔件层120的外部部分120b可以包括更多的氧以降低k值。
之后,根据一些实施例,如图1所示,可以在蚀刻工艺中去除鳍结构108的未被伪栅极结构114覆盖的第一半导体层104和第二半导体层106,以形成源极/漏极开口122。蚀刻工艺可以是干蚀刻工艺。干蚀刻工艺可以包括使用基于氟的蚀刻剂气体,诸如SF6、CxFy(其中x和y可以是正整数)、NF3或它们的组合。
接下来,根据一些实施例,如图1所示,从源极/漏极开口122横向蚀刻第一半导体层104以形成凹槽124。可以去除第一半导体层104的外部部分,并且可以保留第一半导体层104的位于伪栅极结构114或间隔件层120下方的内部部分。第一半导体层104的横向蚀刻可以是干蚀刻工艺、湿蚀刻工艺或它们的组合。在横向蚀刻之后,蚀刻的第一半导体层104的侧壁可能不与第二半导体层106的侧壁对准。
接下来,根据一些实施例,如图2A所示,在凹槽124中形成内部间隔件126。内部间隔件126可以在随后形成的源极/漏极外延结构和栅极结构之间提供阻挡。内部间隔件126可以由氧化硅、氮化硅、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)或它们的组合制成。可以通过沉积工艺和回蚀工艺形成内部间隔件126。沉积工艺可以包括CVD工艺(诸如LPCVD、PECVD、SACVD或FCVD)、ALD工艺、另一种适用的方法或它们的组合。回蚀工艺可以包括干蚀刻工艺或湿蚀刻工艺。
接下来,根据一些实施例,如图2A所示,在源极/漏极开口122中形成源极/漏极外延结构128。如图2A所示,源极/漏极外延结构128形成在鳍结构108的相对侧上方。
可以通过外延(epi)工艺在源极/漏极开口122中生长应变材料以形成源极/漏极外延结构128。此外,应变材料的晶格常数可以不同于衬底102的晶格常数。源极/漏极外延结构128可以包括Ge、SiGe、InAs、InGaAs、InSb、GaAs、GaSb、InAlP、InP、SiC、SiP、其他适用材料或它们的组合。源极/漏极外延结构128可以通过外延生长步骤形成,诸如分子束外延(MBE)、氢化物气相外延(HVPE)、液相外延(LPE)、氯化物气相外延(Cl-VPE)、或任何其他合适的方法。源极/漏极外延结构128可以掺杂有一种或多种掺杂剂。例如,当半导体器件结构10a为p型时,源极/漏极外延结构128可以是掺杂有硼(B)或其他适用的掺杂剂的硅锗(SiGe);并且当半导体器件结构10a为n型时,源极/漏极外延结构128可以包括掺杂有磷(P)或其他适用的掺杂剂的硅(Si)。
在如图2A所示的一些实施例中,源极/漏极外延结构128包括底部部分128a、边缘部分128b和中心部分128c。底部部分128a可以形成在源极/漏极开口122的底部处。边缘部分128b可以形成在源极/漏极开口122中的底部部分128a上方以及第二半导体层106的侧壁上方。中心部分128c可以填充源极/漏极开口122。
源极/漏极外延结构128的底部部分128a、边缘部分128b和中心部分128c中的应变和掺杂剂浓度可以不同。例如,底部部分128a的应变可以小于边缘部分128b的应变,并且边缘部分128b的应变可以小于中心部分128的应变。此外,底部部分128a的掺杂剂浓度可以小于边缘部分128b的掺杂剂浓度,并且边缘部分128b的掺杂剂浓度可以小于中心部分128的掺杂剂浓度。
具有较小应变和掺杂剂浓度的源极/漏极外延结构128的底部部分128a可以有助于减少晶格缺陷。源极/漏极外延结构128的边缘部分128b可以有助于生长源极/漏极外延结构128的中心部分128c。源极/漏极外延结构128的中心部分128c可以主导源极/漏极外延结构128的应变和电阻。
接下来,根据一些实施例,如图2A所示,在间隔件层120的侧壁上方形成第一接触蚀刻停止层130。第一接触蚀刻停止层130可以在随后的注入工艺中限定注入区域,并且还限定随后形成的接触结构的尺寸。第一接触蚀刻停止层130可以包括氮化硅、氧化硅、氮氧化硅(SiON)、碳氮氧化硅(SiOCN)、其他适用材料或它们的组合。可以通过化学气相沉积工艺(例如,等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺(例如,等离子体增强原子层沉积(PEALD)工艺)、物理气相沉积(PVD)工艺(例如,真空蒸发工艺或溅射工艺)、其他适用的工艺或它们的组合形成第一接触蚀刻停止层130。
在第一接触蚀刻停止层130上方形成层间介电(ILD)结构(未示出)。ILD结构可以包括由多种介电材料制成的多层,诸如氧化硅(SiOx,其中x可以是正整数)、碳氧化硅(SiCOy,其中y可以是正整数)、碳氮氧化硅(SiNCOz,其中z可以是正整数)、氮化硅、氮氧化硅、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、低k介电材料或其他适用的介电材料。低k介电材料的示例包括但不限于氟化石英玻璃(FSG)、碳掺杂氧化硅、无定形氟化碳、聚对二甲苯、双苯并环丁烯(BCB)或聚酰亚胺。ILD结构可以通过化学气相沉积(CVD)、旋涂或其他适用工艺形成。
之后,对ILD结构执行平坦化工艺直至暴露伪栅极结构114的顶面(未示出)。在平坦化工艺之后,伪栅极结构114的顶面可以与间隔件层120、第一接触蚀刻停止层130和ILD结构的顶面基本齐平。平坦化工艺可包括研磨工艺、化学机械抛光(CMP)工艺、蚀刻工艺、其他适用工艺或它们的组合。
接下来,去除包括伪栅极介电层116和伪栅电极层118的伪栅极结构114(未示出)。因此,在鳍结构108上方的间隔件层120之间形成栅极沟槽,并且第二半导体层106从沟槽中暴露。可以通过干蚀刻工艺或湿蚀刻工艺去除伪栅极结构114。
在形成栅极沟槽之后,去除第一半导体层104以在相邻的第二导体层106之间形成间隙(未示出)。去除工艺可以包括选择性蚀刻工艺。根据一些实施例,选择性蚀刻工艺可以去除第一半导体层104以释放第二半导体层106作为纳米结构106(作为半导体器件结构10a的沟道区)。
去除第一半导体层104的选择性蚀刻工艺可以包括湿蚀刻工艺、干蚀刻工艺或它们的组合。选择性蚀刻工艺可以是无等离子体干化学蚀刻工艺。干化学蚀刻工艺的蚀刻剂可包括自由基,诸如HF、NF3、NH3、H2或它们的组合。
根据一些实施例,如图2A所示,在形成间隙之后,在纳米结构106周围和上方形成栅极结构132。栅极结构132可以是多层结构。每个栅极结构132可以包括界面层134、高k介电层136、功函层138和栅电极层140。栅极结构132围绕纳米结构106,这可以增强栅极控制能力。纳米结构106可以被界面层134围绕并且与界面层134直接接触,并且界面层134可以被高k介电层136围绕。另外,高k介电层136可以被功函层138围绕。
界面层134可以由氧化硅制成,并且界面层134可以通过热氧化形成。高k介电层136可以包括介电材料,诸如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他适用的高-k介电材料,或它们的组合。高k介电层136可以通过使用CVD、ALD、其他适用方法或它们的组合来形成。
功函层138可以由金属材料制成,并且金属材料可以包括N功函金属或P功函金属。N功函金属可以包括钨(W)、铜(Cu)、钛(Ti)、银(Ag)、铝(Al)、钛铝合金(TiAl)、氮化钛铝(TiAlN)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化硅钽(TaSiN)、锰(Mn)、锆(Zr)或它们的组合。P功函金属可以包括氮化钛(TiN)、氮化钨(WN)、氮化钽(TaN)、钌(Ru)或它们的组合。功函层138可以通过使用CVD、ALD、其他适用的方法或它们的组合来形成。
应该注意,图2A所示的功函层138的数量仅仅是示例,并且不限于此,这取决于目标功函值的需求。
接下来,使高k介电层136、功函层138和间隔件层120凹进以在栅极结构132之上形成凹槽(未示出)。凹进工艺可包括一种或多种蚀刻工艺,诸如干蚀刻和/或湿蚀刻。在凹进工艺之后,间隔件层120的顶面高于高k介电层136和功函层138的顶面。
接下来,根据一些实施例,如图2A所示,栅电极层140形成在高k介电层136和功函层138上方的凹槽中。栅电极层140可以形成为填充功函层138之间的凹槽。栅电极层140也可以形成为覆盖间隔件层120之间的高k介电层136和功函层138的顶面,以用于随后形成的接触结构的更大接合区域。
栅电极层140可以由一个或多个导电材料层制成,导电材料诸如铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他适用材料或它们的组合。栅电极层140可以通过使用CVD、ALD、电镀、其他可应用的方法或它们的组合来形成。
接下来,根据一些实施例,如图2A所示,在栅极结构132和间隔件120之上的凹槽中形成硬掩模层142。硬掩模层142可以为随后形成的接触结构和附近的导电元件提供隔离。硬掩模层142可以由相对于随后形成的保护层和接触结构具有蚀刻选择性的材料制成。更具体地,硬掩模层142可以具有相对于SiN和金属的蚀刻选择性。例如,硬掩模层142可以包括半导体氧化物、金属氧化物、Si、Ge、SiGe、TiN、LaO、AlO、YO、TaCN、ZrSi、SiOCN、SiOC、SiCN、LaO、ZrN、ZrAlO、TiO、TaO、ZrO、HfO、SiN、HfSi、AlON、SiO、SiC、ZnO、其他适用材料或它们的组合。在一个实施例中,硬掩模层142可以由诸如Si、Ge或SiGe的半导体材料形成。硬掩模层142可以通过CVD(诸如HDP-CVD、PECVD或HARP)、ALD、其他合适的方法和/或它们的组合沉积在凹槽中。在沉积硬掩模层142之后,可以可选地执行平坦化工艺(例如,化学机械抛光工艺或回蚀工艺)以去除过量的介电材料。
在沉积硬掩模层142之后,可以可选地执行平坦化工艺(例如,化学机械抛光工艺或回蚀工艺)以去除过量的介电材料。
接下来,根据一些实施例,如图2A所示,可以去除源极/漏极外延结构128上方的ILD结构,并且可以在栅极结构132之间的源极/漏极外延结构128上方形成接触开口144。接触开口144可以通过诸如干蚀刻工艺或湿蚀刻工艺的蚀刻工艺形成。如图2A所示,接触开口144限定在第一接触蚀刻停止层130之间。
之后,根据一些实施例,如图2B所示,在源极/漏极外延结构128上方执行注入工艺146。注入工艺146可以是预非晶注入工艺,并且可以在源极/漏极外延结构128的顶部处形成非晶层。随后形成的第一金属半导体化合物层可以被限制在非晶区域中。在注入工艺146中使用的注入可以包括Si、Ge、C、Xe、其他适用的注入或它们的组合。可以修改注入能量或源以实现所需的注入深度。
接下来,根据一些实施例,如图2C所示,去除第一接触蚀刻停止层130,并且暴露间隔件层120和硬掩模层142的侧壁。可以通过诸如干蚀刻工艺或湿蚀刻工艺的蚀刻工艺来去除第一接触蚀刻停止层130。
根据一些实施例,如图2D所示,在去除第一接触蚀刻停止层130之后,在间隔件层120和硬掩模层142的侧壁上方形成伪层148。伪层148可以由相对于随后形成的保护层和接触结构具有蚀刻选择性的材料制成。更具体地,伪层148可以具有对SiN和金属的蚀刻选择性。伪层148可以包括半导体氧化物、金属氧化物、Si、Ge、SiGe、TiN、LaO、AlO、YO、TaCN、ZrSi、SiOCN、SiOC、SiCN、LaO、ZrN、ZrAlO、TiO、TaO、ZrO、HfO、SiN、HfSi、AlON、SiO、SiC、ZnO、其他适用材料或它们的组合。在一些实施例中,伪层148和硬掩模142由相同的材料制成。在一个实施例中,伪层148可以具有与硬掩模层142相同的组分并且可以包括半导体材料,诸如Si、Ge或SiGe。伪层148可以首先通过ALD、CVD(诸如HDP-CVD、PECVD或HARP)、其他合适的方法和/或它们的组合共形地沉积在接触开口144中和硬掩模层142上方。之后,可以蚀刻掉硬掩模142和源极/漏极极外延结构128的顶面上方的伪层148,并且可以暴露硬掩模142和源极/漏极极外延结构128的顶面。伪层148可以通过各向同性蚀刻工艺来蚀刻,诸如干蚀刻工艺。在一些实施例中,伪层148的厚度小于10nm,其受限于栅极结构132之间的空间。
之后,根据一些实施例,如图2E所示,在伪层148的侧壁上方形成保护层150。保护层150可以由半导体氮化物、半导体氧化物、金属氧化物、金属氮化物、其他适用的材料或它们的组合制成。例如,保护层150可以包括氧化硅、氮化硅、TiN、LaO、AlO、YO、TaCN、SiOCN、SiOC、SiCN、LaO、ZrN、ZrAlO、TiO、TaO、ZrO、HfO、SiN、HfSi、AlON、SiO、SiC或ZnO。在随后的退火工艺中,保护层150不会与随后形成的金属层发生反应。保护层150可以在后续的工艺期间维持蚀刻工艺以去除伪层148和硬掩模层142,否则可能会影响用于减小寄生电容的间隙。在一个实施例中,虽然伪层148和硬掩模层142由诸如Si、Ge或SiGe的半导体材料形成,但保护层150由氮化硅、氮氧化硅或氧化硅形成。
保护层150可以首先通过ALD、CVD(诸如HDP-CVD、PECVD或HARP)、其它合适的方法和/或它们的组合共形地沉积在接触开口144中和硬掩模层142上方。之后,可以蚀刻掉硬掩模142和源极/漏极外延结构128的顶面上方的保护层150,并且可以暴露硬掩模142和源极/漏极外延结构128的顶面。保护层150可以通过各向异性蚀刻工艺来蚀刻,诸如干蚀刻工艺。在一些实施例中,伪层148和保护层150的总厚度与在图2A中形成的第一接触蚀刻停止层130的厚度基本相同。
接下来,根据一些实施例,如图2F所示,可以在源极/漏极外延结构128上方形成第一硅化物层152a。第一硅化物层152a可以降低源极/漏极外延结构128和随后在源极/漏极外延结构128上方形成的接触结构之间的接触电阻。第一硅化物层152a可以由硅化钛(TiSi2)、硅化镍(NiSi)、硅化钴(CoSi)或其他合适的低电阻材料制成。第一硅化物层152a可以是第一金属半导体化合物层152a。通过首先在源极/漏极外延结构128上方形成金属层,可以在源极/漏极外延结构128上方形成第一硅化物层152a。金属层可以在退火工艺中与源极/漏极外延结构128反应并且可以产生第一硅化物层152a。之后,可以在蚀刻工艺中去除未反应的金属层并且可以留下第一硅化物层152a。
接下来,根据一些实施例,如图2F所示,阻挡层154可以共形地形成在接触开口144的底面和侧壁上方。阻挡层154可以在将导电材料填充到接触开口144中之前形成,以防止导电材料扩散出去。阻挡层154也可以用作粘合剂或胶层。阻挡层154也可以作为晶种层,以用于在接触开口144中形成导电材料。阻挡层154的材料可以是TiN、Ti、TaN、Ta、其他适用材料或它们的组合。阻挡层154可以通过物理气相沉积工艺(PVD)(例如,蒸发或溅射)、原子层沉积工艺(ALD)、电镀工艺、其他适用工艺或它们的组合沉积阻挡层154的材料形成。
之后,根据一些实施例,如图2F所示,在接触开口144中形成导电材料并且在源极/漏极外延结构128上方形成接触结构156。接触结构156可以包括阻挡层154和填充在接触开口144中的导电材料。导电材料可以由金属材料(例如,Co、Ni、W、Ti、Ta、Cu、Al、Ru、Mo、TiN、TaN和/或它们的组合)、金属合金、其他适用的导电材料或它们的组合制成。导电材料可以通过化学气相沉积工艺(CVD)、物理气相沉积工艺(PVD)(例如,蒸发或溅射)、原子层沉积工艺(ALD)、电镀工艺、其他合适的工艺或它们的组合形成。
然后,根据一些实施例,如图2G所示,可选地执行诸如化学机械抛光(CMP)工艺或回蚀工艺的平坦化工艺以去除过量的导电材料。在平坦化工艺之后可以暴露硬掩模142的顶面。在平坦化工艺之后,接触结构156的顶面可以与硬掩模层142、伪层148和保护层150的顶面齐平。
接下来,根据一些实施例,如图2H所示,去除硬掩模层142和伪层148,并在间隔件层120和保护层150之间形成沟槽158。在一些实施例中,间隔件层120和保护层150的侧壁以及源极/漏极外延结构128的部分顶面从沟槽158暴露。由于硬掩模层142和伪层148的材料相对于接触结构156和保护层150的材料具有蚀刻选择性,因此在去除硬掩模层142和伪层148之后,接触结构156和保护层150可以基本保留。硬掩模层142和伪层148可以通过诸如干蚀刻工艺或湿蚀刻工艺的蚀刻工艺去除。在一些实施例中,沟槽158的底面与栅极结构132和间隔件层120的顶面之间存在高度差。
接下来,根据一些实施例,如图2I所示,在栅极结构132和接触结构156上方形成密封衬垫层160。在一些实施例中,间隔件层120和保护层150之间的沟槽158被密封衬垫层160密封,并且空气间隔件162形成在密封衬垫层160下方。在一些实施例中,密封衬垫层160共形地形成在栅极结构132和接触结构156上方。在一些实施例中,密封衬垫层160沉积在空气间隔件162上方。在一些实施例中,空气间隔件162形成在间隔件层120和接触结构156之间。在一些实施例中,空气间隔件162形成在保护层150和栅极结构132之间。在一些实施例中,空气间隔件162的顶面低于接触结构156的顶面。在一些实施例中,空气间隔件162的顶面低于间隔件层120的顶面。
密封衬垫层160可以具有低k值,并且可以保留在随后的蚀刻工艺中。在一些实施例中,密封衬垫层160和保护层150由不同的材料制成。空气间隔件162可以帮助减少寄生电容。在一些实施例中,密封衬垫层160可以由SiOCN制成。密封衬垫层160中的硅组分在从约30%至约40%的范围内。密封衬垫层160中的氧组分在约30%至约60%的范围内。较高的氧组分可能有助于降低k值。然而,如果氧组分太高,则在随后的蚀刻工艺期间可能难以保留密封衬垫层160。密封衬垫层160中的碳组分在约1%至约30%的范围内。较高的碳组分可能有助于降低k值。然而,如果碳组分太高,则在随后的蚀刻工艺期间可能难以保持密封衬垫层160。密封衬垫层160中的氮组分在约5%至约30%的范围内。密封衬垫层160中较高的氮组分可有助于在随后的蚀刻工艺中保留密封衬垫层160。然而,如果氮组分太高,则k值可能太高。
在一些实施例中,密封衬垫层160和保护层150由相同的材料制成。因此,密封衬垫层160和保护层150之间的界面可能难以观察到甚至不可观察。
密封衬垫层160可以通过原子层沉积工艺(ALD)、化学气相沉积工艺(CVD)、物理气相沉积工艺(PVD)(例如,蒸发或溅射)、电镀工艺形成、其他合适的方法,或它们的组合形成。在一些实施例中,密封衬垫层160通过类ALD沉积工艺形成。
接下来,根据一些实施例,如图2I所示,在密封衬垫层160上方形成填充膜164。填充膜164可以沉积在相邻接触结构156之间的栅极结构132上方。填充膜164可以具有低k值以降低寄生电容。填充膜164可以由氧化硅、碳氧化硅、碳氮氧化硅、氮化硅、氮氧化硅、未掺杂的硅酸盐玻璃、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、低k金属氧化物制成,或其他适用的材料,或它们的组合制成。示例性低k金属氧化物可以包括多孔金属氧化物物质,诸如氧化铝、氧化镁、氧化锌、氧化铟锌(IZO)或氧化铟镓锌(IGZO)。填充膜164可以通过物理气相沉积工艺(PVD)(例如,蒸发或溅射)、化学气相沉积工艺(CVD)、可流动CVD(FCVD)工艺、旋涂工艺、其他合适的工艺,或它们的组合形成。在一些实施例中,填充膜164通过类PVD沉积工艺形成。
接下来,根据一些实施例,如图2J所示,在填充膜164上方执行平坦化工艺直至暴露密封衬垫层160的顶面。平坦化工艺可包括研磨工艺、化学机械抛光(CMP)工艺、蚀刻工艺、其他适用工艺或它们的组合。
接下来,根据一些实施例,如图2J所示,在填充膜164和密封衬垫层160上方形成第二接触蚀刻停止层166。第二接触蚀刻停止层166可以具有与第一接触蚀刻停止层130相同的组分。在一些可选实施例中,第二接触蚀刻停止层166可以包括SiC、LaO、AlO、AlON、ZrO、HfO、SiN、ZnO、ZrN、ZrAlO、TiO、TaO、YO、TaCN、ZrSi、SiOCN、SiOC、SiCN、HfSi、SiO或未掺杂的硅。第二接触蚀刻停止层166可以使用CVD(诸如LPCVD、PECVD、HDP-CVD、HARP和FCVD)、ALD、其他合适的方法或它们的组合来形成。
在伪层148和栅极结构132上方的硬掩模层142由相同材料形成的情况下,可以在去除伪层148和硬掩模层142之后,可以在保护层150和间隔件层120之间形成沟槽158。密封衬垫层160沉积在沟槽158上方,并且可以形成空气间隔件162。如本文所述,空气间隔件162是密封间隙,在间隙被密封衬垫层160密封之前,该间隙中可能充满存在于该间隙中的气体物质。在处理室处于真空下的一些情况下,密封间隙(即,空气间隔件162)可以包括很少或不包括气体物质。通过在间隔件层120和接触结构156之间形成空气间隔件162,可以降低寄生电容。在图2J所示的实施例中,空气间隔件162可以具有约1nm和约10nm之间的宽度和约10nm和约30nm之间的高度。在这些实施例中,空气间隔件162可以具有约3和约10之间的高宽比。
可以对本公开的实施例进行许多变化和/或修改。图3A-图3C是根据本公开的一些实施例的形成半导体器件结构10b(图3C所示)的各个阶段的截面图。一些工艺或器件与上述实施例中描述的那些相同或类似,并且因此在此不再重复描述这些工艺和器件。与以上结合图2A至图2J描述的实施例相比,一个明显的区别是,如图3A所示,间隔件层120延伸更高。
在一些实施例中,在栅极结构132上方形成硬掩模层142之后,剩余的间隔件层120延伸更高。在一些实施例中,间隔件层120的顶面与硬掩模层142的顶面基本齐平。
在一些实施例中,半导体器件结构10b中的间隔件层120的碳含量可以更高。因此,在栅极结构132上方形成凹槽后,间隔件层120的材料可蚀刻较慢且间隔件层120可以更高。在这些实施例中,间隔件层120可以由SiCN、SiC、其他适用材料制成,或它们的组合制成。可以通过含碳气体或碳掺杂来增加间隔件层120的碳含量。
根据一些实施例,如图3B所示,由于较高的间隔件层120,在去除硬掩模层142和伪层148之后,沟槽158更深。换言之,沟槽158可以具有比图2H中的沟槽158更大的高宽比。在一些实施例中,间隔件层120的顶面与接触结构156的顶面基本齐平。
接下来,根据一些实施例,如图3C所示,在形成密封衬垫层160之后形成空气间隔件162。由于沟槽158更深,因此空气间隔件162可以更高。寄生电容可以随着更高的空气间隔件162而进一步降低。在一些实施例中,空气间隔件162高于栅极结构132。在一些实施例中,空气间隔件162与接触插塞156基本一样高。如果空气间隔件162高于接触插塞156,则空气间隔件162在随后的蚀刻工艺期间可能不会被密封。
应当注意,尽管空气间隔件162与图3C中所示的接触插塞156基本一样高,但是空气间隔件162的高度不限于此,并且可以根据半导体器件结构10b的设计而更大或更小。在图3C所示的实施例中,空气间隔件162可以具有约1nm和约10nm之间的宽度和约30nm和约50nm之间的高度。在这些实施例中,空气间隔件162的高宽比可以在约5和约30之间。间隔件层120的碳组分可以被修改以满足空气间隔件162的目标高度。
在伪层148和栅极结构132上方的硬掩模层142由相同的材料形成的情况下,在去除伪层148和硬掩模层142之后,可以在保护层150和间隔件层120之间形成沟槽158。密封衬垫层160沉积在沟槽158上方,并且可以形成空气间隔件162。通过在间隔件层120和接触结构156之间形成空气间隔件162,可以降低寄生电容。可以通过改变间隔件层120的材料硬度来改变空气间隔件162的高度和寄生电容。
可以对本公开的实施例进行许多变化和/或修改。图4A-图4B是根据本公开的一些实施例的形成半导体器件结构10c的各个阶段的截面图。一些工艺或器件与上述实施例中描述的那些相同或类似,并且因此在此不再重复描述这些工艺和器件。与以上结合图2A至图2J描述的实施例相比,一个明显的区别是,如图4A所示,沟槽158进一步延伸至源极/漏极外延结构128中。
在一些实施例中,源极/漏极外延结构128在形成沟槽158时被进一步蚀刻。在一些实施例中,源极/漏极外延结构128的边缘部分128b被蚀刻。在一些实施例中,蚀刻工艺包括使用基于Ar或基于Cl的蚀刻剂气体的干蚀刻工艺。在一些实施例中,蚀刻工艺在源极/漏极外延结构128和第一硅化物层152a之间提供蚀刻选择性。这尤其正确,因为伪层148和硬掩模层142都可以由半导体材料形成,如源极/漏极外延结构128。因此,第一硅化物层152a可能不会被损坏,并且电阻可能不会增加。此外,沟槽158附近的第二半导体层106也在蚀刻工艺之后保留。
之后,形成延伸至源极/漏极外延结构128中的空气间隔件162。由于空气间隔件162的总高度更大,因此可以减小寄生电容。在一些实施例中,空气间隔件162的底面较浅或与第一硅化物层152a的底面具有相同的深度。如果空气间隔件162比第一硅化物层152a的底面进一步延伸至源极/漏极外延结构128中,则寄生电容可能不会进一步减小。在图4B所示的实施例中,空气间隔件162可以具有约1nm和约10nm之间的宽度和约15nm和约35nm之间的高度。在这些实施例中,空气间隔件162可以具有约3.5和约15之间的高宽比。
在通过相同材料形成伪层148和栅极结构132上方的硬掩模层142的情况下,在去除伪层148和硬掩模层142之后,可以在保护层150和间隔件层120之间形成沟槽158。密封衬垫层160沉积在沟槽158上方,并且可以形成空气间隔件162。通过在间隔件层120和接触结构156之间形成空气间隔件162,可以降低寄生电容。虽然允许空气间隔件162进一步延伸至源极/漏极外延结构128中可以进一步减小寄生电容,但是这种过度向下延伸的空气间隔件162可能禁用至最顶部沟道区206。
可以对本公开的实施例进行许多变化和/或修改。图5A-图5C是根据本公开的一些实施例的形成半导体器件结构10d(图5C所示)的各个阶段的截面图。一些工艺或器件与上述实施例中描述的那些相同或类似,并且因此在此不再重复描述这些工艺和器件。与以上结合图2A至图2J描述的实施例相比,一个明显的区别是,如图5A和图5B所示,空气间隔件162的顶面较高并且空气间隔件162进一步延伸至源极/漏极外延结构128中。在图5C所示的实施例中,空气间隔件162可以具有约1nm和约10nm之间的宽度以及约35nm和约55nm之间的高度。在这些实施例中,空气间隔件162可以具有约5.5和约3.5之间的高宽比。
根据一些实施例,如图5A所示,间隔件层120可以由较硬的材料(即,较慢蚀刻材料)制成,并且在形成硬掩模层142时间隔件层120较高。随后,根据一些实施例,如图5B所示,将沟槽158进一步蚀刻到源极/漏极外延结构128中。因此,在一些实施例中,空气间隔件162高于栅极结构132。在一些实施例中,空气间隔件162的顶面高于栅极结构132的顶面,并且空气间隔件162的底面低于栅极结构132的底面。
根据一些实施例,如图5A所示,通过组合图3A-图3C和图4A-图4B所示的实施例的特征,所得到的空气间隔件162更高。因此,可以进一步减小寄生电容。
在伪层148和栅极结构132上方的硬掩模层142由相同材料形成的情况下,在去除伪层148和硬掩模层142之后,可以在保护层150和间隔件层120之间形成沟槽158。密封衬垫层160沉积在沟槽158上方,并且可以形成空气间隔件162。通过在间隔件层120和接触结构156之间形成空气间隔件162,可以降低寄生电容。由于间隔件层120由较硬的材料制成,并通过沟槽158进一步蚀刻源极/漏极外延结构128,因此空气间隔件162可以更高,并且可以进一步降低寄生电容。
可以对本公开的实施例进行许多变化和/或修改。图6是根据本公开的一些实施例的半导体器件结构10e的截面图。一些工艺或器件与上述实施例中描述的那些相同或类似,并且因此在此不再重复描述这些工艺和器件。与以上结合图2A至图2J描述的实施例相比,一个明显的区别是,如图6所示,在填充膜164中形成空隙168。
在一些实施例中,填充膜164可以通过具有较少孔填充能力的类PVD沉积工艺形成,从而使得填充膜164可能过早合并,从而在填充膜164中留下空隙168。示例性类PVD沉积工艺可以包括PVD工艺或CVD工艺。为了形成空隙168,填充膜164可以不使用具有良好孔填充能力的沉积技术形成,该沉积技术诸如ALD、FCVD、旋涂或PECVD。空隙168形成在相邻接触结构156之间的栅极结构132上方。因此,相邻接触结构156之间的寄生电容可以通过填充膜164中的空隙168来减小。在一些实施例中,空隙168在形成填充膜164时形成。
在一些实施例中,由于空隙168由于填充膜164悬垂而形成,所以空隙168的底部比空隙168的顶部宽。
在伪层148和栅极结构132上方的硬掩模层142由相同材料形成的情况下,在去除伪层148和硬掩模层142之后,可以在保护层150和间隔件层120之间形成沟槽158。密封衬垫层160沉积在沟槽158上方,并且可以形成空气间隔件162。通过在间隔件层120和接触结构156之间形成空气间隔件162,可以降低寄生电容。可以在填充层164中形成空隙168,并且可以减小相邻接触结构156之间的寄生电容。
可以对本公开的实施例进行许多变化和/或修改。图7A-图7F是根据本公开的一些实施例的形成半导体器件结构10f(图7F所示)的各个阶段的截面图。一些工艺或器件与上述实施例中描述的那些相同或类似,并且因此在此不再重复描述这些工艺和器件。与以上结合图2A至图2J描述的实施例相比,一个明显的区别是,如图7A所示,伪层148较厚,并且保护层150未形成在伪层148的侧壁上方。
接下来,根据一些实施例,如图7B所示,在硅化物工艺中通过退火步骤在源极/漏极外延结构128上方形成第一硅化物层152a的同时,当伪层148由半导体材料(诸如Si、Ge或SiGe)形成时,在伪层148的侧壁上方形成第二硅化物层152b。第二硅化物层152b可以是第二金属半导体层152b并且可以具有与第一硅层152a类似或不同的组分。当伪层148和源极/漏极部件128的组分相同时,第一硅化物层152a和第二硅化物层152b可以具有相同的组分。当伪层148和源极/漏极极部件128的组分不同时,第一硅化物层152a和第二硅化物层152b可以具有不同的组分。在一些实施例中,第二硅化物层152b仅形成在伪层148的靠近接触结构156的表面上方。在一些实施例中,第二硅化物层152b沿着伪层148的侧壁形成并且与接触结构156接触。在一些实施例中,靠近栅极结构132的伪层148保留。
在一些实施例中,当形成第一硅化物层152a和第二硅化物层152b时,硅化物工艺中的退火步骤的退火温度在约400℃至约800℃的范围内。在一些实施例中,形成第一硅化物层152a和第二硅化物层152b的硅化物工艺中的退火步骤的退火持续时间在约30秒至约10分钟的范围内。
接下来,根据一些实施例,如图7C所示,在平坦化工艺之后,在第二硅化物层152b旁边形成接触结构156。硬掩模142的顶面可以在平坦化工艺之后暴露。在平坦化工艺之后,接触结构156的顶面可以与硬掩模层142、伪层148和第二硅化物层152b的顶面齐平。平坦化工艺可以与前述实施例中的平坦化工艺相同或类似。为简洁起见,在此不再重复描述这些工艺。
接下来,根据一些实施例,如图7D所示,去除硬掩模层142和伪层148,并且在间隔件层120和第二硅化物层152b之间形成沟槽158。在一些实施例中,间隔件层120和第二硅化物层152b的侧壁以及源极/漏极外延结构128的部分顶面从沟槽158暴露。去除工艺可以与前述实施例中的去除工艺相同或类似。为简洁起见,在此不再重复描述这些工艺。
接下来,根据一些实施例,如图7E所示,在栅极结构132和接触结构156上方形成密封衬垫层160。在一些实施例中,沟槽158被密封,并且空气间隔件162形成在间隔件层120和第二硅化物层152b之间的密封衬垫层160下方,根据一些实施例,如图7E所示。用于形成密封衬垫层160的工艺可以与前述实施例中形成密封衬垫层160的形成工艺相同或类似。为简洁起见,在此不再重复描述这些工艺。
之后,根据一些实施例,如图7E所示,填充膜164填充在密封衬垫层160上方。随后,根据一些实施例,如图7F所示,在填充膜164上方执行平坦化工艺直至暴露密封衬垫层160的顶面。接下来,根据一些实施例,如图7F所示,在填充膜164和密封衬垫层160上方形成第二接触蚀刻停止层166。用于形成填充膜164和第二接触刻蚀停止层166的工艺可以与前述实施例中形成填充膜164和第二接触刻蚀停止层166的工艺相同或类似。为简洁起见,在此不再重复描述这些工艺。
在伪层148和栅极结构132上方的硬掩模层142由相同材料形成的情况下,在去除伪层148和硬掩模层142之后,可以在保护层150和间隔件层120之间形成沟槽158。密封衬垫层160沉积在沟槽158上方,并且可以形成空气间隔件162。通过在间隔件层120和接触结构156之间形成空气间隔件162,可以降低寄生电容。较厚的伪层148可能在硅化物工艺中发生反应,并且第二硅化物层152b可以形成在靠近接触结构156的伪层148中。第二硅化物层152b可以代替保护层150。因此,可以跳过形成保护层150的工艺,并且可以减少生产时间和成本。
如前所述,在间隔件层120和接触结构156之间形成空气间隔件162,可以降低寄生电容。在间隔件层120旁的伪层148与栅极结构132上方的硬掩模层142由相同材料形成的情况下,可以在同一工艺中去除伪层148和硬掩模层142,并且当沉积密封衬垫层160时,伪层148和硬掩模层142之间的高度差可有助于形成空气间隔件162。在如图3C所示的一些实施例中,空气间隔件162的高度通过增加间隔件层120的抗蚀刻性而增加。空气间隔件162越高,寄生电容进一步降低。在如图4B所示的一些实施例中,空气间隔件162延伸至源极/漏极外延结构128中,空气间隔件162的高度增加。在如图5C所示的一些实施例中,间隔件层120的抗蚀刻性增加,并且源极/漏极外延结构128被进一步蚀刻,使得空气间隔件162的总高度进一步增加。在如图6所示的一些实施例中,在填充膜164中形成空隙168。接触结构156之间的寄生电容通过空隙168减小。在如图7A所示的一些实施例中,在间隔件层120和第二硅化物层152b之间形成空气间隔件,第二硅化物层152b沿着伪层148的靠近接触结构156的侧壁形成。
提供了半导体器件结构及其形成方法的实施例。用于形成半导体器件结构的方法可以包括在栅极结构和接触结构上方沉积密封衬垫层,并且在间隔件层和保护层之间形成空气间隔件。利用空气间隔件,可以减少寄生电容。
在一些实施例中,提供了半导体器件结构。半导体器件结构包括形成在衬底上方的纳米结构。半导体器件结构还包括形成在纳米结构上方和周围的栅极结构。半导体器件结构还包括在纳米结构上方的栅极结构的侧壁上方形成的间隔件层。半导体器件结构还包括邻近间隔件层形成的源极/漏极外延结构。半导体器件结构还包括形成在源极/漏极外延结构上方的接触结构,以及形成在间隔件层和接触结构之间的空气间隔件。
在一些实施例中,半导体器件结构还包括:保护层,形成在所述接触结构的侧壁上方,其中,所述空气间隔件设置在所述保护层和所述栅极结构之间。在一些实施例中,半导体器件结构还包括:密封衬垫层,沉积在所述栅极结构和所述接触结构上方,其中,所述密封衬垫层沉积在所述空气间隔件上方。在一些实施例中,所述空气间隔件高于所述栅极结构。在一些实施例中,所述空气间隔件延伸至所述源极/漏极外延结构中。在一些实施例中,所述空气间隔件的顶面高于所述栅极结构的顶面,并且所述空气间隔件的底面低于所述栅极结构的底面。在一些实施例中,所述空气间隔件的顶面低于所述接触结构的顶面。
在一些实施例中,提供了半导体器件结构。半导体器件结构包括形成在衬底上方的鳍结构。半导体器件结构还包括形成在鳍结构上方的纳米结构。半导体器件结构还包括包裹纳米结构的栅极结构。半导体器件结构还包括在纳米结构之上的栅极结构的相对侧上方形成的间隔件层。半导体器件结构还包括形成在纳米结构的相对侧上方的源极/漏极外延结构。半导体器件结构还包括形成在源极/漏极外延结构上方的接触结构。半导体器件结构还包括形成在接触结构的侧壁上方的保护层,以及形成在间隔件层和保护层之间的空气间隔件。
在一些实施例中,半导体器件结构还包括:密封衬垫层,覆盖所述栅极结构和所述接触结构,其中,所述密封衬垫层和所述保护层由不同的材料制成。在一些实施例中,所述空气间隔件的顶面低于所述间隔件层的顶面。在一些实施例中,半导体器件结构还包括:第一硅化物层,形成在所述源极/漏极外延结构上方;第二硅化物层,形成在所述接触结构的侧壁上方,其中,所述空气间隔件位于所述第二硅化物层和所述间隔件层之间。在一些实施例中,半导体器件结构还包括:填充膜,形成在所述接触结构之间的所述栅极结构上方。在一些实施例中,半导体器件结构还包括:空隙,设置在所述填充膜中。
在一些实施例中,提供了用于形成半导体器件结构的方法。用于形成半导体器件结构的方法还包括在衬底上方形成纳米结构。用于形成半导体器件结构的方法还包括在纳米结构周围和上方形成栅极结构。用于形成半导体器件结构的方法还包括在纳米结构上方的栅极结构的相对侧上方形成间隔件层。用于形成半导体器件结构的方法还包括在间隔件层的侧壁上方形成伪层。用于形成半导体器件结构的方法还包括在栅极结构旁边形成接触结构。用于形成半导体器件结构的方法还包括去除伪层以在间隔件层和接触结构之间形成空气间隔件。用于形成半导体器件结构的方法还包括在栅极结构、接触结构和空气间隔件上方沉积密封衬垫层。
在一些实施例中,用于形成半导体器件结构的方法还包括:在形成所述接触结构之前,在所述伪层的侧壁上方形成保护层,其中,所述空气间隔件形成在所述间隔件层和所述保护层之间。在一些实施例中,用于形成半导体器件结构的方法还包括:对所述伪层进行退火以在所述伪层的与所述接触结构接触的部分中形成第二硅化物层,其中,所述空气间隔件形成在所述间隔件层和所述第二硅化物层之间。在一些实施例中,用于形成半导体器件结构的方法还包括:在所述密封衬垫层上方形成填充膜;以及在所述填充膜上方沉积接触蚀刻停止层。在一些实施例中,用于形成半导体器件结构的方法还包括:在形成所述填充膜的同时在所述栅极结构上方的所述填充膜中形成空隙。在一些实施例中,用于形成半导体器件结构的方法还包括:在所述纳米结构旁边形成源极/漏极外延结构,其中,形成所述伪层包括在所述源极/漏极外延结构上形成伪层,其中,去除所述伪层包括蚀刻所述源极/漏极外延结构的位于所述伪层下方的部分。在一些实施例中,用于形成半导体器件结构的方法还包括:在形成所述伪层之前,在所述栅极结构上方形成硬掩模层;以及去除所述伪层时去除所述硬掩模层。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种半导体器件结构,包括:
纳米结构,形成在衬底上方;
栅极结构,形成在所述纳米结构上方和周围;
间隔件层,形成在所述纳米结构上方的所述栅极结构的侧壁上方;
源极/漏极外延结构,形成为邻近所述间隔件层;
接触结构,形成在所述源极/漏极外延结构上方;以及
空气间隔件,设置在所述间隔件层和所述接触结构之间。
2.根据权利要求1所述的半导体器件结构,还包括:
保护层,形成在所述接触结构的侧壁上方,
其中,所述空气间隔件设置在所述保护层和所述栅极结构之间。
3.根据权利要求1所述的半导体器件结构,还包括:
密封衬垫层,沉积在所述栅极结构和所述接触结构上方,
其中,所述密封衬垫层沉积在所述空气间隔件上方。
4.根据权利要求1所述的半导体器件结构,其中,所述空气间隔件高于所述栅极结构。
5.根据权利要求1所述的半导体器件结构,其中,所述空气间隔件延伸至所述源极/漏极外延结构中。
6.根据权利要求1所述的半导体器件结构,其中,所述空气间隔件的顶面高于所述栅极结构的顶面,并且所述空气间隔件的底面低于所述栅极结构的底面。
7.根据权利要求1所述的半导体器件结构,其中,所述空气间隔件的顶面低于所述接触结构的顶面。
8.一种半导体器件结构,包括:
鳍结构,形成在衬底上方;
纳米结构,形成在所述鳍结构上方;
栅极结构,包裹所述纳米结构;
间隔件层,形成在所述纳米结构之上的所述栅极结构的相对侧上方;
源极/漏极外延结构,形成在所述纳米结构的相对侧上方;
接触结构,形成在所述源极/漏极外延结构上方;
保护层,形成在所述接触结构的侧壁上方;以及
空气间隔件,设置在所述间隔件层和所述保护层之间。
9.根据权利要求8所述的半导体器件结构,还包括:
密封衬垫层,覆盖所述栅极结构和所述接触结构,
其中,所述密封衬垫层和所述保护层由不同的材料制成。
10.一种用于形成半导体器件结构的方法,包括:
在衬底上方形成纳米结构;
在所述纳米结构周围和上方形成栅极结构;
在所述纳米结构上方的所述栅极结构的相对侧上方形成间隔件层;
在所述间隔件层的侧壁上方形成伪层;
在所述栅极结构旁边形成接触结构;
去除所述伪层以在所述间隔件层和所述接触结构之间形成空气间隔件;以及
在所述栅极结构、所述接触结构和所述空气间隔件上方沉积密封衬垫层。
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