CN115000251A - Preparation method of GaP surface treated ITO structure LED - Google Patents
Preparation method of GaP surface treated ITO structure LED Download PDFInfo
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- CN115000251A CN115000251A CN202210590382.2A CN202210590382A CN115000251A CN 115000251 A CN115000251 A CN 115000251A CN 202210590382 A CN202210590382 A CN 202210590382A CN 115000251 A CN115000251 A CN 115000251A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
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- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 16
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- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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Abstract
The invention relates to the technical field of LEDIn particular to a preparation method of an ITO structure LED with GaP surface treatment, which comprises the following steps: growing an LED epitaxial material; SiO 2 2 Etching the mask and GaP; processing the surface of the GaP window layer; depositing an ITO thin film; preparing a P electrode; preparing an N electrode; and cutting to obtain the required chip. According to the preparation method, the surface of the thinned GaP material is bombarded by the argon plasma, so that the P-type doping concentration of the surface thin layer can be effectively reduced, the surface layer is etched into a rough interface, the contact resistance of the position is increased, the transverse expansion capability of the current is improved, and the light extraction efficiency is improved.
Description
Technical Field
The invention relates to the technical field of LEDs, in particular to a preparation method of an ITO structure LED with GaP surface treatment.
Background
Light Emitting Diodes (LEDs) have the advantages of high light efficiency, low energy consumption, long lifetime, high reliability, high safety, environmental friendliness, etc., and are a recognized green light source of a new generation. Currently, LEDs have been widely used in the field of high-efficiency solid-state lighting, such as display screens, automotive lights, backlights, traffic lights, landscape lighting, and the like. The LED prepared from the quaternary AlGaInP material can cover red, orange, yellow and yellow-green light bands, and ITO (indium tin oxide) thin films with high light transmittance and good conductivity are generally adopted in the industry as transparent electrode materials for improving the brightness of AlGaInP-based LED chips.
In a general practical LED chip growth process, an ITO thin film is deposited on a GaP layer of an epitaxial wafer, and then a metal electrode is evaporated to be used as a conductive pad material, however, since the metal electrode completely blocks light, if a current is excessively concentrated under the electrode to emit light, the light emitting efficiency of the whole LED is very low, and the brightness is also affected accordingly. In the industry, the GaP material below the metal electrode is generally etched and thinned to achieve the purpose of improving the light emitting efficiency, but the current spreading and the light emitting brightness are still not ideal. Therefore, it is very critical to solve the current spreading problem of the ITO structure LED chip.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a preparation method of an ITO structure LED with a GaP surface treatment, which can effectively reduce the P-type doping concentration of a thin layer on the GaP surface by bombarding the GaP surface below an electrode by argon plasma, thereby enlarging the contact resistance below the electrode, being beneficial to guiding the transverse expansion of current and improving the light extraction efficiency.
The invention aims to provide a preparation method of an LED with an ITO structure subjected to GaP surface treatment, which comprises the following specific steps:
s1, growing the LED epitaxial material: growing a GaAs buffer layer, an N-type limiting layer, an N-surface space layer, a multi-quantum well active layer, a P-surface space layer, a P-type limiting layer, a P-type transition layer and a GaP window layer on a GaAs substrate upwards in sequence;
S2、SiO 2 mask and GaP etching: depositing SiO on the GaP surface of the GaP window layer 2 As a mask, patterning by photolithography, and etching the SiO layer at the position corresponding to the position right below the P electrode with an etching solution 2 And GaP;
s3, surface treatment of a GaP window layer: putting the wafer into an ICP (inductively coupled plasma) etching machine, performing argon plasma bombardment treatment on the GaP material at the corresponding position under a preset P electrode, washing with deionized water, and soaking with corrosive liquid to remove SiO on the surface 2 ；
S4, ITO film deposition: depositing an ITO film on the surface of the GaP window layer processed by S3 by utilizing a PECVD (plasma enhanced chemical vapor deposition) technology;
s5, preparing a P electrode: coating negative photoresist on the surface of the ITO film by utilizing a photoetching patterning technology, baking, exposing and developing, putting the wafer into electron beam evaporation equipment, and evaporating a P electrode;
s6, preparing an N electrode: after the GaAs substrate is thinned by grinding and polishing technologies, putting the wafer into electron beam evaporation equipment, and evaporating an N electrode;
s7, cutting: and cutting and separating the periphery of the prepared wafer by using a grinding wheel or laser to obtain the required chip.
Argon plasma bombardment is used as a pure physical etching surface treatment method, and can bombard phosphorus elements on a thin GaP surface layer to generate a large number of group-five element vacancies, which are donor impurities for a group-III-group-V element semiconductor, so as to achieve the effect of surface modification. According to the invention, after the GaP window layer is thinned, the surface of the thinned GaP material is bombarded by argon plasma by using ICP equipment, then an ITO transparent conductive film is deposited, and then a P electrode is evaporated to effectively reduce the P-type doping concentration of the surface thin layer, so that the contact resistance below the electrode is large, the current is not easy to gather below the shading metal electrode, the transverse extension of the current is guided, and the light extraction efficiency is improved.
Further, in the technical scheme S3, the working pressure of the ICP is 0.5Pa to 1Pa, the power of the upper electrode is 280W to 320W, the power of the lower electrode is 100W to 120W, the flow rate of argon is 100sccm to 1000sccm, and the etching time is 8min to 10 min.
Further, in the above technical solution S3, the thickness of the GaP window layer after being processed and thinned is 100nm to 200 nm.
Further, in the above technical solution S2, the etching solution is a mixture of iodic acid, hydrochloric acid, and deionized water at a volume ratio of 1:3: 100.
Further, in the above technical solution S4, the thickness of the deposited ITO thin film is 200nm to 300 nm.
Further, in the above technical solution, the material of the P electrode is one or a combination of more of Au, Zn, Pt, Al, and Ti.
Further, in the above technical solution, the N-type confinement layer and the P-type confinement layer are both made of AlInP; the N-plane spatial layer, the P-plane spatial layer and the P-type transition layer are all made of AlGaInP.
The second purpose of the invention is to provide an ITO structure LED chip prepared by the preparation method.
Compared with the prior art, the invention has the following beneficial effects:
1. after the GaP window layer is thinned, the surface of the thinned GaP material is bombarded by using argon plasma through utilizing an ICP (inductively coupled plasma) technology, phosphorus elements on the surface of the GaP window layer can be bombarded to generate a large number of group-five element vacancies, the P-type doping concentration of the surface thin layer can be reduced, the surface layer is etched into a rough interface, the contact resistance of the position is increased, and therefore the transverse expansion capability and the light extraction efficiency of current are improved.
2. The preparation method provided by the invention is basically consistent with the existing process, no extra complicated process is added, the light emitting efficiency of the LED chip can be improved on the basis of the existing technology, the repeatability is high, and the preparation method has an important significance for mass production.
Drawings
FIG. 1 is a schematic view of an epitaxial material structure of an LED chip with an ITO structure;
FIG. 2 is a schematic diagram of an LED chip with an ITO structure typical in the industry;
fig. 3 is a schematic view of an LED chip structure with an ITO structure treated by GaP surface according to the invention;
FIG. 4 is a test chart of wavelength and brightness of an LED chip with an ITO structure typical in the industry, wherein a is a brightness test chart, and b is a wavelength test chart;
FIG. 5 is a test chart of wavelength and brightness of an LED chip with an ITO structure prepared by the invention, wherein a is a brightness test chart, and b is a wavelength test chart.
Number in the schematic diagrams illustrates:
a GaAs substrate; a GaAs buffer layer; an N-type confinement layer; an N-plane spatial layer; 5. a multiple quantum well active layer; a P-plane spatial layer; a P-type confinement layer; a P-type transition layer; GaP window layer; an ITO film; a P-type electrode; an N-type electrode.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the application, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be understood that the terms "first", "second", etc. are used to define the components, and are used only for the convenience of distinguishing the corresponding components, and if not otherwise stated, the terms have no special meaning, and thus, should not be construed as limiting the scope of the present application.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
Referring to fig. 1 to 5, it should be noted that the drawings provided in the present embodiment are only schematic illustrations of the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be changed arbitrarily, and the layout configuration of the components may be more complicated.
At present, the preparation method of the typical ITO structure LED chip in the industry mainly comprises the following steps:
1. epitaxial material structure preparation
The structural schematic diagram of the epitaxial material of the LED chip with the ITO structure is shown in figure 1, and the epitaxial material of the LED chip with the ITO structure grows on a GaAs substrate 1 by utilizing the technology and equipment of Metal Organic Chemical Vapor Deposition (MOCVD), and sequentially comprises a GaAs buffer layer 2, an N-type limiting layer 3, an N-surface space layer 4, a multi-quantum well active layer 5, a P-surface space layer 6, a P-type limiting layer 7, a P-type transition layer 8 and a GaP window layer 9 from bottom to top.
2. The preparation process of the ITO structure LED chip comprises the following steps:
(1) cleaning the surface of the epitaxial structure by using an organic matter cleaning agent;
(2) depositing SiO on the GaP surface of the GaP window layer 9 2 As a mask, etching the SiO at the position corresponding to the position right below the preset P electrode by photoetching and patterning 2 And GaA P material;
(3) solution corrosion for removing SiO 2 Masking, and then depositing an ITO film 10 transparent conductive film on the surface of the wafer;
(4) coating negative photoresist for electrode stripping on the surface of a wafer through photoetching patterning, and then evaporating a P electrode 11;
(5) removing the metal electrode above the photoresist by using a metal stripping technology, then removing the photoresist, and cleaning the photoresist by using deionized water;
(6) grinding, thinning and polishing the substrate on the back of the wafer, and then evaporating an N electrode 12 on the surface of the substrate;
(7) the schematic structural diagram of the prepared ITO structure LED chip is shown in FIG. 2 by cutting and separating the chip along the periphery of the chip by using laser or a grinding wheel.
However, although the etching and thinning of the GaP window layer material under the P electrode can play a positive role in current spreading, the ITO-structured LED chip typically used in the industry still has significant disadvantages: even if the GaP window layer material is thinned, the doping concentration of the GaP window layer under the P electrode is still higher, which can reach 1 × 10 18 cm -3 ～5×10 18 cm -3 Still, more current is gathered under the electrode to emit light, which affects current spreading and light extraction efficiency.
In order to further solve the problems in the prior art, after the GaP window layer is thinned by using an etching solution, an ICP (inductively coupled plasma) device is used for bombarding the surface of the thinned GaP material by argon plasma, then an ITO (indium tin oxide) transparent conductive film is deposited, and finally a P electrode is evaporated.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment of the invention provides a preparation method of an ITO structure LED with GaP surface treatment, which comprises the following specific steps:
s1, growing an LED epitaxial material with an ITO structure: the structural schematic diagram of the epitaxial material is shown in fig. 1, and the epitaxial material comprises the following components from bottom to top: the GaAs substrate 1, GaAs buffer layer 2, N type limiting layer 3, N face space layer 4, multi-quantum well active layer 5, P face space layer 6, P type limiting layer 7, P type transition layer 8, GaP window layer 9;
specifically, the epitaxial material is prepared by using an MOCVD (metal organic chemical vapor deposition) technology, the used metal organic source materials comprise trimethyl gallium, trimethyl aluminum, trimethyl indium, cyclopentadienyl magnesium and carbon tetrachloride, the five-group element source materials comprise arsine, phosphine and silane, the source materials are carried into a reaction chamber by carrier gas, the epitaxial material grows layer by layer in a low-pressure environment with the growth temperature of 600-800 ℃, and specifically, the component and the doping concentration of each single epitaxial layer are regulated and controlled by corresponding flow and growth temperature.
S2、SiO 2 Mask and GaP etching: depositing SiO on the GaP surface of the GaP window layer 2 As a mask, etching the SiO at the position corresponding to the position right below the preset P electrode by photoetching and patterning 2 And GaP;
specifically, an organic cleaning solution is used for cleaning the surface of the epitaxial structure;
depositing SiO on the surface of GaP window layer by PECVD technology 2 The film is patterned by photoetching, coated with positive photoresist, exposed and developed;
preparing a GaP etching solution with iodic acid: hydrochloric acid: soaking the wafer in the corrosive liquid for 5-6 min, then washing the wafer with deionized water for 10min, and spin-drying the wafer with a spin dryer;
SiO removal by degumming solution 2 And (5) masking residual photoresist on the surface layer.
S3, surface treatment of a GaP window layer: putting the wafer into an ICP etching machine, performing argon plasma bombardment treatment on the GaP material at the corresponding position under the preset P electrode, washing with deionized water, and soaking with an etching solution to remove SiO on the surface 2 ；
Specifically, the wafer is placed in an ICP etching machine, and the working conditions are as follows: the working pressure is 0.5 Pa-1 Pa, the power of an upper electrode is 280W-320W, the power of a lower electrode is 100W-120W, the flow of argon is 100 sccm-1000 sccm, and the etching time is 8 min-10 min;
after surface treatment, the substrate was rinsed with deionized water for 10min, then hydrofluoric acid: soaking and cleaning the surface to remove SiO by using a 1:10 deionized water corrosive solution 2 The time is 10min, then the mixture is washed by deionized water for 10min and is dried by a drying machine
S4, ITO film deposition: depositing an ITO film on the surface of the GaP window layer processed by S3 by utilizing a PECVD technology;
specifically, the thickness of the deposited ITO film is 200 nm-300 nm;
s5, preparing a P electrode: coating negative photoresist on the surface of the ITO film by utilizing a photoetching patterning technology, baking, exposing and developing, putting the wafer into electron beam evaporation equipment, and evaporating a P electrode;
specifically, a negative photoresist is coated on the surface of the ITO film by utilizing a photoetching patterning technology, and the ITO film is baked, exposed and developed;
putting the wafer into an electron beam evaporation device, and setting the vacuum of a cavity to be 1 multiplied by 10 -4 Baking at the temperature of Pa and 120 ℃ for 20min, then cooling to 80 ℃ to evaporate the metal of the P electrode, wherein the evaporated P electrode is made of one or more of Au, Zn, Pt, Al and Ti;
removing metals except the P electrode by using a metal stripping machine;
soaking the wafer in a photoresist solution to remove residual photoresist, then washing with deionized water for 10min, and spin-drying with a spin dryer;
s6, preparing an N electrode: after the GaAs substrate is thinned by grinding and polishing technologies, putting the wafer into electron beam evaporation equipment, and evaporating and plating an N electrode;
specifically, the GaAs substrate is thinned by utilizing grinding and polishing technologies;
putting the wafer into an electron beam evaporation device, and setting the vacuum of a cavity to be 1 multiplied by 10 -4 And Pa, baking at 120 ℃ for 20min, and evaporating N electrode metal at 120 ℃, wherein the evaporated N electrode material is a Ni/Au/Ge/Au laminated metal combination.
S7, cutting: cutting and separating the periphery of the prepared wafer by using a grinding wheel or laser to obtain the ITO structure LED chip with the GaP surface treatment, wherein the structural schematic diagram is shown in fig. 3.
Based on all the above embodiments of the present invention, in another embodiment of the present invention, there is further provided an ITO structure LED chip, as shown in fig. 3, the ITO structure LED chip includes, from bottom to top, an N electrode 12, a GaAs substrate 1, a GaAs buffer layer 2, an N-type confinement layer 3, an N-plane spatial layer 4, a multiple quantum well active layer 5, a P-plane spatial layer 6, a P-type confinement layer 7, a P-type transition layer 8, a GaP window layer 9, an ITO thin film 10, and a P electrode 11;
and (3) performing argon plasma bombardment treatment on the GaP surface of the GaP window layer at the corresponding position under the P electrode, then depositing an ITO film, and then preparing the P electrode by evaporation.
Specifically, the device used for processing the GaP surface is an inductively coupled plasma etcher (ICP), the gas participating in etching is argon, and the GaP surface is physically etched by the argon plasma formed by ionization in the ICP device. The scheme can generate five-group element vacancies on the GaP surface layer, and simultaneously etch the surface layer into a rough interface, thereby increasing the contact resistance of the position and improving the lateral expansion capability of the current.
Typical ITO structure LED chips in the industry and the ITO structure LED chips with GaP surface treatment prepared by the invention are respectively put into an LED wafer point measuring machine for wavelength and brightness test, and the results are shown in fig. 4 and fig. 5. The chip sizes are all 106 micrometers multiplied by 106 micrometers, the test currents are all 20mA, and the test equipment is an LED chip point test machine.
As can be seen from the test results of FIG. 4, the typical ITO structure LED chip in the industry has a light-emitting wavelength of 621-622 nm, and the light-emitting brightness is mainly distributed in the range of 135-145 mcd; as can be seen from the test results of FIG. 5, the LED chip with the ITO structure prepared by the method has the light-emitting wavelength of 621-622 nm, and the light-emitting brightness is mainly distributed in 165-175 mcd. Comparing the data of the two, the LED chip of the invention can be seen to improve the brightness by about 20% compared with the LED chip with the TIO structure in the industry.
Finally, it should be emphasized that the above-described preferred embodiments of the present invention are merely examples of implementations, rather than limitations, and that many variations and modifications of the invention are possible to those skilled in the art, without departing from the spirit and scope of the invention.
Claims (9)
1. A preparation method of an ITO structure LED with GaP surface treatment is characterized by comprising the following specific steps:
s1, growing the LED epitaxial material: growing a GaAs buffer layer, an N-type limiting layer, an N-surface space layer, a multi-quantum well active layer, a P-surface space layer, a P-type limiting layer, a P-type transition layer and a GaP window layer on a GaAs substrate upwards in sequence;
S2、SiO 2 mask and GaP etching: depositing SiO on the GaP surface of the GaP window layer 2 As a mask, etching the SiO at the position corresponding to the position right below the preset P electrode by using an etching solution through photoetching patterning 2 And GaP;
s3, surface treatment of a GaP window layer: putting the wafer into an ICP etching machine, performing argon plasma bombardment treatment on the GaP material at the corresponding position under the preset P electrode, washing with deionized water, and soaking with an etching solution to remove SiO on the surface 2 ；
S4, ITO film deposition: depositing an ITO film on the surface of the GaP window layer processed in S3 by using a PECVD (plasma enhanced chemical vapor deposition) technology;
s5, preparing a P electrode: coating negative photoresist on the surface of the ITO film by utilizing a photoetching patterning technology, baking, exposing and developing, putting the wafer into electron beam evaporation equipment, and evaporating a P electrode;
s6, preparing an N electrode: after the GaAs substrate is thinned by grinding and polishing technologies, putting the wafer into electron beam evaporation equipment, and evaporating an N electrode;
s7, cutting: and cutting and separating the periphery of the prepared wafer by using a grinding wheel or laser to obtain the required chip.
2. The method of claim 1, wherein in S3, the ICP has a working pressure of 0.5Pa to 1Pa, an upper electrode power of 280W to 320W, a lower electrode power of 100W to 120W, an argon flow of 100sccm to 1000sccm, and an etching time of 8min to 10 min.
3. The method of claim 1, wherein in S3, the thickness of the GaP window layer is thinned to 100nm to 200nm after surface treatment.
4. The method of claim 1, wherein in S2, the etching solution is a mixture of iodic acid, hydrochloric acid, and deionized water at a volume ratio of 1:3: 100.
5. The method of claim 1, wherein in S4, the ITO film is deposited to a thickness of 200nm to 300 nm.
6. The method of claim 1, wherein the P electrode is made of one or more of Au, Zn, Pt, Al and Ti.
7. The method of claim 1, wherein the N electrode is made of a stacked metal combination of Ni/Au/Ge/Au.
8. The method of claim 1, wherein the N-type and P-type confinement layers are made of AlInP; the N-plane spatial layer, the P-plane spatial layer and the P-type transition layer are all made of AlGaInP.
9. An LED chip of ITO structure prepared by the preparation method of any one of claims 1 to 8.
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