CN112750929A - P-GAN layer modified LED chip and manufacturing method thereof - Google Patents
P-GAN layer modified LED chip and manufacturing method thereof Download PDFInfo
- Publication number
- CN112750929A CN112750929A CN202110102443.1A CN202110102443A CN112750929A CN 112750929 A CN112750929 A CN 112750929A CN 202110102443 A CN202110102443 A CN 202110102443A CN 112750929 A CN112750929 A CN 112750929A
- Authority
- CN
- China
- Prior art keywords
- gan layer
- layer
- led chip
- gan
- ito transparent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000004048 modification Effects 0.000 claims abstract description 4
- 238000012986 modification Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 24
- 238000002161 passivation Methods 0.000 claims description 24
- 238000000059 patterning Methods 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 12
- 238000001704 evaporation Methods 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 abstract description 5
- 238000002347 injection Methods 0.000 abstract description 4
- 239000007924 injection Substances 0.000 abstract description 4
- 229910002601 GaN Inorganic materials 0.000 description 68
- 239000000243 solution Substances 0.000 description 17
- 230000008021 deposition Effects 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 238000001259 photo etching Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 239000012459 cleaning agent Substances 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N SnO2 Inorganic materials O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000011259 mixed solution Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000004506 ultrasonic cleaning Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- -1 indium tin metal oxide Chemical class 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a P-GAN layer modified LED chip and a manufacturing method thereof, wherein the LED chip sequentially comprises the following layers from bottom to top: the ITO transparent conducting layer is arranged on the top layer; the upper surface of the epitaxial wafer is a P-GaN layer; and the P-GaN layer needs to be subjected to plasma bombardment modification treatment. The P-GaN layer is modified, so that the crystal structure on the surface of the P-GaN layer is damaged, the interface energy between the ITO transparent conductive layer and the surface of the P-GaN layer is reduced, and the hole injection efficiency of the ITO transparent conductive layer is improved, so that the forward voltage of the LED chip is reduced, and the brightness of the LED chip is improved.
Description
Technical Field
The invention relates to the technical field of photoelectrons, in particular to a P-GAN layer modified LED chip and a manufacturing method thereof.
Background
A Light-Emitting Diode (LED) is a semiconductor electronic device that converts electrical energy into optical energy. With the rapid development of the third generation semiconductor technology, semiconductor lighting has the advantages of energy conservation, environmental protection, high brightness, long service life and the like, becomes the focus of social development, and also drives the rapid development of the upstream, middle and downstream industries in the whole industry.
The IIIA-VA group compound semiconductor material is the mainstream semiconductor material for manufacturing the LED chip at present, wherein gallium nitride-based materials and aluminum gallium indium phosphide-based materials are the most popular. The current spreading performance of the conventional P-type iiia-VA compound semiconductor material is poor, and in order to enable the current to be uniformly injected into the light emitting layer, a transparent conductive layer is usually added on the P-type iiia-VA compound semiconductor material layer.
The ITO (nano indium tin metal oxide) film has high penetration rate and low sheet resistivity, is widely applied to the field of LEDs and is used as a transparent conducting layer in the LED chip process. The work function difference exists between the ITO and the P-GaN, wherein the ITO is about 4.7eV, and the P-GaN is about 7.2eV, so that the ITO transparent conducting layer can generate a huge contact barrier as a current diffusion layer of the P-GaN layer. The driving voltage of the LED chip is increased, affecting the light emitting efficiency.
Therefore, there is a need for a new LED chip having a low driving voltage and a high luminance and a method for manufacturing the same.
Disclosure of Invention
The first technical problem to be solved by the invention is as follows: a P-GAN layer modified LED chip has low driving voltage and high brightness.
The second technical problem to be solved by the invention is as follows: the manufacturing method of the P-GAN layer modified LED chip is provided.
In order to solve the first technical problem, the technical scheme provided by the invention is as follows: a P-GAN layer modified LED chip comprises the following layers from bottom to top in sequence: the ITO transparent conducting layer is arranged on the top layer;
the upper surface of the epitaxial wafer is a P-GaN layer;
and the P-GaN layer needs to be subjected to plasma bombardment modification treatment.
When the ITO transparent conducting layer is deposited, in a vacuum environment, the surface of the substrate is bombarded by plasma, and then the ITO transparent conducting layer is deposited. And adjusting a proper plasma bombardment process to destroy the crystal structure on the surface of the P-GaN layer, reduce the interface energy between the ITO transparent conductive layer and the surface of the P-GaN layer, and bond the deposited ITO atomic groups with atoms on the surface of the P-GaN layer. But also increases the roughness of the surface of the P-GaN layer, so that the contact area between the deposited ITO atomic groups and the surface of the P-GaN layer is increased. The hole injection efficiency of the ITO transparent conducting layer is improved, the forward voltage of the LED chip is reduced, and the brightness of the LED chip is improved.
According to some embodiments of the present invention, the P-GAN layer modified LED chip is divided into a P region (i) and an N region (ii).
According to some embodiments of the invention, the epitaxial wafer is composed of, from bottom to top: the GaN-based light-emitting diode comprises a substrate, a buffer GaN layer, an N-GaN layer and a quantum well layer.
According to some embodiments of the invention, a portion of the upper surface of the epitaxial wafer is the P-GaN layer and a remaining portion of the upper surface of the epitaxial wafer is the N-GaN layer.
According to some embodiments of the invention, the top layer is composed of: the device comprises a passivation layer, a P-type electrode and an N-type electrode.
According to some embodiments of the present invention, the passivation layer is etched with a P-region electrode trench extending to the ITO transparent conductive layer, and the passivation layer is etched with an N-region electrode trench extending to the N-GaN layer.
According to some embodiments of the invention, the P-type electrode is connected to the ITO transparent conductive layer.
According to some embodiments of the invention, the N-type electrode is connected to the N-GaN layer.
According to some embodiments of the invention, the P-type electrode is at least one of Cr, Ni, Al, Ti, Ag, Pt and Au.
According to some embodiments of the invention, the N-type electrode is at least one of Cr, Ni, Al, Ti, Ag, Pt and Au.
The P-GAN layer modified LED chip provided by the embodiment of the invention has at least the following beneficial effects: according to the LED chip, the P-GaN layer is bombarded by the plasma, so that the modification of the P-GaN layer is realized, and then the ITO transparent conducting layer is deposited; the crystal structure on the surface of the P-GaN layer is damaged, the interface energy between the ITO transparent conductive layer and the surface of the P-GaN layer is reduced, and the deposited ITO atomic groups are bonded with the atoms on the surface of the P-GaN layer; the roughness of the surface of the P-GaN layer is increased, so that the contact area between the deposited ITO atomic groups and the surface of the P-GaN layer is increased; the hole injection efficiency of the ITO transparent conducting layer is improved, the forward voltage of the LED chip is reduced, and the brightness of the LED chip is improved.
In order to solve the second technical problem, the invention provides a technical solution that the method for manufacturing the P-GAN layer modified LED chip includes the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises from bottom to top: the GaN-based light-emitting diode comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer;
s2, depositing an ITO transparent conductive layer: in a vacuum environment, bombarding the surface of the epitaxial wafer by using plasma, modifying a P-GaN layer on the surface of the epitaxial wafer, and depositing an ITO transparent conducting layer;
s3, surface patterning;
s4, depositing a passivation layer;
s5, evaporating a P-type electrode and an N-type electrode;
s6, annealing;
s7, preparing tablets: and thinning, cutting and inspecting to obtain the P-GAN layer modified LED chip.
According to some embodiments of the invention, the epitaxial wafer is cleaned.
According to some embodiments of the invention, the cleaning is ultrasonic cleaning.
And removing organic impurities and metal ions on the surface by an ultrasonic cleaning technology.
According to some embodiments of the invention, the ultrasonically cleaned cleaning agent is H2SO4Solution, H2O2At least one of a solution, a hydrofluoric acid solution, hydrochloric acid, and ammonia.
According to some embodiments of the invention, the ultrasonically cleaned cleaning agent is H2SO4Solution, H2O2Solution and H2A mixed solution of O; preferably, said H2SO4Mass concentration of the solutionAbout 98%; preferably, said H2O2The mass concentration of the solution is 30-40%; preferably, said H2SO4Solution, H2O2Solution and H2The volume ratio of O is 2-10: 1: 1.
According to some embodiments of the invention, the pressure of the vacuum environment in the step S2 is 7.5 × 10-5Torr～7.5×10-4Torr。
According to some embodiments of the invention, the plasma in step S2 is argon.
According to some embodiments of the invention, the voltage of the plasma discharge in the step S2 is 150V to 180V.
According to some embodiments of the invention, the current of the plasma discharge in step S2 is 4A to 6A.
According to some embodiments of the invention, the time of the plasma discharge in the step S2 is 25S to 45S.
According to some embodiments of the invention, the ITO transparent conductive layer is deposited by at least one of gun evaporation, magnetron sputtering, and RPD (reactive plasma deposition).
According to some embodiments of the invention, the deposition source of the ITO transparent conductive layer is In2O3With SnO2A mixture of (a).
According to some embodiments of the invention, the chamber pressure during the deposition of the ITO transparent conductive layer is 2.0 × 10-6Torr～7.5×10-6Torr。
According to some embodiments of the invention, the deposition rate during the deposition of the ITO transparent conductive layer is 0.02nm/s to 0.12 nm/s.
According to some embodiments of the invention, the deposition temperature of the ITO transparent conductive layer is 260-350 ℃.
According to some embodiments of the invention, the ITO transparent conductive layer is deposited to a thickness of 100nm to 300 nm.
According to some embodiments of the invention, the surface patterning process comprises the following operations:
(1) patterning the ITO transparent conductive layer: carrying out photoetching, etching and photoresist removing processes on the ITO transparent conductive layer to remove the ITO transparent conductive layer in a partial area;
(2) and (3) patterning the N region: and completely removing the P-GaN layer and the quantum well layer in the N region through photoetching, etching and photoresist removing processes, and then partially removing the N-GaN layer to expose the N-GaN layer in the N region.
According to some embodiments of the invention, the etching in the patterning operation of the ITO transparent conductive layer is wet etching.
According to some embodiments of the invention, the etching in the N region patterning process is dry etching.
According to some embodiments of the invention, the dry etching is at least one of reactive ion etching and inductively coupled plasma etching.
According to some embodiments of the invention, the process of depositing the passivation layer comprises the following operations:
(1) depositing the passivation layer on the upper surfaces of the ITO transparent conducting layer and the N-GaN layer in the N region by a plasma enhanced chemical vapor deposition method;
(2) and carrying out photoetching, etching and photoresist removing processes on the passivation layer, and removing the passivation layer of the P-area electrode groove and the passivation layer of the N-area electrode groove.
According to some embodiments of the invention, the electrode patterning process is: and stripping and removing the photoresist to leave the P-type electrode of the P-area electrode tank and the N-type electrode of the N-area electrode tank.
According to some embodiments of the present invention, a rapid annealing furnace or a high temperature furnace tube is used in the annealing process of step S6.
According to some embodiments of the invention, the annealing temperature in the step S6 is 400 ℃ to 600 ℃.
According to some embodiments of the invention, the atmosphere of annealing in step S6 is N2。
According to some embodiments of the invention, the annealing time in the step S6 is 1min to 3 min.
The method for manufacturing the P-GAN layer modified LED chip provided by the embodiment of the invention at least has the following beneficial effects: the preparation method of the invention is simple and convenient to operate and is suitable for large-scale industrial application.
Drawings
FIG. 1 is a schematic diagram of a P-GAN layer modified LED chip according to the embodiment of the present invention.
Description of reference numerals:
1. a substrate; 2. a buffer layer; 3. an N-GaN layer; 4. a quantum well layer; 5. modifying the P-GaN layer; 6. an ITO transparent conductive layer; 7. a passivation layer; 8. a P-type electrode; 9. an N-type electrode; i and P regions; II, N region.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments. The test methods used in the examples are all conventional methods unless otherwise specified; the materials, reagents and the like used are commercially available reagents and materials unless otherwise specified.
The structure of the P-GAN layer modified LED chip prepared by the embodiment of the present invention is shown in fig. 1: the P-GAN layer modified LED chip is divided into a P area I and an N area II; the P region I sequentially comprises a substrate 1, a buffer layer 2, an N-GaN layer 3, a quantum well layer 4, a modified P-GaN layer 5, an ITO transparent conducting layer 6 and a partial passivation layer 7 from bottom to top; the P-type electrode 8 is positioned in the P-region electrode groove of the passivation layer; the N region II sequentially comprises a substrate 1, a buffer layer 2, an N-GaN layer 3 and another part of a passivation layer 7 from bottom to top; the N-type electrode 9 is positioned in the N-region electrode groove of the passivation layer.
The embodiment of the invention is as follows: a manufacturing method of a P-GAN layer modified LED chip comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises from bottom to top: the GaN-based light-emitting diode comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer; the substrate is a sapphire substrate, and the quantum well layer is an InGaN/GaN multi-quantum well layer.
S2, cleaning the epitaxial wafer: cleaning an epitaxial wafer by ultrasonic; wherein the cleaning agent is H2SO4Solution (mass fraction 98%), H2O2Solution (35% by mass) andH2mixed solution of O (sulfuric acid solution, H)2O2The volume ratio of the solution to water was 6:1: 1).
S3, depositing an ITO transparent conductive layer on the P-GaN layer: in a vacuum environment, firstly, bombarding the surface of an epitaxial wafer by using plasma, introducing argon, and controlling the pressure of a chamber to be 1 multiplied by 10-4Torr, a plasma discharge voltage was 150V, a plasma discharge current was 4A, and a discharge time was 30 s. Then, an electron gun is used for evaporating an ITO transparent conductive layer and an In source2O3With SnO2The mass ratio of (1) to (5) is 95:5, the deposition temperature is 300 ℃, and the chamber pressure is 5 x 10-6Torr, the deposition rate is 0.07nm/s, and the film thickness is 200 nm.
S4, patterning the ITO transparent conductive layer: optimizing the processes of pattern photoetching, etching and photoresist removal through the ITO transparent conductive layer, and removing the ITO transparent conductive layer at the edges of the N region and the P-GaN layer; wherein, the ITO transparent conducting layer adopts wet etching.
S5, N area patterning: removing the P-GaN layer, the quantum well layer and the upper part of the N-GaN layer in the N region by ICP optimized pattern photoetching, dry etching and photoresist removal to expose the N-GaN layer in the N region; wherein the dry etching is reactive ion etching.
S6, depositing SiO on the ITO transparent conductive layer and the N-GaN layer through the plasma enhanced chemical vapor deposition method2And a passivation layer.
S7, patterning of the passivation layer: and photoetching, etching and removing the photoresist through a passivation layer optimized pattern to manufacture a P-area electrode groove and an N-area electrode groove, wherein the ITO transparent conducting layer is exposed out of the P-area electrode groove, and the N-GaN layer is exposed out of the N-area electrode groove.
S8, evaporating a P-type electrode and an N-type electrode layer: evaporating metal electrodes by using an electron gun, and evaporating metal layers of the electrodes in sequence; wherein the cavity pressure is 5 × 10-6Torr, deposition rate 0.7 nm/s; wherein, the P-type electrode and the N-type electrode layer are both Cr/Pt/Au (the thickness of each layer is 10nm/25nm/1000nm respectively).
S9, electrode patterning: and stripping and removing the photoresist to leave the P-type electrode and the N-type electrode.
S10, annealing: at a temperature of 500 ℃ N2And (5) annealing for 2min in an atmosphere.
And S11, finishing the procedures to obtain the LED wafer, and thinning, cutting and inspecting the wafer to obtain the P-GAN layer modified LED chip.
The comparative examples of the present invention are: a manufacturing method of an LED chip comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer from bottom to top.
S2, cleaning the epitaxial wafer: cleaning an epitaxial wafer by ultrasonic; wherein the cleaning agent is H2SO4Solution (mass fraction 98%), H2O2Solution (35% by mass) and H2Mixed solution of O (sulfuric acid solution, H)2O2The volume ratio of the solution to water was 6:1: 1).
S3, depositing an ITO transparent conductive layer on the P-GaN layer: evaporating ITO transparent conductive layer and source In by using electron gun2O3With SnO2The mass ratio of (1) to (5) is 95:5, the deposition temperature is 300 ℃, and the chamber pressure is 5 x 10-6Torr, the deposition rate is 0.07nm/s, and the film thickness is 200 nm.
S4, patterning the ITO transparent conductive layer: optimizing the processes of pattern photoetching, etching and photoresist removal through the ITO transparent conductive layer, and removing the ITO transparent conductive layer at the edges of the N region and the P-GaN layer; wherein, the ITO transparent conducting layer adopts wet etching.
S5, N area patterning: removing the P-GaN layer, the quantum well layer and the upper part of the N-GaN layer in the N region by ICP optimized pattern photoetching, dry etching and photoresist removal to expose the N-GaN layer in the N region; wherein, the dry etching is inductively coupled plasma etching.
S6, depositing SiO on the ITO transparent conductive layer and the N-GaN layer through the plasma enhanced chemical vapor deposition method2And a passivation layer.
S7, patterning of the passivation layer: and photoetching, etching and removing the photoresist through a passivation layer optimized pattern to manufacture a P-area electrode groove and an N-area electrode groove, wherein the ITO transparent conducting layer is exposed out of the P-type electrode groove, and the N-GaN layer is exposed out of the N-type electrode groove.
S8, evaporating a P-type electrode and an N-type electrode layer: evaporating metal electrodes by an electron gun, and sequentially evaporating each electrodeA metal layer; wherein the cavity pressure is 5 × 10-6Torr, deposition rate 0.7 nm/s; wherein, the P-type electrode and the N-type electrode layer are both Cr/Pt/Au (the thickness of each layer is 10nm/25nm/1000nm respectively).
S9, electrode patterning: and stripping and removing the photoresist to leave the P-type electrode and the N-type electrode.
S10, annealing: at a temperature of 500 ℃ N2And (5) annealing for 2min in an atmosphere.
And S11, finishing the procedures to obtain the LED wafer, and thinning, cutting and inspecting the wafer to obtain the LED chip.
On the same machine, the LED chips are manufactured according to the methods of the embodiment and the comparative example, the sample is ground and cut into chip particles of 5mil × 7mil under the same condition, then the crystal grains are respectively selected at the same position in the embodiment and the comparative example, and the LED is packaged under the same packaging process. And testing the photoelectric property of the sample by using an electric property analyzer and a spectrum analyzer by using the same driving current. The results of the photoelectric property test are shown in Table 1.
TABLE 1 comparison table of photoelectric parameters of inventive examples and comparative examples
| Detecting items | Chip size (mil)2) | Dominant wavelength (nm) | Forward voltage (V) | Light intensity (mcd) | Yield (%) |
| Examples | 5*7 | 457.3 | 2.39 | 54.3 | 91.6 |
| Comparative example | 5*7 | 457.3 | 2.45 | 58.9 | 91.6 |
As can be seen from the comparison of the data in Table 1, in the example, the forward voltage is reduced from 2.45V to 2.39V, and the light intensity is increased from 54.3mcd to 58.9mcd, compared with the comparative example, which shows that the forward voltage is reduced and the light intensity is obviously increased in the LED chip manufactured in the example.
In conclusion, according to the manufacturing method of the P-GAN layer modified LED chip provided by the invention, the P-GaN layer is modified by bombarding the P-GaN layer with plasma, and then the ITO transparent conducting layer is deposited; the crystal structure on the surface of the P-GaN layer is damaged, the interface energy between the ITO transparent conductive layer and the surface of the P-GaN layer is reduced, and the deposited ITO atomic groups are bonded with the atoms on the surface of the P-GaN layer; the roughness of the surface of the P-GaN layer is increased, so that the contact area between the deposited ITO atomic groups and the surface of the P-GaN layer is increased; the hole injection efficiency of the ITO transparent conductive layer is improved, the forward voltage of the LED chip is reduced, and the brightness of the LED chip is improved.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (10)
1. A P-GAN layer modified LED chip is characterized in that: the coating sequentially comprises the following layers from bottom to top: the ITO transparent conducting layer is arranged on the top layer;
the upper surface of the epitaxial wafer is a P-GaN layer;
and the P-GaN layer needs to be subjected to plasma bombardment modification treatment.
2. The P-GAN layer modified LED chip of claim 1, wherein: the epitaxial wafer sequentially comprises the following layers from bottom to top: the GaN-based light-emitting diode comprises a substrate, a buffer GaN layer, an N-GaN layer and a quantum well layer; and the partial area of the upper surface of the epitaxial wafer is the P-GaN layer, and the rest area of the upper surface of the epitaxial wafer is the N-GaN layer.
3. The P-GAN layer modified LED chip of claim 2, wherein: the top layer is composed of the following layers: the passivation layer, the P type electrode and the N type electrode; and the passivation layer is etched with a P-region electrode groove extending to the ITO transparent conductive layer, and the passivation layer is etched with an N-region electrode groove extending to the N-GaN layer.
4. The P-GAN layer modified LED chip of claim 3, wherein: and the P-type electrode is connected with the ITO transparent conducting layer.
5. The P-GAN layer modified LED chip of claim 3, wherein: the N-type electrode is connected with the N-GaN layer.
6. The P-GAN layer modified LED chip of claim 4, wherein: the P-type electrode is at least one of Cr, Ni, Al, Ti, Ag, Pt and Au.
7. The P-GAN layer modified LED chip of claim 5, wherein: the N-type electrode is at least one of Cr, Ni, Al, Ti, Ag, Pt and Au.
8. A method of fabricating a P-GAN layer modified LED chip according to any of claims 2 to 7, wherein: the method comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises from bottom to top: the GaN-based light-emitting diode comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer;
s2, depositing an ITO transparent conductive layer: in a vacuum environment, bombarding the surface of the epitaxial wafer by using plasma, modifying a P-GaN layer on the surface of the epitaxial wafer, and depositing an ITO transparent conducting layer;
s3, surface patterning;
s4, depositing a passivation layer;
s5, evaporating a P-type electrode and an N-type electrode;
s6, annealing;
s7, preparing tablets: and thinning, cutting and inspecting to obtain the P-GAN layer modified LED chip.
9. The method of claim 8, wherein: the process parameters in the plasma bombardment process in the step S2 are as follows: the discharge voltage is 150V-180V; the discharge current is 4A-6A; the discharge time is 25s to 45 s.
10. The method of claim 8, wherein: the annealing temperature in the step S6 is 400-600 ℃; the annealing atmosphere in the step S6 is N2An atmosphere; the annealing time in the step S6 is 1-3 min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110102443.1A CN112750929A (en) | 2021-01-26 | 2021-01-26 | P-GAN layer modified LED chip and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110102443.1A CN112750929A (en) | 2021-01-26 | 2021-01-26 | P-GAN layer modified LED chip and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112750929A true CN112750929A (en) | 2021-05-04 |
Family
ID=75653105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110102443.1A Pending CN112750929A (en) | 2021-01-26 | 2021-01-26 | P-GAN layer modified LED chip and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112750929A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113410362A (en) * | 2021-05-25 | 2021-09-17 | 长沙壹纳光电材料有限公司 | LED chip and manufacturing method and application thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101335204A (en) * | 2007-06-29 | 2008-12-31 | 北京大学 | Surface processing method of p type gallium nitride |
| CN103117344A (en) * | 2013-02-05 | 2013-05-22 | 海迪科（南通）光电科技有限公司 | Light emitting diode (LED) light emitting device and manufacturing method thereof |
| CN104022200A (en) * | 2013-02-28 | 2014-09-03 | 山东浪潮华光光电子股份有限公司 | GaN-based light emitting diode chip and preparation method thereof |
-
2021
- 2021-01-26 CN CN202110102443.1A patent/CN112750929A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101335204A (en) * | 2007-06-29 | 2008-12-31 | 北京大学 | Surface processing method of p type gallium nitride |
| CN103117344A (en) * | 2013-02-05 | 2013-05-22 | 海迪科（南通）光电科技有限公司 | Light emitting diode (LED) light emitting device and manufacturing method thereof |
| CN104022200A (en) * | 2013-02-28 | 2014-09-03 | 山东浪潮华光光电子股份有限公司 | GaN-based light emitting diode chip and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113410362A (en) * | 2021-05-25 | 2021-09-17 | 长沙壹纳光电材料有限公司 | LED chip and manufacturing method and application thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7829909B2 (en) | Light emitting diodes and fabrication methods thereof | |
| CN102157640B (en) | Method for manufacturing gallium nitride (GaN)-based light-emitting diode (LED) chip with p-GaN layer subjected to surface roughening | |
| CN101789478B (en) | Light-emitting diode chip and manufacturing method thereof | |
| CN108231966A (en) | A kind of LED chip with speculum and preparation method thereof | |
| CN105140368A (en) | High-performance light-emitting diode (LED) chip and fabrication method thereof | |
| CN112750933B (en) | LED chip and manufacturing method thereof | |
| CN112750929A (en) | P-GAN layer modified LED chip and manufacturing method thereof | |
| CN103137795B (en) | A kind of preparation method of GaN base light-emitting diode chip for backlight unit structure cell | |
| KR101239852B1 (en) | GaN compound semiconductor light emitting element | |
| US20130075779A1 (en) | Light emitting diode with multiple transparent conductive layers and method for manufacturing the same | |
| KR20030077149A (en) | P-type ohmic electrode in gallium nitride based optical device and fabrication method thereof | |
| CN112820807A (en) | Preparation method of LED chip with roughened surface | |
| CN214336736U (en) | LED chip structure of double-layer ITO film | |
| CN104465907A (en) | Method for improving electrical property of P-type gallium nitride thin film | |
| CN113410362B (en) | LED chip and manufacturing method and application thereof | |
| CN114400276A (en) | Manufacturing method of high-voltage LED chip | |
| CN109755356B (en) | Method for improving built-in ohmic contact performance of GaN-based light emitting diode | |
| CN100442560C (en) | Method for producing light-emitting diodes | |
| CN105932133B (en) | A kind of high brightness LED chip and preparation method thereof | |
| CN117096244A (en) | LED chip and preparation method and application thereof | |
| CN115000251A (en) | Preparation method of GaP surface treated ITO structure LED | |
| CN114597295B (en) | Chip structure of Mini/Micro LED and preparation method | |
| CN107221584A (en) | A kind of preparation method of the GaAs base LED chips of electrode not damaged and easy bonding wire | |
| KR20180060491A (en) | Hybrid transparent electrode and light emitting diode comprising the same | |
| Li et al. | Plasma-induced damage in GaN-based light emitting diodes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210504 |
|
| RJ01 | Rejection of invention patent application after publication |