CN116387428B - LED chip preparation method - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 253
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 53
- 239000011265 semifinished product Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 30
- 239000011248 coating agent Substances 0.000 claims abstract description 28
- 238000000576 coating method Methods 0.000 claims abstract description 28
- 230000000903 blocking effect Effects 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000001259 photo etching Methods 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 239000011241 protective layer Substances 0.000 claims abstract description 10
- 238000001704 evaporation Methods 0.000 claims abstract description 4
- 239000000047 product Substances 0.000 claims abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 34
- 229910002601 GaN Inorganic materials 0.000 claims description 27
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 26
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910003437 indium oxide Inorganic materials 0.000 claims description 7
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 7
- 150000002739 metals Chemical class 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 238000000313 electron-beam-induced deposition Methods 0.000 claims 1
- 230000003213 activating effect Effects 0.000 abstract description 5
- 230000031700 light absorption Effects 0.000 abstract description 2
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 6
- 239000005977 Ethylene Substances 0.000 description 6
- 238000010521 absorption reaction Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
The invention provides a preparation method of an LED chip, which comprises the steps of coating a photoresist layer on a transparent conductive layer, etching a preset pattern layer on the photoresist layer by photoetching, transferring the preset pattern layer to the transparent conductive layer in an etching mode to form a patterned transparent conductive layer, then carrying out counter doping on a second semi-finished product chip to form a counter doping high resistance area, activating the counter doping high resistance area, then alternately carrying out two photoresist coating and two photoetching, carrying out etching on the semi-finished product chip after the two photoresist coating and the two photoetching is completed to obtain a fifth semi-finished product chip, evaporating a metal electrode layer on the surface of the fifth semi-finished product chip to obtain a sixth semi-finished product chip, depositing an insulating protective layer on the surface of the sixth semi-finished product chip, and coating a photoresist layer on the surface of the insulating protective layer to carry out photoetching to obtain the finished product LED chip, so that the light absorption of the current blocking layer can be effectively reduced, and the luminous efficiency of the LED chip can be effectively improved.
Description
Technical Field
The invention relates to the technical field of LED chips, in particular to a preparation method of an LED chip.
Background
With the rapid development of LED technology and the gradual improvement of LED light efficiency, LED applications are becoming more and more widespread. Today there is increasing interest in the development of LEDs in the lighting market, which will be potential light sources replacing incandescent, tungsten and fluorescent lamps. The LED chip is a solid semiconductor device, the heart of the LED is a semiconductor wafer, one end of the wafer is attached to a bracket, the other end of the wafer is a negative electrode, and the other end of the wafer is connected with the positive electrode of a power supply, so that the whole wafer is encapsulated by epoxy resin.
In the prior art, a layer of insulating layer is deposited on P-type GaN as a current blocking layer of an LED chip, but the insulating layer such as silicon oxide or silicon nitride is used as a current blocking layer to absorb light to some extent, which results in a decrease in light efficiency of the LED chip.
Disclosure of Invention
Based on this, an object of the present invention is to provide a method for manufacturing an LED chip, which at least solves the above-mentioned drawbacks of the prior art.
The invention provides a preparation method of an LED chip, which comprises the following steps:
step one, providing a substrate, and sequentially growing an N-type gallium nitride layer, a multiple quantum well layer and a P-type gallium nitride layer on the substrate to obtain a first semi-finished chip;
depositing a transparent conductive layer on the first semi-finished chip, coating a photoresist layer on the surface of the transparent conductive layer, etching a preset pattern layer on the photoresist layer by photoetching, transferring the preset pattern layer onto the transparent conductive layer in an etching mode to form a patterned transparent conductive layer, wherein the patterned transparent conductive layer is particularly a current blocking layer, and obtaining a second semi-finished chip;
performing counter doping on the second semi-finished chip by taking the patterned transparent conducting layer as a mask to form a counter doping high-resistance region, and activating the counter doping high-resistance region through an annealing process to obtain a third semi-finished chip;
step four, performing first photoresist coating and first photoetching on the third semi-finished product chip, and performing first etching on the third semi-finished product chip to obtain a fourth semi-finished product chip;
step five, performing second photoresist coating and second photoetching on the fourth semi-finished product chip, and performing second etching on the fourth semi-finished product chip to obtain a fifth semi-finished product chip;
step six, coating a layer of negative photoresist on the substrate on the fifth semi-finished chip, sequentially developing and exposing, and evaporating a metal electrode layer on the surface of the fifth semi-finished chip to obtain a sixth semi-finished chip;
and step seven, depositing an insulating protective layer on the surface of the sixth semi-finished product chip, coating a photoresist layer on the surface of the insulating protective layer for photoetching, and exposing the metal electrode layer to obtain the finished product LED chip.
Compared with the prior art, the invention has the beneficial effects that: coating a photoresist layer on a transparent conducting layer on a first semi-finished product chip, etching a preset pattern layer on the photoresist layer by photoetching, transferring the preset pattern layer onto the transparent conducting layer in an etching mode to form a patterned transparent conducting layer, wherein the patterned transparent conducting layer is a current blocking layer, counter doping is carried out on a second semi-finished product chip by taking the patterned transparent conducting layer as a mask to form a counter doping high resistance region, the counter doping high resistance region is activated, and the current blocking layer deposited with the counter doping high resistance region can effectively reduce the absorption of the current blocking layer to light, so that the luminous efficiency of the LED chip can be effectively improved.
Further, the substrate is made of one of silicon, silicon carbide, zinc oxide or sapphire.
Further, in the second step, the transparent conductive layer is made of one of gallium doped with indium, zinc indium tin oxide, indium tin oxide or nano silver wire, the transparency of the transparent conductive layer is greater than 80%, the resistivity of the transparent conductive layer is lower than that of the P-type gallium nitride layer, and the deposition of the transparent conductive layer is one of chemical vapor deposition or magnetron sputtering.
Further, in the second step, after the photoresist layer is subjected to photoresist formation to form the preset pattern layer, the transparent conductive layer is placed into etching solution to be soaked for 3-15 min, and photoresist removal and cleaning are sequentially performed on the substrate on the second semi-finished chip.
Further, in the third step, the second semi-finished product chip is placed in a chemical vapor deposition cavity, the temperature in the chemical vapor deposition cavity is 220-270 ℃, 30-500 sccm of methane and 950-2450 sccm of nitrogen are introduced into the chemical vapor deposition cavity, the radio frequency power in the chemical vapor deposition cavity is 35-150W, and the radio frequency time is 45s-255s.
Further, in the third step, after the deposition of the anti-doped high-resistance region is completed, the second semi-finished chip is put into an annealing furnace for annealing at the annealing temperature of 450-650 ℃ so that the anti-doped high-resistance region is activated.
Further, in the fourth step, the first photoresist coating and the first photolithography are performed on the third semi-finished product chip by using the MESA layer as a mask.
Further, in the fifth step, the second photoresist coating and the second photolithography are performed on the fourth semi-finished chip using the ISO layer as a mask.
Further, in the step six, a layer of the metal electrode layer is evaporated on the surface of the fifth semi-finished product chip by using an electron beam evaporation manner, the metal electrode layer is composed of multiple layers of metals, the metals are one of nickel, aluminum, titanium, gold or platinum, and a floating process is adopted to remove the negative photoresist and the metals on the fifth semi-finished product chip.
Further, in the seventh step, the insulating protection layer is one of silicon oxide or aluminum oxide.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an LED chip according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a finished LED chip according to a first embodiment of the present invention.
Description of main reference numerals:
10. a substrate; 20. an N-type gallium nitride layer; 30. a multiple quantum well layer; 40. a P-type gallium nitride layer; 50. a transparent conductive layer; 60. a counter doping high resistance region; 70. a metal electrode layer; 80. and an insulating protective layer.
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1, a method for manufacturing an LED chip according to a first embodiment of the present invention is shown, and the method includes steps one to seven:
step one, providing a substrate 10, and growing an N-type gallium nitride layer 20, a multiple quantum well layer 30 and a P-type gallium nitride layer 40 on the substrate in sequence to obtain a first semi-finished chip;
it should be noted that the substrate is made of one of silicon, silicon carbide, zinc oxide, or sapphire, and in this embodiment, a sapphire substrate is used as the substrate.
Depositing a transparent conductive layer 50 on the first semi-finished chip, coating a photoresist layer on the surface of the transparent conductive layer, etching a preset pattern layer on the photoresist layer by photoetching, transferring the preset pattern layer onto the transparent conductive layer in an etching mode to form a patterned transparent conductive layer, wherein the patterned transparent conductive layer is a current blocking layer in particular, and obtaining a second semi-finished chip;
in the embodiment, a transparent conductive layer is deposited on the first semi-finished chip by a chemical vapor deposition mode or a magnetron sputtering mode, in the embodiment, a layer of transparent conductive layer is deposited on the first semi-finished chip by a chemical vapor deposition mode, the transparent conductive layer is used for transmitting current to a P-type gallium nitride layer, the transparent conductive layer is made of one of indium oxide doped with gallium, zinc indium tin oxide, indium tin oxide or nano silver wires, in the embodiment, the transparent conductive layer is made of indium oxide doped with gallium, after a preset pattern layer is photoetched, the preset pattern layer is transferred onto the transparent conductive layer by an etching mode to form a patterned transparent conductive layer, in the embodiment, the patterned transparent conductive layer is specifically a current blocking layer, then the transparent conductive layer is soaked in etching liquid for 3min, the purpose is to etch the transparent conductive layer which is not protected by photoresist, photoresist on a substrate on the second semi-finished chip is removed completely, and then the second semi-finished chip is cleaned by clean water.
It should be explained that the transparency of the transparent conductive layer is greater than 80%, the resistivity of the transparent conductive layer is lower than that of the P-type gallium nitride layer, the transparent conductive layer does not have a great influence on the brightness of the chip only when the light transmittance of the transparent conductive layer is greater than 80% in the light-emitting surface direction, and the other function of the transparent conductive layer is to help the P-type gallium nitride layer to expand the current, and only the resistivity of the transparent conductive layer is lower than that of the P-type gallium nitride layer to play a role of expanding the current.
It should be noted that, the transparent conductive layer is deposited on the first semi-finished chip by chemical vapor deposition, in this embodiment, the transparent conductive layer is deposited on the P-type gallium nitride layer, and the chemical vapor deposition uses methane or ethylene as a reaction gas, so that the methane or ethylene counter-dope the surface of the P-type gallium nitride layer, so that the deposition region becomes a low-doped region, the contact resistance of the deposition region and the mobility of carriers are reduced, and in this embodiment, the resistivity of the low-doped region can be increased to 10 4 Ω·cm。
Performing counter doping on the second semi-finished chip by taking the patterned transparent conducting layer as a mask to form a counter doping high-resistance region, and activating the counter doping high-resistance region through an annealing process to obtain a third semi-finished chip;
in the specific implementation, the cleaned second semi-finished chip is placed in a chemical vapor deposition cavity, methane with the flow of 30sccm and nitrogen with the flow of 950sccm are introduced into the chemical vapor deposition cavity, then the temperature in the chemical vapor deposition cavity is 220 ℃, the radio frequency power in the chemical vapor deposition cavity is 35W, the radio frequency time is 45s, and therefore the patterned transparent conducting layer on the second semi-finished chip can be counter doped to form a counter doped high-resistance region.
It should be explained that, the transparent conductive layer is used as a counter-doped mask, which not only can replace the function of the current blocking layer in the traditional LED chip, but also can form a counter-doped high-resistance region at the edge of the chip, thereby reducing the probability of carrier recombination at the edge, improving the anti-static capability of the edge and improving the edge breakdown voltage.
It is worth to say that the anti-doped high-resistance region deposited on the current blocking layer can effectively reduce the absorption of the current blocking layer to light, and further can effectively improve the luminous efficiency of the chip.
Step four, performing first photoresist coating and first photoetching on the third semi-finished product chip, and performing first etching on the third semi-finished product chip to obtain a fourth semi-finished product chip;
in specific implementation, the MESA layer is used as a mask to perform first photoresist coating and first photoetching on the third semi-finished product chip, so that an N-type semiconductor table-board is formed on the third semi-finished product chip.
Step five, performing second photoresist coating and second photoetching on the fourth semi-finished product chip, and performing second etching on the fourth semi-finished product chip to obtain a fifth semi-finished product chip;
in a specific implementation, the second photoresist coating and the second photolithography are performed on the fourth semi-finished chip by using the ISO layer as a mask, so that a channel is formed on the fourth semi-finished chip.
Step six, coating a layer of negative photoresist on the substrate on the fifth semi-finished chip, sequentially developing and exposing, and then evaporating a layer of metal electrode layer 70 on the surface of the fifth semi-finished chip to obtain a sixth semi-finished chip;
in the specific implementation, a layer of negative photoresist is coated on the surface of a substrate on a fifth semi-finished chip, then the fifth semi-finished chip is developed and exposed in sequence, then a layer of metal electrode layer is evaporated on the surface of the fifth semi-finished chip in an electron beam evaporation mode, the metal electrode layer consists of multiple layers of metals, one of nickel, aluminum, titanium, gold or platinum is adopted as the metal, and a floating process is adopted to remove the negative photoresist and the metal on the fifth semi-finished chip, namely the negative photoresist and the metal layer on the unnecessary positions on the fifth semi-finished chip are removed, and the fifth semi-finished chip is cleaned after the removal is completed.
Step seven, depositing a layer of insulating protective layer 80 on the surface of the sixth semi-finished product chip, and coating a layer of photoresist on the surface of the insulating protective layer for photoetching to expose the metal electrode layer, so as to obtain a finished product LED chip;
it should be noted that, in this embodiment, the insulating protection layer is made of one of silicon oxide or aluminum oxide, and the exposed metal electrode may be deposited on the bonding pad later, so that a finished LED chip can be obtained, as shown in fig. 2.
In summary, in the method for manufacturing an LED chip according to the foregoing embodiment of the present invention, a photoresist layer is coated on a transparent conductive layer on a first semi-finished product chip, a preset pattern layer is etched on the photoresist layer by photolithography, and the preset pattern layer is transferred onto the transparent conductive layer by etching, so as to form a patterned transparent conductive layer, the patterned transparent conductive layer is a current blocking layer, and the patterned transparent conductive layer is used as a mask to counterdope a second semi-finished product chip to form a counterdoping high resistance region, and activate the counterdoping high resistance region, so that the current blocking layer deposited with the counterdoping high resistance region can effectively reduce the absorption of light by the current blocking layer, thereby effectively improving the luminous efficiency of the LED chip, and using the transparent conductive layer as a counterdoping mask not only can replace the effect of the current blocking layer in the conventional LED chip, but also can form the counterdoping high resistance region at the chip edge, reduce the probability of carrier recombination at the edge, improve the anti-static capability of the edge, and improve the edge breakdown voltage.
Example two
The LED chip manufacturing method in the present embodiment is different from the LED chip manufacturing method in the first embodiment in that:
depositing a transparent conductive layer on the first semi-finished chip, coating a photoresist layer on the surface of the transparent conductive layer, etching a preset pattern layer on the photoresist layer by photoetching, transferring the preset pattern layer onto the transparent conductive layer in an etching mode to form a patterned transparent conductive layer, wherein the patterned transparent conductive layer is particularly a current blocking layer, and obtaining a second semi-finished chip;
in the embodiment, a transparent conductive layer is deposited on the first semi-finished chip by a chemical vapor deposition mode or a magnetron sputtering mode, in the embodiment, a layer of transparent conductive layer is deposited on the first semi-finished chip by a chemical vapor deposition mode, the transparent conductive layer is used for transmitting current to a P-type gallium nitride layer, the transparent conductive layer is made of one of indium oxide doped with gallium, zinc indium tin oxide, indium tin oxide or nano silver wires, in the embodiment, the transparent conductive layer is made of indium oxide doped with gallium, after a preset pattern layer is photoetched, the preset pattern layer is transferred onto the transparent conductive layer by an etching mode to form a patterned transparent conductive layer, in the embodiment, the patterned transparent conductive layer is specifically a current blocking layer, then the transparent conductive layer is immersed in etching liquid for 10min, the purpose is to etch the transparent conductive layer which is not protected by photoresist, photoresist on a substrate on the second semi-finished chip is removed completely, and then the second semi-finished chip is cleaned by clean water.
It should be explained that the transparency of the transparent conductive layer is greater than 80%, and the resistivity of the transparent conductive layer is lower than that of the P-type gallium nitride layer.
It should be noted that, the transparent conductive layer is deposited on the first semi-finished chip by chemical vapor deposition, in this embodiment, the transparent conductive layer is deposited on the P-type gallium nitride layer, and the chemical vapor deposition uses methane or ethylene as a reaction gas, so that the methane or ethylene counter-dope the surface of the P-type gallium nitride layer, so that the deposition region becomes a low-doped region, the contact resistance of the deposition region and the mobility of carriers are reduced, and in this embodiment, the resistivity of the low-doped region can be increased to 10 4 Ω·cm。
Performing counter doping on the second semi-finished chip by taking the patterned transparent conducting layer as a mask to form a counter doping high-resistance region, and activating the counter doping high-resistance region through an annealing process to obtain a third semi-finished chip;
in the specific implementation, the cleaned second semi-finished chip is placed in a chemical vapor deposition cavity, methane with the flow of 300sccm and nitrogen with the flow of 1800sccm are introduced into the chemical vapor deposition cavity, then the temperature in the chemical vapor deposition cavity is enabled to be 250 ℃, the radio frequency power in the chemical vapor deposition cavity is enabled to be 90W, the radio frequency time is enabled to be 100s, and accordingly the patterned transparent conducting layer on the second semi-finished chip can be counter doped to form a counter-doped high-resistance region.
It should be explained that, the transparent conductive layer is used as a counter-doped mask, which not only can replace the function of the current blocking layer in the traditional LED chip, but also can form a counter-doped high-resistance region at the edge of the chip, thereby reducing the probability of carrier recombination at the edge, improving the anti-static capability of the edge and improving the edge breakdown voltage.
It is worth to say that the anti-doped high-resistance region deposited on the current blocking layer can effectively reduce the absorption of the current blocking layer to light, and further can effectively improve the luminous efficiency of the chip.
Example III
The method for manufacturing an LED chip in this embodiment is different from the method for manufacturing an LED chip in the above embodiment in that:
depositing a transparent conductive layer on the first semi-finished chip, coating a photoresist layer on the surface of the transparent conductive layer, etching a preset pattern layer on the photoresist layer by photoetching, transferring the preset pattern layer onto the transparent conductive layer in an etching mode to form a patterned transparent conductive layer, wherein the patterned transparent conductive layer is particularly a current blocking layer, and obtaining a second semi-finished chip;
in the embodiment, a transparent conductive layer is deposited on the first semi-finished chip by a chemical vapor deposition mode or a magnetron sputtering mode, in the embodiment, a layer of transparent conductive layer is deposited on the first semi-finished chip by a chemical vapor deposition mode, the transparent conductive layer is used for transmitting current to a P-type gallium nitride layer, the transparent conductive layer is made of one of indium oxide doped with gallium, zinc indium tin oxide, indium tin oxide or nano silver wires, in the embodiment, the transparent conductive layer is made of indium oxide doped with gallium, after a preset pattern layer is photoetched, the preset pattern layer is transferred onto the transparent conductive layer by an etching mode to form a patterned transparent conductive layer, in the embodiment, the patterned transparent conductive layer is specifically a current blocking layer, then the transparent conductive layer is immersed in etching liquid for 15min, the purpose is to etch the transparent conductive layer which is not protected by photoresist, photoresist on a substrate on the second semi-finished chip is removed completely, and then the second semi-finished chip is cleaned by clean water.
It should be explained that the transparency of the transparent conductive layer is greater than 80%, and the resistivity of the transparent conductive layer is lower than that of the P-type gallium nitride layer.
It should be noted that, the transparent conductive layer is deposited on the first semi-finished chip by chemical vapor deposition, in this embodiment, the transparent conductive layer is deposited on the P-type gallium nitride layer, and the chemical vapor deposition uses methane or ethylene as a reaction gas, so that the methane or ethylene counter-dope the surface of the P-type gallium nitride layer, so that the deposition region becomes a low-doped region, the contact resistance of the deposition region and the mobility of carriers are reduced, and in this embodiment, the resistivity of the low-doped region can be increased to 10 4 Ω·cm。
Performing counter doping on the second semi-finished chip by taking the patterned transparent conducting layer as a mask to form a counter doping high-resistance region, and activating the counter doping high-resistance region through an annealing process to obtain a third semi-finished chip;
in the specific implementation, the cleaned second semi-finished chip is placed in a chemical vapor deposition cavity, methane with the flow of 500sccm and nitrogen with the flow of 2450sccm are introduced into the chemical vapor deposition cavity, then the temperature in the chemical vapor deposition cavity is 270 ℃, the radio frequency power in the chemical vapor deposition cavity is 150W, the radio frequency time is 255s, and therefore the patterned transparent conducting layer on the second semi-finished chip can be counter doped to form a counter doped high-resistance region.
It should be explained that, the transparent conductive layer is used as a counter-doped mask, which not only can replace the function of the current blocking layer in the traditional LED chip, but also can form a counter-doped high-resistance region at the edge of the chip, thereby reducing the probability of carrier recombination at the edge, improving the anti-static capability of the edge and improving the edge breakdown voltage.
It is worth to say that the anti-doped high-resistance region deposited on the current blocking layer can effectively reduce the absorption of the current blocking layer to light, and further can effectively improve the luminous efficiency of the chip.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (9)
1. The preparation method of the LED chip is characterized by comprising the following steps of:
step one, providing a substrate, and sequentially growing an N-type gallium nitride layer, a multiple quantum well layer and a P-type gallium nitride layer on the substrate to obtain a first semi-finished chip;
depositing a transparent conductive layer on the first semi-finished chip, coating a photoresist layer on the surface of the transparent conductive layer, etching a preset pattern layer on the photoresist layer by photoetching, transferring the preset pattern layer onto the transparent conductive layer in an etching mode to form a patterned transparent conductive layer, wherein the patterned transparent conductive layer is particularly a current blocking layer, and obtaining a second semi-finished chip;
thirdly, counter doping is carried out on the second semi-finished product chip by taking the patterned transparent conducting layer as a mask to form a counter doping high-resistance region, the counter doping high-resistance region is activated through an annealing process, a third semi-finished product chip is obtained, the transparent conducting layer is taken as a counter doping mask to replace a current expansion layer, and a counter doping high-resistance region is formed on the edge of the third semi-finished product chip;
step four, performing first photoresist coating and first photoetching on the third semi-finished product chip, and performing first etching on the third semi-finished product chip to obtain a fourth semi-finished product chip;
step five, performing second photoresist coating and second photoetching on the fourth semi-finished product chip, and performing second etching on the fourth semi-finished product chip to obtain a fifth semi-finished product chip;
step six, coating a layer of negative photoresist on the substrate on the fifth semi-finished chip, sequentially developing and exposing, and evaporating a metal electrode layer on the surface of the fifth semi-finished chip to obtain a sixth semi-finished chip;
depositing an insulating protective layer on the surface of the sixth semi-finished product chip, coating a photoresist layer on the surface of the insulating protective layer for photoetching, and exposing the metal electrode layer to obtain a finished product LED chip;
in the second step, the transparent conductive layer is made of one of indium oxide doped with gallium, zinc indium tin oxide, indium tin oxide or nano silver wire, the transparency of the transparent conductive layer is more than 80%, the resistivity of the transparent conductive layer is lower than that of the P-type gallium nitride layer, and the deposition of the transparent conductive layer is one of chemical vapor deposition or magnetron sputtering;
the transparency of the transparent conductive layer is greater than 80%, and the resistivity of the transparent conductive layer is lower than that of the P-type gallium nitride layer, so that the transparent conductive layer helps the P-type gallium nitride layer to expand current.
2. The method of manufacturing an LED chip of claim 1, wherein said substrate is made of one of silicon, silicon carbide, zinc oxide or sapphire.
3. The method according to claim 1, wherein in the second step, after the photoresist layer is subjected to photolithography to form the preset pattern layer, the transparent conductive layer is immersed in an etching solution for 3min to 15min, and the substrate on the second semi-finished chip is sequentially photoresist removed and cleaned.
4. The method according to claim 1, wherein in the third step, the second semi-finished chip is placed in a chemical vapor deposition chamber, the temperature in the chemical vapor deposition chamber is 220 ℃ to 270 ℃, 30sccm to 500sccm of methane and 950sccm to 2450sccm of nitrogen are introduced into the chemical vapor deposition chamber, the radio frequency power in the chemical vapor deposition chamber is 35W to 150W, and the radio frequency time is 45s to 255s.
5. The method of manufacturing an LED chip as recited in claim 1, wherein in said step three, after said depositing is completed, said second semi-finished chip is placed in an annealing furnace for annealing at a temperature of 450 ℃ to 650 ℃ so that said counter-doped high-resistance region is activated.
6. The method of manufacturing an LED chip as set forth in claim 1, wherein in the fourth step, the first photoresist coating and the first photolithography are performed on the third semi-finished chip using the MESA layer as a mask.
7. The method of manufacturing an LED chip as set forth in claim 1, wherein in the fifth step, the fourth semi-finished chip is subjected to the second photoresist coating and the second photolithography using an ISO-pattern layer as a mask.
8. The method according to claim 1, wherein in the sixth step, a layer of the metal electrode layer is deposited on the surface of the fifth semi-finished chip by using an electron beam deposition method, the metal electrode layer is composed of multiple layers of metals, the metals are one of nickel, aluminum, titanium, gold or platinum, and a floating process is used to remove the negative photoresist and the metals on the fifth semi-finished chip.
9. The method of manufacturing an LED chip of claim 1, wherein in the seventh step, the insulating protective layer is one of silicon oxide or aluminum oxide.
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