CN111244236A - LED chip structure and manufacturing method thereof - Google Patents
LED chip structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 145
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 19
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 214
- 230000000903 blocking effect Effects 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 13
- 229910052681 coesite Inorganic materials 0.000 claims description 11
- 229910052906 cristobalite Inorganic materials 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 229910052682 stishovite Inorganic materials 0.000 claims description 11
- 229910052905 tridymite Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000003292 glue Substances 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 238000000576 coating method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000009501 film coating Methods 0.000 description 1
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
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Abstract
The invention discloses an LED chip structure and a manufacturing method thereof, wherein the LED chip structure comprises a substrate, a U-shaped gallium nitride layer, an N-shaped semiconductor layer, a luminous layer, a P-shaped semiconductor layer and a transparent conducting layer which are sequentially arranged, the LED chip structure also comprises a P electrode positioned on the transparent conducting layer and an N electrode positioned on the N-shaped semiconductor layer, the N-shaped semiconductor layer comprises an N-shaped semiconductor heavily doped layer and an N-shaped semiconductor lightly doped layer, the N-shaped semiconductor heavily doped layer comprises a plurality of first bulges and a plurality of grooves, the N-shaped semiconductor lightly doped layer comprises a plurality of second bulges and hollowed-out parts, and the hollowed-out parts and the grooves form grooves together; the LED chip is formed by sequentially manufacturing a substrate, a U-shaped gallium nitride layer, an N-shaped semiconductor layer, a light emitting layer, a P-shaped semiconductor layer and a transparent conducting layer. According to the invention, through the manufacturing process of selective etching, the electron flow surface diffusion regions are formed on the N-type semiconductor heavily doped layer and the N-type semiconductor lightly doped layer, and the luminous efficiency of the LED chip can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an LED chip structure and a manufacturing method thereof.
Background
At present, LED chip structure has just adorn structure, vertical structure and flip-chip bonding structure, and the LED chip of just adorning the structure is only considered in this application, and the LED chip of just adorning the structure has following problem: 1. the current accumulation effect of the LED chip causes the current to be mainly concentrated in a partial area on one side of the N electrode wire and the P electrode wire, and when the current is more diffused in the N-type semiconductor layer than the P-type semiconductor layer, the current is mainly concentrated near the N electrode wire; when the current is diffused in the P-type semiconductor layer more than the N-type semiconductor layer, the current is mainly concentrated near the P electrode wire, and the current is concentrated in a partial area on one side of the N electrode wire and the P electrode wire, so that the longitudinal diffusion of the current is less, the local current density is overlarge, the heat is overhigh, and the service efficiency and the service life of the chip are reduced; 2. in order to improve the light-emitting efficiency of the light transparent conducting layer, the light transparent conducting layer is thinned as much as possible, and meanwhile, the current diffusion of the P electrode is far smaller than that of the N electrode, and the current is concentrated in the N electrode wire.
In view of the above problems, it is a general practice to plate a silicon oxide insulating medium as a current blocking layer under the N-electrode, so that although the current ratio under the N-electrode can be reduced and the current diffusivity can be increased to a certain extent, the increase of the current blocking layer also limits the formation of the process, and therefore, there is a need to provide an improved LED chip structure to overcome the above problems.
Disclosure of Invention
In view of the above, the present invention provides an LED chip structure and a method for fabricating the same, in which an electron flow surface diffusion region is formed on an N-type semiconductor heavily doped layer and an N-type semiconductor lightly doped layer through a selective etching process, and simultaneously, low-doped gallium nitride and SiO are formed2As the material of the current blocking layer, the luminous efficiency of the LED chip can be improved.
The LED chip structure comprises a substrate, a U-shaped gallium nitride layer, an N-shaped semiconductor layer, a light emitting layer, a P-shaped semiconductor layer and a transparent conducting layer which are sequentially arranged, and further comprises a P electrode and an N electrode, wherein the P electrode is positioned on one side, far away from the P-shaped semiconductor layer, of the transparent conducting layer;
the N-type semiconductor layer comprises an N-type semiconductor heavily doped layer and an N-type semiconductor lightly doped layer, and the N-type semiconductor lightly doped layer is positioned on one side, close to the light emitting layer, of the N-type semiconductor heavily doped layer; the N-type semiconductor heavily-doped layer comprises a plurality of first bulges and a plurality of grooves, and the grooves are positioned between any two adjacent first bulges; the N-type semiconductor light-doped layer comprises a plurality of second bulges and hollow parts, the second bulges are positioned on one side of the first bulges, which is far away from the substrate, the orthographic projections of the second bulges on the substrate are not overlapped with the grooves, and the hollow parts are positioned between any two adjacent second bulges; the hollow part and the groove form a groove together;
the N electrode covers one side of the second protrusion far away from the first protrusion and the groove.
Optionally, the depth of the groove is smaller than the thickness of the heavily doped N-type semiconductor layer in a direction perpendicular to the plane of the substrate.
Optionally, the depth of the trench is H, and H is greater than or equal to 10nm and less than or equal to 1500nm, along a direction perpendicular to the plane of the substrate.
Alternatively, H1000 nm.
Alternatively, the first protrusion and the second protrusion adjacent to each other in a direction perpendicular to the plane of the substrate may have a trapezoidal overall cross-sectional shape.
Optionally, a current blocking layer is disposed between the P-type semiconductor layer and the transparent conductive layer, and a protective layer is disposed on the side surface of the light emitting layer, the side surface of the P-type semiconductor layer, and the side surface of the current blocking layer.
Optionally, the transparent conductive layer is made of indium tin oxide.
Optionally, the protective layer is made of SiO2。
Optionally, the current blocking layer is made of low-doped gallium nitride and SiO2。
The application provides a manufacturing method of an LED chip structure, which comprises the following steps:
providing a substrate;
forming a U-shaped gallium nitride layer on a substrate;
forming an N-type semiconductor heavily-doped layer on one side of the U-type gallium nitride layer, which is far away from the substrate, wherein the N-type semiconductor heavily-doped layer comprises a plurality of first bulges and a plurality of grooves;
forming an N-type semiconductor lightly doped layer on one side, far away from the substrate, of the N-type semiconductor heavily doped layer, wherein the N-type semiconductor lightly doped layer comprises a plurality of second bulges and hollow parts, the second bulges are located on one side, far away from the substrate, of the first bulges, the orthographic projections of the second bulges on the substrate are not overlapped with the grooves, and the hollow parts are located between any two adjacent second bulges; the hollow part and the groove form a groove together; the N-type semiconductor heavily doped layer and the N-type semiconductor lightly doped layer jointly form an N-type semiconductor layer, and the N-type semiconductor layer comprises a first region and a second region;
forming a light emitting layer on one side of the N-type semiconductor layer, which is far away from the substrate, wherein the light emitting layer is positioned in the first area;
forming a P-type semiconductor layer on one side of the light-emitting layer far away from the substrate;
forming a transparent conducting layer on one side of the P-type semiconductor layer, which is far away from the substrate;
and forming a P electrode on one side of the transparent conductive layer, which is far away from the P-type semiconductor layer, and forming an N electrode in a second region of the N-type semiconductor layer, wherein the N electrode is positioned on one side of the second protrusion, which is far away from the first protrusion, and in the groove.
Compared with the prior art, the LED chip structure and the manufacturing method thereof provided by the invention at least realize the following beneficial effects: this application is embedded in N type semiconductor heavily doped layer and N type semiconductor lightly doped layer with the N electrode, adopt such structure, make the current diffusion become the face from the line, reduce the degree that current edge gathered to the N electrode, in addition, the common slot that forms of fretwork portion and recess makes first arch and second arch can block partial current, reduce the heat that can reduce the production below the P electrode when the current gathers in the P electrode below, improve the thermal stability performance of LED chip, and simultaneously, the life of extension LED chip.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a diagram illustrating a structure distribution of an LED chip provided by an embodiment of the present application;
FIG. 2 shows a distribution diagram of an N electrode on an N-type semiconductor lightly doped layer provided by an embodiment of the present application;
FIG. 3 is a diagram illustrating an N-electrode in a heavily doped N-type semiconductor layer according to an embodiment of the present disclosure;
FIG. 4 illustrates a dimensional diagram of a trench provided by an embodiment of the present application;
fig. 5 shows a flowchart of a method for manufacturing an LED chip structure according to an embodiment of the present application.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
The following detailed description is to be read in connection with the drawings and the detailed description.
Example one
Fig. 1 is a distribution diagram of an LED chip structure provided in this embodiment, fig. 2 is a distribution diagram of an N electrode provided in this embodiment located in an N-type semiconductor lightly doped layer, fig. 3 is a distribution diagram of an N electrode provided in this embodiment located in an N-type semiconductor heavily doped layer, as shown in fig. 1-3, an LED chip structure includes a substrate, a U-type gallium nitride layer, an N-type semiconductor layer, a light emitting layer 4, a P-type semiconductor layer 5, and a transparent conductive layer 8, which are sequentially disposed, and the LED chip structure further includes a P electrode 10 located on one side of the transparent conductive layer 8 away from the P-type semiconductor layer and an N electrode 11 located on the N-type semiconductor layer;
the N-type semiconductor layer comprises an N-type semiconductor heavily doped layer and an N-type semiconductor lightly doped layer, and the N-type semiconductor lightly doped layer is positioned on one side, close to the light emitting layer 4, of the N-type semiconductor heavily doped layer; the N-type semiconductor heavily-doped layer comprises a plurality of first bulges 12 and a plurality of grooves 14, and the grooves 14 are positioned between any two adjacent first bulges 12; the N-type semiconductor lightly doped layer comprises a plurality of second protrusions 13 and hollow parts, the second protrusions 13 are located on one side, away from the substrate, of the first protrusions 12, the orthographic projection of each second protrusion 13 on the substrate is not overlapped with the groove 14, and the hollow parts are located between any two adjacent second protrusions 13; the hollow part and the groove 14 together form a groove;
the N electrode covers the side of the second protrusion 13 away from the first protrusion 12 and the groove.
Specifically, the N-electrode 11 is located on the N-type semiconductor layer, and the N-electrode 11 covers the second protrusions 13 on the N-type semiconductor lightly doped layer 3, and the N-electrode 11 covers the grooves 14 on the N-type semiconductor heavily doped layer 2.
This application is embedded in N type semiconductor light doping layer 3 and N type semiconductor heavily doped layer 2 with N electrode 11, adopt such structure, make the electric current diffusion become the face from the line, reduce the degree that electric current gathers to N electrode 11 edge, in addition, the common slot that forms of fretwork portion and recess 14 makes first arch 12 and second arch 13 can block partial electric current, reduce the electric current and gather the heat that can reduce the P electrode below and produce in the time of P electrode 10 below, improve the thermal stability performance of LED chip, and simultaneously, the life of extension LED chip.
Optionally, the depth of the groove 14 in the direction perpendicular to the plane of the substrate is less than the thickness of the heavily doped N-type semiconductor layer.
Specifically, the depth of the groove 14 is smaller than the thickness of the N-type semiconductor heavily doped layer 2, so that the N-electrode is not in contact with the U-type gallium nitride layer 1.
It should be noted that the widths of the first protrusion 12, the second protrusion 13 and the groove 14 are equal and are all greater than the width of the N electrode, so that the N electrode 11 completely covers the second protrusion and the groove 14, and meanwhile, the widths of the first protrusion 12, the second protrusion 13 and the groove 14 cannot be too wide and are different from the width of the N electrode 11 by 3um to 10um, so that the process for manufacturing the first protrusion 12, the second protrusion and the groove 14 is simple and convenient.
Optionally, the depth of the trench is H, and H is greater than or equal to 10nm and less than or equal to 1500nm, along a direction perpendicular to the plane of the substrate.
Specifically, the depth of the groove refers to the distance from the upper surface of the second protrusion 13 to the lower bottom surface of the groove 14, and when the depth of the groove is greater than 10nm, the groove can be ensured to play a role in blocking current, so that the current accumulation degree is effectively reduced; when the depth of the trench is less than 1500nm, the bottom surface of the trench is ensured to be positioned on the N-type semiconductor heavily doped layer 2 and penetrates through the N-type semiconductor heavily doped layer 2.
Alternatively, H1000 nm.
Specifically, when the size of H is 1000nm, the lower bottom surface of the groove is ensured to be positioned on the N-type semiconductor heavily-doped layer, the N-type semiconductor heavily-doped layer is not hollowed out, and in addition, when the size of the groove is 1000nm, the current can be properly blocked.
Alternatively, the first and second protrusions 12 and 13 adjacent in the direction perpendicular to the plane of the substrate may have a trapezoidal overall cross-sectional shape.
Specifically, since the photoresist is vitrified after the photoresist treatment, a certain slope is formed, and the slope is generally 35 to 45 °, so that the included angle between the side edges of the first protrusion and the second protrusion and the horizontal plane is 135 to 145 °, the N electrode 11 is disposed right above the second protrusion 13 and the groove, and the current diffusion below the N electrode 11 is more uniform.
Optionally, a current blocking layer is disposed between the P-type semiconductor layer and the transparent conductive layer, and a protective layer is disposed on the side surface of the light emitting layer, the side surface of the P-type semiconductor layer, and the side surface of the current blocking layer.
In particular, the protective layer serves to protect the chip.
Optionally, the transparent conductive layer is made of indium tin oxide.
Specifically, the material of the transparent conductive layer 8 is tin oxide, so that the transparent conductive layer 8 has good conductivity and high transmittance.
Optionally, the protective layer is made of SiO2。
Specifically, the protective layer is made of SiO2，SiO2Has good insulating effect, SiO2The LED chip can be used as a protective layer.
Optionally, the current blocking layer is made of low-doped gallium nitride and SiO2。
Specifically, the main material of the current blocking layer is SiO2Wherein, a small amount of gallium nitride, SiO is doped2The gallium nitride has stable physical and chemical properties and higher hardness, is a good coating protective material and SiO2And meanwhile, the current can be well blocked when the device is used.
Example two
Fig. 5 is a flowchart of a method for manufacturing an LED chip structure according to an embodiment of the present disclosure, and as shown in fig. 5, the method for manufacturing an LED chip structure includes:
102, forming a U-shaped gallium nitride layer on a substrate;
103, forming an N-type semiconductor heavily-doped layer on one side of the U-type gallium nitride layer away from the substrate, wherein the N-type semiconductor heavily-doped layer comprises a plurality of first bulges 12 and a plurality of grooves 14;
104, forming an N-type semiconductor lightly doped layer on one side, far away from the substrate, of the N-type semiconductor heavily doped layer, wherein the N-type semiconductor lightly doped layer comprises a plurality of second protrusions 13 and hollow parts, the second protrusions 13 are located on one side, far away from the substrate, of the first protrusions 12, the orthographic projections of the second protrusions 13 on the substrate are not overlapped with the grooves 14, and the hollow parts are located between any two adjacent second protrusions 13; the hollow part and the groove 14 together form a groove; the N-type semiconductor heavily doped layer and the N-type semiconductor lightly doped layer jointly form an N-type semiconductor layer, and the N-type semiconductor layer comprises a first region and a second region;
105, forming a light-emitting layer on one side of the N-type semiconductor layer, which is far away from the substrate, wherein the light-emitting layer is positioned in a first area;
and 108, forming a P electrode on one side of the transparent conducting layer, which is far away from the P-type semiconductor layer, and forming an N electrode in a second region of the N-type semiconductor layer, wherein the N electrode is positioned on one side of the second protrusion 13, which is far away from the first protrusion 12, and in the groove.
In the step, the LED chip is cleaned, and a groove 14 is etched on the N-type semiconductor heavily doped layer by adopting an inductively coupled plasma etching method after glue homogenizing, exposure, development and film hardening; replacing the photomask, and etching and hollowing the N-type semiconductor lightly doped layer by adopting an inductively coupled plasma etching method to form a second bulge 13 after glue homogenizing, exposure, development and film hardening; plating a current barrier layer 7(CB) on the P-type semiconductor layer 5 by adopting plasma enhanced chemical vapor deposition, etching a pattern on the current barrier layer by adopting a wet etching mode after glue homogenizing, exposure, development and film hardening, then removing glue and cleaning; plating a transparent conducting layer 8(ITO) on the current blocking layer 7(CB) and the P-type semiconductor layer 5 by adopting an evaporation table; after negative photoresist homogenizing, exposure, hard baking and development, a P electrode 10(P-PAD) is plated on the transparent conducting layer 8 and an N electrode 11(N-PAD) is plated on the N-type semiconductor layer by adopting a sputtering coating method, and then the part with the negative photoresist is removed in a stripping mode to obtain the P electrode 10(P-PAD) and the N electrode 11 (N-PAD); and plating a protective layer 9(PV) on the side surface of the light-emitting layer 4, the side surface of the P-type semiconductor layer 5 and the side surface of the current barrier layer 7(CB) by adopting plasma enhanced chemical vapor deposition, etching a pattern by adopting a wet etching mode after glue homogenizing, exposure, development and film hardening, then removing glue and cleaning. It should be noted that the steps of photoresist coating, exposure, development and film hardening are photolithography steps, in order to obtain the required pattern, when forming the electrodes, in addition to the evaporation stage, the N electrode 11 and the P electrode 10 can be plated by sputtering coating, and in addition, the shapes of the chips with different sizes are different, and the specific etched pattern is determined according to the requirement.
EXAMPLE III
This embodiment introduces a kind of LED chip manufacturing process in detail, including: selecting a substrate, specifically a PSS patterned substrate 6, sequentially arranging a U-shaped gallium nitride layer 1, an N-shaped semiconductor layer, a light emitting layer 4(MQW), a P-shaped semiconductor layer 5, a current blocking layer 7(CB), a transparent conducting layer 8 and a protective layer on the PSS patterned substrate 6, wherein the N-shaped semiconductor layer comprises an N-shaped semiconductor heavy doping layer and an N-shaped semiconductor light doping layer, an N electrode 11 is arranged on the N-shaped semiconductor layer, a P electrode 10 is arranged on the P-shaped semiconductor layer 5, the N electrode 11 is electrically connected with the N-shaped semiconductor layer, the P electrode 10 is electrically connected with the P-shaped semiconductor layer 5, in the specific manufacturing process, cleaning a chip, etching a groove 14 on the N-shaped semiconductor heavy doping layer by adopting a photoetching mode, replacing a photomask, etching and hollowing out to form a second bulge 13 on the N-shaped semiconductor light doping layer, the second bulge 13 is positioned on one side of the first bulge 12 far away from the substrate, and, after the N-type semiconductor light-doped layer and the N-type semiconductor heavy-doped layer are etched, a light-emitting layer 4(MQW) is arranged on a part of the N-type semiconductor light-doped layer, a P-type semiconductor layer 5 is arranged on the light-emitting layer 4(MQW), a current blocking layer 7(CB) is plated on the P-type semiconductor layer 5 by adopting plasma enhanced chemical vapor deposition, the pattern is etched in a photoetching mode, photoresist is removed, cleaning is carried out, a patterned current blocking layer 7(CB) is obtained, a transparent conducting layer 8 is plated on the upper portion of the P-type semiconductor layer 5 in a wrapping mode of the current blocking layer 7(CB) through a sputtering film coating method, a P electrode 10 is plated on the transparent conducting layer 8, an N electrode 11 is plated on the N-type semiconductor layer, then the portion with negative photoresist is removed in a stripping mode, the P electrode 10 and the N electrode 11 are obtained, and finally the side face of the N-type semiconductor, And plating a protective layer on the side surface of the light-emitting layer 4, the side surface of the P-type semiconductor layer 5 and the side surface of the current blocking layer, obtaining a protective layer pattern through photoetching, removing photoresist and cleaning.
In summary, the LED chip structure and the manufacturing method provided by the invention at least achieve the following beneficial effects: this application is embedded in N type semiconductor light doping layer and N type semiconductor heavily doped layer with the N electrode, adopt such structure, make the electric current diffusion become the face from the line, reduce the degree that electric current gathered to N electrode edge, in addition, the common slot that forms of fretwork portion and recess makes first arch and second arch can block partial current, reduce the electric current and gather the heat that can reduce the production below the P electrode when in the P electrode below, improve the thermal stability performance of LED chip, and simultaneously, the life of extension LED chip.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (10)
1. The LED chip structure is characterized by comprising a substrate, a U-shaped gallium nitride layer, an N-shaped semiconductor layer, a light emitting layer, a P-shaped semiconductor layer and a transparent conducting layer which are sequentially arranged, and the LED chip structure further comprises a P electrode and an N electrode, wherein the P electrode is positioned on one side, far away from the P-shaped semiconductor layer, of the transparent conducting layer;
the N-type semiconductor layer comprises an N-type semiconductor heavily doped layer and an N-type semiconductor lightly doped layer, and the N-type semiconductor lightly doped layer is positioned on one side, close to the light emitting layer, of the N-type semiconductor heavily doped layer; the N-type semiconductor heavily-doped layer comprises a plurality of first bulges and a plurality of grooves, and the grooves are positioned between any two adjacent first bulges; the N-type semiconductor lightly doped layer comprises a plurality of second protrusions and hollow parts, the second protrusions are located on one side, away from the substrate, of the first protrusions, the orthographic projections of the second protrusions on the substrate are not overlapped with the grooves, and the hollow parts are located between any two adjacent second protrusions; the hollow part and the groove together form a groove;
the N electrode covers one side of the second protrusion far away from the first protrusion and the groove.
2. The LED chip structure of claim 1, wherein the depth of said recess is less than the thickness of said heavily doped N-type semiconductor layer in a direction perpendicular to the plane of the substrate.
3. The LED chip structure of claim 1, wherein the depth of the trench is H, H is 10nm or more and 1500nm or less in a direction perpendicular to the plane of the substrate.
4. The LED chip structure of claim 1, wherein H is 1000 nm.
5. The LED chip structure of claim 1, wherein the first protrusion and the second protrusion adjacent to each other in a direction perpendicular to the plane of the substrate have a trapezoidal overall cross-sectional shape.
6. The LED chip structure of claim 1, wherein a current blocking layer is disposed between the P-type semiconductor layer and the transparent conductive layer, and a protective layer is disposed on the side of the light emitting layer, the side of the P-type semiconductor layer, and the side of the current blocking layer.
7. The LED chip structure of claim 1, wherein the transparent conductive layer is made of ITO.
8. The LED chip structure of claim 1, wherein the protective layer is made of SiO2。
9. The LED chip structure of claim 1, wherein the current blocking layer is made of low-doped GaN and SiO2。
10. A method for fabricating the LED chip structure according to any one of claims 1 to 9, wherein the method for fabricating comprises:
providing a substrate;
forming a U-shaped gallium nitride layer on a substrate;
forming an N-type semiconductor heavily-doped layer on one side, far away from the substrate, of the U-shaped gallium nitride layer, wherein the N-type semiconductor heavily-doped layer comprises a plurality of first bulges and a plurality of grooves;
forming an N-type semiconductor lightly doped layer on one side, far away from the substrate, of the N-type semiconductor heavily doped layer, wherein the N-type semiconductor lightly doped layer comprises a plurality of second protrusions and hollow parts, the second protrusions are located on one side, far away from the substrate, of the first protrusions, the orthographic projections of the second protrusions on the substrate are not overlapped with the grooves, and the hollow parts are located between any two adjacent second protrusions; the hollow part and the groove together form a groove; the N-type semiconductor heavily doped layer and the N-type semiconductor lightly doped layer jointly form an N-type semiconductor layer, and the N-type semiconductor layer comprises a first region and a second region;
forming a light emitting layer on one side of the N-type semiconductor layer, which is far away from the substrate, wherein the light emitting layer is positioned in the first area;
forming a P-type semiconductor layer on one side of the light-emitting layer far away from the substrate;
forming a transparent conducting layer on one side of the P-type semiconductor layer far away from the substrate;
and forming a P electrode on one side of the transparent conducting layer, which is far away from the P-type semiconductor layer, and forming an N electrode in a second region of the N-type semiconductor layer, wherein the N electrode is positioned on one side of the second protrusion, which is far away from the first protrusion, and in the groove.
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