CN112366264B

CN112366264B - Light emitting diode chip and manufacturing method thereof

Info

Publication number: CN112366264B
Application number: CN202011024565.5A
Authority: CN
Inventors: 张奕; 董彬忠; 王江波
Original assignee: HC Semitek Zhejiang Co Ltd
Current assignee: HC Semitek Zhejiang Co Ltd
Priority date: 2020-09-25
Filing date: 2020-09-25
Publication date: 2022-01-14
Anticipated expiration: 2040-09-25
Also published as: CN112366264A

Abstract

The disclosure provides a light emitting diode chip and a manufacturing method thereof, and belongs to the technical field of semiconductors. The light-emitting diode chip comprises a substrate, an epitaxial layer positioned on the substrate and a transparent conducting layer positioned on the epitaxial layer, and further comprises an N electrode and a P electrode, wherein the transparent conducting layer is provided with a through hole extending to the N layer, the N electrode is arranged in the through hole and in ohmic contact with the N layer, the P electrode is arranged on a region of the transparent conducting layer corresponding to the P layer and in ohmic contact with the P layer, the light-emitting diode chip further comprises a passivation layer arranged on the transparent conducting layer, and the orthographic projection of the passivation layer on the transparent conducting layer is positioned outside the orthographic projection of the N electrode and the P electrode on the transparent conducting layer; the surface of the transparent conducting layer, which is in contact with the passivation layer, is also provided with a plurality of grooves, the passivation layer is positioned in the grooves and is made of SiO₂And (3) a layer. The chip can reduce the light absorption of the transparent conducting layer and improve the light emitting efficiency of the chip.

Description

Light emitting diode chip and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a light emitting diode chip and a method for manufacturing the same.

Background

A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. The chip is the core component of the LED.

The LED chip comprises a substrate and an epitaxial layer arranged on the substrate, wherein the epitaxial layer comprises an N-type layer, an active layer and a P-type layer which are sequentially stacked on the substrate, the LED chip further comprises an N electrode and a P electrode, a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N electrode is arranged on the N-type semiconductor layer in the groove, and the P electrode is arranged on the P-type semiconductor layer. Since the mobility of holes in the P-type semiconductor is poor, the lateral spread of the current injected through the P-electrode in the P-type semiconductor layer is poor, which leads to low luminous efficiency of the LED. In order to promote the lateral spreading of the current injected by the P-electrode, a transparent conductive layer is usually laid on the epitaxial layer, and the P-electrode is disposed on the region of the transparent conductive layer corresponding to the P-type layer. In this way, the current injected by the P electrode can be laterally expanded in the transparent conductive layer and then longitudinally injected into the P-type semiconductor layer, so as to promote the lateral expansion of the current and improve the light emitting efficiency of the chip. In order to protect the chip, a passivation layer is generally applied to the surface of the chip except for the areas where the P-electrode and the N-electrode are disposed.

The transparent conductive layer is usually made of Indium Tin Oxide (ITO), and although the transparent conductive layer is transparent, light emitted from the active layer is absorbed, which may affect the light-emitting efficiency of the chip and reduce the light-emitting brightness of the chip.

Disclosure of Invention

The embodiment of the disclosure provides a light emitting diode chip and a manufacturing method thereof, which can reduce light absorption of a transparent conducting layer and improve light extraction efficiency of the chip. The technical scheme is as follows:

in one aspect, a light emitting diode chip is provided, the light emitting diode chip comprising a substrate, an epitaxial layer on the substrate, and a transparent conductive layer on the epitaxial layer, the epitaxial layer comprises an N-type layer, an active layer and a P-type layer which are sequentially stacked on the substrate, the light emitting diode chip further comprises an N electrode and a P electrode, the transparent conducting layer is provided with a through hole extending to the N-type layer, the N electrode is arranged in the through hole and in ohmic contact with the N-type layer, the P electrode is arranged on the region of the transparent conducting layer corresponding to the P-type layer, ohmic contact with the P-type layer, the light emitting diode chip further comprising a passivation layer disposed on the transparent conductive layer, the orthographic projection of the passivation layer on the transparent conducting layer is positioned outside the orthographic projection of the N electrode and the P electrode on the transparent conducting layer;

the surface of the transparent conducting layer, which is in contact with the passivation layer, is also provided with a plurality of grooves, the passivation layer is positioned in the grooves and is made of SiO₂And (3) a layer.

Optionally, the N electrode includes a first pad and a first finger, the first pad is located at one end of the light emitting diode chip in the cross-sectional direction of the light emitting diode chip, one end of the first finger is connected to the first pad, and the other end of the first finger extends toward the other end of the light emitting diode chip;

the P electrode comprises a second bonding pad and a second finger, the second bonding pad is positioned at the other end of the light-emitting diode chip in the cross section direction of the light-emitting diode chip, one end of the second finger is connected with the second bonding pad, and the other end of the second finger extends towards one end of the light-emitting diode chip;

the first finger and the second finger are arranged in parallel at intervals, and the plurality of grooves are arranged between the first finger and the second finger.

Optionally, the plurality of grooves are arranged between the first finger and the second finger in multiple rows side by side, each row of grooves is parallel to the first finger and the second finger, and each row of grooves comprises a plurality of grooves arranged at intervals.

Optionally, the cross-section of a plurality of said grooves is circular.

Optionally, in a direction from the second finger to the first finger, the diameters of the cross sections of the grooves in the multiple rows are gradually increased, and the diameters of the cross sections of the grooves in the same row are the same.

Optionally, the interval between each groove in the same row of grooves is d times of the diameter of the cross section of each groove in the row of grooves, and the value of d gradually decreases from the second finger to the first finger.

Optionally, the transparent conductive layer is provided with a plurality of strip-shaped areas between the first finger and the second finger, the plurality of strip-shaped areas extend along the extending direction of the first finger or the second finger, the plurality of grooves are respectively distributed in the plurality of strip-shaped areas, and the number of the grooves in the plurality of strip-shaped areas gradually increases from the second finger to the first finger.

Optionally, the cross-sectional areas of the plurality of strip-shaped regions are equal, and the grooves in each strip-shaped region are uniformly distributed in the strip-shaped region.

Optionally, the distance between the first finger and the second finger is 180-250 um.

In another aspect, a method for manufacturing a light emitting diode chip is provided, where the method includes:

providing a substrate;

growing an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type layer, an active layer and a P-type layer which are sequentially grown;

forming a transparent conducting layer on the epitaxial layer, wherein the transparent conducting layer is provided with a through hole extending to the N-type layer, and the transparent conducting layer is also provided with a plurality of grooves;

forming an N electrode on the N-type layer, wherein the N electrode is arranged in the through hole and in ohmic contact with the N-type layer;

forming a P electrode on the transparent conducting layer, wherein the P electrode is arranged on the region, corresponding to the P-type layer, of the transparent conducting layer and is in ohmic contact with the P-type layer;

forming a passivation layer on the transparent conductive layer, wherein the orthographic projection of the passivation layer on the transparent conductive layer is positioned outside the orthographic projection of the N electrode and the orthographic projection of the P electrode on the transparent conductive layer, the passivation layer is positioned in the grooves, and the passivation layer is made of SiO₂And (3) a layer.

The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:

by arranging the plurality of grooves on the transparent conductive layer, the passivation layer is positioned in the plurality of grooves, and the groove part can be covered and filled by the passivation layer, which is equivalent to the reduction of the arrangement of the transparent conductive layer. Because the passivation layer is SiO₂Layer of SiO₂The layer has better light transmission effect, therefore, SiO with better light transmission is adopted₂The passivation layer replaces part of the transparent conducting layer, so that the light absorption effect of the transparent conducting layer can be reduced, and the light emitting efficiency of the chip is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a front view of a light emitting diode chip provided in an embodiment of the present disclosure;

fig. 2 is a top view of a light emitting diode chip provided in an embodiment of the present disclosure;

fig. 3 is a top view of another led chip provided in the embodiments of the present disclosure;

fig. 4 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a front view of a light emitting diode chip provided by an embodiment of the present disclosure, and as shown in fig. 1, the light emitting diode chip includes a substrate 10, an epitaxial layer 20 on the substrate 10, and a transparent conductive layer 30 on the epitaxial layer 20. The epitaxial layer 20 includes an N-type layer 21, an active layer 22, and a P-type layer 23 sequentially stacked on the substrate 10.

The light emitting diode chip further includes an N electrode 40 and a P electrode 50. The transparent conductive layer 30 is provided with a through hole extending to the N-type layer, and the N electrode 40 is disposed in the through hole to make ohmic contact with the N-type layer 21. The P-electrode 50 is disposed on a region of the transparent conductive layer 30 corresponding to the P-type layer 23, and is in ohmic contact with the P-type layer 23.

The light emitting diode chip further includes a passivation layer 60 disposed on the transparent conductive layer 30, and an orthogonal projection of the passivation layer 60 on the transparent conductive layer 30 is located outside an orthogonal projection of the N electrode 40 and the P electrode 50 on the transparent conductive layer 60.

A plurality of grooves 30b (see fig. 2 or 3) are further formed on one surface of the transparent conductive layer 30, which is in contact with the passivation layer 60, the passivation layer 60 is located in the grooves 30b, and the passivation layer 60 is SiO₂And (3) a layer.

According to the embodiment of the disclosure, the plurality of grooves are arranged on the transparent conductive layer, so that the passivation layer is positioned in the plurality of grooves, and the grooves can be covered and filled by the passivation layer, which is equivalent to reduction of the number of groovesAnd arranging a transparent conductive layer. Because the passivation layer is SiO₂Layer of SiO₂The layer has better light transmission effect, therefore, SiO with better light transmission is adopted₂The passivation layer replaces part of the transparent conducting layer, so that the light absorption effect of the transparent conducting layer can be reduced, and the light emitting efficiency of the chip is improved.

In the embodiment of the present disclosure, the transparent conductive layer 30 is generally an Indium Tin Oxide (ITO) layer, and the ITO layer is an In layer₂O₃And SnO₂The materials are uniformly mixed according to a certain proportion. After the contact surface of the ITO layer and the semiconductor and the contact surface of the metal electrode are subjected to annealing process under certain conditions, very small contact resistance can be formed. When the ITO layer reaches a certain deposition thickness, the capability of conducting current transversely can be greatly enhanced, so that the light-emitting area and the efficiency of the light-emitting diode are improved.

Fig. 2 is a top view of a light emitting diode chip provided by an embodiment of the present disclosure, and as shown in fig. 2, the N electrode 40 includes a first pad 41 and a first finger 42. In the cross-sectional direction of the led chip, the first pad 41 is located at one end of the led chip, one end of the first finger 42 is connected to the first pad 41, and the other end of the first finger 42 extends toward the other end of the led chip.

The P-electrode 50 includes a second pad 51 and a second finger 52. In the cross-sectional direction of the led chip, the second bonding pad 51 is located at the other end of the led chip, and one end of the second finger 52 is connected to the second bonding pad 51, and the other end of the second finger 52 extends toward the one end of the led chip.

The first finger 42 and the second finger 52 are arranged in parallel and spaced apart, and the plurality of grooves 30b are arranged between the first finger 42 and the second finger 52, and the current can be conducted from the second finger 52 to the first finger 42 in parallel and transversely.

In the disclosed embodiment, the first finger 42 and the second finger 52 are the same in shape and size, and are both strip-shaped. The length of the fingers in the extending direction may be set according to the size of the chip.

In a first implementation of the disclosed embodiment, as shown in fig. 2, a plurality of grooves 30b are arranged in a plurality of rows side by side between the first finger 42 and the second finger 52, each row of grooves is parallel to the first finger 42 and the second finger 52, and each row of grooves includes a plurality of grooves 30b spaced apart.

Considering that the current in the transparent conductive layer is gradually attenuated as the distance from the second finger 52 increases, the arrangement direction of the grooves for dispersing the current is arranged to be parallel to the fingers, so that the current density in the transparent conductive layer of each row of the pattern area can be ensured to be basically consistent, and the uniformity of the light emission of the epitaxial layer can be ensured to the maximum extent.

Alternatively, the plurality of grooves 30b are all circular in cross-section. The circular design is relatively simple, and the symmetrical characteristic of the circular design is favorable for uniform scattering of light.

In other implementations of the disclosed embodiment, the cross section of the plurality of grooves 30b may also be in a regular pattern such as an ellipse, a square, a trapezoid, a triangle, or a polygon. When the cross section of the plurality of grooves 30b is a trapezoid, the narrow side of the trapezoid may face the second finger 52, and when the cross section of the plurality of grooves 30b is an isosceles triangle, the vertex angle of the isosceles triangle may face the second finger 52, which has a better effect on current dispersion.

Because the N-type layer can be exposed only by etching, and the area of an effective light-emitting area can be eliminated in the etching process, the etching area of the N-type layer is usually only enough to be used as an electrode, the injection current of the P-side electrode is basically and completely conducted and expanded by the transparent conducting layer covered on the surface of the P-type GaN, and the area of the transparent conducting layer covered on the surface of the P-type GaN is far larger than that covered by the N-type GaN. As the current in the transparent conductive layer decays with increasing distance from the P electrode, the current spreading work gradually turns to be borne by the N-type layer. That is, the closer to the P electrode, the lower the sheet resistance of the transparent conductive layer is required.

The current is gathered in the finger area close to the P electrode, so that the opening area of the transparent conductive layer cannot be too large, otherwise, the outward expansion of the current is influenced, the current throughput in the transparent conductive layer of the finger area close to the N electrode is little, so that the opening can be enlarged, and the coverage area of the transparent conductive layer is reduced.

Alternatively, the cross-sectional diameters of the grooves in the rows increase progressively in the direction from the second finger 52 to the first finger 42, with the cross-sectional diameters of the grooves 30b in the same row being the same.

The arrangement may be such that the diameter of the cross section of the groove near the N-electrode is larger than the diameter of the cross section of the groove near the N-electrode to secure the current spreading effect of the current spreading layer.

It should be noted that, in the embodiment of the present disclosure, the number of rows of the grooves depends on the chip size and the size of the space between the first finger 42 and the second finger 52. If the number of columns is too large, the ITO volume will be insufficient, and thicker ITO may be needed to compensate for the current spreading problem, which also results in reduced light extraction. If the number of rows is too small, the effect of improving the light output will be greatly reduced.

Illustratively, as shown in fig. 2, 5 rows of grooves are provided between the first finger 42 and the second finger 52, and the 5 rows of grooves are, in order from the second finger 52 to the first finger 42, a first row of grooves M1, a second row of grooves M2, a third row of grooves M3, a fourth row of grooves M4 and a fifth row of grooves M5.

Wherein, the diameter d1 of first row recess M1 is 1 ~ 3um, and the diameter d2 of second row recess M2 is 3 ~ 5um, and the diameter d3 of third row recess M3 is 5 ~ 7um, and the diameter d4 of fourth row recess M4 is 8 ~ 10um, and the diameter d5 of fifth row recess M5 is 10 ~ 15 um.

Optionally, the interval between the grooves 30b in the same row of grooves is f times the diameter of the cross section of each groove 30b in the row of grooves, and f gradually decreases from the second finger 52 to the first finger 42.

Since the diameter of each row of grooves gradually increases in the direction from the second finger 52 to the first finger 42, setting f to gradually decrease can ensure that the area occupied by the whole of the plurality of grooves is smaller and the arrangement of the plurality of grooves can be made tighter. The transparent conducting layer provided with the grooves is thin, so that high light-emitting rate can be obtained, and meanwhile, the porous structure has the effect similar to surface roughening and is also beneficial to light emitting. Therefore, the grooves are arranged closely, the two light emitting effects are overlapped, and the light emitting can be promoted to the maximum extent.

Illustratively, as shown in FIG. 2, the spacing between each groove 30b in the first row of grooves M1 is f1 times of d1, 10 ≦ f1 ≦ 15, the spacing between each groove 30b in the second row of grooves M2 is f2 times of d2, 10 ≦ f2 ≦ 12, the spacing between each groove 30b in the third row of grooves M3 is f3 times of d3, 8 ≦ f3 ≦ 10, the spacing between each groove 30b in the fourth row of grooves M4 is f4 times of d4, 5 ≦ f4 ≦ 8, and the spacing between each groove 30b in the fifth row of grooves M5 is f5 times of d5, 4 ≦ f5 ≦ 6.

It should be noted that, in the embodiment of the present disclosure, the interval Q between the grooves is the distance between the centers of the cross sections of the grooves.

Illustratively, as shown in fig. 2, a distance L1 between the first row of grooves M1 and the second row of grooves M2 is 20um, a distance L2 between the second row of grooves M2 and the third row of grooves M3 is 40um, a distance L3 between the third row of grooves M3 and the fourth row of grooves M4 is 50um, and a distance L4 between the fourth row of grooves M4 and the fifth row of grooves M5 is 60 um.

It should be noted that, in the embodiment of the present disclosure, the distance between two rows of grooves is the distance between the line connecting the centers of the cross sections of the plurality of grooves in the same row of grooves and the line connecting the centers of the cross sections of the plurality of grooves in the other row of grooves.

Illustratively, the fifth row of grooves M5 is the row of grooves closest to the first finger 42, the first row of grooves M1 is the row of grooves closest to the second finger 52, the distance L5 between the fifth row of grooves M5 and the first finger 42 is 20um, and the distance L0 between the first row of grooves M1 and the second finger 52 is 10 um.

It should be noted that, in the embodiments of the present disclosure, the distance from each row of grooves to the finger is the distance between the line connecting the centers of the cross sections of the plurality of grooves in each row of grooves and the center line of the finger.

In a second implementation of the disclosed embodiment, there are multiple transparent conductive layers of strip-shaped areas between the first finger 42 and the second finger 52. The plurality of bar-shaped areas extend along the extending direction of the first finger 42 or the second finger 52. The plurality of grooves 30b are respectively distributed in the plurality of bar-shaped areas. The number of grooves 30b in the plurality of bar-shaped areas gradually increases in a direction from the second finger 52 to the first finger 42.

The occupation ratio of the grooves in each stripe region gradually increases from the P electrode to the N electrode. The transparent conducting layer current close to the P electrode is gathered, so that the occupation ratio of the groove close to the P electrode is less, the current is favorably diffused to the N electrode, the throughput of the current in the transparent conducting layer close to the N electrode is less, and the occupation ratio of the groove close to the N electrode is larger, so that the light extraction efficiency is improved.

Alternatively, the cross-sectional areas of the plurality of stripe regions are equal, and the grooves 30b in each stripe region are uniformly distributed in the stripe region.

Because the porous structure has the effect similar to surface roughening, the grooves 30b in each strip-shaped area are uniformly distributed, namely, the surface of each strip-shaped area is uniformly roughened, and light emission is facilitated.

Alternatively, the cross-sectional area of the plurality of bar-shaped regions gradually increases from the second finger 52 to the first finger 51. The number of grooves 30b that can be provided in each strip-shaped area is larger, and it can be facilitated to realize a gradual increase in the number of grooves 30b in a plurality of strip-shaped areas.

Alternatively, the cross section of the groove 30b in each strip-shaped region is circular, the circular design is relatively simple, and the symmetrical characteristic is favorable for uniform scattering of light.

Alternatively, the cross-sectional diameters of the grooves 30b in the respective strip-shaped regions are all equal.

Illustratively, there are 20 bar-shaped regions of transparent conductive layer between the first finger 42 and the second finger 52. The total cross-sectional area of the grooves 30b in the region closest to the second finger 52 accounts for 2% of the total cross-sectional area of the transparent conductive layer 30, and the total cross-sectional area of the grooves 30b in the region closest to the first finger 42 accounts for 70% of the total cross-sectional area of the transparent conductive layer 30.

Alternatively, in the direction from the second finger 52 to the first finger 42, the ratio of the total cross-sectional area of the grooves 30b in the plurality of stripe-shaped regions to the total cross-sectional area of the transparent conductive layer 30 gradually increases at a rate of 20.5%, that is, the total cross-sectional area of the grooves 30b in the next stripe-shaped region is 1.205 times the total cross-sectional area of the grooves 30b in the current stripe-shaped region.

Fig. 3 is a top view of another light emitting diode chip provided in the embodiment of the present disclosure, and as shown in fig. 3, there are 10 stripe regions between the first finger 42 and the second finger 52, where the 10 stripe regions include: regions P1, P2, … …, P10. Wherein the cross-sectional areas S of the 10 strip-shaped regions are all equal. The number of grooves 30b in each region gradually increases from region P1 to region P10. Only a partial region and a partial recess 30b are shown in fig. 3.

Illustratively, the cross-sectional area S of each strip-shaped region is 10000um²Wherein the length L of the cross section of each strip-shaped region_SIs 500um, width D_sIs 20 um. The cross-section S of the groove 30b in each strip-shaped region has a diameter of 1 um.

600 grooves 30b are uniformly distributed in the region P1, and the total area of the cross sections of the grooves 30b in the region P1 is less than 5% of the total cross section area of the transparent conductive layer. 2500 grooves 30b are uniformly distributed in the region P10, and the total area of the cross sections of the grooves 30b in the region P10 is more than 20% of the total cross section area of the transparent conductive layer.

Alternatively, from the region P1 to the region P10, the proportion of the total cross-sectional area of the respective region grooves 30b to the total cross-sectional area of the transparent conductive layer 30 gradually increases at a rate of 16%. For example, the total cross-sectional area of grooves 30b in region P2 is 1.61 times the total cross-sectional area of grooves 30b in region P1.

Optionally, the first finger 42 and the second finger 52 are spaced apart 180-250 um.

In the disclosed embodiment, the size of the chip is 10 mils by 20 mils, i.e., 254um by 508 um. The fingers are parallel to the long sides of the chip, so the finger pitch is smaller than the width of the chip, i.e. smaller than 254 um.

Illustratively, the spacing L between the first finger 42 and the second finger 52 is 200 um. As shown in fig. 2, at this time, L0+ L1+ L2+ L3+ L4+ L5 is L200 um.

Optionally, the depths of the grooves 30b are the same, and all the grooves are equal to or greater than 50nm and less than or equal to h and less than or equal to 160 nm. The depth of the groove is not suitable to be too deep, otherwise the epitaxial layer can be damaged in the process, so that the current expansion is insufficient, and the carrier injection efficiency is low. And the depth of the groove is too shallow, and the light emitting efficiency cannot be effectively improved.

Alternatively, the thickness of the transparent conductive layer 30 may be 100nm to 300nm, such as 200 nm. The thickness of the passivation layer may be 200nm to 1 um.

Alternatively, the material of the substrate 10 may be one of sapphire, silicon, gallium nitride, silicon carbide, and glass, such as a flat sapphire substrate or a patterned sapphire substrate. The material of the N-type layer 21 may be N-type doped (e.g., Si) GaN. The active layer 22 may include a plurality of quantum wells and a plurality of quantum barriers, which are alternately stacked. The material of the quantum well can adopt InGaN, and the material of the quantum barrier can adopt GaN. The P-type layer 23 may be P-doped (e.g., Mg) GaN. The material of the N-electrode 51 and the P-electrode 52 may be one or more of gold (Au), aluminum (Al), nickel (Ni), platinum (Pt), chromium (Cr), and titanium (Ti).

Further, the thickness of the N-type layer 21 may be from lum to 5um, preferably 3 μm. The doping concentration of the N-type dopant in the N-type layer 21 may be 10¹⁸/cm³～10¹⁹/cm³Preferably 5 x 10¹⁸/cm³. The quantum well may have a thickness of 2.5nm to 3.5nm, preferably 3 nm. The thickness of the quantum barrier may be 9nm to 20nm, preferably 15 nm. The number of quantum wells is the same as the number of quantum barriers, and the number of quantum barriers may be 5 to 15, preferably 10. The thickness of the P-type layer 23 may be 100nm to 800nm, preferably 450 nm. The doping concentration of the P-type dopant in the P-type layer 23 may be 10¹⁸/cm³～10²⁰/cm³Preferably 10¹⁹/cm³。

The embodiment of the present disclosure provides a method for manufacturing a light emitting diode chip, which is suitable for manufacturing the light emitting diode chip described in the above embodiment, and fig. 4 is a flowchart of a method for manufacturing a light emitting diode chip provided in the embodiment of the present disclosure, and as shown in fig. 4, the method for manufacturing a light emitting diode chip includes:

step 401, a substrate is provided.

Illustratively, the material of the substrate may be one of sapphire, silicon, gallium nitride, silicon carbide, and glass, such as a flat sapphire substrate or a patterned sapphire substrate.

Step 402, an epitaxial layer is grown on a substrate.

The epitaxial layer comprises an N-type layer, an active layer and a P-type layer which are grown in sequence. An N-type layer, an active layer, and a P-type layer may be sequentially grown on the substrate using a Metal Organic Chemical Vapor Deposition (MOCVD) technique.

Illustratively, an N-type layer is grown on the substrate by controlling the temperature of the reaction chamber at 1100 ℃ and the pressure at 200 torr. And controlling the temperature of the reaction cavity to be 700-800 ℃, and the pressure to be 200torr, and growing an active layer on the N-type layer. And controlling the temperature of the reaction cavity at 900 ℃ and the pressure at 200torr, and growing a P-type layer on the active layer.

Illustratively, step 402 may further include:

and forming a groove extending to the N-type layer on the P-type layer by utilizing a photoetching technology and an etching technology so as to expose the N-type layer.

This is conventional technology, and the embodiments of the present disclosure are not described herein again.

Step 403, forming a transparent conductive layer on the epitaxial layer.

As shown in fig. 1 to 3, the transparent conductive layer 30 is provided with a through hole 30a extending to the N-type layer 21, and the transparent conductive layer 30 is further provided with a plurality of grooves 30 b.

Illustratively, step 403 may include:

evaporating an ITO film with the thickness of 100 nm-300 nm on the surface of the epitaxial layer, and annealing the ITO film, wherein the annealing temperature is 550-650 ℃, and the annealing time is 4-5 min;

uniformly spin-coating the positive photoresist on the surface of the epitaxial layer, wherein the spin-coating thickness is 8-20 um;

baking the epitaxial layer after the spin coating for 5-20 min at 150 ℃;

covering a photoetching plate on the epitaxial layer, and carrying out exposure treatment on the epitaxial layer for 1-2 min, wherein the design pattern of the photoetching plate requires that a plurality of grooves 30b shown in the above-mentioned figure 2 or figure 3 can be formed on the transparent conducting layer 30, and the embodiment of the disclosure is not described again here;

cleaning the epitaxial layer subjected to exposure treatment by using a potassium hydroxide developing solution, and removing the photoresist at the exposure softening position until the photoetching pattern transfer is finished;

etching the epitaxial layer subjected to pattern transfer by using an ITO (indium tin oxide) etching solution, wherein the etching depth of the ITO is 80-95% of the deposition thickness of the ITO, and the ITO etching solution can be a hydrogen chloride solution;

and removing residual ITO corrosive liquid and photoresist by using potassium hydroxide, acetone and absolute ethyl alcohol until only an ITO deposition layer is on the surface.

Wherein, annealing the ITO thin film can reduce the square resistance and the contact resistance.

Step 404 forms a passivation layer on the transparent conductive layer.

Wherein, the orthographic projection of the passivation layer on the transparent conducting layer is positioned outside the orthographic projection of the N electrode and the P electrode on the transparent conducting layer, the passivation layer is positioned in the grooves, and the passivation layer is SiO₂And (3) a layer.

Step 404 may include:

and placing the cleaned epitaxial layer in a PECVD (Plasma Enhanced Chemical Vapor Deposition) cavity, and performing passivation layer Deposition treatment, wherein the Deposition thickness of the passivation layer is 200 nm-1 um.

Step 405, form an N electrode on the N-type layer.

And the N electrode is arranged in the through hole and in ohmic contact with the N type layer.

As shown in fig. 2, the N electrode 40 includes a first pad 41 and a first finger 42. In the cross-sectional direction of the led chip, the first pad 41 is located at one end of the led chip, one end of the first finger 42 is connected to the first pad 41, and the other end of the first finger 42 extends toward the other end of the led chip.

An N electrode material is laid in the through hole 30a of the transparent conductive layer 30, so that the N electrode is in ohmic contact with the N type layer, and the N electrode can be formed.

Step 406, forming a P electrode on the transparent conductive layer.

The P electrode is arranged on the region of the transparent conducting layer corresponding to the P type layer and is in ohmic contact with the P type layer.

As shown in fig. 2, the P-electrode 50 includes a second pad 51 and a second finger 52. In the cross-sectional direction of the led chip, the second bonding pad 51 is located at the other end of the led chip, and one end of the second finger 52 is connected to the second bonding pad 51, and the other end of the second finger 52 extends toward the one end of the led chip.

And laying a P-electrode material on the region of the transparent conductive layer 30 corresponding to the P-type layer, so that the P-electrode is in ohmic contact with the P-type layer, and thus the P-electrode can be formed.

According to the embodiment of the disclosure, the plurality of grooves are formed in the transparent conductive layer, so that the passivation layer is positioned in the plurality of grooves, and the grooves can be covered and filled by the passivation layer, which is equivalent to the reduction of the arrangement of the transparent conductive layer. Because the passivation layer is SiO₂Layer of SiO₂The layer has better light transmission effect, therefore, SiO with better light transmission is adopted₂The passivation layer replaces part of the transparent conducting layer, so that the light absorption effect of the transparent conducting layer can be reduced, and the light emitting efficiency of the chip is improved.

The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims

1. A light emitting diode chip is characterized by comprising a substrate, an epitaxial layer positioned on the substrate and a transparent conducting layer positioned on the epitaxial layer, the epitaxial layer comprises an N-type layer, an active layer and a P-type layer which are sequentially stacked on the substrate, the light emitting diode chip further comprises an N electrode and a P electrode, the transparent conducting layer is provided with a through hole extending to the N-type layer, the N electrode is arranged in the through hole and in ohmic contact with the N-type layer, the P electrode is arranged on the region of the transparent conducting layer corresponding to the P-type layer, and is in ohmic contact with the P-type layer, the light emitting diode chip further comprises a passivation layer disposed on the transparent conductive layer, the orthographic projection of the passivation layer on the transparent conducting layer is positioned outside the orthographic projection of the N electrode and the P electrode on the transparent conducting layer;

the surface of the transparent conducting layer, which is in contact with the passivation layer, is also provided with a plurality of grooves, the passivation layer is positioned in the grooves and is made of SiO₂A layer;

the N electrode comprises a first bonding pad and a first finger, the first bonding pad is positioned at one end of the light-emitting diode chip in the cross section direction of the light-emitting diode chip, one end of the first finger is connected with the first bonding pad, and the other end of the first finger extends towards the other end of the light-emitting diode chip;

the first finger and the second finger are arranged in parallel at intervals, and the plurality of grooves are arranged between the first finger and the second finger;

the grooves are arranged between the first finger and the second finger in multiple rows in parallel, each row of grooves is parallel to the first finger and the second finger, and each row of grooves comprises a plurality of grooves arranged at intervals;

or, a transparent conductive layer having a plurality of strip-shaped areas is disposed between the first finger and the second finger, the plurality of strip-shaped areas extend along an extending direction of the first finger or the second finger, the plurality of grooves are respectively distributed in the plurality of strip-shaped areas, and the number of grooves in the plurality of strip-shaped areas gradually increases from the second finger to the first finger.

2. The light emitting diode chip of claim 1, wherein the cross-section of each of the plurality of grooves is circular.

3. The light emitting diode chip of claim 2, wherein the cross-sectional diameters of the grooves in the rows increase gradually from the second finger to the first finger, and the cross-sectional diameters of the grooves in the same row are the same.

4. The light emitting diode chip of claim 2, wherein the spacing between each of the grooves in the same row of grooves is f times the diameter of the cross section of each of the grooves in the same row of grooves, and f gradually decreases from the second finger to the first finger.

5. The light-emitting diode chip as claimed in claim 1, wherein the cross-sectional area of a plurality of the stripe regions is equal, and the grooves in each of the stripe regions are uniformly distributed in the stripe regions.

6. The light emitting diode chip of claim 1, wherein a distance between the first finger and the second finger is 180-250 um.

7. A manufacturing method of a light emitting diode chip is characterized by comprising the following steps:

providing a substrate;

forming a passivation layer on the transparent conductive layer, wherein the orthographic projection of the passivation layer on the transparent conductive layer is positioned outside the orthographic projection of the N electrode and the P electrode on the transparent conductive layer, and the passivation layer is positioned at the position of the orthographic projectionIn the grooves, the passivation layer is made of SiO₂A layer;