CN115000093A - Array substrate, manufacturing method thereof and display panel - Google Patents

Array substrate, manufacturing method thereof and display panel Download PDF

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Publication number
CN115000093A
CN115000093A CN202210617497.6A CN202210617497A CN115000093A CN 115000093 A CN115000093 A CN 115000093A CN 202210617497 A CN202210617497 A CN 202210617497A CN 115000093 A CN115000093 A CN 115000093A
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China
Prior art keywords
layer
drain
source
contact
substrate
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CN202210617497.6A
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Chinese (zh)
Inventor
陈寿清
卢马才
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TCL Huaxing Photoelectric Technology Co Ltd
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TCL Huaxing Photoelectric Technology Co Ltd
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Priority to CN202210617497.6A priority Critical patent/CN115000093A/en
Publication of CN115000093A publication Critical patent/CN115000093A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Abstract

The embodiment of the application discloses an array substrate, a manufacturing method thereof and a display panel, wherein the array substrate comprises: the semiconductor device comprises a substrate, an active layer, a first metal layer, an insulating layer and a second metal layer which are arranged in a stacked mode, wherein the active layer comprises a source contact part and a drain contact part; a first connecting hole is formed in the insulating layer between the second metal layer and the source electrode contact part, and a second connecting hole is formed in the insulating layer between the second metal layer and the drain electrode contact part; metal protective layers are arranged between the insulating layer and the source electrode contact part and between the insulating layer and the drain electrode contact part, and the orthographic projection of the metal protective layers in the direction vertical to the substrate at least covers the orthographic projection of the first connecting hole and the orthographic projection of the second connecting hole; according to the technical scheme, the LTPS array substrate can be etched by adopting a conventional gas dry etching scheme, the obtained product has stable performance, the risk coefficient in the etching process is low, the price is low, and the production cost of the LTPS array substrate is effectively reduced.

Description

Array substrate, manufacturing method thereof and display panel
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display panel.
Background
Low Temperature Poly-silicon (LTPS) has the advantages of high mobility and good stability, and is widely used in small-sized display devices.
At present, conventional LTPS dielectric layer etching techniques generally employ a high selectivity etching system, such as hydrofluoric acid wet etching or octafluorocyclobutane plasma etching, wherein hydrofluoric acid hasThe octafluorocyclobutane is a special gas, so that the price is high and the production cost is high. Conventional gas (CF) in the production process of display panel 4 Or NF 3 ) The dry etching scheme has mature technology and low cost, but the problem of polysilicon over-etching is easy to occur during etching.
Therefore, there is a need for an LTPS array substrate structure that is stable and compatible with conventional gas dry etching schemes.
Disclosure of Invention
The embodiment of the application provides an array substrate, a manufacturing method thereof and a display panel, wherein conventional gas (CF) can be adopted 4 Or NF 3 ) The dry etching scheme is used for etching the LTPS array substrate, the obtained product has stable performance, the risk coefficient in the etching process is low, the price is low, and the production cost of the LTPS array substrate is effectively reduced.
An embodiment of the present application provides an array substrate, including:
a substrate;
the active layer is arranged on the substrate and comprises a channel part, a source contact part and a drain contact part, wherein the source contact part and the drain contact part are arranged on two sides of the channel part and are electrically connected with the channel part;
an insulating layer disposed on the substrate and the active layer;
a first metal layer stacked on the insulating layer and provided corresponding to the channel portion;
the second metal layer is arranged above the insulating layer and corresponds to the source electrode contact part and the drain electrode contact part, a first connecting hole is formed in the insulating layer between the second metal layer and the source electrode contact part, a second connecting hole is formed in the insulating layer between the second metal layer and the drain electrode contact part, and the second metal layer penetrates through the first connecting hole and the second connecting hole to be electrically connected with the source electrode contact part and the drain electrode contact part;
and metal protective layers are arranged between the insulating layer and the source electrode contact part and between the insulating layer and the drain electrode contact part, and the orthographic projection of each metal protective layer at least covers the orthographic projection of the first connecting hole and the orthographic projection of the second connecting hole in the direction vertical to the substrate.
Optionally, in a direction perpendicular to the substrate, an orthogonal projection of the metal protection layer is located within an orthogonal projection of the source contact and the drain contact.
Optionally, the active layer further includes a first connection portion disposed between and connecting the source contact portion and the channel portion, and a second connection portion disposed between and connecting the drain contact portion and the channel portion;
the source contact part and the drain contact part are made of amorphous silicon heavily doped with phosphine, and the first connecting part and the second connecting part are made of amorphous silicon lightly doped with phosphine.
Optionally, in a direction perpendicular to the substrate, a thickness of the first connection portion is greater than a thickness of the source contact portion, and a thickness of the second connection portion is greater than a thickness of the drain contact portion.
Optionally, a silicon-based insulating layer is arranged on the metal protection layer, a third connecting hole and a fourth connecting hole are arranged on the silicon-based insulating layer, the third connecting hole is communicated with the first via hole, the fourth connecting hole is communicated with the second via hole, and the material of the silicon-based insulating layer is the same as that of the channel portion.
Optionally, the source contact and the drain contact are made of materials including phosphine-doped amorphous silicon or borane-doped amorphous silicon.
Optionally, the material of the metal protection layer includes any one of Mo, Ti, and an alloy thereof.
The application also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a substrate;
forming an active layer on the substrate, wherein the active layer comprises a channel part, a source contact part and a drain contact part which are arranged at two sides of the channel part and electrically connected with the channel part;
forming a metal protection layer on the source contact and the drain contact;
forming an insulating layer, a first metal layer and a second metal layer stacked on the substrate, the active layer and the metal protection layer, the first metal layer is disposed corresponding to the channel portion, the second metal layer is disposed on the insulating layer, the second metal layer is arranged above the source contact part and the drain contact part, a first connecting hole is arranged on the insulating layer between the second metal layer and the source contact part, a second connection hole is formed in the insulating layer between the second metal layer and the drain contact portion, the second metal layer is electrically connected to the source contact and the drain contact through the first connection hole and the second connection hole, respectively, in a direction perpendicular to the substrate, an orthographic projection of the metal protection layer at least covers orthographic projections of the first connection hole and the second connection hole.
Optionally, the active layer further includes a first connection portion disposed between and connecting the source contact portion and the channel portion, and a second connection portion disposed between and connecting the drain contact portion and the channel portion;
the method comprises the steps that an active layer is formed on a substrate, and the active layer comprises a channel portion, a source contact portion and a drain contact portion, wherein the source contact portion and the drain contact portion are arranged on two sides of the channel portion and electrically connected with the channel portion; the step of forming a metal protection layer on the source contact and the drain contact includes:
forming a source contact portion, a source connecting section connected with the source contact portion, a drain contact portion and a drain connecting section which is connected with the drain contact portion and is close to the source contact portion on the substrate;
forming a metal protection layer on the source contact and the drain contact;
forming a source electrode connecting section on the source electrode connecting section, forming a drain electrode connecting section on the drain electrode connecting section, forming a channel part precursor on the substrate between the source electrode connecting section and the drain electrode connecting section, annealing the source electrode connecting section and the source electrode connecting section to form the first connecting part, annealing the drain electrode connecting section and the drain electrode connecting section to form the second connecting part, and annealing the channel part precursor to form the channel part.
The present application further provides a display panel including the array substrate according to any one of the above embodiments.
The beneficial effects of the invention at least comprise:
through set up the metal protection layer on source contact site and drain contact site, and perpendicular in the direction of substrate, the orthographic projection of metal protection layer covers at least first connecting hole with the orthographic projection of second connecting hole for adopt conventional gas etching insulating layer to form the in-process of first connecting hole and second connecting hole, can not take place the problem of polycrystalline silicon overetching, make the production of LTPS array substrate need not additionally adopt high selection ratio sculpture system, for example hydrofluoric acid wet etching or plasma etching such as octafluorocyclobutane, reduced the manufacturing cost and the production danger coefficient of LTPS array substrate.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a metal protection layer in another structure of an array substrate provided in this embodiment of the present application;
fig. 3 is a schematic structural diagram of another array substrate provided in the present embodiment;
fig. 4 is a schematic structural diagram of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 7 is a structural view of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of a manufacturing method of an array substrate according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 13 is a flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present disclosure;
fig. 14 is a partial manufacturing flow chart of another array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides an array substrate, a manufacturing method thereof and a display panel. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms first, second, third and the like are used merely as labels, and do not impose numerical requirements or an established order. Various embodiments of the invention may exist in a range of versions; it is to be understood that the description in the form of a range is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention; accordingly, the described range descriptions should be considered to have specifically disclosed all the possible sub-ranges as well as individual numerical values within that range. For example, it is contemplated that the description of a range from 1 to 6 has specifically disclosed sub-ranges such as, for example, from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as individual numbers within a range such as, for example, 1, 2, 3, 4, 5, and 6, as applicable regardless of the range. In addition, whenever a numerical range is indicated herein, it is meant to include any number (fractional or integer) recited within the indicated range.
An embodiment of the present application provides an array substrate 101, as shown in fig. 1 and fig. 2, including:
a substrate 10;
an active layer disposed on the substrate 10, the active layer including a channel portion 401, and a source contact 201 and a drain contact 202 disposed at both sides of the channel portion 401 and electrically connected to the channel portion 401;
an insulating layer 50 disposed on the substrate 10 and the active layer;
a first metal layer 60 stacked on the insulating layer 50 and provided corresponding to the channel portion 401;
a second metal layer 70 disposed above the insulating layer 50 and corresponding to the source contact 201 and the drain contact 202, wherein a first connection hole 503 is disposed on the insulating layer 50 between the second metal layer 70 and the source contact 201, a second connection hole 504 is disposed on the insulating layer 50 between the second metal layer 70 and the drain contact 202, and the second metal layer 70 is electrically connected to the source contact 201 and the drain contact 202 through the first connection hole 503 and the second connection hole 504, respectively;
a metal protection layer 30 is disposed between the insulating layer 50 and the source contact 201, and between the insulating layer 50 and the drain contact 202, and an orthogonal projection of the metal protection layer 30 at least covers an orthogonal projection of the first connection hole 503 and an orthogonal projection of the second connection hole 504 in a direction perpendicular to the substrate 10.
It should be noted that the array substrate 101 in the present application includes a plurality of control devices, where the control devices may be Thin Film Transistors (TFTs), and the embodiment of the present application is described in terms of a film structure of one control device.
Specifically, the substrate 10 includes a substrate 101 and a buffer layer 102 disposed on the substrate 101, wherein the substrate 101 includes a glass substrate 101, and the buffer layer 102 is made of a material including, but not limited to, at least one of SiOx, SiNx/SiOx, and SiNOx, and has a thickness of 1500 to 4000 angstroms.
Specifically, the active layer includes a channel portion 401, and a source contact portion 201 and a drain contact portion 202 disposed on two sides of the channel portion 401 and electrically connected to the channel portion 401, wherein a material of the channel portion 401 is different from a material of the source contact portion 201 and a material of the drain contact portion 202, the channel portion 401 is made of low temperature polysilicon, and the source contact portion 201 and the drain contact portion 202 are made of conductive silicon materials, wherein the conductive silicon materials may be P-type hybrid materials formed by doping phosphane or N-type materials formed by doping borane, and a deposition thickness of the conductive silicon materials may be 400 to 1000 angstroms.
Specifically, as shown in fig. 1, the insulating layer 50 is disposed on the substrate 10, the active layer and the metal protection layer 30, the insulating layer 50 includes a gate insulating layer 501 and a dielectric layer 502, the gate insulating layer 501 is disposed on the substrate 10, the active layer and the metal protection layer 30, a first metal layer 60 is disposed on the gate insulating layer 501, the first metal layer 60 includes a gate, the dielectric layer 502 is disposed on the gate and the gate insulating layer 501, a second metal layer 70 is disposed on the dielectric layer 502, the second metal layer 70 includes a source 701 and a drain 702, and the second metal layer 70 includes a source 701 and a drain 702 as an example for explanation in this embodiment.
Specifically, the gate is disposed corresponding to the channel portion 401, the source 701 is disposed corresponding to the source contact portion 201, and the drain 702 is disposed corresponding to the drain contact portion 202.
It should be noted that, in the embodiment of the present application, the gate is located above the channel portion 401 and has a top gate structure, but the arrangement manner of the source 701, the drain 702, the partial insulating layer 50 and the active layer in the embodiment of the present application is also applicable to the bottom gate structure, and details of the array substrate 101 with the bottom gate structure are not repeated in the present application, and specific reference may be made to the array substrate 101 with the top gate structure, which is taken as an example for description in the present application.
Specifically, the material of the first metal layer 60 and the second metal layer 70 includes, but is not limited to, one or more combinations of copper, silver, aluminum, steel, titanium, and alloys thereof.
Specifically, the material of the gate insulating layer 501 and the dielectric layer 502 includes, but is not limited to, silicon dioxide.
Specifically, a first connection hole 503 is disposed on the insulating layer 50 between the second metal layer 70 and the source contact portion 201, a second connection hole 504 is disposed on the insulating layer 50 between the second metal layer 70 and the drain contact portion 202, the second metal layer 70 is electrically connected to the source contact portion 201 and the drain contact portion 202 through the first connection hole 503 and the second connection hole 504, respectively, and in this embodiment, a source 701 is electrically connected to the source contact portion 201 through the first connection hole 503, and a drain 702 is electrically connected to the drain contact portion 202 through the second connection hole 504 will be described as an example.
It should be noted that, in the manufacturing process of the conventional LTPS array substrate 101, the insulating layer 50 is etched to form via holes (i.e., the first connection hole 503 and the second connection hole 504) corresponding to the source/drain contact portion 202 and the drain contact portion 202, so as to avoid the problem of over-etching of polysilicon, but the above-mentioned etching system with a high selection ratio has the disadvantages of high risk coefficient and high cost, and limits the application of the LTPS array substrate 101 to the production of a large-sized display panel, and in order to further reduce the production cost and improve the stability of the process, the conventional gas is used for etching, which provides the technical solution of this embodiment.
As shown in fig. 1 and 2, a metal protection layer 30 is disposed between the source contact 201 and the insulating layer 50, and between the drain contact 202 and the insulating layer 50, respectively, in a conventional gas (CF) 4 Or NF 3 ) During dry etching of the insulating layer 50, a conventional gas (CF) is generated due to the barrier of the metal protection layer 30 4 Or NF 3 ) Polysilicon materials cannot be etched, the manufacturing cost of the LTPS array substrate 101 is effectively reduced, and the production stability of the LTPS array substrate 101 is improved.
Specifically, the material of the metal protection layer 30 may be a high temperature resistant metal, specifically, a high temperature resistant metal resistant to 1000 ℃ or higher, so as to prevent the metal protection layer 30 from melting in a subsequent production process, which may cause other problems.
Specifically, the material of the metal protection layer 30 may be one or a combination of Mo, Ti, or Mo/Ti, and may be formed by PVD deposition, and the deposition thickness may be 50 to 400 angstroms, specifically, any one of 50 angstroms, 80 angstroms, 120 angstroms, 200 angstroms, 350 angstroms, and 400 angstroms, and may be specifically selected according to actual production conditions.
Specifically, the metal protection layer 30 functions to prevent a conventional gas (CF) 4 Or NF 3 ) The polysilicon material is etched, so that the area of the metal protection layer 30 at least covers the orthographic projection of the first connection hole 503 and the second connection hole 504 in the direction perpendicular to the substrate 10.
It should be noted that, in the usual actual production, the vertical cross-sectional shapes of the first connection hole 503 and the second connection hole 504 are inverted trapezoids, so the orthographic projection of the first connection hole 503 refers to the orthographic projection of the opening of the first connection hole 503 near the end of the source contact portion 201, and the orthographic projection of the second connection hole 504 refers to the orthographic projection of the opening of the second connection hole 504 near the end of the drain contact portion 202.
Specifically, an orthogonal projection of the metal protection layer 30 on the source contact 201 may coincide with an orthogonal projection of a contact surface between the source contact 201 and the metal protection layer 30, as shown in fig. 1, or may be smaller than an orthogonal projection of the source contact 201 (upper surface), as shown in fig. 2.
It can be understood that, by disposing the metal protection layer 30 on the source contact 201 and the drain contact 202, and in a direction perpendicular to the substrate 10, the orthographic projection of the metal protection layer 30 at least covers the orthographic projection of the first connection hole 503 and the orthographic projection of the second connection hole 504, so that in the process of etching the insulating layer 50 by using a conventional gas to form the first connection hole 503 and the second connection hole 504, the problem of polysilicon over-etching does not occur, and the LTPS array substrate 101 does not need to be produced by additionally using a high selectivity etching system, such as hydrofluoric acid wet etching or octafluorocyclobutane plasma etching, which effectively reduces the production cost and the production risk coefficient of the LTPS array substrate 101 and improves the stability of the device.
In one embodiment, as shown in fig. 2, an orthogonal projection of the metal protection layer 30 is located within an orthogonal projection of the source contact 201 and the drain contact 202 in a direction perpendicular to the substrate 10.
Specifically, an orthogonal projection of the metal protection layer 30 on the source contact 201 is located on an upper surface of the source contact 201, and an orthogonal projection of the metal protection layer 30 on the drain contact 202 is located on an upper surface of the drain contact 202.
In another example, an orthogonal projection of the metal protection layer 30 is disposed within an orthogonal projection of the source contact 201 and the drain contact 202.
It can be understood that, by the above arrangement, the amount of the material used for the metal protection layer 30 can be reduced, and the production cost of the LTPS array substrate 101 can be reduced.
In one embodiment, as shown in fig. 3, the active layer further includes a first connection portion 402 disposed between the source contact portion 201 and the channel portion 401 and connecting the source contact portion 201 and the channel portion 401, a second connection portion 403 disposed between the drain contact portion 202 and the channel portion 401 and connecting the drain contact portion 202 and the channel portion 401;
wherein the material of the source contact 201 and the drain contact 202 comprises phosphine-doped amorphous silicon layer 20, and the material of the first connection 402 and the second connection 403 comprises phosphine-lightly doped amorphous silicon.
It should be noted that, in particular, in the structure of the P-type controller, in order to further improve the stability of the thin film transistor, improve the electric field distribution at the connection end of the source/drain 702, and reduce the electron migration phenomenon at the connection end of the source/drain 702 in the off state, thereby reducing the leakage current of the thin film transistor and reducing the power loss, the first connection portion 402 and the second connection portion 403 which are lightly doped are respectively disposed between the source contact portion 201 and the drain contact portion 202, and the channel portion 401.
Specifically, the first connection portion 402 and the second connection portion 403 may be formed by the same process as the channel portion 401.
It can be understood that by disposing the active layer of the P-type thin film transistor including the first connection portion 402 disposed between the source contact portion 201 and the channel portion 401 and connecting the source contact portion 201 and the channel portion 401, and the second connection portion 403 disposed between the drain contact portion 202 and the channel portion 401 and connecting the drain contact portion 202 and the channel portion 401, the electric field distribution at the connection end of the source 701 and the drain 702 can be improved, the electron transfer phenomenon at the connection end of the source 701 and the drain 702 in the off state can be reduced, and thus the device leakage current can be reduced, and the power loss can be reduced.
In the above embodiment, the thickness of the first connection portion 402 is greater than that of the source contact portion 201, and the thickness of the second connection portion 403 is greater than that of the drain contact portion 202 in the direction perpendicular to the substrate 10.
Note that, the conventional manner of forming the lightly doped first connection portion 402 and the second connection portion 403 includes:
firstly, an ion implantation mode is adopted, the implementation mode is different from that of the embodiment, the ion implantation scheme is mainly applied to the field of small-size LTPS display panels, and in the large-size field, the scheme is difficult to implement due to the limitation of cost and machine;
and secondly, a scheme of covering a grid electrode is adopted, and the scheme has influence on the reduction of the mobility of the device.
In order to avoid the additional formation of the first connection portion 402 and the second connection portion 403 by ion implantation, the present embodiment provides the following processes, as shown in fig. 5, 7, 8, 9 and 10, the present embodiment forms a phosphine-doped amorphous silicon layer 20, a source contact 201, a drain contact 202, a source connection segment 4021 connected to the source contact 201, and a drain connection segment 4031 connected to the drain contact 202 and located adjacent to the source contact 201 are then formed by a yellow lithography and dry etch process, the distance between one side of the protective metal layer on the source contact portion 201 close to the channel and one side of the source contact portion 201 close to the channel is about 1-3 μm, and the distance between one side of the protective metal layer on the drain contact portion 202 close to the channel and one side of the drain contact portion 202 close to the channel is about 1-3 μm;
as shown in fig. 9, an amorphous silicon layer 40 is deposited on the source connection segment 4021 to form a source connection segment 4022, and then, the heavily doped phosphorus in the source connection segment 4021 is diffused longitudinally and laterally into the amorphous silicon layer 40 (the source connection segment 4022) and crystallized together with the amorphous silicon layer to form a low doped polysilicon, i.e., a first connection 402, by a blue laser annealing technique; the amorphous silicon layer 40 is deposited on the drain connecting segment 4031 to form a drain connecting segment 4032, and then the phosphor in the heavily doped drain connecting segment 4031 is diffused longitudinally and laterally to the amorphous silicon layer 40 (the drain connecting segment 4032) by a blue laser annealing technique to be crystallized together with the amorphous silicon layer 40 into low-doped polysilicon, i.e., the second connecting portion 403.
Specifically, the source connecting segment 4022 and the drain connecting segment 4032 may be formed by the same process.
It can be understood that the lightly doped structures (the first connection portion 402 and the second connection portion 403) are formed by stacking and diffusing, so that the thickness of the first connection portion 402 is greater than that of the source contact portion 201, and the thickness of the second connection portion 403 is greater than that of the drain contact portion 202, thereby avoiding forming an LDD (light-doping-drain) structure by ion implantation, and being capable of implementing the manufacture of a large-sized LTPS display panel, and meanwhile, the stability of the device is high.
In view of the above embodiments, as shown in fig. 11 and 12, a silicon-based insulating layer 50 is disposed on the metal protection layer 30, a third connection hole 405 and a fourth connection hole 406 are disposed on the silicon-based insulating layer 404, the third connection hole 405 is communicated with the first via, the fourth connection hole 406 is communicated with the second via, and the material of the silicon-based insulating layer 404 is the same as that of the channel portion 401.
Specifically, the material of the silicon-based insulating layer 404 is the same as that of the channel portion 401, and is low-temperature polysilicon.
Specifically, the silicon-based insulating layer 404 and the channel portion 401 are formed in the same process.
It can be understood that in the embodiment of the present application, the amorphous silicon layer 20 doped with phosphane and the amorphous silicon layer 40 are stacked, and a blue laser annealing technology is used to process the amorphous silicon layer, so that part of the phosphorus in the heavily doped amorphous silicon layer not covered by the metal protection layer 30 is diffused longitudinally and laterally into the amorphous silicon layer 40 stacked later to form a lightly doped structure, and the rest amorphous silicon is converted into low temperature polysilicon to obtain the silicon-based insulating layer 404, by using the above technical solution, the etching precision requirement of the amorphous silicon layer 40 formed later is significantly reduced, i.e. the etching precision of the amorphous silicon layer 40 deposited later can be around the source contact 201 and the drain contact 202, as shown in fig. 9, the etching precision requirement is lower, the production is convenient, the formed silicon-based insulating layer 404 does not affect the TFT device, and the structure avoids forming an LDD structure by using an ion implantation method, so that the array substrate 101 of the LTPS can be applied to a large-sized flexible display panel.
In one embodiment, the material of the source contact 201 and the drain contact 202 comprises phosphine doped amorphous silicon or borane doped amorphous silicon.
Specifically, the material of the source contact 201 and the drain contact is a silicon-based material which is made of a conductor.
Specifically, the thin film transistor formed by phosphine-doped amorphous silicon is a P-type thin film transistor, and the thin film transistor formed by borane-doped amorphous silicon is an N-type thin film transistor.
In an embodiment, the material of the metal protection layer 30 includes any one of Mo, Ti, and an alloy thereof.
Specifically, the metal Mo, the metal Ti, and the metal alloy thereof are all metal materials capable of resisting a high temperature of more than 1000 ℃, and since some steps in the subsequent process of the array substrate 101 need to be performed in a high temperature environment, the material for disposing the metal protection layer 30 includes any one of Mo, Ti, and the metal alloy thereof, which can effectively prevent the metal protection layer 30 from melting and failing in the subsequent process and affecting other structures of the array substrate 101.
The present application further provides a manufacturing method of the array substrate 101, as shown in fig. 13, including the following steps:
s1, providing a substrate 10;
s2, forming an active layer on the substrate 10, the active layer including a channel portion 401, a source contact 201 and a drain contact 202 disposed at both sides of the channel portion 401 and electrically connected to the channel portion 401;
s3, forming a metal protection layer 30 on the source contact 201 and the drain contact 202;
s4, forming an insulating layer 50, a first metal layer 60 and a second metal layer 70 stacked on the substrate 10, the active layer and the metal protection layer 30, the first metal layer 60 being disposed corresponding to the channel portion 401, the second metal layer 70 being disposed on the insulating layer 50, the second metal layer 70 corresponding to the upper portions of the source contact portion 201 and the drain contact portion 202, a first connection hole 503 being disposed on the insulating layer 50 between the second metal layer 70 and the source contact portion 201, a second connection hole 504 being disposed on the insulating layer 50 between the second metal layer 70 and the drain contact portion 202, the second metal layer 70 being electrically connected to the source contact portion 201 and the drain contact portion 202 through the first connection hole 503 and the second connection hole 504, respectively, in a direction perpendicular to the substrate 10, the orthographic projection of the metal protection layer 30 covers at least the orthographic projections of the first connection hole 503 and the second connection hole 504.
In particular, the structure and material of the substrate 10 can be seen in the above structural embodiments.
Specifically, the metal layer of the metal protection layer 30 may be deposited by PVD, and the patterning of the metal layer to form the metal protection layer 30 may employ a PHO (yellow light) process and a wet etching process.
Specifically, the first metal layer 60 includes a plurality of gates, the second metal layer 70 includes a plurality of sources 701 and a plurality of drains 702, and the first metal layer 60 and the second metal layer 70 are formed by a PHO (yellow light) process and a wet etching process after metal PVD deposition.
Specifically, the thickness of the metal protection layer 30 is 50 to 400 angstroms.
Specifically, the first connection hole 503 and the second connection hole 504 are formed in such a manner that a conventional plasma etching gas system, for example, CF 4 Or NF 3 The dielectric layer 502 (the insulating layer 50) and the gate insulating layer 501 (the insulating layer 50) are sequentially etched by the system dry etching process, and in some embodiments, the polysilicon layer is etched until reaching the metal protection layer 30(MoTi), so that the source contact 201 and the drain contact 202 are effectively prevented from being over-etched.
It can be understood that the manufacturing method described above enables the LTPS array substrate 101 to be manufactured without using an additional etching system with a high selectivity ratio, such as hydrofluoric acid wet etching or octafluorocyclobutane plasma etching, thereby reducing the manufacturing cost and the production risk factor of the LTPS array substrate 101.
In one embodiment, as shown in fig. 14, the active layer further includes a first connection portion 402 disposed between the source contact portion 201 and the channel portion 401 and connecting the source contact portion 201 and the channel portion 401, a second connection portion 403 disposed between the drain contact portion 202 and the channel portion 401 and connecting the drain contact portion 202 and the channel portion 401;
forming an active layer on the substrate 10, wherein the active layer comprises a channel portion 401, a source contact portion 201 and a drain contact portion 202 which are arranged at two sides of the channel portion 401 and electrically connected with the channel portion 401; the step of forming a metal protection layer 30 on the source contact 201 and the drain contact 202 includes:
s21, forming a source contact 201 on the substrate 10, a source contact segment 4021 connected to the source contact 201, a drain contact 202, and a drain contact segment 4031 connected to the drain contact 202 and located adjacent to the source contact 201;
s3, forming a metal protection layer 30 on the source contact 201 and the drain contact 202;
s31, forming a source connecting piece 4022 on the source connecting piece 4021, forming a drain connecting piece 4032 on the drain connecting piece 4031, forming a channel portion 401 precursor on the substrate 10 between the source connecting piece 4021 and the drain connecting piece 4031, annealing the source connecting piece 4021 and the source connecting piece 4022 to form the first connecting portion 402, annealing the drain connecting piece 4031 and the drain connecting piece 4032 to form the second connecting portion 403, and annealing the channel portion 401 precursor to form the channel portion 401.
Specifically, the Annealing treatment employs a Blue Laser Annealing (BLDA) technique.
Specifically, the distance between one side of the protective metal layer on the source contact 201 close to the channel and one side of the source contact 201 close to the channel is about 1-3 μm, and the distance between one side of the protective metal layer on the drain contact 202 close to the channel and one side of the drain contact 202 close to the channel is about 1-3 μm.
In one embodiment, the steps are as follows:
as shown in fig. 4, a substrate 10 is provided, which includes a substrate 101 layer and a buffer layer 102;
as shown in fig. 5, depositing a phosphane-doped amorphous silicon layer 20 on the substrate 10, and laminating a metal layer on the phosphane-doped amorphous silicon layer 20;
as shown in fig. 6, the metal layer is patterned by a yellow light process and a wet etching process to form a metal protection layer 30, and a photoresist PR is coated on the metal protection layer;
as shown in fig. 7, by using a yellow light process and a dry etching process, a photoresist PR is coated on a section 4021 corresponding to the source connection section and a section 4031 corresponding to the drain connection section, and a fosfame-doped amorphous silicon layer 20 is patterned to form a source contact 201, a section 4021 corresponding to the source contact 201, a drain contact 202 connected to the source contact 201, and a section 4031 corresponding to the drain contact 202 and located close to the source contact 201, wherein a distance between one side of the protective metal layer on the source contact 201 close to the channel and one side of the source contact 201 close to the channel is about 1-3 μm, and a distance between one side of the protective metal layer on the drain contact 202 close to the channel and one side of the drain contact 202 close to the channel is about 1-3 μm;
as shown in fig. 8, an amorphous silicon layer 40 is deposited on the substrate 10, the metal protective layer 30, the source connection segment 4021, and the drain connection segment 4031;
as shown in fig. 9, a yellow light process and a dry etching process are used to pattern the amorphous silicon layer 40, so as to form a source connection segment 4022 on a source connection segment 4021, a drain connection segment 4032 on a drain connection segment 4031, and a channel portion 401 precursor on the substrate 10 between the source connection segment 4021 and the drain connection segment 4031;
as shown in fig. 10, the channel portion 401 precursor (amorphous silicon layer 40) is crystallized into low-temperature polysilicon (channel portion 401) by Blue Laser Annealing (BLDA) in which the scanning direction is vertical channel scanning or parallel channel scanning, and phosphorus in the source connection segment 4021 and the drain connection segment 4031 (heavily doped and phosphine-doped amorphous silicon layer 20 uncovered by the metal protective layer 30) is longitudinally and laterally diffused into the amorphous silicon layer 40 (source connection segment 4022 and drain connection segment 4032) and crystallized together therewith into low-doped polysilicon (first connection portion 402 and second connection portion 403) by phosphorus diffusion occurring at high temperature during BLDA.
As shown in fig. 11, the active layer and the metal protection layer 30 are sequentially formed on the substrate 10The gate insulator 501 (insulator 50), gate and dielectric 502 (insulator 50) are deposited using conventional CF 4 Or NF 3 The dielectric layer 502, the gate insulating layer 501, and the silicon-based insulating layer 404 (low-temperature polysilicon) are sequentially etched by the system dry etching process until the metal protection layer 30(MoTi) is etched, thereby forming a first connection hole 503 and a second connection hole 504, wherein the first connection hole 503 is disposed corresponding to the source contact portion 201, and the second connection hole 504 is disposed corresponding to the drain contact portion 202.
As shown in fig. 12, a source electrode 701 and a drain electrode 702 are formed on the insulating layer 50, the source electrode 701 is electrically connected to the source contact portion 201 through a first connection hole 503, the drain electrode 702 is electrically connected to the drain contact portion 202 through a second connection hole 504, a planarization layer 90 is formed on the drain electrode 702 and the drain electrode 702, a fifth connection hole is opened in a position of the planarization layer 90 corresponding to the source electrode 701, and an ITO layer 80 is formed on the planarization layer 90 such that the ITO layer 80 is electrically connected to the source electrode 701 through a via hole provided on the planarization layer 90.
The present application further provides a display panel including the array substrate 101 according to any one of the above embodiments.
In particular, the display panel includes, but is not limited to, the following types: cell-phone, wrist-watch, bracelet, TV or other wearable type display device to and panel computer, notebook computer, desktop display, TV set, intelligent glasses, intelligent wrist-watch, ATM, digital camera, vehicle mounted display, medical treatment shows, industry control shows, the paper book, electrophoresis display device, game machine, transparent display, two-sided display, bore hole 3D display, mirror surface display device, half anti-semi permeable type display device etc..
In summary, by disposing the metal protection layer 30 on the source contact 201 and the drain contact 202, and in a direction perpendicular to the substrate 10, the orthographic projection of the metal protection layer 30 at least covers the orthographic projection of the first connection hole 503 and the orthographic projection of the second connection hole 504, so that the problem of over-etching does not occur in the process of forming the first connection hole 503 and the second connection hole 504 by etching the insulating layer 50 with a conventional gas, and the LTPS array substrate 101 does not need to be produced by additionally adopting a high selectivity etching system, such as hydrofluoric acid wet etching or plasma etching such as octafluorocyclobutane, thereby reducing the production cost and the production risk coefficient of the LTPS array substrate 101.
The array substrate, the manufacturing method thereof, and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the embodiments above is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. An array substrate, comprising:
a substrate;
the active layer is arranged on the substrate and comprises a channel part, a source electrode contact part and a drain electrode contact part, wherein the source electrode contact part and the drain electrode contact part are arranged on two sides of the channel part and are electrically connected with the channel part;
an insulating layer disposed on the substrate and the active layer;
a first metal layer stacked on the insulating layer and provided corresponding to the channel portion;
the second metal layer is arranged above the insulating layer and corresponds to the source electrode contact part and the drain electrode contact part, a first connecting hole is formed in the insulating layer between the second metal layer and the source electrode contact part, a second connecting hole is formed in the insulating layer between the second metal layer and the drain electrode contact part, and the second metal layer penetrates through the first connecting hole and the second connecting hole to be electrically connected with the source electrode contact part and the drain electrode contact part;
and metal protective layers are arranged between the insulating layer and the source electrode contact part and between the insulating layer and the drain electrode contact part, and the orthographic projection of each metal protective layer at least covers the orthographic projection of the first connecting hole and the orthographic projection of the second connecting hole in the direction vertical to the substrate.
2. The array substrate of claim 1, wherein an orthographic projection of the metal protection layer is located within an orthographic projection of the source contact and the drain contact in a direction perpendicular to the substrate.
3. The array substrate of claim 2, wherein the active layer further comprises a first connection portion disposed between and connecting the source contact portion and the channel portion, a second connection portion disposed between and connecting the drain contact portion and the channel portion;
wherein the material of the source contact and the drain contact comprises phosphine-doped amorphous silicon 20, and the material of the first connection part and the second connection part comprises phosphine-lightly doped amorphous silicon.
4. The array substrate of claim 3, wherein the first connection portion has a thickness greater than a thickness of the source contact portion and the second connection portion has a thickness greater than a thickness of the drain contact portion in a direction perpendicular to the substrate.
5. The array substrate of claim 3, wherein a silicon-based insulating layer is disposed on the metal protection layer, a third connection hole and a fourth connection hole are disposed on the silicon-based insulating layer, the third connection hole is communicated with the first via hole, the fourth connection hole is communicated with the second via hole, and a material of the silicon-based insulating layer is the same as a material of the channel portion.
6. The array substrate of claim 1, wherein the material of the source contact and the drain contact comprises phosphine doped amorphous silicon or borane doped amorphous silicon.
7. The array substrate of claim 1, wherein the material of the metal protection layer comprises any one of Mo, Ti, and alloys thereof.
8. The manufacturing method of the array substrate is characterized by comprising the following steps:
providing a substrate;
forming an active layer on the substrate, wherein the active layer comprises a channel part, a source contact part and a drain contact part which are arranged at two sides of the channel part and electrically connected with the channel part;
forming a metal protection layer on the source contact and the drain contact;
forming an insulating layer, a first metal layer and a second metal layer stacked on the substrate, the active layer and the metal protection layer, the first metal layer is disposed corresponding to the channel portion, the second metal layer is disposed on the insulating layer, the second metal layer is arranged above the source contact part and the drain contact part, a first connecting hole is arranged on the insulating layer between the second metal layer and the source contact part, a second connection hole is formed in the insulating layer between the second metal layer and the drain contact portion, the second metal layer is electrically connected with the source contact and the drain contact through the first connection hole and the second connection hole, respectively, in a direction perpendicular to the substrate, an orthographic projection of the metal protection layer at least covers orthographic projections of the first connection hole and the second connection hole.
9. The method of fabricating an array substrate according to claim 8, wherein the active layer further includes a first connection portion disposed between and connecting the source contact portion and the channel portion, and a second connection portion disposed between and connecting the drain contact portion and the channel portion;
the active layer is formed on the substrate and comprises a channel part, a source electrode contact part and a drain electrode contact part, wherein the source electrode contact part and the drain electrode contact part are arranged on two sides of the channel part and are electrically connected with the channel part; the step of forming a metal protection layer on the source contact and the drain contact includes:
forming a source contact portion, a source connecting section connected with the source contact portion, a drain contact portion and a drain connecting section which is connected with the drain contact portion and is close to the source contact portion on the substrate;
forming a metal protection layer on the source contact and the drain contact;
forming a source electrode connecting section on the source electrode connecting section, forming a drain electrode connecting section on the drain electrode connecting section, forming a channel part precursor on the substrate between the source electrode connecting section and the drain electrode connecting section, annealing the source electrode connecting section and the source electrode connecting section to form the first connecting part, annealing the drain electrode connecting section and the drain electrode connecting section to form the second connecting part, and annealing the channel part precursor to form the channel part.
10. A display panel comprising the array substrate according to any one of claims 1 to 7.
CN202210617497.6A 2022-06-01 2022-06-01 Array substrate, manufacturing method thereof and display panel Pending CN115000093A (en)

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CN202210617497.6A CN115000093A (en) 2022-06-01 2022-06-01 Array substrate, manufacturing method thereof and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210617497.6A CN115000093A (en) 2022-06-01 2022-06-01 Array substrate, manufacturing method thereof and display panel

Publications (1)

Publication Number Publication Date
CN115000093A true CN115000093A (en) 2022-09-02

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