CN115939036A - Manufacturing method of array substrate, array substrate and display panel - Google Patents

Abstract

The application provides a manufacturing method of an array substrate, the array substrate and a display panel, wherein the manufacturing method of the array substrate separately manufactures a source electrode and a drain electrode on an active layer and on the active layer, specifically, firstly, a composition process is adopted to etch and form one of the source electrode and the drain electrode, part of the active layer is etched to form a main pattern of the active layer, a first insulating layer is deposited on the manufactured source electrode or drain electrode, the first insulating layer wraps the source electrode or drain electrode through the composition process, then, a compensation pattern of the active layer pattern is formed on the main pattern again, a channel groove is formed between the main pattern and the compensation pattern, a part of the first insulating layer is filled in the channel groove, at the moment, the length of the channel groove is the width of the first insulating layer, the other one of the source electrode and the drain electrode is manufactured after the active layer is manufactured, the source electrode and the drain electrode are separated by the first insulating layer in the channel groove, and therefore, the width of the first insulating layer formed in the channel groove is controlled to be reduced so as to further reduce the length of the channel groove.

Description

Manufacturing method of array substrate, array substrate and display panel

Technical Field

The present disclosure relates to the field of display device technologies, and in particular, to a manufacturing method of an array substrate, an array substrate and a display panel.

Background

The TFT display panel is a display panel having a Thin Film Transistor (TFT) as a corresponding pixel unit driving switch, and is widely applied to display devices such as mobile phones and computers. At present, the TFT display panel is also gradually developed toward high resolution and high aperture ratio, so that the TFT narrow channel has become one of the main development trends of the TFT.

However, in the actual manufacturing process of the TFT, the metal lines on both sides of the TFT channel are affected by the etching solution, which increases the channel length, and in order to prevent the metal from remaining on the interface of the channel, the over-etching is required, and the metal lines on both sides of the channel have longer etching time in the over-etching process, which further increases the channel length, is not favorable for realizing the narrow channel of the TFT, and tends to reduce the on-state current of the TFT.

Disclosure of Invention

The application provides a manufacturing method of an array substrate, the array substrate and a display panel, and aims to solve the problem that narrow channeling of a thin film transistor in the array substrate is not easy to realize.

In one aspect, the present application provides a method for manufacturing an array substrate, where the method includes:

sequentially forming a gate electrode, a gate insulating layer and an active layer on a substrate;

forming one of a source electrode and a drain electrode on the active layer and etching a portion of the active layer to form a main pattern of the active layer;

forming a patterned first insulating layer on one of the source electrode or the drain electrode, wherein the first insulating layer coats the one of the source electrode or the drain electrode;

forming a compensation pattern of the active layer pattern on the main pattern, forming a channel groove between the main pattern and the compensation pattern, wherein a part of the first insulating layer is filled in the channel groove;

forming the other of the source electrode or the drain electrode on the compensation pattern of the active layer.

In one possible implementation manner of the present application, the step of forming one of a source electrode and a drain electrode on the active layer and etching a portion of the active layer to form a main pattern of the active layer includes:

depositing a source drain metal layer on the whole surface of the active layer;

etching in the source drain metal layer by adopting a composition process of wet etching to form one of a source electrode or a drain electrode;

and etching part of the active layer pattern by using a patterning process of dry etching to form a main pattern of the active layer.

In one possible implementation manner of the present application, the forming an active layer step includes:

depositing a semiconductor layer on the whole surface of the gate insulating layer;

preparing an ohmic contact layer on the whole surface of the gate insulating layer;

etching the semiconductor layer and the ohmic contact layer by adopting a one-step composition process to form the active layer;

the step of forming one of a source electrode or a drain electrode on the active layer and etching a portion of the active layer to form a main pattern of the active layer includes:

depositing the source drain metal layer on the whole surface of the ohmic contact layer;

forming one of a source electrode and a drain electrode in the source-drain metal layer by adopting a one-step composition process;

and etching part of the ohmic contact layer until the semiconductor layer is exposed to form the main pattern.

In one possible implementation manner of the present application, etching a portion of the ohmic contact layer until the semiconductor layer is exposed to form a main pattern of the active layer, and then:

and performing over-etching on the exposed semiconductor layer to enable the ohmic contact layer to be completely etched, so that the etched semiconductor layer and the ohmic contact layer form a main pattern of the active layer.

In one possible implementation manner of the present application, the step of forming a compensation pattern of the active layer pattern on the main pattern includes:

depositing the semiconductor layer again on the first insulating layer and the main pattern entirely;

depositing the ohmic contact layer on the whole surface of the semiconductor layer again;

and etching the semiconductor layer and the ohmic contact layer by adopting a one-step composition process to form the compensation pattern.

On the other hand, the application provides an array substrate, which comprises a substrate, and a grid electrode, a grid insulating layer, an active layer, a source drain metal layer and a first insulating layer which are sequentially arranged on the substrate;

the active layer is provided with a channel groove, the source drain metal layer comprises a source electrode and a drain electrode which are positioned on two sides of the active layer, and the channel groove is positioned between the source electrode and the drain electrode;

the first insulating layer is partially positioned in the channel groove and covers the surface of the active layer exposed on the channel groove, and the first insulating layer partially covers the source electrode or partially covers the drain electrode.

In one possible implementation manner of the present application, the active layer includes:

an ohmic contact layer disposed on the gate insulating layer;

the semiconductor layer is arranged on the ohmic contact layer, the channel groove penetrates through the ohmic contact layer and penetrates through part of the semiconductor layer, the semiconductor layer is partially exposed in the channel groove, and the first insulating layer is partially positioned in the channel groove and covers the surface of the semiconductor layer exposed in the channel groove.

In one possible implementation manner of the present application, the array substrate further includes:

the first electrode layer is arranged on the grid insulation layer, the first electrode layer and the active layer are arranged on the grid insulation layer at intervals, and the drain electrode part is lapped on the surface of the first electrode layer, which faces away from the substrate base plate;

when the first insulating layer partially covers the drain electrode, the edge of the first insulating layer is positioned and lapped on the surface of the first electrode layer, which faces away from the substrate base plate.

In one possible implementation manner of the present application, the array substrate further includes:

the whole surface of the second insulating layer is arranged on the first insulating layer;

when the first insulating layer partially covers the source electrode, the second insulating layer is partially arranged on one surface of the first insulating layer, which is opposite to the substrate base plate, and the second insulating layer is partially positioned on the drain electrode;

when the first insulating layer portion covers the drain electrode, the second insulating layer portion is arranged on one surface, back to the substrate, of the first insulating layer, and the second insulating layer portion is located on the source electrode.

On the other hand, the application also provides a display panel comprising the array substrate.

According to the manufacturing method of the array substrate, the array substrate and the display panel, the grid electrode, the grid insulating layer and the active layer are sequentially formed on the substrate in the manufacturing method of the array substrate; the active layer and the source electrode and the drain electrode on the active layer are manufactured separately, specifically, one of the source electrode and the drain electrode is prepared firstly, part of the active layer is etched to form a main pattern of the active layer, a first insulating layer is deposited on the manufactured source electrode or the drain electrode, a patterned first insulating layer is formed through a composition process, the first insulating layer coats the source electrode or the drain electrode, so that the first insulating layer plays a role in protecting in subsequent processes, then a compensation pattern of the active layer is formed on the main pattern, a main channel is formed between the compensation pattern and the main channel, a part of the first insulating layer is filled in the channel, the length of the channel is the width of the first insulating layer, the other of the source electrode and the drain electrode is formed by etching on the compensation pattern of the active layer after the pattern of the active layer is manufactured, the source electrode and the drain electrode are separated by the first insulating layer in the channel, therefore, the length of the channel can be further reduced by controlling the width of the first insulating layer formed in the channel, the risk of short circuit of the source electrode and the drain electrode is avoided, the array substrate is beneficial to form a narrow-channel transistor, and the open-state display effect is improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic manufacturing flow diagram of a manufacturing method of an array substrate according to an embodiment of the present disclosure.

Fig. 2 is a schematic view of a manufacturing flow of step S110 in the manufacturing method of the embodiment of the present application.

Fig. 3 is a schematic view of a manufacturing flow of step S110 in the manufacturing method according to the embodiment of the application.

Fig. 4 is a schematic view of a manufacturing flow in step S110 of the manufacturing method according to the embodiment of the present application.

Fig. 5 is a schematic view of a manufacturing flow in step S110 of the manufacturing method according to the embodiment of the application.

Fig. 6 is a schematic view of a manufacturing flow in step S110 of the manufacturing method according to the embodiment of the application.

Fig. 7 is a schematic view of a manufacturing flow in step S110 of the manufacturing method according to the embodiment of the application.

Fig. 8 is a schematic view of a manufacturing flow in step S110 of the manufacturing method according to the embodiment of the application.

Fig. 9 is a schematic view of a manufacturing flow in step S110 of the manufacturing method according to the embodiment of the application.

Fig. 10 is a schematic view of a manufacturing flow in step S110 of the manufacturing method according to the embodiment of the application.

Fig. 11 is a schematic view of a manufacturing flow in step S110 of the manufacturing method according to the embodiment of the application.

Fig. 12 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 13 is a schematic structural diagram of an array substrate according to still another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the features of the terms "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise. It is to be understood that, unless otherwise expressly stated or limited, the terms "connected" and "connecting" are used broadly and can refer to, for example, a direct connection, an indirect connection via an intermediary, a connection between two elements, or an interaction between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

Embodiments of the present disclosure provide a method for manufacturing an array substrate, an array substrate and a display panel, which are described in detail below.

Referring to fig. 1, an embodiment of the present application further provides a manufacturing method of an array substrate, where the manufacturing method includes the following steps S100 to S500:

s100, sequentially forming a gate electrode 20, a gate insulating layer 60, and an active layer 30 on the base substrate 10.

Specifically, in the embodiment of the present application, the step SS100 of sequentially forming the gate electrode 20, the gate insulating layer 60, and the active layer 30 on the substrate 10 may specifically include the following steps S101 to S103:

s101, a substrate 10 is provided.

S102, depositing a whole gate metal layer (not shown) on the substrate 10, and forming a patterned gate 20 and a gate scan line 21 in the gate metal layer by using a one-step patterning process. As shown in fig. 2 or fig. 4, the gate electrode 20 and the gate scan line 21 are disposed in the same layer and made of the same material.

And S103, depositing and forming a gate insulating layer 60 on the whole surface of the patterned gate electrode 20 and the gate scanning line 21.

And S104, depositing and forming the active layer 30 on the whole surface of the gate insulating layer 60, and forming the main pattern 31 of the active layer 30 by adopting a patterning process.

S200, forming one of the source electrode 42 or the drain electrode 41 on the active layer 30, and etching a portion of the active layer 30 to form the main pattern 31 of the active layer 30.

In the embodiment of the present invention, the gate electrode 20, the active layer 30, the source electrode 42 and the drain electrode 41 form a thin film transistor, and the source electrode 42 or the drain electrode 41 is a metal film layer, so that the metal film layer can be patterned by a photolithography process to form the patterned source electrode 42 or the patterned drain electrode 41. The photoetching process further comprises the steps of sequentially carrying out processes of exposure, development, etching, stripping and the like on the metal film layer, and patterning the metal film layer is completed. The metal film layer may be etched by wet etching with fast etching rate, poor anisotropy and low cost, or may be etched by other etching methods, which are not limited herein.

Correspondingly, the active layer 30 of the embodiment of the present application may be partially etched by using a dry etching process.

S300, forming a patterned first insulating layer 50 on one of the source electrode 42 or the drain electrode 41, wherein the first insulating layer 50 covers the one of the source electrode 42 or the drain electrode 41.

In the embodiment of the present invention, the first insulating layer 50 can function as an etching stop, wherein when the first insulating layer 50 covers the source 42 or the drain 41, the first insulating layer 50 covers the surface of the source 42 or the drain 41 opposite to the substrate 10 and the side surface facing the channel 301, so as to function as an etching stop, thereby preventing the widths of the metal lines of the drain 41 and the source 42 from being reduced due to over-etching.

Specifically, the first insulating layer 50 may be made of at least one of silicon oxide (SiOx) and silicon nitride (SiNx), wherein the first insulating layer 50 may have a single-layer structure or a multi-layer structure, and is not limited in this respect.

S400, the compensation pattern 32 of the active layer 30 is formed on the main pattern 31, a channel groove 301 is formed between the main pattern 31 and the compensation pattern 32, and a portion of the first insulating layer 50 is filled in the channel groove 301.

Specifically, the length of the channel trench 301 prepared as described above may range from 2.25um to 2.5um, and exemplarily, the length of the channel trench 301 may range from 2.25um, 2.3752um, 2.5um, and so on, so that the charging rate of the thin film transistor device may be further improved, and the display quality of the product may be optimized.

S500, the other of the source electrode 42 or the drain electrode 41 is formed on the compensation pattern 32 of the active layer 30.

In the embodiment of the present invention, when the source electrode 42 and the drain electrode 41 are patterned, the drain electrode 41 may be first formed, and then the source electrode 42 is formed, or the source electrode 42 may be first formed, and then the drain electrode 41 is formed, which is not particularly limited in this application. In addition, when the drain electrode 41 is manufactured, a patterned data line 43 may be simultaneously manufactured, wherein the data line 43 is connected to the drain electrode 41.

Specifically, referring to fig. 2 and fig. 3, taking the fabrication of the drain 41 first and then the source 42 as an example, the steps S200 to S500 may include the following steps S210 to S510:

s110, sequentially forming a gate electrode 20, a gate insulating layer 60, and an active layer 30 on the base substrate 10.

S210, forming a drain electrode 41 on the active layer 30, and etching a portion of the active layer 30 to form a main pattern 31 of the active layer 30.

S310, a patterned first insulating layer 50 is formed on the drain 41, and the first insulating layer 50 covers the drain 41.

S410, the compensation pattern 32 of the active layer 30 is formed on the main pattern 31, a channel groove 301 is formed between the main pattern 31 and the compensation pattern 32, and a portion of the first insulating layer 50 is filled in the channel groove 301.

S510, a source electrode 42 is formed on the compensation pattern 32 of the active layer 30.

In the embodiment, the main pattern 31 of the drain electrode 41 and the active layer 30 is firstly manufactured, and then the compensation pattern 32 of the source electrode 42 and the active layer 30 is separated by the first insulating layer 50 and manufactured, so that the widths of the metal lines of the drain electrode 41 and the source electrode 42 are increased, the length of the channel groove 301 is reduced, and further the on-state current of the thin film transistor in the array substrate is increased.

In other embodiments, referring to fig. 4 and fig. 5, taking the fabrication of the source 42 first and the fabrication of the drain 41 second as an example, the steps S200 to S500 may further include the following steps S220 to S520:

and S120, sequentially forming a gate electrode 20, a gate insulating layer 60 and an active layer 30 on the substrate 10.

S220, forming a source electrode 42 on the active layer 30 and etching a portion of the active layer 30 to form the main pattern 31 of the active layer 30.

S320, forming a patterned first insulating layer 50 on the source electrode 42, wherein the first insulating layer 50 covers the source electrode 42.

S420, the compensation pattern 32 of the active layer 30 is formed on the main pattern 31, a channel groove 301 is formed between the main pattern 31 and the compensation pattern 32, and a portion of the first insulating layer 50 is filled in the channel groove 301.

S520, the drain electrode 41 is formed on the compensation pattern 32 of the active layer 30.

In the embodiment, the main pattern 31 of the source electrode 42 and the active layer 30 is firstly manufactured, and then the compensation pattern 32 of the drain electrode 41 and the active layer 30 is separated and manufactured by the first insulating layer 50, so that the widths of the metal wires of the drain electrode 41 and the source electrode 42 are increased, the length of the channel groove 301 is reduced, and further the on-state current of the thin film transistor in the array substrate is increased.

According to the preparation method of the array substrate, the grid electrode 20, the grid insulating layer 60 and the active layer 30 are sequentially prepared and formed on the substrate 10; and by separately manufacturing the active layer 30 and the source electrode 42 and the drain electrode 41 on the active layer 30, specifically, etching to form one of the source electrode 42 or the drain electrode 41 by using a patterning process, etching a portion of the active layer 30 to form the main pattern 31 of the active layer 30, depositing the first insulating layer 50 on the manufactured source electrode 42 or drain electrode 41, and making the first insulating layer 50 wrap the source electrode 42 or the drain electrode 41 by using a one-time patterning process, so that the first insulating layer 50 plays a role in subsequent processes, and then depositing the active layer 30 again, forming the compensation pattern 32 of the active layer 30 pattern on the main pattern 31 by using a patterning process, forming a channel groove 301 between the main pattern 31 and the compensation pattern 32, filling a portion of the first insulating layer 50 into the channel groove 301, where the length of the channel groove 301 is the width of the first insulating layer 50, etching to form the other of the source electrode 42 or the drain electrode 41 on the compensation pattern 32 of the active layer 30 by using a patterning process after the pattern of the active layer 30 is manufactured, so that the source electrode 42 and the drain electrode 41 are separated by the first insulating layer 50 in the channel groove 301, and the thin film transistor can be advantageously reduced in the short-open state.

In some embodiments, referring to fig. 6, the step S200 of forming one of the source electrode 42 or the drain electrode 41 on the active layer 30 and etching a portion of the active layer 30 to form the main pattern 31 of the active layer 30 includes the following steps S201 to S203:

s201, depositing a source drain metal layer 40 on the whole surface of the active layer 30.

The source drain metal layer 40 may be deposited by physical vapor deposition, and in other embodiments, other deposition methods may be used, such as sputtering deposition, chemical vapor deposition, and the like. The material of the source drain metal layer 40 may be one or a combination of aluminum, molybdenum and copper, and is not particularly limited herein.

S202, etching and forming one of the source electrode 42 or the drain electrode 41 in the source drain metal layer 40 by adopting a patterning process of wet etching.

The wet etching has the characteristics of high etching rate, poor anisotropy, low cost and the like, so that the manufacturing cost can be reduced while the preparation efficiency is improved by forming the patterned source electrode 42 or the patterned drain electrode 41 by the wet etching in the embodiment of the application.

And S203, etching part of the active layer 30 pattern by using a patterning process of dry etching to form the main pattern 31 of the active layer 30.

The dry etching may specifically use an etching gas for etching, where the etching gas may include at least one of chlorine, nitrogen trifluoride, sulfur hexafluoride, and the like.

In some embodiments, as shown in fig. 7, in the step S100 of sequentially forming the gate electrode 20, the gate insulating layer 60 and the active layer 30 on the substrate 10, the step of forming the active layer 30 specifically includes the following steps S104 to S106:

and S104, depositing a semiconductor layer 33 on the whole surface of the gate insulating layer 60.

The semiconductor layer 33 of the embodiment of the present application may be made of amorphous silicon (a-Si) material. Of course, in other embodiments, the semiconductor layer 33 may also be made of a metal oxide semiconductor, low temperature polysilicon, or the like, and is not limited herein.

And S105, preparing the ohmic contact layer 34 on the whole surface of the gate insulating layer 60.

The ohmic contact layer 34 is used to form an ohmic contact between the gate 20 layer and the semiconductor layer 33, so As to reduce the potential difference of the interface, and the ohmic contact layer 34 may be made of a doped amorphous silicon material, specifically, an amorphous silicon doped with N-type ions, such As elements doped with nitrogen (N), phosphorus (P), arsenic (As), and the like.

And S106, etching the semiconductor layer 33 and the ohmic contact layer 34 by adopting a one-step patterning process to form an active layer 30 pattern.

Correspondingly, as shown in fig. 8, in step S200, depositing a source-drain metal layer 40 on the active layer 30, etching one of the source 42 and the drain 41 in the source-drain metal layer 40 by using a patterning process, and etching a part of the active layer 30 pattern to form the main pattern 31 of the active layer 30, specifically, steps S204 to S206:

s204, depositing a source drain metal layer 40 on the whole surface of the ohmic contact layer 34;

and S205, forming one of the source electrode 42 or the drain electrode 41 in the source drain metal layer 40 by adopting a one-step patterning process.

And S206, etching part of the ohmic contact layer 34 until the semiconductor layer 33 is exposed, and forming the main pattern 31 of the active layer 30.

In the present embodiment, the source electrode 42 or the drain electrode 41 may serve as an etching barrier for a portion of the ohmic contact layer 34, and specifically, a portion of the ohmic contact layer 34 corresponding to the portion under the source electrode 42 or the drain electrode 41 etched in step S205 is exposed under the etching barrier of the source electrode 42 or the drain electrode 41, and the portion exposed to the source electrode 42 or the drain electrode 41 is etched away, so that the etched ohmic contact layer 34 is formed only on the surface of the source electrode 42 or the drain electrode 41.

In some embodiments, as shown in fig. 9, step S206, etching a portion of the ohmic contact layer 34 until the semiconductor layer 33 is exposed, and forming the main pattern 31 of the active layer 30, further includes the following step S207:

and S207, excessively etching the exposed semiconductor layer 33 to completely etch the ohmic contact layer 34, so that the etched semiconductor layer 33 and the ohmic contact layer 34 form the main pattern 31 of the active layer 30.

Wherein the semiconductor layer 33 may be over-etched using a dry etching process. In the embodiment of the present application, the semiconductor layer 33 is over-etched, so that the ohmic contact layer 34 on the upper surface of the semiconductor layer 33 can be completely removed, the ohmic contact layer 34 is prevented from remaining, the semiconductor layer 33 is ensured to be exposed, and the subsequent conduction of the source electrode 42 and the drain electrode 41 through the ohmic contact layer 34 is avoided. Correspondingly, in the present embodiment, the channel groove 301 formed between the main pattern 31 and the compensation pattern 32 of the active layer 30 completely penetrates the ohmic contact layer 34 and partially penetrates the semiconductor layer 33 along the thickness direction of the array substrate 10, and in addition, when the first insulating layer 50 is partially formed in the channel groove 301, the first insulating layer 50 covers the surface of the semiconductor layer 33 exposed to the channel groove 301.

In some embodiments, as shown in fig. 10, the step S400 of forming the compensation pattern 32 of the active layer 30 on the main pattern 31 specifically includes the following steps S401 to S403:

s401, the semiconductor layer 33 is again deposited on the entire surface of the first insulating layer 50 and the main pattern 31.

S402, depositing the ohmic contact layer 34 again on the entire surface of the semiconductor layer 33.

And S403, etching the semiconductor layer 33 and the ohmic contact layer 34 by adopting a one-step patterning process to form the compensation pattern 32.

Since the main pattern 31 of the active layer 30 formed by the method of the present embodiment includes the patterned semiconductor layer 33 and the patterned ohmic contact layer 34, the semiconductor layer 33 and the ohmic contact layer 34 are correspondingly formed when the compensation pattern 32 of the active layer 30 is formed, so as to ensure the structural integrity of the active layer 30. In addition, in the manufacturing method of the embodiment of the application, the compensation pattern 32 of the active layer 30 is formed by a one-time composition process after the semiconductor layer 33 and the ohmic contact layer 34 are deposited on the whole surface, so that the semiconductor layer 33 and the ohmic contact layer 34 do not need to be separately etched, and the manufacturing efficiency of the array substrate is improved.

Of course, in other embodiments, the semiconductor layer 33 and the ohmic contact layer 34 may be separately etched, which is not limited in this embodiment.

In some embodiments, as shown in fig. 1 and 11, the step S100 of sequentially forming the gate electrode 20, the gate insulating layer 60 and the active layer 30 on the substrate 10 may further include a step of fabricating a patterned first electrode layer 70, wherein the source electrode 42 is partially overlapped on the first electrode layer 70.

Correspondingly, step S500, forming the other of the source electrode 42 or the drain electrode 41 on the compensation pattern 32 of the active layer 30, may further include the following steps S600-S700:

s600, fabricating a second insulating layer 80 on the first insulating layer 50 and the drain electrode 41 or on the first insulating layer 50 and the source electrode 42.

S700, a patterned second electrode layer 90 is formed on the second insulating layer 80.

The first electrode layer 70 and the second electrode layer 90 may be transparent electrode layers made of transparent materials, and specifically, the first electrode layer 70 and the second electrode layer 90 may be made of any one of Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO). The first electrode layer 70 and the second electrode layer 90 may be made of the same material. In the embodiment of the present application, the first electrode layer 70 may be a pixel electrode layer, and correspondingly, the second electrode layer 90 may be a common electrode layer.

In order to better implement the array substrate manufacturing method of the present application, please refer to fig. 12-13, the embodiment of the present application further provides an array substrate, which includes a substrate 10, and a gate 20, a gate insulating layer 60, an active layer 30, a source 42, a drain 41, and a first insulating layer 50 sequentially disposed on the substrate 10.

The substrate 10 may be a glass substrate or a flexible substrate, and is not limited in particular.

A channel groove 301 is formed on the active layer 30, the source-drain metal layer 40 includes a source electrode 42 and a drain electrode 41 positioned on both sides of the active layer 30, and the channel groove 301 is positioned between the source electrode 42 and the drain electrode 41;

the first insulating layer 50 is partially disposed in the channel trench 301 and covers the active layer 30 exposed on the surface of the channel trench 301, and the first insulating layer 50 partially covers the source electrode 42 or partially covers the drain electrode 41.

In the embodiment of the present invention, the first insulating layer 50 can function as an etching stop, wherein when the first insulating layer 50 covers the source 42 or the drain 41, the first insulating layer 50 covers the surface of the source 42 or the drain 41 opposite to the substrate 10 and the side surface facing the channel 301, so as to function as an etching stop, thereby preventing the widths of the metal lines of the drain 41 and the source 42 from being reduced due to over-etching.

Specifically, the first insulating layer 50 may be made of at least one material of silicon oxide (SiOx) and silicon nitride (SiNx), wherein the first insulating layer 50 may have a single-layer structure or a multi-layer structure, and is not particularly limited herein.

The shape of the channel 301 suitable for the design of the channel 301 of the array substrate may include a plurality of different channel 301 shapes, such as U-shape, double U-shape, L-shape, semicircular shape, or straight shape, which is not limited in this embodiment.

According to the preparation method of the array substrate, the grid electrode 20, the grid insulating layer 60 and the active layer 30 are sequentially arranged on the substrate 10, the channel groove 301 is arranged on the active layer 30, a part of the first insulating layer 50 is filled in the channel groove 301, at the moment, the length of the channel groove 301 is the width of the first insulating layer 50, after the pattern of the active layer 30 is manufactured, the other of the source electrode 42 or the drain electrode 41 in the source and drain metal layer 40 is formed on the compensation pattern 32 of the active layer 30 through etching by adopting the composition process, so that the source electrode 42 and the drain electrode 41 are separated by the first insulating layer 50 in the channel groove 301, the width of the first insulating layer 50 formed in the channel groove 301 can be controlled to be reduced, the length of the channel groove 301 is further reduced, the risk of short circuit of the source electrode 42 and the drain electrode 41 is avoided, the array substrate is beneficial to forming a thin film transistor with a narrow channel, the on-state current is increased, and the display effect is improved.

In some embodiments, the active layer 30 includes an ohmic contact layer 34 and a semiconductor layer 33.

Wherein the ohmic contact layer 34 is disposed on the gate insulating layer 60. The semiconductor layer 33 is disposed on the ohmic contact layer 34, the channel groove 301 completely penetrates through the ohmic contact layer 34 and part of the semiconductor layer 33, the semiconductor layer 33 is partially exposed in the channel groove 301, and the first insulating layer 50 is partially disposed in the channel groove 301 and covers the surface of the semiconductor layer 33 exposed in the channel groove 301.

The semiconductor layer 33 of the embodiment of the present application may be made of amorphous silicon (a-Si) material. Of course, in other embodiments, the semiconductor layer 33 may also be made of a metal oxide semiconductor, low temperature polysilicon, or the like, and is not limited herein. The ohmic contact layer 34 is used to form an ohmic contact between the gate 20 layer and the semiconductor layer 33, so As to reduce the potential difference of the interface, and the ohmic contact layer 34 may be made of a doped amorphous silicon material, specifically, an amorphous silicon doped with N-type ions, such As elements doped with nitrogen (N), phosphorus (P), arsenic (As), and the like.

In some embodiments, the array substrate further includes a first electrode layer 70.

The first electrode layer 70 is a patterned film layer. Specifically, referring to fig. 12, the first electrode layer 70 is disposed on the gate 20 insulating layer, the first electrode layer 70 and the active layer 30 are disposed on the gate 20 insulating layer at an interval, and the drain 41 is partially overlapped on the surface of the first electrode layer 70 facing away from the substrate 10.

When the first insulating layer 50 partially covers the drain 41, the edge of the first insulating layer 50 is overlapped on the surface of the first electrode layer 70 facing away from the substrate 10.

The first electrode layer 70 and the second electrode layer 90 may be transparent electrode layers made of a transparent material, and specifically, the first electrode layer 70 and the second electrode layer 90 may be made of any one of Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO). The first electrode layer 70 and the second electrode layer 90 may be made of the same material. In the embodiment of the present application, the first electrode layer 70 may be a patterned pixel electrode layer, and correspondingly, the second electrode layer 90 may be a common electrode layer.

In some embodiments, the array substrate further includes a second insulating layer 80. The second insulating layer 80 is disposed on the first insulating layer 50. The second insulating layer 80 may serve as an insulation between the film layers of the source and drain electrodes 42 and 41 and the film layer of the second electrode layer 90. Specifically, the second insulating layer 80 may be made of at least one material of silicon oxide (SiOx) and silicon nitride (SiNx), and the material of the second insulating layer 80 in the embodiment of the present application may be the same as or different from that of the first insulating layer 50, which is not particularly limited.

Specifically, referring to fig. 12, when the first insulating layer 50 partially covers the source 42, the second insulating layer 80 is partially disposed on a surface of the first insulating layer 50 opposite to the substrate 10, and the second insulating layer 80 is partially disposed on the drain 41. Referring to fig. 13, when the first insulating layer 50 partially covers the drain 41, the second insulating layer 80 is partially disposed on a surface of the first insulating layer 50 opposite to the substrate 10, and the second insulating layer 80 is partially disposed on the source 42.

On the other hand, in order to better implement the array substrate of the present application, embodiments of the present application further provide a display panel including the array substrate described above. Since the display panel has the display panel, all the same beneficial effects are achieved, and the description of the embodiment is omitted.

The Display panel may be an Organic Light Emitting Diode (OLED) Display panel, a Quantum Dot Light Emitting Diode (QLED) Display panel, or a Liquid Crystal Display (LCD) Display panel.

The embodiment of the application is not specifically limited to the application of the display panel, and the display panel can be a display panel applied to any product or component with a display function, such as a handheld Device (a smart phone, a tablet personal computer and the like), a wearable Device (a smart bracelet, a wireless headset, a smart watch, smart glasses and the like), an on-board Device (a navigator, an auxiliary reversing system, a vehicle recorder, an on-board refrigerator and the like), a virtual reality Device, an augmented reality Device, a Terminal Device (Terminal Device) and the like.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. In a specific implementation, each unit or structure may be implemented as an independent entity, or may be combined arbitrarily to be implemented as one or several entities, and the specific implementation of each unit or structure may refer to the foregoing method embodiment, which is not described herein again.

The above detailed description is given to the manufacturing method of the array substrate, and the display panel provided in the embodiments of the present application, and a specific example is applied in the present application to explain the principle and the implementation manner of the embodiments of the present application, and the description of the above embodiments is only used to help understanding the technical solution and the core idea of the embodiments of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A manufacturing method of an array substrate is characterized by comprising the following steps:

sequentially forming a gate electrode, a gate insulating layer and an active layer on a substrate;

forming one of a source electrode and a drain electrode on the active layer and etching a portion of the active layer to form a main pattern of the active layer;

forming a patterned first insulating layer on one of the source electrode or the drain electrode, wherein the first insulating layer coats the one of the source electrode or the drain electrode;

forming a compensation pattern of the active layer on the main pattern, forming a channel groove between the main pattern and the compensation pattern, wherein the channel groove is filled with a part of the first insulating layer;

forming the other of the source electrode or the drain electrode on the compensation pattern of the active layer.

2. The method of claim 1, wherein the step of forming one of a source electrode and a drain electrode on the active layer and etching a portion of the active layer to form the main pattern of the active layer comprises:

depositing a source drain metal layer on the whole surface of the active layer;

etching the source drain metal layer by adopting a composition process of wet etching to form one of a source electrode and a drain electrode;

and etching part of the active layer by using a patterning process of dry etching to form a main pattern of the active layer.

3. The method of claim 1 or 2, wherein the step of forming the active layer comprises:

depositing a semiconductor layer on the whole surface of the gate insulating layer;

preparing an ohmic contact layer on the whole surface of the gate insulating layer;

etching the semiconductor layer and the ohmic contact layer by adopting a one-step composition process to form the active layer;

the step of forming one of a source electrode and a drain electrode on the active layer and etching a portion of the active layer to form a main pattern of the active layer includes:

depositing the source drain metal layer on the whole surface of the ohmic contact layer;

forming one of a source electrode and a drain electrode in the source-drain metal layer by adopting a one-step composition process;

and etching part of the ohmic contact layer until the semiconductor layer is exposed to form the main pattern.

4. The method of claim 3, wherein etching a portion of the ohmic contact layer until the semiconductor layer is exposed to form a main pattern of the active layer, and then comprising:

and performing over-etching on the exposed semiconductor layer to enable the ohmic contact layer to be completely etched, so that the etched semiconductor layer and the ohmic contact layer form a main pattern of the active layer.

5. The method of claim 3, wherein the step of forming the compensation pattern of the active layer on the main pattern comprises:

depositing the semiconductor layer again on the first insulating layer and the main pattern entirely;

depositing the ohmic contact layer on the whole surface of the semiconductor layer again;

and etching the semiconductor layer and the ohmic contact layer by adopting a one-step composition process to form the compensation pattern.

6. The array substrate is characterized by comprising a substrate, and a grid electrode, a grid insulating layer, an active layer, a source drain metal layer and a first insulating layer which are sequentially arranged on the substrate;

the active layer is provided with a channel groove, the source drain metal layer comprises a source electrode and a drain electrode which are positioned at two sides of the active layer, and the channel groove is positioned between the source electrode and the drain electrode;

the first insulating layer is partially positioned in the channel groove and covers the surface of the active layer exposed on the channel groove, and the first insulating layer partially covers the source electrode or partially covers the drain electrode.

7. The array substrate of claim 6, wherein the active layer comprises:

an ohmic contact layer disposed on the gate insulating layer;

the semiconductor layer is arranged on the ohmic contact layer, the channel groove penetrates through the ohmic contact layer and penetrates through part of the semiconductor layer, the semiconductor layer is partially exposed in the channel groove, and the first insulating layer is partially positioned in the channel groove and covers the surface of the semiconductor layer exposed in the channel groove.

8. The array substrate of claim 6, further comprising:

the first electrode layer is arranged on the grid insulation layer, the first electrode layer and the active layer are arranged on the grid insulation layer at intervals, and the drain electrode part is lapped on the surface of the first electrode layer, which faces away from the substrate base plate;

when the first insulating layer partially covers the drain electrode, the edge of the first insulating layer is positioned and lapped on the surface of the first electrode layer, which faces away from the substrate base plate.

9. The array substrate of claim 6, further comprising:

the whole surface of the second insulating layer is arranged on the first insulating layer;

when the first insulating layer partially covers the source electrode, the second insulating layer is partially arranged on one surface of the first insulating layer, which is opposite to the substrate base plate, and the second insulating layer is partially positioned on the drain electrode;

when the first insulating layer portion covers the drain electrode, the second insulating layer portion is arranged on one surface, back to the substrate, of the first insulating layer, and the second insulating layer portion is located on the source electrode.

10. A display panel comprising the array substrate according to any one of claims 6 to 9.

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