CN114999953A - WAT electrical property test layout - Google Patents
WAT electrical property test layout Download PDFInfo
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- CN114999953A CN114999953A CN202210702675.5A CN202210702675A CN114999953A CN 114999953 A CN114999953 A CN 114999953A CN 202210702675 A CN202210702675 A CN 202210702675A CN 114999953 A CN114999953 A CN 114999953A
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- 238000012360 testing method Methods 0.000 title claims abstract description 43
- 238000003466 welding Methods 0.000 claims abstract description 13
- 239000011159 matrix material Substances 0.000 claims abstract description 5
- 230000007547 defect Effects 0.000 abstract description 18
- 229910005883 NiSi Inorganic materials 0.000 abstract description 8
- 238000001514 detection method Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003203 everyday effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Automation & Control Theory (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a WAT electrical property test layout which comprises a plurality of active area graphs which are distributed in a matrix and have the same shape; the first device area graph and the second device area graph are arranged in sequence and alternately across the active area graph, and the cross boundary line of the first device area graph and the second device area graph equally divides the active area graph across the first device area graph and the second device area graph; the contact hole patterns are arranged on the active region patterns, and the relative positions of the contact hole patterns on each row of active region patterns are different; in each row of active area patterns, a first welding pad pattern is arranged on two adjacent active area patterns and contact hole patterns on the active area patterns; in each row of active area patterns, a second welding pad pattern which spans two adjacent active area patterns and contact hole patterns on the active area patterns; wherein the first and second pad patterns form non-overlapping test loops that span each active area pattern. The device manufactured by the layout can judge whether NiSi abnormity exists in the junction area of the low-voltage active area and the medium-voltage active area by testing the resistance value of the graph during testing, and the defect detection efficiency is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a WAT electrical property test layout.
Background
With the development of the times, the chip becomes a ' necessity ' of global life, with the progress of chip technology, people's life is more and more intelligent, each trip is more and more convenient, and the amount of information available every day is also more and more large.
The high voltage chip is also important in a large family of chips as a driving chip for displays such as LCD/OLED.
High-voltage devices can exist in the high-voltage chip, and compared with the traditional MOS device, the gate oxide layer thickness difference of the three devices is large, and the corresponding process difference is also large. The high-voltage tube has independent area relatively, and the processing procedure degree of difficulty is still good, and low-voltage tube and well medium voltage tube have interactive area to a certain extent, then appear on same active area to two kinds of bars oxygen processing procedures after, will appear some processing procedure defects, influence the yield of product.
One defect that is typical today is oxide residue at the interface region of the low and medium voltage active regions, resulting in NiSi forming defects. The defects can only be found by a defect scanning mode at present, the sampling speed of the defects is limited, and the defect detection efficiency is low.
In order to solve the above problems, a new WAT electrical test layout is needed.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a WAT electrical test layout for solving the problem that the oxide residue in the junction region of the low-voltage active region and the medium-voltage active region in the prior art causes NiSi to form a defect, which can only be found by a defect scanning method at present and has low defect detection efficiency.
To achieve the above and other related objects, the present invention provides a WAT electrical test layout, comprising:
a plurality of active area patterns with the same shape are distributed in a matrix;
the first device area graph and the second device area graph are arranged in sequence and alternately and cross the active area graph, and the cross boundary line of the first device area graph and the second device area graph equally divides the cross active area graph;
contact hole patterns arranged on the active region patterns, wherein the relative positions of the contact hole patterns on each row of the active region patterns are different;
in each row of active area patterns, a first welding pad pattern is arranged on two adjacent active area patterns and the contact hole patterns on the active area patterns;
in each row of the active area patterns, a second welding pad pattern which spans two adjacent active area patterns and the contact hole patterns on the active area patterns;
wherein the first and second pad patterns form a test loop which is non-overlapping and spans each of the active region patterns.
Preferably, the first device region pattern is a pattern for forming a low voltage device region.
Preferably, the second device region pattern is a pattern forming a medium voltage device region.
Preferably, two of the contact patterns are disposed on each of the active region patterns.
Preferably, each of the contact hole patterns is sequentially and equidistantly distributed on the active region of each column.
Preferably, the first and second pad patterns are disposed on two adjacent active region patterns and two adjacent contact hole patterns, and the first and second pad patterns do not share the same contact hole pattern.
Preferably, the first and second patterns form S-shaped test loops which are not overlapped and cross each active region pattern.
Preferably, the two ends of the S-shaped test loop are provided with a third pad pattern and a fourth pad pattern which are not shared with the first pad pattern and the second pad pattern by the same contact hole.
Preferably, the layout is in a rectangular shape.
As described above, the WAT electrical test layout of the present invention has the following beneficial effects: the device manufactured by the layout can judge whether NiSi abnormity exists in the junction area of the low-voltage active area and the medium-voltage active area on the wafer or not by testing the resistance value of the graph during testing, thereby improving the efficiency of defect detection.
Drawings
FIG. 1 is a schematic diagram of an electrical test layout according to the present invention;
FIG. 2 is a schematic diagram of a normal electrical test of the present invention;
FIG. 3 is a schematic diagram of an electrical test under abnormal conditions according to the present invention.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 1, the invention provides a WAT electrical test layout, which includes:
a plurality of active area patterns 01 which are distributed in a matrix and have the same shape;
first and second device region patterns (02, 03) alternately arranged in sequence across the active region pattern 01, and the boundary lines of the first and second device region patterns (02, 03) are divided into the active region pattern 01 across the first and second device region patterns;
in an embodiment of the present invention, the first device region pattern 02 is a pattern forming a low voltage device region.
In an embodiment of the present invention, the second device region pattern 03 is a pattern forming a medium voltage device region.
That is, the active region patterns 01 in the matrix are equally divided by the patterns of the low and medium voltage device forming regions, that is, half of the low voltage process and half of the medium voltage process are performed on each active region pattern 01.
The contact hole patterns are arranged on the active region patterns 01, the relative positions of the contact hole patterns on each row of the active region patterns 01 are different, and the contact hole patterns cover the region where the defects appear from left to right;
in the embodiment of the present invention, two contact patterns are disposed on each active region pattern 01.
In the embodiment of the invention, each contact hole pattern is sequentially distributed at equal intervals on the active regions of each column.
In each row of active region patterns 01, a first pad pattern 04 arranged on two adjacent active region patterns 01 and contact hole patterns thereon;
in each row of active area patterns 01, a second welding pad pattern 05 which spans two adjacent active area patterns 01 and contact hole patterns on the active area patterns;
wherein the first and second pad patterns (04, 05) constitute non-overlapping test loops crossing each active region pattern 01, and a series resistance can be obtained when a semiconductor device is manufactured by the layout.
In the embodiment of the invention, the first and second pad patterns (04, 05) are both disposed on the two adjacent active region patterns 01 and the two adjacent contact hole patterns thereof, and the first and second pad patterns (04, 05) do not share the same contact hole pattern.
In an embodiment of the present invention, the first and second patterns form a continuous S-shaped test loop that is non-overlapping and spans each active area pattern 01.
In the embodiment of the invention, the two ends of the S-shaped test loop are provided with third and fourth bonding pad patterns (06, 07) which are not shared with the first and second bonding pad patterns (04, 05) and share the same contact hole.
For example, in one possible implementation, on four rows and six columns of active area patterns 01, adjacent first and second device area patterns (02, 03) form a group, the active area patterns include six groups of first and second device area patterns (02, 03), then first pad patterns 04 sequentially arranged in a plurality of columns are respectively arranged on each column of active area patterns 01, a second pad pattern 05 is used for connecting the two adjacent columns of active area patterns, and third and fourth pad patterns (06, 07) are used as two testing ends of an S-shaped testing structure.
Referring to fig. 2, which shows the electrical test of the semiconductor device manufactured by the layout of the present embodiment under normal conditions, a smaller active region resistance value can be obtained by measuring the resistance between the pads manufactured by the third and fourth pad patterns (06, 07), which indicates that no formation defect such as NiSi occurs.
Referring to fig. 3, which shows the electrical test of the semiconductor device manufactured by the layout of the present embodiment under abnormal conditions, by measuring the resistance between the pads manufactured by the third and fourth pad patterns (06, 07), a larger or even close to open active region resistance value is obtained, which indicates that a defect such as NiSi formation occurs, resulting in an increase in contact resistance between the contact hole and the active region.
That is, the resistance test between the pads made of the third and fourth pad patterns (06, 07) is performed on the test key on each wafer, so as to determine whether the wafer has defects caused by abnormal formation of NiSi in the cross-connection region of low and medium voltage devices.
In the embodiment of the invention, the layouts are all in a rectangular shape.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In conclusion, the device manufactured by the layout can judge whether NiSi abnormity exists in the junction area of the low-voltage active area and the medium-voltage active area on the wafer or not by testing the resistance value of the pattern during testing, and the defect detection efficiency is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A WAT electrical test layout, comprising:
a plurality of active area patterns with the same shape are distributed in a matrix;
the first device area graph and the second device area graph are arranged in sequence and alternately and cross the active area graph, and the cross boundary line of the first device area graph and the second device area graph equally divides the cross active area graph;
the contact hole patterns are arranged on the active region patterns, and the relative positions of the contact hole patterns on each row of the active region patterns are different;
in each row of active area patterns, a first welding pad pattern is arranged on two adjacent active area patterns and the contact hole patterns on the active area patterns;
in each row of the active area patterns, a second welding pad pattern which spans two adjacent active area patterns and the contact hole patterns on the active area patterns;
the first and second pad patterns form a test loop which is not overlapped and spans each active region pattern.
2. The WAT electrical test layout of claim 1, wherein: the first device area pattern is a pattern for forming a low-voltage device area.
3. The WAT electrical test layout of claim 1, wherein: the second device region pattern is a pattern forming a medium voltage device region.
4. The WAT electrical test layout of claim 1, wherein: and two contact patterns are arranged on each active region pattern.
5. The WAT electrical test layout of claim 4, wherein: each contact hole pattern is distributed on the active region of each column in sequence at equal intervals.
6. The WAT electrical test layout of claim 5, wherein: the first welding pad graph and the second welding pad graph are arranged on the two adjacent active area graphs and the two adjacent contact hole graphs, and the first welding pad graph and the second welding pad graph do not share the same contact hole graph.
7. The WAT electrical test layout of claim 6, wherein: the first and second patterns form an S-shaped test loop which is not overlapped and spans each active region pattern.
8. The WAT electrical test layout of claim 7, wherein: and third and fourth welding pad patterns which are not shared with the first and second welding pad patterns and are not arranged at the two ends of the S-shaped test loop.
9. The WAT electrical test layout of claim 1, wherein: the layout is in a rectangular shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210702675.5A CN114999953A (en) | 2022-06-21 | 2022-06-21 | WAT electrical property test layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210702675.5A CN114999953A (en) | 2022-06-21 | 2022-06-21 | WAT electrical property test layout |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114999953A true CN114999953A (en) | 2022-09-02 |
Family
ID=83037236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210702675.5A Pending CN114999953A (en) | 2022-06-21 | 2022-06-21 | WAT electrical property test layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114999953A (en) |
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2022
- 2022-06-21 CN CN202210702675.5A patent/CN114999953A/en active Pending
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