CN213660352U

CN213660352U - Test structure of SDB technology

Info

Publication number: CN213660352U
Application number: CN202021810675.XU
Authority: CN
Inventors: 张璐
Original assignee: Hangzhou Guangli Microelectronics Co ltd
Current assignee: Hangzhou Guangli Microelectronics Co ltd
Priority date: 2020-08-26
Filing date: 2020-08-26
Publication date: 2021-07-09
Anticipated expiration: 2030-08-26

Abstract

The utility model provides a test structure of SDB technology for detect the process conditions that single diffusion area cut off, test structure includes at least one elementary cell: the basic unit comprises two fin field effect transistors: a first fin field effect transistor and a second fin field effect transistor; the fin field effect transistor comprises a plurality of adjacent parallel fins and a grid electrode structure crossing the fins, and a source electrode and a drain electrode of the fin field effect transistor are respectively arranged on the fins on two sides of the grid electrode structure; the first fin field effect transistor and the second fin field effect transistor share the same grid structure; and the single diffusion region is cut off and arranged on the grid structure of the second fin field effect transistor and is used for cutting off the source electrode and the drain electrode of the second fin field effect transistor.

Description

Test structure of SDB technology

Technical Field

The utility model relates to a semiconductor design and manufacturing field, in particular to test structure that single-diffusion break (SDB) technology among fin type field effect transistor (FINFET).

Background

With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the semiconductor industry has progressed to nanotechnology process nodes due to demands for high device density, high performance, and low cost, and the fabrication of semiconductor devices is limited by various physical limitations. With the continuous reduction of the size of the CMOS device, the CMOS device develops from a two-dimensional planar type to a three-dimensional type, and a fin field effect transistor (FinFET) is produced accordingly. A FinFET structure is typically formed by forming several strips of fins parallel to each other and gate structures crossing the fins on a silicon substrate. And forming a source region and a drain region on the fin portion. The source region and the drain region are respectively positioned on two sides of the grid structure and are collectively called as the active region of the fin field effect transistor.

In order to increase the density of devices in the FinFET process, a single-diffusion break (SDB) process is commonly used in the semiconductor fabrication of nodes below 14 nm.

Referring to fig. 1, fig. 1 is a schematic diagram of a FinFET structure with SDB structure. The FinFET structure in fig. 1 has a horizontal fin 1001 and a vertical gate structure 1002, a dummy gate structure 1003 is formed on a portion of the gate structure 1002 by cutting through an SDB process, and the SDB on the dummy gate structure 1003 cuts off the source and drain on both sides thereof. However, the SDB process is difficult, has a smaller process window, and is prone to failure. Therefore, designing a test structure of the SDB process for detecting problems occurring in the SDB process during development and mass production becomes a technical problem to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

The main object of the utility model is to provide a test structure of SDB technology. It can be detected whether the SDB process is failing.

The utility model provides a test structure of SDB technology for detect the process conditions that single diffusion area cut off, test structure includes at least one elementary cell: the basic unit comprises two fin field effect transistors: a first fin field effect transistor and a second fin field effect transistor; the fin field effect transistor comprises one fin part or at least two adjacent parallel fin parts and a grid electrode structure crossing the fin parts; the source electrode and the drain electrode of the fin field effect transistor are respectively arranged on the fin parts at two sides of the grid structure; the first fin field effect transistor and the second fin field effect transistor share the same grid structure; the single diffusion region is cut off and arranged on the grid structure of the second fin field effect transistor and used for cutting off the source electrode and the drain electrode of the second fin field effect transistor; the first fin field effect transistor and the second fin field effect transistor share a source metal line and a drain metal line; the source metal lines are respectively connected to a source of the first FinFET and a source of the second FinFET, and the drain metal lines are respectively connected to a drain of the first FinFET and a drain of the second FinFET.

Preferably, the type of the active region of the fin field effect transistor is L-shaped or rectangular; when the active region is L-shaped, the number of fin parts occupied by the source region and the drain region is different, namely the number of fin parts on two sides of the grid electrode structure is different; when the active region is rectangular, the number of the fin parts occupied by the source region and the drain region is the same, namely the number of the fin parts on two sides of the gate structure is the same.

Preferably, in the basic unit, the first fin field effect transistor and the second fin field effect transistor can adopt different types of active regions.

Preferably, the number of fins on at least one side of two sides of the gate structure of the first fin field effect transistor is 1.

The utility model discloses still relate to the test structure who provides a SDB technology, test structure includes a plurality of elementary cells, parallelly connected between a plurality of elementary cells: the source metal line of each basic unit is connected to the same source measurement signal line, the drain metal line of each basic unit is connected to the same drain measurement signal line, and the gate structure of each basic unit is connected to the same gate measurement signal line.

The utility model discloses still relate to the test structure who provides another kind of SDB technology, test structure includes a plurality of elementary cells, establish ties between a plurality of elementary cells: the drain metal line of the previous basic unit is connected with the source metal line of the next basic unit, the source metal line of the first basic unit is connected to the source measuring signal line, the drain metal line of the last basic unit is connected to the drain measuring signal line, and the grid structure of each basic unit is connected to the same grid measuring signal line.

The utility model has the advantages that: through the utility model discloses a test structure of SDB technology can be used for analyzing two kinds of failure conditions simply conveniently: firstly, cutting off a single diffusion region on the second fin field effect transistor to judge whether the source electrode and the drain electrode of the second fin field effect transistor are not completely cut off; and secondly, whether the single diffusion region on the second fin field effect transistor is cut off affects the first fin field effect transistor or not.

In combination with different DOEs (design of experiment), the utility model discloses a test structure can be used to analyze more SDB process problems.

Drawings

FIG. 1 is a schematic diagram of a prior art SDB process;

FIG. 2 is a schematic diagram of a test structure of the SDB process according to the first embodiment of the present invention;

fig. 3 is a schematic diagram of a test structure of the SDB process according to a second embodiment of the present invention;

fig. 4 is a schematic diagram of a test structure of an SDB process with a plurality of basic units connected in parallel according to a third embodiment of the present invention;

fig. 5 is a schematic diagram of a test structure of an SDB process in which a plurality of basic units are connected in series according to a fourth embodiment of the present invention.

The reference numbers in the figures are: 1001 fin portion; 1002 a gate structure; 1003 a dummy gate structure; 10 a basic unit; 11 a first fin field effect transistor; 12 a second finfet; 151 source metal lines; 152 a drain metal line; 153 a source contact; 154 drain contact; 155 a gate contact.

Detailed Description

The technical solutions of the present invention are described in further detail below with reference to the accompanying drawings, but the following detailed description does not represent the only configurations in which the present invention can be practiced. The following detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

Referring to fig. 2, the present embodiment provides a test structure of an SDB process, which includes at least one basic unit 10. The basic unit 10 includes at least a first finfet 11 and a second finfet 12, and the first finfet 11 and the second finfet 12 are disposed in an up-and-down manner.

In this embodiment, the active regions of the first finfet transistor 11 and the second finfet transistor 12 are both rectangular, that is, the number of fins occupied by the source region and the drain region of either one of the first finfet transistor 11 and the second finfet transistor 12 is the same. Specifically, the source region and the drain region of the first finfet 11 occupy the same fin. The source region and the drain region of the second finfet 12 occupy a fin group formed by a plurality of fins. The gate structure 1002 is perpendicular to the fin direction, and the first finfet 11 and the second finfet 12 share the same gate structure 1002.

In a second embodiment of the present invention, referring to fig. 3, the basic unit 10 ' includes a first finfet 11 ' and a second finfet 12 ', the active regions of the first finfet 11 ' and the second finfet 12 ' may be L-shaped, and the number of fins occupied by the source region and the drain region of the first finfet 11 ' and the second finfet 12 ' is different. Specifically, in the embodiment in fig. 3, the drain region of the first finfet 11' occupies 1 fin, and the source region occupies 2 fins. The drain region of the second finfet 12 'occupies 3 fins, and the source region of the second finfet 12' occupies 2 fins.

The utility model discloses in, how many fin portions can be adjusted according to actual need are occupied in first fin formula field effect transistor and the respective active area of second fin formula field effect transistor, and first fin formula field effect transistor and the active area of second fin formula field effect transistor can adopt the different grade type.

Referring to fig. 2, the first finfet transistor 11 and the second finfet transistor 12 share the gate structure 1002, the source metal line 151, and the drain metal line 152, i.e., the source of the first finfet transistor 11 and the source of the second finfet transistor 12 are commonly connected to the source metal line 151, and the drain of the first finfet transistor 11 and the drain of the second finfet transistor 12 are commonly connected to the drain metal line 152.

In a first embodiment of the present invention, referring to fig. 2, a single-diffused-region cut-off 14 is disposed on the gate structure of the second finfet 12, and the single-diffused-region cut-off 14 cuts off the source and drain of the second finfet 12.

The gate structure 1002 has a gate contact 155 connected to a gate measurement signal line V_GThe source metal line 151 has a source contact 153 connected to the source measurement signal line V_SThe drain metal line 152 has a drain contact 154 connected to the drain measurement signal line V_D. The SDB process conditions in the base unit 10 can be detected by current testing.

The test principle for testing the single diffusion area cutoff 14 (SDB) process failure using the test structure constituted by one base unit 10 of the present embodiment is as follows:

first, gate off (GT close), test if SDB causes the second finfet 12 LK to fail: normally, the source and drain of the second finfet 12 are cut off by SDB, the first finfet 11 is turned off, and the drain-source leakage current is < 1e-9(V = 1.2V); however, when SDB does not completely cut off the source and drain of the second finfet 12, leakage current becomes large, and LK is found to be failed.

Second, the gate (GT open) is opened, and the first finfet 11 is tested for SDB effects without finding the aforementioned LK failure: under normal conditions, Ids current exists between the source and the drain; however, when the active region of the first finfet 11 is SDB cut, the current drops sharply, and it is found that the active region of the first finfet 11 is affected by the underlying SDB.

In a specific application, the test structure comprises a plurality of basic units 10, and the plurality of basic units 10 can be connected in series or in parallel.

The third embodiment of the present invention provides a schematic diagram of a test structure with a plurality of basic units 10 connected in parallel. Referring to fig. 4, the test structure includes a plurality of basic cells 10, and the plurality of basic cells 10 are connected in parallel in such a manner that the source metal lines 151 of all the plurality of basic cells 10 are connected to the same source measurement signal line V_SThe drain metal lines 152 of all the plurality of unit cells 10 are connected to the same drain measurement signal line V_DAll the grid structures of the multiple basic units are connected to the same grid measuring signal line V_G。

The embodiment of the utility model provides a fourth provides a plurality of elementary cell 10 series connection's test structure's schematic diagram. Referring to fig. 5, the test structure includes a plurality of basic units 10, and the basic units 10 are connected in series; the drain metal line 152 of the previous basic cell is connected with the source metal line 151 of the next basic cell; the source metal line 151 of the first basic cell is connected to the source measurement signal line V_SThe drain metal line 152 of the last basic cell is connected to the drain measurement signal line V_D(ii) a The gate structures of all the basic units are connected to the same gate measurement signal line V_G。

It should be noted that the above two failure detections can be simultaneously realized by using the test structure formed by connecting the plurality of basic units 10 in parallel, but the first failure cannot be detected by using the test structure formed by connecting the plurality of basic units 10 in series.

Based on the test structure, different design of experiments (DOE) are combined to analyze more process problems of the SDB, for example, the process problems of the SDB are analyzed by designing test structures with different sizes and positions (extension AA distance, X misalign) and other data by making the DOE in relation to the active region of the second fin field effect transistor.

It should be noted that the above-mentioned embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the present invention. It is obvious that the present invention is not limited to the above embodiments, and other variations and modifications may be made. Obvious variations or modifications which can be derived from the disclosure of the present invention by a person skilled in the art are within the scope of the present invention.

Claims

1. A test structure for SDB process for detecting process conditions for single diffusion cutoff, said test structure comprising at least one basic unit:

the basic unit comprises two fin field effect transistors: a first fin field effect transistor and a second fin field effect transistor; the fin field effect transistor comprises one fin part or at least two adjacent parallel fin parts and a grid electrode structure crossing the fin parts; the source electrode and the drain electrode of the fin field effect transistor are respectively arranged on the fin parts at two sides of the grid structure;

the first fin field effect transistor and the second fin field effect transistor share the same grid structure; the single diffusion region is cut off and arranged on the grid structure of the second fin field effect transistor and used for cutting off the source electrode and the drain electrode of the second fin field effect transistor;

the first fin field effect transistor and the second fin field effect transistor share a source metal line and a drain metal line; the source metal lines are respectively connected to a source of the first FinFET and a source of the second FinFET, and the drain metal lines are respectively connected to a drain of the first FinFET and a drain of the second FinFET.

2. The test structure of the SDB process of claim 1, wherein the type of active region of the finfet is L-shaped or rectangular;

when the active region is L-shaped, the number of fin parts occupied by the source region and the drain region is different, namely the number of fin parts on two sides of the grid electrode structure is different;

when the active region is rectangular, the number of the fin parts occupied by the source region and the drain region is the same, namely the number of the fin parts on two sides of the gate structure is the same.

3. The test structure of the SDB process of claim 2, wherein the first finfet and the second finfet are capable of different types of active areas in the basic cell.

4. The test structure of claim 1, wherein the number of fins on at least one side of the gate structure of the first finfet is 1.

5. The test structure of the SDB process of any one of claims 1 to 4, wherein the test structure comprises a plurality of basic units, and the basic units are connected in parallel:

the source metal line of each basic unit is connected to the same source measurement signal line, the drain metal line of each basic unit is connected to the same drain measurement signal line, and the gate structure of each basic unit is connected to the same gate measurement signal line.

6. The test structure of the SDB process of any one of claims 1 to 4, wherein the test structure comprises a plurality of basic units, and the basic units are connected in series:

the drain metal line of the previous basic unit is connected with the source metal line of the next basic unit, the source metal line of the first basic unit is connected to the source measuring signal line, the drain metal line of the last basic unit is connected to the drain measuring signal line, and the grid structure of each basic unit is connected to the same grid measuring signal line.