CN114995581B - Power detection circuit and electronic equipment - Google Patents
Power detection circuit and electronic equipment Download PDFInfo
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- CN114995581B CN114995581B CN202210540152.5A CN202210540152A CN114995581B CN 114995581 B CN114995581 B CN 114995581B CN 202210540152 A CN202210540152 A CN 202210540152A CN 114995581 B CN114995581 B CN 114995581B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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- G05F3/262—Current mirrors using field-effect transistors only
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Abstract
The invention discloses a power detection circuit and electronic equipment, wherein the power detection circuit comprises a current mirror circuit, a voltage attenuation circuit, a multiplier circuit, a phase delay circuit, a current compensation circuit, an offset compensation circuit and a differential-to-single-ended circuit; the power detection circuit is insensitive to load impedance change of the load circuit and is used for detecting output power of the power amplifier circuit. Therefore, the invention can reduce the detection error in high power, improve the detection precision in high power and increase the inclusion of the subsequent circuit.
Description
Technical Field
The present invention relates to the field of detection technologies, and in particular, to a power detection circuit and an electronic device.
Background
In a radio frequency chip, in order to accurately control the transmitter output power, a power calibration loop is required, which includes a power detection circuit that measures the power amplifier output power to adjust the transmitter gain accordingly in a closed loop fashion. The existing power detection function is usually implemented by adopting a current mirror image and a multiplier circuit, but the detection error is gradually increased along with the increase of the output power of the power amplifier, so that the maximum detection range is limited. Therefore, it is necessary to provide a power detection circuit to reduce the detection error at high power, improve the detection accuracy at high power, and increase the inclusion of the following circuits.
Disclosure of Invention
The invention aims to solve the technical problem of providing a power detection circuit so as to reduce detection errors during high power, improve detection precision during high power and increase inclusion of subsequent circuits.
In order to solve the above technical problems, a first aspect of the present invention discloses a power detection circuit, which includes a current mirror circuit, a voltage attenuation circuit, a multiplier circuit, a phase delay circuit, a current compensation circuit, a misalignment compensation circuit, and a differential to single-ended circuit, wherein:
the first end of the current mirror circuit is electrically connected with the first end of the power amplifying circuit; the second end of the current mirror circuit is electrically connected with the second end of the power amplifying circuit; the third end of the current mirror circuit is electrically connected with the first end of the current compensation circuit and the first end of the multiplier circuit respectively; the fourth end of the current mirror circuit is electrically connected with the second end of the current compensation circuit and the second end of the multiplier circuit respectively; a third end of the multiplier circuit is electrically connected with a first end of the phase delay circuit; the fourth end of the multiplier circuit is electrically connected with the second end of the phase delay circuit; the fifth end of the multiplier circuit is electrically connected with the first end of the differential-to-single-ended circuit and the first end of the offset compensation circuit respectively; the sixth end of the multiplier circuit is electrically connected with the second end of the differential-to-single-ended circuit and the second end of the offset compensation circuit respectively; the third end of the phase delay circuit is electrically connected with the first end of the voltage attenuation circuit; the fourth end of the phase delay circuit is electrically connected with the second end of the voltage attenuation circuit; the third end of the voltage attenuation circuit is electrically connected with the third end of the power amplification circuit and the first end of the load circuit respectively; the fourth end of the voltage attenuation circuit is electrically connected with the fourth end of the power amplification circuit and the second end of the load circuit respectively; the third end of the current compensation circuit is used for being grounded; the third end of the differential-to-single-ended circuit is used for outputting single-ended voltage;
The power detection circuit is insensitive to load impedance changes of the load circuit and is used for detecting output power of the power amplifier circuit.
As an alternative embodiment, in the first aspect of the present invention, the multiplier circuit includes a gilbert cell and a driver stage circuit;
the first end of the Gilbert cell is electrically connected with the third end of the current mirror circuit and the first end of the current compensation circuit respectively; the second end of the Gilbert cell is electrically connected with the fourth end of the current mirror circuit and the second end of the current compensation circuit respectively; the third end of the Gilbert cell is electrically connected with the first end of the phase delay circuit; the fourth end of the Gilbert cell is electrically connected with the second end of the phase delay circuit; the fifth end of the Gilbert cell is electrically connected with the first end of the driving stage circuit; the sixth end of the Gilbert cell is electrically connected with the second end of the drive stage circuit; the third end of the driving stage circuit is electrically connected with the first end of the differential-to-single-ended circuit and the first end of the offset compensation circuit respectively; the fourth end of the driving stage circuit is electrically connected with the second end of the differential-to-single-ended circuit and the second end of the offset compensation circuit respectively;
The multiplier circuit is used for multiplying the current obtained by the current mirror circuit image and the voltage after attenuation and delay adjustment to obtain a pair of differential signals.
As an alternative embodiment, in the first aspect of the present invention, the driving stage circuit includes a first PM transistor PM1, a second PM transistor PM2, a third PM transistor PM3, a fourth PM transistor PM4, a fifth PM transistor PM5, a sixth PM transistor PM6, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2;
wherein a first end of the first PM transistor PM1 is electrically connected to a fifth end of the gilbert cell, a second end of the third PM transistor PM3, and a second end of the first PM transistor PM1, respectively; a third terminal of the first PM transistor PM1 is electrically connected to a third terminal of the second PM transistor PM2, a third terminal of the third PM transistor PM3, and a third terminal of the fourth PM transistor PM4, respectively; the first end of the second PM transistor PM2 is electrically connected to the sixth end of the gilbert cell, the second end of the second PM transistor PM2 and the second end of the fourth PM transistor PM4, respectively; a first end of the third PM transistor PM3 is electrically connected to a third end of the fifth PM transistor PM 5; a first end of the fourth PM transistor PM4 is electrically connected to a third end of the sixth PM transistor PM 6; a second terminal of the fifth PM transistor PM5 is electrically connected to a second terminal of the sixth PM transistor PM 6; the first end of the fifth PM transistor PM5 is electrically connected to the first end of the first resistor R1, the first end of the first capacitor C1, the first end of the differential-to-single-ended circuit, and the first end of the offset compensation circuit, respectively; the first end of the sixth PM transistor PM6 is electrically connected to the first end of the second resistor R2, the first end of the second capacitor C2, the second end of the differential-to-single-ended circuit, and the second end of the offset compensation circuit, respectively; the second end of the first resistor R1 is used for being grounded; the second end of the first capacitor C1 is used for being grounded; the second end of the second resistor R2 is used for being grounded; the second end of the second capacitor C2 is connected to ground.
As an alternative embodiment, in the first aspect of the present invention, the gilbert cell includes a first NM transistor NM1, a second NM transistor NM2, a third NM transistor NM3, and a fourth NM transistor NM4;
wherein a first terminal of the first NM transistor NM1 is electrically connected to a first terminal of the driving stage circuit and a first terminal of the third NM transistor NM3, respectively; the second end of the first NM transistor NM1 is respectively and electrically connected with the second end of the fourth NM transistor NM4 and the first end of the phase delay circuit; a third terminal of the first NM transistor NM1 is electrically connected to a third terminal of the second NM transistor NM2, a third terminal of the current mirror circuit, and a first terminal of the current compensation circuit, respectively; a first terminal of the second NM transistor NM2 is electrically connected to a first terminal of the fourth NM transistor NM4 and a second terminal of the driving stage circuit, respectively; the second end of the second NM transistor NM2 is respectively and electrically connected with the second end of the third NM transistor NM3 and the second end of the phase delay circuit; the third terminal of the third NM transistor NM3 is electrically connected to the third terminal of the fourth NM transistor NM4, the fourth terminal of the current mirror circuit, and the second terminal of the current compensation circuit, respectively.
As an optional implementation manner, in the first aspect of the present invention, the differential to single-ended circuit includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and an operational amplifier;
the first end of the third resistor R3 is used for being electrically connected with a common mode voltage; the second end of the third resistor R3 is electrically connected with the first end of the fourth resistor R4 and the first end of the operational amplifier respectively; the second end of the fourth resistor R4 is electrically connected with the fifth end of the multiplier circuit and the first end of the offset compensation circuit respectively; the first end of the fifth resistor R5 is electrically connected with the second end of the operational amplifier and the first end of the sixth resistor R6 respectively; the second end of the fifth resistor R5 is electrically connected with the sixth end of the multiplier circuit and the second end of the offset compensation circuit respectively; the third end of the operational amplifier is electrically connected with the second end of the sixth resistor R6 and the single-ended voltage output end respectively;
the differential to single-ended circuit is configured to convert a differential signal of the multiplier circuit to a single-ended voltage output.
As an optional implementation manner, in the first aspect of the present invention, the phase delay circuit includes a seventh resistor R7 and an eighth resistor R8;
Wherein a first end of the seventh resistor R7 is electrically connected with a first end of the voltage attenuation circuit; a second terminal of the seventh resistor R7 is electrically connected to a fifth terminal of the multiplier circuit; a first end of the eighth resistor R8 is electrically connected with a second end of the voltage attenuation circuit; a second terminal of the eighth resistor R8 is electrically connected to a sixth terminal of the multiplier circuit;
the phase delay circuit is used for compensating deviation between the image current of the current image circuit and the attenuation voltage of the voltage attenuation circuit.
As an alternative embodiment, in the first aspect of the present invention, the current mirror circuit includes a mirror source module Gm2;
the first end of the mirror image source module Gm2 is electrically connected with the first end of the power amplifying circuit; the second end of the mirror image source module Gm2 is electrically connected with the second end of the power amplifying circuit; the third end of the mirror image source module Gm2 is respectively and electrically connected with the first end of the current compensation circuit and the first end of the multiplier circuit; the fourth end of the mirror image source module Gm2 is electrically connected with the second end of the current compensation circuit and the second end of the multiplier circuit respectively;
the current mirror circuit is used for obtaining a mirror current proportional to the output current of the power amplifying circuit.
As an alternative embodiment, in the first aspect of the present invention, the current compensation circuit includes an Icomp module;
wherein a first terminal of the Icomp module is electrically connected to a third terminal of the current mirror circuit and a first terminal of the multiplier circuit, respectively; the second end of the Icomp module is electrically connected with the fourth end of the current mirror circuit and the second end of the multiplier circuit respectively;
the current compensation circuit is used for increasing the direct current input into the multiplier circuit, avoiding saturation when large alternating current is input, and reducing detection errors when large power is input.
As an alternative embodiment, in the first aspect of the present invention, the offset compensation circuit includes an Ical module;
the first end of the Ical module is electrically connected with the fifth end of the multiplier circuit and the first end of the differential-to-single-ended circuit respectively; the second end of the Ical module is electrically connected with the sixth end of the multiplier circuit and the second end of the differential-to-single-ended circuit respectively;
the offset compensation circuit is used for calibrating offset of the power detection circuit.
A second aspect of the present invention discloses an electronic device, which is characterized in that the electronic device includes the power detection circuit according to any one of the first aspects.
The implementation of the invention has the following beneficial effects:
in the invention, the power detection circuit comprises a current mirror circuit, a voltage attenuation circuit, a multiplier circuit, a phase delay circuit, a current compensation circuit, a maladjustment compensation circuit and a differential to single-ended circuit, wherein: the first end of the current mirror circuit is electrically connected with the first end of the power amplifying circuit; the second end of the current mirror circuit is electrically connected with the second end of the power amplifying circuit; the third end of the current mirror circuit is electrically connected with the first end of the current compensation circuit and the first end of the multiplier circuit respectively; the fourth end of the current mirror circuit is electrically connected with the second end of the current compensation circuit and the second end of the multiplier circuit respectively; the third end of the multiplier circuit is electrically connected with the first end of the phase delay circuit; the fourth end of the multiplier circuit is electrically connected with the second end of the phase delay circuit; the fifth end of the multiplier circuit is electrically connected with the first end of the differential-to-single-ended circuit and the first end of the offset compensation circuit respectively; the sixth end of the multiplier circuit is electrically connected with the second end of the differential-to-single-ended circuit and the second end of the offset compensation circuit respectively; the third end of the phase delay circuit is electrically connected with the first end of the voltage attenuation circuit; the fourth end of the phase delay circuit is electrically connected with the second end of the voltage attenuation circuit; the third end of the voltage attenuation circuit is electrically connected with the third end of the power amplification circuit and the first end of the load circuit respectively; the fourth end of the voltage attenuation circuit is electrically connected with the fourth end of the power amplification circuit and the second end of the load circuit respectively; the third end of the current compensation circuit is used for grounding; the third end of the differential-to-single-ended circuit is used for outputting single-ended voltage; the power detection circuit is insensitive to load impedance change of the load circuit and is used for detecting output power of the power amplifier circuit. Therefore, the invention can reduce the detection error in high power, improve the detection precision in high power and increase the inclusion of the subsequent circuit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a power detection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another power detection circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a power detection circuit according to another embodiment of the present invention;
fig. 4 is a schematic diagram of a power detection circuit according to another embodiment of the present invention.
Detailed Description
For a better understanding and implementation, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, unless explicitly specified and limited otherwise, the term "electrically connected" in the description of the invention and in the claims and in the above-mentioned figures should be understood in a broad sense, for example, as a fixed electrical connection, as a removable electrical connection, or as an integral electrical connection; can be mechanically and electrically connected or can be mutually communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. Furthermore, the terms first, second and the like in the description and in the claims of the invention and in the foregoing figures, are used for distinguishing between different objects and not for describing a particular sequential order, and are not intended to cover any exclusive inclusion. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Before describing the embodiments of the present invention, some of the prior art to which the embodiments of the present invention are directed will be described, in which a power calibration loop is required in order to accurately control the transmitter output power, and a power detection circuit is included to measure the power amplifier output power to adjust the transmitter gain accordingly in a closed loop fashion. In a specific implementation, according to the type of the detection signal, two modes can be divided, one is that under the condition that the load is not changed, the power value can be obtained by detecting the output voltage of the power amplifier and dividing the output voltage by a fixed resistance value based on the square of the voltage, and the power detection circuit is realized based on a squarer. The other is to detect the output voltage and current of the power amplifier at the same time and multiply the output voltage and current to obtain the power value, and the power detection circuit is realized based on a multiplier. In practical applications, the load may vary with the operating environment, and the accuracy of the power detection circuit implemented with the squarer may deteriorate, while the absolute transmit power obtained with the multiplier is still accurate. For the power detection circuit realized by the existing multiplier, it is most important to be able to accurately acquire voltage and current signals. The voltage is generally obtained by capacitive voltage division, the current is obtained by mirror image method, or by balun coupling method. If the current is obtained through the mirror structure, there is a problem that as the output power of the power amplifier increases, the detection error gradually increases, so that the maximum detection range is limited; if the mirror current is not adopted, the mirror current is obtained through a balun coupling mode, and the requirements on a process and a layout drawing method are high in the mode, so that the mirror current is not universal.
Example 1
Referring to fig. 1, fig. 1 is a schematic diagram of a power detection circuit according to an embodiment of the present invention, and the circuit can be applied to any circuit requiring power detection, which is not limited by the embodiment of the present invention. As shown in fig. 1, the power detection circuit includes a current mirror circuit, a voltage decay circuit, a multiplier circuit, a phase delay circuit, a current compensation circuit, a misalignment compensation circuit, and a differential to single-ended circuit, wherein:
the first end of the current mirror circuit is electrically connected with the first end of the power amplifying circuit; the second end of the current mirror circuit is electrically connected with the second end of the power amplifying circuit; the third end of the current mirror circuit is electrically connected with the first end of the current compensation circuit and the first end of the multiplier circuit respectively; the fourth end of the current mirror circuit is electrically connected with the second end of the current compensation circuit and the second end of the multiplier circuit respectively; the third end of the multiplier circuit is electrically connected with the first end of the phase delay circuit; the fourth end of the multiplier circuit is electrically connected with the second end of the phase delay circuit; the fifth end of the multiplier circuit is electrically connected with the first end of the differential-to-single-ended circuit and the first end of the offset compensation circuit respectively; the sixth end of the multiplier circuit is electrically connected with the second end of the differential-to-single-ended circuit and the second end of the offset compensation circuit respectively; the third end of the phase delay circuit is electrically connected with the first end of the voltage attenuation circuit; the fourth end of the phase delay circuit is electrically connected with the second end of the voltage attenuation circuit; the third end of the voltage attenuation circuit is electrically connected with the third end of the power amplification circuit and the first end of the load circuit respectively; the fourth end of the voltage attenuation circuit is electrically connected with the fourth end of the power amplification circuit and the second end of the load circuit respectively; the third end of the current compensation circuit is used for grounding; the third end of the differential-to-single-ended circuit is used for outputting single-ended voltage;
The power detection circuit is insensitive to load impedance change of the load circuit and is used for detecting output power of the power amplifier circuit.
Optionally, the voltage attenuation circuit includes an ATT module.
Optionally, the voltage attenuation circuit is used for obtaining an attenuation voltage proportional to the output voltage of the power amplification circuit, and the phase delay circuit is used for partially compensating the deviation between the image current and the initial attenuation voltage output by the voltage attenuation circuit, and obtaining a corresponding attenuation voltage after passing through the voltage attenuator and the phase delay circuit.
Optionally, the differential-to-single-ended circuit converts a differential voltage in a differential signal of the multiplier circuit into a single-ended voltage to be output, and amplifies the voltage by a plurality of times while realizing the conversion from differential to single-ended through the virtual short-circuit and virtual disconnection of the operational amplifier and the proportional relation action of the two groups of resistors.
Optionally, the differential signal output PDout of the multiplier circuit is:
PDout＝a*b*Gc*PAout；
optionally, the single-ended signal output pdout_single of the differential-to-single-ended circuit is:
PDout_single＝a*b*Gc*k*PAout；
the current mirror circuit has a current mirror ratio of a, an attenuator ratio of a voltage attenuation circuit of b, a multiplier gain of a multiplier circuit of Gc, a differential gain of a differential-to-single-ended circuit of k, and an output power of a power amplification circuit of PAout.
Optionally, the detection current of the power detection circuit is obtained through a mirror image structure, and two paths of compensation currents are added at the same time, so that the detection result is still accurate when the power is high, and the upper limit of power detection is expanded. Compared with the method for obtaining the detection current through balun coupling, the method has low requirements on the process and the layout drawing method, and is more universal. Furthermore, the power detection circuit can realize gain adjustment, and can output differential signals and single-ended signals simultaneously, so that the inclusion of the power detection circuit on subsequent circuits is improved.
Therefore, the power detection circuit described in the first embodiment can reduce the detection error at high power, improve the detection accuracy at high power, and increase the inclusion of the following circuits.
Example two
Referring to fig. 2, as shown in fig. 2, fig. 2 is a schematic diagram of a power detection circuit according to another embodiment of the present application, and as shown in fig. 2, the multiplier circuit includes a gilbert cell and a driver stage circuit;
the first end of the Gilbert cell is electrically connected with the third end of the current mirror circuit and the first end of the current compensation circuit respectively; the second end of the Gilbert cell is electrically connected with the fourth end of the current mirror circuit and the second end of the current compensation circuit respectively; the third end of the Gilbert cell is electrically connected with the first end of the phase delay circuit; the fourth end of the Gilbert cell is electrically connected with the second end of the phase delay circuit; the fifth end of the Gilbert cell is electrically connected with the first end of the driving stage circuit; the sixth end of the Gilbert cell is electrically connected with the second end of the driving stage circuit; the third end of the driving stage circuit is electrically connected with the first end of the differential-to-single-ended circuit and the first end of the offset compensation circuit respectively; the fourth end of the driving stage circuit is electrically connected with the second end of the differential-to-single-ended circuit and the second end of the offset compensation circuit respectively;
The multiplier circuit is used for multiplying the current obtained by the current mirror image circuit image and the voltage after attenuation and delay adjustment to obtain a pair of differential signals.
Therefore, the power detection circuit described in the second embodiment can reduce the detection error at high power, improve the detection accuracy at high power, and increase the inclusion of the following circuits.
Example III
Referring to fig. 3, fig. 3 is a schematic diagram of a power detection circuit according to another embodiment of the present invention, and as shown in fig. 3, the driving stage circuit includes a first PM transistor PM1, a second PM transistor PM2, a third PM transistor PM3, a fourth PM transistor PM4, a fifth PM transistor PM5, a sixth PM transistor PM6, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2;
wherein the first end of the first PM transistor PM1 is electrically connected to the fifth end of the gilbert cell, the second end of the third PM transistor PM3, and the second end of the first PM transistor PM1, respectively; the third terminal of the first PM transistor PM1 is electrically connected to the third terminal of the second PM transistor PM2, the third terminal of the third PM transistor PM3 and the third terminal of the fourth PM transistor PM4, respectively; the first terminal of the second PM transistor PM2 is electrically connected to the sixth terminal of the gilbert cell, the second terminal of the second PM transistor PM2 and the second terminal of the fourth PM transistor PM4, respectively; the first terminal of the third PM transistor PM3 is electrically connected to the third terminal of the fifth PM transistor PM 5; the first terminal of the fourth PM transistor PM4 is electrically connected to the third terminal of the sixth PM transistor PM 6; a second terminal of the fifth PM transistor PM5 is electrically connected to a second terminal of the sixth PM transistor PM 6; the first end of the fifth PM transistor (PM 5) is electrically connected with the first end of the first resistor R1, the first end of the first capacitor C1, the first end of the differential-to-single-ended circuit and the first end of the offset compensation circuit respectively; the first end of the sixth PM transistor PM6 is electrically connected to the first end of the second resistor R2, the first end of the second capacitor C2, the second end of the differential-to-single-ended circuit, and the second end of the offset compensation circuit, respectively; the second end of the first resistor R1 is used for grounding; the second end of the first capacitor C1 is used for grounding; the second end of the second resistor R2 is used for grounding; the second terminal of the second capacitor C2 is connected to ground.
Optionally, the driving stage circuit includes four transistors, 2 resistors and 2 capacitors, which are a first PM transistor PM1, a second PM transistor PM2, a third PM transistor PM3, a fourth PM transistor PM4, a fifth PM transistor PM5, a sixth PM transistor PM6, a first resistor R1, a second resistor R2, a first capacitor C1 and a second capacitor C2, respectively. Further, the first PM transistor PM1 and the second PM transistor PM2 are the same in size, and the third PM transistor PM3 and the fourth PM transistor PM4 are the same in size. Further, the first PM transistor PM1 and the third PM transistor PM3 form a current mirror structure, where the first PM transistor PM1 is connected to the first output current Ioutp of the gilbert cell, and the drain terminal of the third PM transistor PM3 is connected to the output PDoutp of the multiplier circuit through the fifth PM transistor PM 5. Further, the second PM transistor PM2 and the fourth PM transistor PM4 form a current mirror structure, the second PM transistor PM2 is connected to the second output current Ioutn of the gilbert cell, and the drain terminal of the fourth PM transistor PM4 is connected to the output PDoutn of the multiplier circuit through the sixth PM transistor PM 6.
Further, two sets of parallel resistors (a first resistor R1 and a second resistor R2) and capacitors (a first capacitor C1 and a second capacitor C2) are connected to the output of the multiplier circuit at one end and to ground at the other end. The resistor provides gain and the capacitor filters out high frequency waves.
In yet another alternative embodiment, the gilbert cell includes a first NM transistor NM1, a second NM transistor NM2, a third NM transistor NM3, and a fourth NM transistor NM4;
wherein the first end of the first NM transistor NM1 is electrically connected with the first end of the driving stage circuit and the first end of the third NM transistor NM3 respectively; the second end of the first NM transistor NM1 is respectively and electrically connected with the second end of the fourth NM transistor NM4 and the first end of the phase delay circuit; the third terminal of the first NM transistor NM1 is electrically connected with the third terminal of the second NM transistor NM2, the third terminal of the current mirror circuit and the first terminal of the current compensation circuit respectively; the first terminal of the second NM transistor NM2 is electrically connected to the first terminal of the fourth NM transistor NM4 and the second terminal of the driving stage circuit, respectively; the second end of the second NM transistor NM2 is respectively and electrically connected with the second end of the third NM transistor NM3 and the second end of the phase delay circuit; the third terminal of the third NM transistor NM3 is electrically connected to the third terminal of the fourth NM transistor NM4, the fourth terminal of the current mirror circuit, and the second terminal of the current compensation circuit, respectively.
Optionally, the gilbert cell includes four transistors of the same size, which are a first NM transistor NM1, a second NM transistor NM2, a third NM transistor NM3, and a fourth NM transistor NM4, respectively. Further, the source terminals of the first NM transistor NM1 and the second NM transistor NM2 receive the first image current Idetp of the current mirror circuit and the compensation current Icomp of the current compensation circuit, the source terminals of the third NM transistor NM3 and the fourth NM transistor NM4 receive the second image current Idetn of the current mirror circuit and the compensation current Icomp of the current compensation circuit, the gate terminals of the first NM transistor NM1 and the fourth NM transistor NM4 receive the attenuation voltage Vdetp after being attenuated by the voltage attenuation circuit and phase-shifted by the phase delay circuit, the gate terminals of the second NM transistor NM2 and the third NM transistor NM3 receive the attenuation voltage Vdetn after being attenuated by the voltage attenuation circuit and phase-shifted by the phase delay circuit, the drain terminals of the first NM transistor NM1 and the third NM transistor NM3 are connected to the first output current Ioutp of the driving stage circuit, and the drain terminals of the second NM2 and the fourth NM transistor 4 are connected to the second output current Ioutn of the driving stage circuit.
Optionally, the first current I1 and the first voltage V of the first NM transistor NM1 GS1 The relation of (2) is:
optionally, a second current I2 and a second voltage V of the second NM transistor NM2 GS2 The relation of (2) is:
optionally, a third current I3 and a third voltage V of the third NM transistor NM3 GS3 The relation of (2) is:
optionally, a fourth current I4 and a fourth voltage V of the fourth NM transistor NM4 GS4 The relation of (2) is:
wherein beta is the transistor coefficient, v detp For a first input AC voltage, and v detn For a second input AC voltage, V th For threshold voltage, V GS1 ＝V GS2 ，V GS3 ＝V GS4 。
Optionally, the first voltage V GS1 The dc voltage between the gate and the source of the first NM transistor NM1 is characterized.
Optionally, the second voltage V GS2 The dc voltage between the gate and the source of the second NM transistor NM2 is characterized.
Optionally, the third voltage V GS3 The dc voltage between the gate and the source of the third NM transistor NM3 is characterized.
Optionally, the fourth voltage V GS4 The dc voltage between the gate and the source of the fourth NM transistor NM4 is characterized.
Optionally, the conversion gain Gc of the multiplier circuit includes a first gain G1 of the gilbert cell and a second gain G2 of the driver stage circuit. The gilbert cell can implement multiplication through the square-rate relation of transistor current and voltage.
Optionally, the conversion gain Gc is in a specific form of
Gc＝G1*G2；
Optionally, the specific form of the first gain G1 is:
optionally, the specific form of the second gain G2 is:
G2＝m*R；
wherein Icomp is the compensation current, idetp is the first mirror current of the current mirror circuit, idetn is the second mirror current of the current mirror circuit, m is the current mirror ratio in the driving stage, and R is the resistance value.
Optionally, the resistance value of the first resistor R1 and the resistance value of the second resistor R2 are both R.
Therefore, the power detection circuit described in the third embodiment can reduce the detection error at high power, improve the detection precision at high power, and increase the inclusion of the following circuits.
Example IV
Referring to fig. 4, fig. 4 is a schematic diagram of a power detection circuit according to another embodiment of the present invention, and as shown in fig. 4, the differential-to-single-ended circuit includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and an operational amplifier;
the first end of the third resistor R3 is used for being electrically connected with a common mode voltage; the second end of the third resistor R3 is electrically connected with the first end of the fourth resistor R4 and the first end of the operational amplifier respectively; the second end of the fourth resistor R4 is electrically connected with the fifth end of the multiplier circuit and the first end of the offset compensation circuit respectively; the first end of the fifth resistor R5 is electrically connected with the second end of the operational amplifier and the first end of the sixth resistor R6 respectively; the second end of the fifth resistor R5 is electrically connected with the sixth end of the multiplier circuit and the second end of the offset compensation circuit respectively; the third end of the operational amplifier is electrically connected with the second end of the sixth resistor R6 and the single-ended voltage output end respectively;
The differential to single-ended circuit is used for converting differential signals of the multiplier circuit into single-ended voltage output.
Optionally, the specific form of the single-ended voltage PDout of the differential to single-ended circuit is:
where k represents the differential to single ended circuit gain.
Alternatively, the differential-to-single-ended circuit gain may be a ratio of the third resistor R3 to the fourth resistor R4, or may be a ratio of the sixth resistor R6 to the fifth resistor R5, which is not limited in the embodiment of the present invention.
In yet another alternative embodiment, the phase delay circuit includes a seventh resistor R7 and an eighth resistor R8;
wherein the first end of the seventh resistor R7 is electrically connected with the first end of the voltage attenuation circuit; a second end of the seventh resistor R7 is electrically connected with a fifth end of the multiplier circuit; the first end of the eighth resistor R8 is electrically connected with the second end of the voltage attenuation circuit; a second end of the eighth resistor R8 is electrically connected with a sixth end of the multiplier circuit;
the phase delay circuit is used for compensating deviation between the image current of the partial current image circuit and the attenuation voltage of the voltage attenuation circuit.
In yet another alternative embodiment, the current mirror circuit includes a mirror source module Gm2;
the first end of the mirror image source module Gm2 is electrically connected with the first end of the power amplifying circuit; the second end of the mirror image source module Gm2 is electrically connected with the second end of the power amplifying circuit; the third end of the mirror image source module Gm2 is respectively and electrically connected with the first end of the current compensation circuit and the first end of the multiplier circuit; the fourth end of the mirror image source module Gm2 is electrically connected with the second end of the current compensation circuit and the second end of the multiplier circuit respectively;
The current mirror circuit is used for obtaining mirror current proportional to the output current of the power amplifying circuit.
In yet another alternative embodiment, the current compensation circuit includes an Icomp module;
wherein the first end of the Icomp module is electrically connected with the third end of the current mirror circuit and the first end of the multiplier circuit respectively; the second end of the Icomp module is electrically connected with the fourth end of the current mirror circuit and the second end of the multiplier circuit respectively;
the current compensation circuit is used for increasing the direct current input into the multiplier circuit, avoiding saturation when large alternating current is input, and reducing detection errors when large power is input.
Optionally, the detection current is obtained through the current mirror circuit, and the compensation current is increased through the current compensation circuit, so that the upper limit of the detection range of the power detection circuit can be expanded. Furthermore, the compensation current of the current compensation circuit can be adjusted according to the requirements of different products on the detection range, and the universality is improved.
In an alternative embodiment, the offset compensation circuit includes an Ical module;
the first end of the Ical module is electrically connected with the fifth end of the multiplier circuit and the first end of the differential-to-single-ended circuit respectively; the second end of the Ical module is electrically connected with the sixth end of the multiplier circuit and the second end of the differential-to-single-ended circuit respectively;
The offset compensation circuit is used for calibrating offset of the power detection circuit.
Optionally, the offset compensation circuit is used for compensating offset generated by device mismatch in the whole path, so as to realize positive and negative inversion of the single-ended output result.
Optionally, by adding a differential-to-single-ended circuit and an offset compensation circuit, the differential signal and the single-ended signal are output simultaneously, so that the universality of the interface can be improved.
Optionally, because of asymmetry in the entire power detection path, such as mismatch between mirror transistors, resistance mismatch, capacitance mismatch, common mode offset of an operational amplifier, etc., the output result is decreased with the increase of power, in order to avoid this, an offset compensation circuit is added, and by injecting current into one side of the driving stage circuit, the offset of the entire channel described above can be uniformly compensated.
It should be noted that, for other descriptions of the power detection circuit, please refer to the related descriptions in the first embodiment, and the descriptions are omitted herein.
For other descriptions of the power detection circuit, please refer to the related descriptions in the first embodiment, the second embodiment and the third embodiment, which are not described herein.
Therefore, the power detection circuit described in the fourth embodiment can reduce the detection error at high power, improve the detection accuracy at high power, and increase the inclusion of the following circuits.
Example five
The embodiment of the invention discloses electronic equipment which is equipment for carrying out power detection and comprises a power detection circuit according to any one embodiment or two embodiments or three embodiments of the first embodiment to the fourth embodiment. It should be noted that, for the detailed description of the power detection circuit, please refer to the detailed description of the related contents in the first to third embodiments, and the detailed description of the embodiment is omitted.
Therefore, the electronic device described in the fifth embodiment can reduce the detection error at high power, improve the detection accuracy at high power, and increase the inclusion of the subsequent circuits.
The foregoing describes in detail a power detection circuit and an electronic device according to embodiments of the present invention, and specific embodiments are applied to illustrate the principles and implementation of the present invention, but the foregoing preferred embodiments are not intended to limit the present invention, and the foregoing embodiments are only used to help understand the method and core idea of the present invention; also, it is apparent to those skilled in the art from this disclosure that many changes can be made in this embodiment and this application without departing from the spirit and scope of the invention, which is set forth in the following claims.
Claims (10)
1. The utility model provides a power detection circuit, its characterized in that, power detection circuit includes current mirror circuit, voltage decay circuit, multiplier circuit, phase delay circuit, current compensation circuit, offset compensation circuit and difference change single-ended circuit, wherein:
the first end of the current mirror circuit is electrically connected with the first end of the power amplifying circuit; the second end of the current mirror circuit is electrically connected with the second end of the power amplifying circuit; the third end of the current mirror circuit is electrically connected with the first end of the current compensation circuit and the first end of the multiplier circuit respectively; the fourth end of the current mirror circuit is electrically connected with the second end of the current compensation circuit and the second end of the multiplier circuit respectively; a third end of the multiplier circuit is electrically connected with a first end of the phase delay circuit; the fourth end of the multiplier circuit is electrically connected with the second end of the phase delay circuit; the fifth end of the multiplier circuit is electrically connected with the first end of the differential-to-single-ended circuit and the first end of the offset compensation circuit respectively; the sixth end of the multiplier circuit is electrically connected with the second end of the differential-to-single-ended circuit and the second end of the offset compensation circuit respectively; the third end of the phase delay circuit is electrically connected with the first end of the voltage attenuation circuit; the fourth end of the phase delay circuit is electrically connected with the second end of the voltage attenuation circuit; the third end of the voltage attenuation circuit is electrically connected with the third end of the power amplification circuit and the first end of the load circuit respectively; the fourth end of the voltage attenuation circuit is electrically connected with the fourth end of the power amplification circuit and the second end of the load circuit respectively; the third end of the current compensation circuit is used for being grounded; the third end of the differential-to-single-ended circuit is used for outputting single-ended voltage;
The power detection circuit is insensitive to load impedance changes of the load circuit and is used for detecting output power of the power amplifier circuit.
2. The power detection circuit of claim 1, wherein the multiplier circuit comprises a gilbert cell and a driver stage circuit;
the first end of the Gilbert cell is electrically connected with the third end of the current mirror circuit and the first end of the current compensation circuit respectively; the second end of the Gilbert cell is electrically connected with the fourth end of the current mirror circuit and the second end of the current compensation circuit respectively; the third end of the Gilbert cell is electrically connected with the first end of the phase delay circuit; the fourth end of the Gilbert cell is electrically connected with the second end of the phase delay circuit; the fifth end of the Gilbert cell is electrically connected with the first end of the driving stage circuit; the sixth end of the Gilbert cell is electrically connected with the second end of the drive stage circuit; the third end of the driving stage circuit is electrically connected with the first end of the differential-to-single-ended circuit and the first end of the offset compensation circuit respectively; the fourth end of the driving stage circuit is electrically connected with the second end of the differential-to-single-ended circuit and the second end of the offset compensation circuit respectively;
The multiplier circuit is used for multiplying the current obtained by the current mirror circuit image and the voltage after attenuation and delay adjustment to obtain a pair of differential signals.
3. The power detection circuit of claim 2, wherein the driver stage circuit comprises a first PM transistor (PM 1), a second PM transistor (PM 2), a third PM transistor (PM 3), a fourth PM transistor (PM 4), a fifth PM transistor (PM 5), a sixth PM transistor (PM 6), a first resistor (R1), a second resistor (R2), a first capacitor (C1), and a second capacitor (C2);
wherein a first end of the first PM transistor (PM 1) is electrically connected to a fifth end of the gilbert cell, a second end of the third PM transistor (PM 3) and a second end of the first PM transistor (PM 1), respectively; a third terminal of the first PM transistor (PM 1) is electrically connected to a third terminal of the second PM transistor (PM 2), a third terminal of the third PM transistor (PM 3) and a third terminal of the fourth PM transistor (PM 4), respectively; a first end of the second PM transistor (PM 2) is electrically connected to a sixth end of the gilbert cell, a second end of the second PM transistor (PM 2) and a second end of the fourth PM transistor (PM 4), respectively; a first terminal of the third PM transistor (PM 3) is electrically connected to a third terminal of the fifth PM transistor (PM 5); a first terminal of the fourth PM transistor (PM 4) is electrically connected to a third terminal of the sixth PM transistor (PM 6); a second terminal of the fifth PM transistor (PM 5) is electrically connected to a second terminal of the sixth PM transistor (PM 6); a first end of the fifth PM transistor (PM 5) is electrically connected to the first end of the first resistor (R1), the first end of the first capacitor (C1), the first end of the differential-to-single-ended circuit, and the first end of the offset compensation circuit, respectively; the first end of the sixth PM transistor (PM 6) is electrically connected with the first end of the second resistor (R2), the first end of the second capacitor (C2), the second end of the differential-to-single-ended circuit and the second end of the offset compensation circuit respectively; the second end of the first resistor (R1) is used for grounding; the second end of the first capacitor (C1) is used for grounding; a second end of the second resistor (R2) is used for grounding; the second end of the second capacitor (C2) is used for grounding.
4. The power detection circuit according to claim 2, wherein the gilbert cell comprises a first NM transistor (NM 1), a second NM transistor (NM 2), a third NM transistor (NM 3) and a fourth NM transistor (NM 4);
wherein a first terminal of the first NM transistor (NM 1) is electrically connected to a first terminal of the driving stage circuit and a first terminal of the third NM transistor (NM 3), respectively; the second end of the first NM transistor (NM 1) is respectively and electrically connected with the second end of the fourth NM transistor (NM 4) and the first end of the phase delay circuit; a third terminal of the first NM transistor (NM 1) is electrically connected to a third terminal of the second NM transistor (NM 2), a third terminal of the current mirror circuit, and a first terminal of the current compensation circuit, respectively; a first terminal of the second NM transistor (NM 2) is electrically connected to a first terminal of the fourth NM transistor (NM 4) and a second terminal of the driving stage circuit, respectively; a second end of the second NM transistor (NM 2) is respectively and electrically connected with a second end of the third NM transistor (NM 3) and a second end of the phase delay circuit; a third terminal of the third NM transistor (NM 3) is electrically connected to a third terminal of the fourth NM transistor (NM 4), a fourth terminal of the current mirror circuit and a second terminal of the current compensation circuit, respectively.
5. The power detection circuit of claim 1, wherein the differential to single ended circuit comprises a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), and an operational amplifier;
wherein a first end of the third resistor (R3) is used for electrically connecting a common mode voltage; the second end of the third resistor (R3) is electrically connected with the first end of the fourth resistor (R4) and the first end of the operational amplifier respectively; a second end of the fourth resistor (R4) is electrically connected with a fifth end of the multiplier circuit and a first end of the offset compensation circuit respectively; a first end of the fifth resistor (R5) is electrically connected to a second end of the operational amplifier and a first end of the sixth resistor (R6), respectively; a second end of the fifth resistor (R5) is electrically connected with a sixth end of the multiplier circuit and a second end of the offset compensation circuit respectively; a third end of the operational amplifier is electrically connected with a second end of the sixth resistor (R6) and a single-ended voltage output end respectively;
the differential to single-ended circuit is configured to convert a differential signal of the multiplier circuit to a single-ended voltage output.
6. The power detection circuit according to claim 1, wherein the phase delay circuit comprises a seventh resistor (R7) and an eighth resistor (R8);
Wherein a first end of the seventh resistor (R7) is electrically connected to a first end of the voltage decay circuit; a second terminal of the seventh resistor (R7) is electrically connected to a fifth terminal of the multiplier circuit; a first end of the eighth resistor (R8) is electrically connected with a second end of the voltage attenuation circuit; a second terminal of the eighth resistor (R8) is electrically connected to a sixth terminal of the multiplier circuit;
the phase delay circuit is used for compensating deviation between the image current of the current image circuit and the attenuation voltage of the voltage attenuation circuit.
7. The power detection circuit according to claim 1, characterized in that the current mirror circuit comprises a mirror source module (Gm 2);
wherein a first end of the mirror source module (Gm 2) is electrically connected to a first end of the power amplifying circuit; a second end of the mirror image source module (Gm 2) is electrically connected with a second end of the power amplifying circuit; a third terminal of the mirror source module (Gm 2) is electrically connected to the first terminal of the current compensation circuit and the first terminal of the multiplier circuit, respectively; a fourth terminal of the mirror source module (Gm 2) is electrically connected to the second terminal of the current compensation circuit and the second terminal of the multiplier circuit, respectively;
The current mirror circuit is used for obtaining a mirror current proportional to the output current of the power amplifying circuit.
8. The power detection circuit of claim 1, wherein the current compensation circuit comprises an Icomp module;
wherein a first terminal of the Icomp module is electrically connected to a third terminal of the current mirror circuit and a first terminal of the multiplier circuit, respectively; the second end of the Icomp module is electrically connected with the fourth end of the current mirror circuit and the second end of the multiplier circuit respectively;
the current compensation circuit is used for increasing the direct current input into the multiplier circuit, avoiding saturation when large alternating current is input, and reducing detection errors when large power is input.
9. The power detection circuit of claim 1, wherein the offset compensation circuit comprises an Ical module;
the first end of the Ical module is electrically connected with the fifth end of the multiplier circuit and the first end of the differential-to-single-ended circuit respectively; the second end of the Ical module is electrically connected with the sixth end of the multiplier circuit and the second end of the differential-to-single-ended circuit respectively;
the offset compensation circuit is used for calibrating offset of the power detection circuit.
10. An electronic device comprising a power detection circuit according to any of claims 1-9.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010083708A (en) * | 2000-02-21 | 2001-09-01 | 박종섭 | Zero-crossing detection circuit |
| CN101019314A (en) * | 2004-08-06 | 2007-08-15 | 皇家飞利浦电子股份有限公司 | RF power sensing circuit |
| CN110989756A (en) * | 2019-12-05 | 2020-04-10 | 思瑞浦微电子科技（苏州）股份有限公司 | Low dropout regulator based on constant power protection |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010083708A (en) * | 2000-02-21 | 2001-09-01 | 박종섭 | Zero-crossing detection circuit |
| CN101019314A (en) * | 2004-08-06 | 2007-08-15 | 皇家飞利浦电子股份有限公司 | RF power sensing circuit |
| CN110989756A (en) * | 2019-12-05 | 2020-04-10 | 思瑞浦微电子科技（苏州）股份有限公司 | Low dropout regulator based on constant power protection |
Non-Patent Citations (1)
| Title |
|---|
| 大电容负载下的高速、低功耗动态摆率增强电路研究;叶珍华;杨海钢;李凡阳;程小燕;尹韬;刘飞;;微电子学与计算机(第12期);全文 * |
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