CN110989756A - Low dropout regulator based on constant power protection - Google Patents
Low dropout regulator based on constant power protection Download PDFInfo
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- CN110989756A CN110989756A CN201911237571.6A CN201911237571A CN110989756A CN 110989756 A CN110989756 A CN 110989756A CN 201911237571 A CN201911237571 A CN 201911237571A CN 110989756 A CN110989756 A CN 110989756A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention discloses a low dropout regulator based on constant power protection, which comprises: the LDO unit comprises an error amplifier AMP, a MOS (metal oxide semiconductor) tube MP, a voltage division resistor Rf1 and a voltage division resistor Rf2, and the load current in the LDO unit is IL; the first voltage detection unit is used for outputting a first voltage V1 and comprises a plurality of current mirrors and resistors; the second voltage detection unit is used for outputting a second voltage V2 and comprises an MOS (metal oxide semiconductor) transistor MS and a resistor; the constant power protection unit comprises an analog multiplier, a comparator and a MOS (metal oxide semiconductor) tube PM5, wherein the analog multiplier is used for multiplying a first voltage V1 and a second voltage and outputting Vp, the comparator is used for comparing Vp with a preset power value Vrefp, and whether the LDO unit works is controlled through the MOS tube PM5 according to the comparison result. According to the invention, through the two voltage detection units and the constant power protection unit, when the LDO unit outputs overcurrent, the actual output current IL can be calculated according to the set values of the power P and the VDD-VOUT, and the LDO unit can be intuitively and linearly protected.
Description
Technical Field
The invention belongs to the technical field of low dropout linear regulators, and particularly relates to a low dropout linear regulator based on constant power protection.
Background
Low Dropout regulator (LDO) has the advantages of Low output noise, simple circuit structure, small occupied chip area, small voltage ripple, etc., and has become an important circuit in power management chips. The low-dropout linear regulator can provide a power supply with low output ripples for noise sensitive circuits such as analog circuits, radio frequency circuits and the like, and is widely applied to system-on-chip chips due to the relatively simple structure and few peripheral components.
Referring to fig. 1, the LDO in the prior art mainly includes an error amplifier AMP, a MOS transistor MP, voltage dividing resistors Rf1 and Rf2, and a load (load current is IL). The basic principle of the LDO is as follows: the error amplifier AMP is used for amplifying the difference between the feedback voltage Vfb and the reference voltage Vref, the gate-source voltage Vgs of the MOS transistor MP increases or decreases the current to control the output voltage, so as to stabilize the output voltage, and finally the Vref and Vfb error amplification form negative feedback through the error amplifier EA so that the output voltage is stabilized at Vout-Vref × (Rf1+ Rf2)/Rf 2.
When the LDO in the prior art overflows, just begin the protection when reaching preset current protection point, but this point of overflowing can have great change along with different chips and different conditions, and it is too big and burn the piece that probably can take place like this, especially high-voltage input circuit, also probably takes place the condition that the electric current is not available, to the chip user moreover, can't audio-visual understanding the current capability of chip, bring unnecessary trouble to the use.
Therefore, in view of the above technical problems, it is necessary to provide a low dropout regulator based on constant power protection.
Disclosure of Invention
The invention aims to provide a low dropout regulator based on constant power protection so as to realize the constant power protection of an LDO (low dropout regulator).
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a low dropout linear regulator based on constant power protection, the low dropout linear regulator comprising:
the LDO unit comprises an error amplifier AMP, a MOS (metal oxide semiconductor) tube MP, a voltage division resistor Rf1 and a voltage division resistor Rf2, and the load current in the LDO unit is IL;
the first voltage detection unit is used for outputting a first voltage V1 and comprises a plurality of current mirrors and resistors;
the second voltage detection unit is used for outputting a second voltage V2 and comprises an MOS (metal oxide semiconductor) transistor MS and a resistor;
the constant power protection unit comprises an analog multiplier, a comparator and a MOS (metal oxide semiconductor) tube PM5, wherein the analog multiplier is used for multiplying a first voltage V1 and a second voltage and outputting Vp, the comparator is used for comparing Vp with a preset power value Vrefp, and whether the LDO unit works is controlled through the MOS tube PM5 according to the comparison result.
In one embodiment, the first voltage detection unit includes MOS transistors NM1, NM2, NM3, NM4, NM5, NM6, PM1, PM2, PM3, PM4, resistors R1, R2, R3, NM1, NM2, NM3, NM4, NM5, and NM6 are NMOS transistors, and PM1, PM2, PM3, and PM4 are PMOS transistors; wherein:
the resistor R1 is connected with a power supply voltage VDD;
the resistor R2 is connected with the output voltage VOUT of the LDO unit;
the resistor R3 is connected with the ground potential;
MOS pipe NM1 and NM2 are connected in a common grid mode to form a first current mirror, MOS pipe NM1 is connected between resistor R1 and the ground potential, and MOS pipe NM2 is connected between PM1 and the ground potential;
MOS pipe PM1 and PM2 are connected in a common grid mode to form a second current mirror, MOS pipe PM1 is connected between power supply voltage VDD and MOS pipe NM2, and MOS pipe PM2 is connected between power supply voltage VDD and MOS pipe NM 3;
MOS pipe NM3 and NM6 are connected in a common grid mode to form a third current mirror, MOS pipe NM3 is connected between MOS pipe PM2 and the ground potential, and MOS pipe NM6 is connected between MOS pipe PM3 and the ground potential;
MOS transistor NM4 and NM5 are connected in a common gate mode to form a fourth current mirror, MOS transistor NM4 is connected between the gate of NM3 and the ground potential, and NM5 is connected between resistor R2 and the ground potential;
MOS pipe PM3 and PM4 are connected in a common gate mode to form a fifth current mirror, MOS pipe PM3 is connected between power supply voltage VDD and MOS pipe NM6, and MOS pipe PM4 is connected between power supply voltage VDD and resistor R3.
In an embodiment, the first voltage V1 output by the first voltage detection unit is a voltage across the resistor R3, and the first voltage V1 ═ IR3 ═ R3 ═ IR1-IR2 ═ R3, where IR1, IR2, and IR3 are currents flowing through the resistors R1, R2, and R3, respectively.
In one embodiment, the first voltage detecting unit includes:
wherein, the size ratio of NM1 and NM2, the size ratio of NM3 and NM6, the size ratio of NM4 and NM5, the size ratio of PM1 and PM2, and the size ratio of PM3 and PM4 are all 1, VGSNM1 and VGSNM5 are the gate-source voltage difference of NM1 and NM5, respectively, and VOUT is less than VDD.
In an embodiment, the voltage difference between the gates and the sources of NM1 and NM5 in the first voltage detecting unit is equal, the resistances of the resistors R1, R2, and R3 are equal, and the first voltage V1 output by the first voltage detecting unit is VDD-VOUT.
In an embodiment, the second voltage detection unit includes a MOS transistor MS and a resistor R4, where the MOS transistor MS and the MOS transistor MP are both PMOS transistors, and the MOS transistors MS and MP are connected in common gate, the MOS transistor MS is connected to a power voltage VDD and the resistor R4, and the resistor R4 is connected to a ground potential.
In an embodiment, in the second voltage detecting unit, a size ratio of MS to MP is 1: n, the current Isen flowing through the MOS tube MS is as follows:
in one embodiment, the second voltage V2 output by the second voltage detecting unit is a voltage across the resistor R4, and the second voltage V2 is:
in one embodiment, in the constant power protection unit, the MOS transistor PM5 is a PMOS transistor, the gate of the MOS transistor PM5 is connected to the output terminal of the analog multiplier, the source is connected to the power supply voltage VDD, and the drain is connected to the output terminal of the error amplifier AMP.
In one embodiment, the constant power protection unit includes:
in a first state, when Vp is V1 × V2> Vrefp, the MOS transistor PM5 is turned on, the MOS transistor MP is turned off, and the LDO unit does not operate;
in the second state, when Vp is V1 × V2< Vrefp, the MOS transistor PM5 is turned off, the MOS transistor MP is not controlled by the MOS transistor PM5, and the LDO unit operates normally.
Compared with the prior art, the invention has the following advantages:
according to the invention, through the two voltage detection units and the constant power protection unit, when the LDO unit outputs overcurrent, the actual output current IL can be calculated according to the set values of the power P and the VDD-VOUT, and the LDO unit can be intuitively and linearly protected.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic circuit diagram of a prior art LDO;
fig. 2 is a schematic circuit diagram of a low dropout linear regulator based on constant power protection according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
The invention discloses a low dropout regulator based on constant power protection, which comprises:
the LDO unit comprises an error amplifier AMP, a MOS (metal oxide semiconductor) tube MP, a voltage division resistor Rf1 and a voltage division resistor Rf2, and the load current in the LDO unit is IL;
the first voltage detection unit is used for outputting a first voltage V1 and comprises a plurality of current mirrors and resistors;
the second voltage detection unit is used for outputting a second voltage V2 and comprises an MOS (metal oxide semiconductor) transistor MS and a resistor;
the constant power protection unit comprises an analog multiplier, a comparator and a MOS (metal oxide semiconductor) tube PM5, wherein the analog multiplier is used for multiplying a first voltage V1 and a second voltage and outputting Vp, the comparator is used for comparing Vp with a preset power value Vrefp, and whether the LDO unit works is controlled through the MOS tube PM5 according to the comparison result.
The present invention is further illustrated by the following specific examples.
Referring to fig. 2, in an embodiment of the present invention, a low dropout regulator based on constant power protection specifically includes:
the LDO unit 10 comprises an error amplifier AMP, a MOS tube MP, voltage dividing resistors Rf1 and Rf2, and the load current in the LDO unit is IL;
a first voltage detecting unit 20 for outputting a first voltage V1, which includes a plurality of current mirrors and resistors;
the second voltage detection unit 30 is configured to output a second voltage V2, and includes a MOS transistor MS and a resistor;
the constant power protection unit 40 comprises an analog multiplier, a comparator and a MOS (metal oxide semiconductor) tube PM5, wherein the analog multiplier is used for multiplying the first voltage V1 and the second voltage and outputting Vp, the comparator is used for comparing Vp with a preset power value Vrefp, and whether the LDO unit works is controlled through the MOS tube PM5 according to the comparison result.
Each unit in the circuit will be described in detail below. In the LDO unit 10, AMP, MP, Rf1, and Rf2 constitute basic LDO circuits, and will not be described herein again.
First voltage detection unit 20:
the first voltage detection unit comprises MOS tubes NM1, NM2, NM3, NM4, NM5, NM6, PM1, PM2, PM3, PM4 and resistors R1, R2, R3, NM1, NM2, NM3, NM4, NM5 and NM6 which are NMOS tubes, and PM1, PM2, PM3 and PM4 which are PMOS tubes.
The connection mode of each component in the embodiment is as follows:
the resistor R1 is connected with a power supply voltage VDD;
the resistor R2 is connected with the output voltage VOUT of the LDO unit;
the resistor R3 is connected with the ground potential;
MOS pipe NM1 and NM2 are connected in a common grid mode to form a first current mirror, MOS pipe NM1 is connected between resistor R1 and the ground potential, MOS pipe NM2 is connected between PM1 and the ground potential, specifically, the drain of NM1 is connected with resistor R1, the source is connected with the ground potential, the drain of NM2 is connected with the drain of PM1, and the source is connected with the ground potential;
MOS pipe PM1 and PM2 are connected in a common grid mode to form a second current mirror, MOS pipe PM1 is connected between a power supply voltage VDD and an MOS pipe NM2, MOS pipe PM2 is connected between the power supply voltage VDD and an MOS pipe NM3, specifically, the source of PM1 is connected with the power supply voltage VDD, the drain of PM 8584 is connected with the drain of NM2, the source of PM2 is connected with the power supply voltage VDD, and the drain of PM3 is connected with the drain of NM 3;
MOS pipe NM3 and NM6 are connected in a common grid mode to form a third current mirror, MOS pipe NM3 is connected between MOS pipe PM2 and the ground potential, MOS pipe NM6 is connected between MOS pipe PM3 and the ground potential, specifically, the drain electrode of NM3 is connected with the drain electrode of PM2, the source electrode of NM6 is connected with the ground potential, the drain electrode of NM6 is connected with the drain electrode of PM3, and the source electrode of NM3 is connected with the ground potential;
MOS pipe NM4 and NM5 are connected in a common grid mode to form a fourth current mirror, MOS pipe NM4 is connected between the grid electrode of NM3 and the ground potential, NM5 is connected between resistor R2 and the ground potential, specifically, the drain electrode of NM4 is connected with the grid electrodes of NM3 and NM6, the source electrode of NM4 is connected with the ground potential, the drain electrode of NM5 is connected with resistor R2, and the source electrode of NM5 is connected with the ground potential;
MOS pipe PM3, PM4 are connected in a common grid mode to form a fifth current mirror, MOS pipe PM3 is connected between a power supply voltage VDD and MOS pipe NM6, MOS pipe PM4 is connected between the power supply voltage VDD and a resistor R3, specifically, the source of PM3 is connected with the power supply voltage VDD, the drain of PM 8584 is connected with the drain of NM6, the source of PM4 is connected with the power supply voltage VDD, and the drain of PM4 is connected with a resistor R3.
In the present embodiment, the size ratio of NM1 and NM2, the size ratio of NM3 and NM6, the size ratio of NM4 and NM5, the size ratio of PM1 and PM2, and the size ratio of PM3 and PM4 are all 1, and thus:
VGSNM1 and VGSNM5 are gate-source voltage differences of NM1 and NM5, respectively.
According to the mirror principle of current mirrors, the current flowing through PM2 equals IR1, the current flowing through NM4 equals IR2, then the current flowing through NM3 equals IR1-IR2, then the current flowing through NM6 equals NM3, i.e. IR1-IR2, and the current flowing through R3, IR3 equals IR1-IR 2.
The output VOUT of the LDO unit is < VDD, VGSNM1 can be equal or approximately equal to VGSNM5 by circuit design, then:
the first voltage V1 (i.e. the voltage across the resistor R3) output by the first voltage detection unit is:
wherein, IR1, IR2, and IR3 are currents flowing through resistors R1, R2, and R3, respectively.
Accordingly, the resistances of the resistors R1, R2, and R3 are set such that R1 is equal to R2 is equal to R3, and the first voltage V1 output by the first voltage detection unit is equal to VDD-VOUT.
Second voltage detection unit 30:
in this embodiment, the second voltage detection unit includes a MOS transistor MS and a resistor R4, the MOS transistor MS and the MOS transistor MP are connected in common gate, a source of the MOS transistor MS is connected to the power supply voltage VDD, a drain of the MOS transistor MS is connected to the resistor R4, a gate of the MOS transistor MS is connected to the AMP output terminal, and the resistor R4 is connected to the ground potential.
Wherein, MP is the power MOS pipe (PMOS pipe), the power tube of LDO unit promptly, and load current IL all need flow through MP, and MS (PMOS pipe) is the current detection pipe, and MS and MP's size ratio is 1: n, so the current flowing through MS is:
as the load current IL gradually increases, Isen also gradually increases.
In this embodiment, the second voltage V2 output by the second voltage detecting unit is a voltage across the resistor R4, and the second voltage V2 is:
where k is R4/N, N is typically hundreds or even thousands, and it is possible to design R4 is N (i.e., k is 1), then the second voltage is V2 is IL.
Constant power protection unit 40:
the constant power protection unit comprises an analog multiplier (analog multiplier), a Comparator (CMP) and a MOS (metal oxide semiconductor) tube PM5, wherein the MOS tube PM5 is a PMOS tube, the grid electrode of the MOS tube PM5 is connected with the output end of the analog multiplier, the source electrode of the MOS tube PM is connected with a power supply voltage VDD, and the drain electrode of the MOS tube PM is connected with the output end of the error amplifier AMP.
An analog multiplier (analog multiplier) is used to multiply the first voltage V1 and the second voltage and output Vp:
Vp＝V1*V2＝(VDD-VOUT)*k*IL。
the comparator compares Vp with a preset power value Vrefp, and controls MP5 according to the comparison result, thereby limiting the current of the power tube MP of the LDO unit.
The working states of the constant power protection unit are as follows:
in a first state, when Vp is V1 × V2> Vrefp, the MOS transistor PM5 is turned on, the MOS transistor MP is turned off, and the LDO unit does not operate;
in the second state, when Vp is V1 × V2< Vrefp, the MOS transistor PM5 is turned off, the MOS transistor MP is not controlled by the MOS transistor PM5, and the LDO unit operates normally.
Vrefp is a set power value, for example, Vrefp 1.5V represents an output limit power of 1.5W.
Thus, when VDD and VOUT are known, by formula
The overflow point IL can be calculated directly.
The technical scheme shows that the invention has the following beneficial effects:
according to the invention, through the two voltage detection units and the constant power protection unit, when the LDO unit outputs overcurrent, the actual output current IL can be calculated according to the set values of the power P and the VDD-VOUT, and the LDO unit can be intuitively and linearly protected.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A low dropout regulator (LDO) based on constant power protection, comprising:
the LDO unit comprises an error amplifier AMP, a MOS (metal oxide semiconductor) tube MP, a voltage division resistor Rf1 and a voltage division resistor Rf2, and the load current in the LDO unit is IL;
the first voltage detection unit is used for outputting a first voltage V1 and comprises a plurality of current mirrors and resistors;
the second voltage detection unit is used for outputting a second voltage V2 and comprises an MOS (metal oxide semiconductor) transistor MS and a resistor;
the constant power protection unit comprises an analog multiplier, a comparator and a MOS (metal oxide semiconductor) tube PM5, wherein the analog multiplier is used for multiplying a first voltage V1 and a second voltage and outputting Vp, the comparator is used for comparing Vp with a preset power value Vrefp, and whether the LDO unit works is controlled through the MOS tube PM5 according to the comparison result.
2. The low dropout linear regulator based on constant power protection according to claim 1, wherein the first voltage detection unit comprises MOS transistors NM1, NM2, NM3, NM4, NM5, NM6, PM1, PM2, PM3, PM4 and resistors R1, R2, R3, NM1, NM2, NM3, NM4, NM5, NM6 are NMOS transistors, PM1, PM2, PM3, PM4 are PMOS transistors; wherein:
the resistor R1 is connected with a power supply voltage VDD;
the resistor R2 is connected with the output voltage VOUT of the LDO unit;
the resistor R3 is connected with the ground potential;
MOS pipe NM1 and NM2 are connected in a common grid mode to form a first current mirror, MOS pipe NM1 is connected between resistor R1 and the ground potential, and MOS pipe NM2 is connected between PM1 and the ground potential;
MOS pipe PM1 and PM2 are connected in a common grid mode to form a second current mirror, MOS pipe PM1 is connected between power supply voltage VDD and MOS pipe NM2, and MOS pipe PM2 is connected between power supply voltage VDD and MOS pipe NM 3;
MOS pipe NM3 and NM6 are connected in a common grid mode to form a third current mirror, MOS pipe NM3 is connected between MOS pipe PM2 and the ground potential, and MOS pipe NM6 is connected between MOS pipe PM3 and the ground potential;
MOS transistor NM4 and NM5 are connected in a common gate mode to form a fourth current mirror, MOS transistor NM4 is connected between the gate of NM3 and the ground potential, and NM5 is connected between resistor R2 and the ground potential;
MOS pipe PM3 and PM4 are connected in a common gate mode to form a fifth current mirror, MOS pipe PM3 is connected between power supply voltage VDD and MOS pipe NM6, and MOS pipe PM4 is connected between power supply voltage VDD and resistor R3.
3. The low dropout linear regulator according to claim 2, wherein the first voltage V1 output by the first voltage detection unit is a voltage across a resistor R3, and the first voltage V1 ═ IR3 ═ R3 ═ (IR1-IR2) — R3, wherein IR1, IR2, and IR3 are currents flowing through resistors R1, R2, and R3, respectively.
4. The low dropout regulator according to claim 3, wherein the first voltage detecting unit comprises:
wherein, the size ratio of NM1 and NM2, the size ratio of NM3 and NM6, the size ratio of NM4 and NM5, the size ratio of PM1 and PM2, and the size ratio of PM3 and PM4 are all 1, VGSNM1 and VGSNM5 are the gate-source voltage difference of NM1 and NM5, respectively, and VOUT is less than VDD.
5. The low dropout regulator according to claim 4, wherein the first voltage detecting unit has the same gate-source voltage difference between NM1 and NM5, the resistances of the resistors R1, R2, and R3 are the same, and the first voltage V1 output by the first voltage detecting unit is VDD-VOUT.
6. The low dropout regulator according to claim 1, wherein the second voltage detection unit comprises a MOS transistor MS and a resistor R4, wherein the MOS transistor MS and the MOS transistor MP are both PMOS transistors, and the MOS transistor MS and the MOS transistor MP are connected in common gate, the MOS transistor MS is connected to a power voltage VDD and the resistor R4, and the resistor R4 is connected to ground potential.
7. The low dropout regulator according to claim 6, wherein in the second voltage detecting unit, the size ratio of MS to MP is 1: n, the current Isen flowing through the MOS tube MS is as follows:
8. the low dropout regulator according to claim 7, wherein the second voltage V2 outputted from the second voltage detecting unit is a voltage across a resistor R4, and the second voltage V2 is:
9. the low dropout regulator according to claim 1, wherein the MOS transistor PM5 in the constant power protection unit is a PMOS transistor, the gate of the MOS transistor PM5 is connected to the output terminal of the analog multiplier, the source is connected to the supply voltage VDD, and the drain is connected to the output terminal of the error amplifier AMP.
10. The low dropout regulator according to claim 9, wherein the constant power protection unit comprises:
in a first state, when Vp is V1 × V2> Vrefp, the MOS transistor PM5 is turned on, the MOS transistor MP is turned off, and the LDO unit does not operate;
in the second state, when Vp is V1 × V2< Vrefp, the MOS transistor PM5 is turned off, the MOS transistor MP is not controlled by the MOS transistor PM5, and the LDO unit operates normally.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114740947A (en) * | 2022-04-26 | 2022-07-12 | 思瑞浦微电子科技（苏州）股份有限公司 | LDO (low dropout regulator) -based dynamic current response circuit, dynamic current control method and chip |
| CN114995581A (en) * | 2022-05-18 | 2022-09-02 | 珠海全志科技股份有限公司 | Power detection circuit and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114740947A (en) * | 2022-04-26 | 2022-07-12 | 思瑞浦微电子科技（苏州）股份有限公司 | LDO (low dropout regulator) -based dynamic current response circuit, dynamic current control method and chip |
| CN114740947B (en) * | 2022-04-26 | 2023-10-20 | 思瑞浦微电子科技（苏州）股份有限公司 | LDO-based dynamic current response circuit, dynamic current control method and chip |
| CN114995581A (en) * | 2022-05-18 | 2022-09-02 | 珠海全志科技股份有限公司 | Power detection circuit and electronic equipment |
| CN114995581B (en) * | 2022-05-18 | 2023-12-01 | 珠海全志科技股份有限公司 | Power detection circuit and electronic equipment |
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