KR20010083708A - Zero-crossing detection circuit - Google Patents

Abstract

PURPOSE: A circuit for detecting a zero-crossing is provided to gain a digital output wave according to an analog input wave by changing a threshold voltage in case that an input noise level is high. CONSTITUTION: A first threshold voltage control unit(22), second threshold voltage(23), and an output circuit unit(24) control a threshold voltage in order to control an amplifying ratio of a differential amplifying unit(21). A current supplying unit(25) supplies a current for the operation of the differential amplifying unit(21), the first and second threshold voltage control unit(22,23), and the output circuit unit(24). The first threshold voltage control unit(22) is composed of a first transistor(PM1) connected to a source and a power voltage end(Vdd). The first transistor(PM1) is a PMOS transistor. The differential amplifying unit(21) is composed of a second transistor(PM2), a third transistor(NM1), a fourth transistor(PM3), and a fifth transistor(NM2). The output circuit unit(24) is provided with an eighth transistor(PM4) and a ninth transistor(NM5). The current supplying unit(25) is composed of a tenth transistor(PM5), an eleventh transistor(NM6), a twelfth transistor(PM6), and a thirteenth transistor(NM7).

Description

ZERO-CROSSING DETECTION CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a zero-crossing sensing circuit capable of obtaining a digital signal synchronized with an analog input by varying a threshold voltage according to the noise level of the analog input voltage.

Hereinafter, a zero-crossing sensing circuit according to the prior art will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a zero-crossing sensing circuit according to the related art.

As shown in FIG. 1, a CMOS type second is connected between a first PMOS transistor PM1 that is a current source connected to a power supply voltage terminal Vdd, and a drain and a ground terminal of the first PMOS transistor PM1. The PMOS transistor PM2 and the first NMOS transistor NM1 are connected to each other, the PMOS transistor PM2 and the first NMOS transistor NM1 are connected in parallel, and the first PMOS transistor ( The third PMOS transistor PM3 and the second NMOS transistor NM2 of the CMOS type are connected between the drain of the PM1 and the ground terminal Vss, and the first NMOS transistor NM1 and the second NMOS are connected. The transistor NM2 has gates connected to each other. The ground voltage Vss is applied to the gate of the second PMOS transistor PM2, and the input voltage Vi is applied to the gate of the third PMOS transistor PM3. A third NMOS transistor NM3 controlled by the source voltage of the third PMOS transistor PM3 and having a drain connected to the ground terminal Vss is configured, and a source and a power supply of the third NMOS transistor NM3. The fourth PMOS transistor PM4 is connected between the voltage terminal Vdd and the gate is connected to the gate of the first PMOS transistor PM1.

The operation of the conventional zero-crossing sensing circuit is as follows.

When the input voltage applied to the gate of the third PMOS transistor PM3 is greater than the ground voltage, the Vgs of the second PMOS transistor PM2 is greater than the Vgs of the third PMOS transistor PM3, and thus, the first voltage. The current output through the PMOS transistor PM1 flows through the second PMOS transistor PM2.

Therefore, since the third NMOS transistor NM3 is turned off, the power supply voltage Vdd flowing through the fourth PMOS transistor PM4 is represented by the output Vo.

On the contrary, when the input voltage applied to the gate of the third PMOS transistor PM3 is smaller than the ground voltage, the Vgs of the third PMOS transistor PM3 is larger than the Vgs of the second PMOS transistor PM2. Therefore, the current output from the first PMOS transistor PM1 flows through the third PMOS transistor PM3.

Accordingly, the third NMOS transistor NM3 is turned on so that the output Vo is represented by the ground voltage Vss.

Such a conventional zero-crossing sensing circuit has the following problems.

As the noise level with the input voltage increases, the digital waveform in the zero-cross portion may bounc or glitch, resulting in unstable detection operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and provides a zero-crossing sensing circuit capable of obtaining a stable digital signal synchronized with an analog input by varying the threshold voltage according to the noise level of the input voltage. The purpose is to provide.

1 is a block diagram of a zero-crossing detection circuit according to the prior art.

2 is a block diagram of a zero-crossing detection circuit according to the present invention.

Explanation of symbols for main parts of the drawings

21: differential amplifier 22,23: first and second threshold voltage adjusting unit

24: output circuit portion 25: current supply portion

The zero-crossing detection circuit of the present invention for achieving the above object is a differential amplifier for differentially amplifying the input analog signal, and the first and second threshold voltage control for adjusting the threshold voltage for gain control of the differential amplifier And a current supply unit for outputting a digital signal corresponding to the adjusted threshold voltage, and a current supply unit for supplying current for operation of the differential amplifier, the first and second threshold voltage regulators, and the output circuit unit. It is composed.

Hereinafter, the zero-crossing sensing circuit of the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram illustrating a zero-crossing sensing circuit of the present invention.

As shown in FIG. 2, the differential amplifier 21, the first threshold voltage controller 22 and the second threshold voltage controller 22 for adjusting the threshold voltage for controlling the amplification ratio of the differential amplifier 21 ( 23 and a current supply unit for supplying current for the operation of the output circuit section 24, the differential amplifier 21, the first and second threshold voltage adjusting sections 22 and 23, and the output circuit section 24 ( 25).

Here, the first threshold voltage controller 22 includes a first transistor PM1 having a source connected to a power supply voltage terminal Vdd, and the first transistor PM1 is a PMOS transistor.

The differential amplifier 21 includes a second transistor PM2 and a third transistor NM1 connected in series between a drain of the first transistor PM1 and a ground terminal Vss, and the second transistor PM2. And a fourth transistor PM3 and a fifth transistor NM2 connected in parallel to the third transistor NM1 and serially connected between the drain of the first transistor PM1 and the ground terminal Vss. .

Here, the second and third transistors PM2 and NM1 are PMOS transistors, and the fourth and fifth transistors NM2 are NMOS transistors.

The second threshold voltage adjusting unit 23 has a gate connected to the gate of the third transistor NM1, a source connected to the ground terminal Vss, and a drain connected to the drain of the fourth transistor PM3. A transistor NM3, a seventh transistor NM4 having a gate connected to the gate of the fifth transistor NM2, a source connected to a ground terminal Vss, and a drain connected to a drain of the second transistor PM2. It consists of.

The sixth and seventh transistors NM3 and NM4 are NMOS transistors.

The output circuit unit 24 includes an eighth transistor PM4 and a ninth transistor NM5 connected in series between the power supply voltage terminal Vdd and the ground terminal Vss. The ninth transistor NM5 is controlled by the drain voltage of the fourth transistor PM3, the eighth transistor PM4 is a PMOS transistor, and the ninth transistor NM5 is an NMOS transistor.

The current supply unit 25 is connected between a tenth transistor PM5 having a source connected to a power supply voltage terminal Vdd and having a drain and a gate in common, and a drain and ground terminal Vss of the tenth transistor PM5. And a twelfth transistor NM6 controlled by a gate input signal, a source connected between a power supply voltage terminal Vdd, a drain and a gate connected in common, and a twelfth transistor PM6; The thirteenth transistor NM7 is connected between the drain and the ground terminal Vss and controlled by the drain voltage of the second transistor PM2.

Here, the tenth and twelfth transistors PM5 and PM6 are PMOS transistors, and the eleventh and thirteenth transistors NM6 and NM7 are NMOS transistors.

Referring to the operation of the zero-crossing detection circuit of the present invention configured as described above are as follows.

First, since the gate of the second transistor PM2 is connected to the ground terminal Vss, the gate of the second transistor PM2 remains turned on. At this time, when a positive voltage (+) higher than the threshold voltage is applied to the gate of the fourth transistor PM3, the fourth transistor PM3 maintains a turn-off state, and the drain voltage thereof becomes a low level.

Therefore, the fifth transistor NM2 whose ON / OFF is determined by the drain voltage of the fourth transistor PM3 is maintained in the OFF state, and thus the power supply voltage Vdd is output to the output terminal Vo.

In this case, the threshold voltage of the fourth transistor PM3 may be represented by the following equation.

Here, I is a source current supplied through the first transistor PM1, β is a transistor size ratio of the third transistor NM1 and the fifth transistor NM2, and βin is a second transistor ( PM2) and the transconductance of the fourth transistor PM3.

Therefore, Vth 로부터 from Equation 1 Therefore, the Vth of the fourth transistor PM3 can be varied by adjusting the size of the first transistor PM1.

In addition, the threshold voltage Vth of the fourth transistor PM3 and the second transistor PM2 may be adjusted by adjusting the β values of the sixth transistor NM3 and the seventh transistor NM4.

As such, the threshold voltage of the fourth transistor PM3 is adjusted by adjusting the size of the first transistor PM1 and the β values of the sixth and seventh NMOS transistors NM3 and NM4. The final output Vo waveform appears in response to the change in the threshold voltage of the transistor PM3.

As described above, the zero-crossing detection circuit of the present invention can obtain a digital output waveform according to the analog input waveform by varying the threshold voltage Vth when the input noise level is large.

Claims (6)

A differential amplifier for differentially amplifying the input analog signal, First and second threshold voltage adjusting units configured to adjust threshold voltages for controlling gain of the differential amplifier; An output circuit unit for outputting a digital signal corresponding to the adjusted threshold voltage; And a current supply unit for supplying current for the operation of the differential amplifier, the first and second threshold voltage adjusting units, and the output circuit unit. The zero-crossing sensing circuit of claim 1, wherein the first threshold voltage adjusting unit comprises a first PMOS transistor having a source connected to a power supply voltage terminal. 2. The display device of claim 1, wherein the differential amplifier comprises a second transistor PM2 and a third transistor NM1 connected in series between a drain of the first PMOS transistor PM1 and a ground terminal Vss. A fourth transistor PM3 and a fifth transistor NM2 connected in parallel to the transistor PM2 and the third transistor NM1 and serially connected between the drain of the first transistor PM1 and the ground terminal Vss. Zero-crossing detection circuit, characterized in that consisting of. The second threshold voltage control unit of claim 1, wherein a gate is connected to a gate of the third transistor NM1, a source is connected to a ground terminal Vss, and a drain is connected to a drain of the fourth transistor PM3. A sixth transistor NM3, a gate connected to a gate of the fifth transistor NM2, a source connected to a ground terminal Vss, and a drain connected to a drain of the second transistor PM2. Zero-crossing sensing circuit, characterized in that consisting of (NM4). The zero-crossing device of claim 1, wherein the output circuit unit comprises an eighth transistor PM4 and a ninth transistor NM5 connected in series between a power supply voltage terminal Vdd and a ground terminal Vss. Sensing circuit. The current supply unit of claim 1, wherein the current supply unit includes a tenth transistor PM5 having a source connected to a power supply voltage terminal Vdd, and a drain and a gate connected in common, and a drain and ground terminal Vss of the tenth transistor PM5. An eleventh transistor NM6 connected between and controlled by a gate input signal, a twelfth transistor PM6 having a source connected between a power supply voltage terminal Vdd, and a drain and a gate connected in common, and the twelfth transistor And a thirteenth transistor (NM7) connected between the drain of the PM6 and the ground terminal (Vss) and controlled by the drain voltage of the second transistor (PM2).