CN114978073A - Amplifying circuit, detection chip and wearable equipment - Google Patents
Amplifying circuit, detection chip and wearable equipment Download PDFInfo
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- CN114978073A CN114978073A CN202210540297.5A CN202210540297A CN114978073A CN 114978073 A CN114978073 A CN 114978073A CN 202210540297 A CN202210540297 A CN 202210540297A CN 114978073 A CN114978073 A CN 114978073A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/30—Input circuits therefor
- A61B5/307—Input circuits therefor specially adapted for particular uses
- A61B5/308—Input circuits therefor specially adapted for particular uses for electrocardiography [ECG]
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/316—Modalities, i.e. specific diagnostic methods
- A61B5/318—Heart-related electrical modalities, e.g. electrocardiography [ECG]
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The application is suitable for the technical field of electronic circuits, and provides an amplifying circuit, a detection chip and wearable equipment. The first logic module in the amplifying circuit is used for receiving the reference voltage and a first signal in the target differential signal and transmitting the first signal to the current generating module. The second logic module is used for receiving the reference voltage and a second signal in the target differential signal and transmitting the second signal to the current generation module. When the first signal and the second signal have direct current deviation, the current generation module is used for generating deviation current according to the direct current deviation, and the deviation current enables the first logic module to generate first direct current voltage and enables the second logic module to generate second direct current voltage. The voltage regulation module is used for collecting the first direct current voltage and the second direct current voltage, and regulating the first direct current voltage and the second direct current voltage to enable the first direct current voltage and the second direct current voltage to be equal to the reference voltage. The application provides an amplifying circuit which can restrain direct current deviation in a target differential signal.
Description
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to an amplifying circuit, a detection chip and wearable equipment.
Background
Along with the improvement of attention of people to self health, wearable devices such as smart bracelets have been widely used. The electrocardiogram signal is an important reference for the health condition of a human body, and the detection of the electrocardiogram signal is an important function of the wearable device. The basic working principle of detecting electrocardiogram signals at present is to collect differential signals through differential electrodes, transmit the collected differential signals to an electrocardiogram signal detection chip, and amplify, filter and quantize electric signals by the electrocardiogram signal detection chip. However, the following problems exist in the treatment process: after the differential electrode is contacted with a human body, the differential signal is transmitted to the input end of an amplifier in the electrocardiogram signal detection chip, and the output of the amplifier is saturated due to the direct current deviation in the differential signal, so that a useful alternating current small signal cannot be amplified.
Disclosure of Invention
The embodiment of the application provides an amplifying circuit, a detection chip and wearable equipment, and can solve the problems that the output of an amplifier is saturated and useful alternating current small signals cannot be amplified due to the fact that direct current deviation exists in collected differential signals in the wearable equipment.
In a first aspect, an embodiment of the present application provides an amplifying circuit, which includes a first logic module, a second logic module, a current generating module, and a voltage regulating module; the current generation module is electrically connected with the first logic module and the second logic module respectively, and the voltage regulation module is electrically connected with the first logic module and the second logic module respectively;
the first logic module is used for receiving a reference voltage and a first signal in a target differential signal and transmitting the first signal to the current generation module; the second logic module is configured to receive a second signal of the reference voltage and the target differential signal and transmit the second signal to the current generation module;
when the first signal and the second signal have a direct current deviation, the current generation module is used for generating a deviation current according to the direct current deviation, and the deviation current enables the first logic module to generate a first direct current voltage and enables the second logic module to generate a second direct current voltage;
the voltage regulation module is used for collecting the first direct-current voltage and the second direct-current voltage, and regulating the first direct-current voltage and the second direct-current voltage to enable the first direct-current voltage and the second direct-current voltage to be equal to the reference voltage.
In one possible implementation manner of the first aspect, the first logic module includes a first operational amplifier, a first field effect transistor, a first current source, a second current source, and a first resistor;
the positive electrode of the first current source is used for being electrically connected with the positive electrode of a first power supply, the non-inverting input end of the first operational amplifier is used for receiving the first signal, the inverting input end of the first operational amplifier is respectively and electrically connected with the source electrode of the first field effect transistor, the negative electrode of the first current source and the current generation module, the output end of the first operational amplifier is electrically connected with the grid electrode of the first field effect transistor, the drain electrode of the first field effect transistor is respectively and electrically connected with the first end of the first resistor, the positive electrode of the second current source and the voltage regulation module, the second end of the first resistor is used for receiving the reference voltage, and the negative electrode of the second current source is used for being electrically connected with the negative electrode of the first power supply; the current provided by the first current source is equal to the current provided by the second current source in magnitude and direction.
In one possible implementation manner of the first aspect, the second logic module includes a second operational amplifier, a second field effect transistor, a third current source, a fourth current source, and a second resistor;
the positive electrode of the third current source is used for being electrically connected with the positive electrode of a second power supply, the non-inverting input end of the second operational amplifier is used for receiving the second signal, the inverting input end of the second operational amplifier is respectively electrically connected with the source electrode of the second field effect transistor, the negative electrode of the third current source and the current generation module, the output end of the second operational amplifier is electrically connected with the grid electrode of the second field effect transistor, the drain electrode of the second field effect transistor is respectively electrically connected with the first end of the second resistor, the positive electrode of the fourth current source and the voltage regulation module, the second end of the second resistor is used for receiving the reference voltage, and the negative electrode of the fourth current source is used for being electrically connected with the negative electrode of the second power supply; the current provided by the third current source and the current provided by the fourth current source are equal in magnitude and same in direction as the current provided by the first current source.
In a possible implementation manner of the first aspect, the first field effect transistor and the second field effect transistor are P-type field effect transistors, the first current source and the third current source are P-type current sources, and the second current source and the fourth current source are N-type current sources.
In one possible implementation manner of the first aspect, the first logic module includes a third operational amplifier, a third field effect transistor, a fifth current source, a sixth current source, a first current mirror, and a third resistor;
the positive electrode of the fifth current source is used for being electrically connected with the positive electrode of the first power supply, the non-inverting input end of the third operational amplifier is used for receiving the first signal, the inverting input end of the third operational amplifier is respectively and electrically connected with the source electrode of the third field effect transistor, the negative electrode of the fifth current source and the current generation module, the output end of the third operational amplifier is electrically connected with the grid electrode of the third field effect transistor, the drain electrode of the third field effect transistor is electrically connected with the input end of the first current mirror, the output end of the first current mirror is respectively and electrically connected with the first end of the third resistor, the negative electrode of the sixth current source and the voltage regulating module, the common end of the first current mirror is used for being electrically connected with the negative pole of the first power supply, the second end of the third resistor is used for receiving the reference voltage, and the positive pole of the sixth current source is used for being electrically connected with the positive pole of the first power supply; the current provided by the fifth current source is equal to the current provided by the sixth current source in magnitude and direction.
In a possible implementation manner of the first aspect, the second logic module includes a fourth operational amplifier, a fourth field effect transistor, a seventh current source, an eighth current source, a second current mirror, and a fourth resistor;
the positive electrode of the seventh current source is used for being electrically connected with the positive electrode of a second power supply, the non-inverting input end of the fourth operational amplifier is used for receiving the second signal, the inverting input end of the fourth operational amplifier is respectively electrically connected with the source electrode of the fourth field effect transistor, the negative electrode of the seventh current source and the current generation module, the output end of the fourth operational amplifier is electrically connected with the gate electrode of the fourth field effect transistor, the drain electrode of the fourth field effect transistor is electrically connected with the input end of the second current mirror, the output end of the second current mirror is respectively electrically connected with the first end of the fourth resistor, the negative electrode of the eighth current source and the voltage regulation module, the common output end of the second current mirror is used for being electrically connected with the negative electrode of the second power supply, and the second end of the fourth resistor is used for receiving the reference voltage, the positive electrode of the eighth current source is used for being electrically connected with the positive electrode of the second power supply; the current provided by the seventh current source and the current provided by the eighth current source are equal in magnitude and same in direction as the current provided by the fifth current source.
In a possible implementation manner of the first aspect, the current generation module includes a fifth resistor; the first end of the fifth resistor is electrically connected with the first logic module, and the second end of the fifth resistor is electrically connected with the second logic module.
In one possible implementation manner of the first aspect, the voltage regulation module includes a first transconductance unit, a second transconductance unit, and a first capacitor;
the positive input end of the first transconductance unit is electrically connected with the positive output ends of the second logic module and the second transconductance unit, the negative input end of the first transconductance unit is electrically connected with the negative output ends of the first logic module and the second transconductance unit, the positive output end of the first transconductance unit is electrically connected with the positive electrode of the first capacitor and the negative input end of the second transconductance unit, and the negative output end of the first transconductance unit is electrically connected with the negative electrode of the first capacitor and the positive input end of the second transconductance unit.
In a second aspect, an embodiment of the present application provides a detection chip, including the amplification circuit described in any one of the first aspects.
In a third aspect, an embodiment of the present application provides a wearable device, including the detection chip of the second aspect.
Compared with the prior art, the embodiment of the application has the beneficial effects that:
the embodiment of the application provides an amplifying circuit, which comprises a first logic module, a second logic module, a current generation module and a voltage regulation module. The current generation module is electrically connected with the first logic module and the second logic module respectively, and the voltage regulation module is electrically connected with the first logic module and the second logic module respectively. The first logic module receives a reference voltage and a first signal in the target differential signal and transmits the first signal to the current generation module. The second logic module receives the reference voltage and a second signal of the target differential signal and transmits the second signal to the current generation module. When a first signal and a second signal in the acquired target differential signal have direct current deviation, a current generation module generates deviation current according to the direct current deviation, the deviation current enables a first logic module to generate a first direct current voltage, a second logic module to generate a second direct current voltage, the first direct current voltage and the second direct current voltage can have deviation due to the existence of the direct current deviation, as long as the first direct current voltage and the second direct current voltage have deviation, a voltage regulation module can always regulate the first direct current voltage and the second direct current voltage, and finally the first direct current voltage and the second direct current voltage are kept equal to a reference voltage, namely the deviation between the first direct current voltage and the second direct current voltage is eliminated, so the direct current deviation between the first signal and the second signal in the target differential signal is inhibited, and the output of an amplifying circuit can not be saturated, useful ac small signals can be amplified. When the first direct-current voltage and the second direct-current voltage are equal to the reference voltage, the current generation module generates a differential current according to the first signal and the second signal, the differential current enables the first logic module to generate a first voltage in the differential voltage, and enables the second logic module to generate a second voltage in the differential voltage, namely the alternating-current small signal in the target differential signal is amplified.
It is to be understood that, for the beneficial effects of the second aspect to the third aspect, reference may be made to the relevant description in the first aspect, and details are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic block diagram of an amplifying circuit provided by an embodiment of the present application;
fig. 2 is a circuit connection diagram of an amplifying circuit according to an embodiment of the present disclosure;
fig. 3 is a circuit connection diagram of an amplifying circuit according to another embodiment of the present application;
fig. 4 is a system equivalent diagram of an amplifying circuit provided in an embodiment of the present application;
FIG. 5 is a schematic diagram of a differential mode response of an amplifying circuit according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a common mode rejection characteristic of an amplifying circuit according to an embodiment of the present disclosure.
In the figure: 100. a first logic module; 200. a current generation module; 300. a second logic module; 400. and a voltage regulation module.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in the specification of this application and the appended claims, the term "if" may be interpreted contextually as "when …" or "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
Wearable equipment such as intelligent bracelet has been used widely, is applied to wearable equipment's such as intelligent bracelet electrocardiogram signal detection chip, should guarantee that electrocardiogram signal detection chip does not have the interchange small-signal of the state of saturation to the difference signal of gathering under the amplifier and enlargies. The existing amplifier adopts a fully differential structure consisting of double operational amplifiers, but the structure has no inhibiting effect on direct current deviation existing in differential signals, and when the direct current deviation is small, the amplifier cannot be saturated. When the dc offset is large, the output of the amplifier is saturated, and the ac small signal in the differential signal cannot be amplified.
In order to solve the above problem, as shown in fig. 1, an embodiment of the present application provides an amplifying circuit, which includes a first logic module 100, a second logic module 300, a current generating module 200, and a voltage regulating module 400. The current generating module 200 is electrically connected to the first logic module 100 and the second logic module 300, respectively. The voltage regulation module 400 is electrically connected to the first logic module 100 and the second logic module 300, respectively.
Specifically, the first logic module 100 receives the reference voltage and a first signal of the target differential signal, and transmits the first signal to the current generation module 200. The second logic module 300 receives the reference voltage and a second signal of the target differential signal and transmits the second signal to the current generation module 200.
When there is a dc offset between the first signal and the second signal, the current generation module 200 generates an offset current according to the dc offset. The offset current causes the first logic block 100 to generate a first dc voltage and the second logic block 300 to generate a second dc voltage. Because the dc offset exists, the first dc voltage and the second dc voltage also exist offset, and in order to eliminate the offset between the first dc voltage and the second dc voltage, the voltage adjusting module 400 collects the first dc voltage and the second dc voltage, and adjusts the first dc voltage and the second dc voltage, so that the first dc voltage and the second dc voltage are kept equal to the reference voltage, that is, the offset between the first dc voltage and the second dc voltage is eliminated, and therefore, the dc offset between the first signal and the second signal in the target differential signal is suppressed, the output of the amplifying circuit is not saturated, and a useful ac small signal can be amplified.
When the first dc voltage and the second dc voltage are equal to the reference voltage, the current generating module 200 generates a differential current according to the first signal and the second signal, and the differential current enables the first logic module 100 to generate the first voltage of the differential voltage and the second logic module 300 to generate the second voltage of the differential voltage, that is, amplifies the ac small signal of the target differential signal.
Note that the dc offset is a dc voltage difference between the first signal and the second signal.
As shown in fig. 2, the first logic block 100 includes a first operational amplifier AMP1, a first field effect transistor M1, a first current source I1, a second current source I2, and a first resistor R1. The positive pole of the first current source I1 is used to be electrically connected to the positive pole of the first power supply, i.e. to the voltage VDD 1. The non-inverting input terminal of the first operational amplifier AMP1 is used for receiving the first signal V IP . The inverting input terminal of the first operational amplifier AMP1 is electrically connected to the source of the first field effect transistor M1, the cathode of the first current source I1, and the current generating module 200, respectively. The output terminal of the first operational amplifier AMP1 is electrically connected to the gate of the first field effect transistor M1. The drain of the first fet M1 is electrically connected to the first terminal of the first resistor R1, the positive terminal of the second current source I2, and the voltage regulation module 400, respectively. The second end of the first resistor R1 is used for receiving a reference voltage V REF . The cathode of the second current source I2 is electrically connected to the cathode of the first power source, i.e., to the voltage VSS 1. The current provided by the first current source I1 is equal in magnitude and same in direction as the current provided by the second current source I2.
Specifically, the non-inverting input terminal of the first operational amplifier AMP1 receives the first signal V IP Due to the action of the operational amplifier, the source of the first field effect transistor M1 is locked, so that the source of the first field effect transistor M1 tracks the first signal V IP Further, one end of the current generation module 200 receives the first signal V IP 。
When the first logic module 100 is analyzed independently, the second terminal of the first resistor R1 receives the reference voltage V REF . The non-inverting input terminal of the first operational amplifier AMP1 receives the first signal V IP In order to make the first fet M1 work normally, the source voltage of the first fet M1 should be greater than the drain voltage, so that the first fet is only used when the first signal V IP Greater than a reference voltage V REF The first fet M1 will not operate normally. When the first fet M1 works normally, the current provided by the first current source I1 flows out through the first fet M1, and since the current provided by the first current source I1 is equal to the current provided by the second current source I2 in magnitude and direction, no current is generated in the first resistor R1, and the voltage output from the first end of the first resistor R1 is the reference voltage V REF 。
As shown in fig. 2, the second logic block 300 includes a second operational amplifier AMP2, a second field effect transistor M2, a third current source I3, a fourth current source I4, and a second resistor R2. The anode of the third current source I3 is used to be electrically connected to the anode of the second power supply, i.e. to the voltage VDD 2. The non-inverting input terminal of the second operational amplifier AMP2 is used for receiving the second signal V IN . The inverting input terminal of the second operational amplifier AMP2 is electrically connected to the source of the second field effect transistor M2, the cathode of the third current source I3, and the current generating module 200, respectively. The output terminal of the second operational amplifier AMP2 is electrically connected to the gate of the second field effect transistor M2. The drain of the second fet M2 is electrically connected to the first terminal of the second resistor R2, the anode of the fourth current source I4, and the voltage regulating module 400, respectively. The second end of the second resistor R2 is used for receiving the reference voltage V REF . The cathode of the fourth current source I4 is used to be electrically connected to the cathode of the second power source, i.e. to the voltage VSS 2. The current provided by the third current source I3 and the current provided by the fourth current source I4 are equal in magnitude and same in direction as the current provided by the first current source I1.
Specifically, the non-inverting input terminal of the second operational amplifier AMP2 receives the second signal V IN The source of the second FET M2 is driven by the operational amplifierLocking the source of the second FET M2 to track the second signal V IN And the other end of the current generation module 200 receives the second signal V IN 。
When the second logic module 300 is analyzed independently, the second terminal of the second resistor R2 receives the reference voltage V REF . The non-inverting input terminal of the second operational amplifier AMP2 receives the second signal V IN In order to make the second fet M2 work normally, the source voltage of the second fet M2 should be greater than the drain voltage, so that only when the second signal V is applied IN Greater than a reference voltage V REF The second fet M2 will not operate normally. When the second fet M2 works normally, the current provided by the third current source I3 flows out through the second fet M2, and since the current provided by the third current source I3 and the current provided by the fourth current source I4 are equal in magnitude and same in direction as the current provided by the first current source I1, no current is generated in the second resistor R2, and the voltage output from the first end of the second resistor R2 is the reference voltage V REF 。
Illustratively, the first fet M1 and the second fet M2 are P-type fets. The first current source I1 and the third current source I3 are P-type current sources, and the second current source I2 and the fourth current source I4 are N-type current sources.
It should be noted that the first resistor R1 and the second resistor R2 in the embodiment of the present application are equal. The first power supply and the second power supply in the embodiment of the present application may be the same power supply or may be two different power supplies.
As shown in fig. 3, the first logic block 100 includes a third operational amplifier AMP3, a third field effect transistor M3, a fifth current source I5, a sixth current source I6, a first current mirror CM1, and a third resistor R3. The positive pole of the fifth current source I5 is used to electrically connect with the positive pole of the first power supply, i.e. with VDD 1. The non-inverting input terminal of the third operational amplifier AMP3 is used for receiving the first signal V IP . The inverting input terminal of the third operational amplifier AMP3 is electrically connected to the source of the third field effect transistor M3, the cathode of the fifth current source I5, and the current generating module 200, respectively. The output terminal of the third operational amplifier AMP3 is electrically connected to the gate of the third field effect transistor M3. Third field effect transistorThe drain of M3 is electrically connected to the input of the first current mirror CM 1. The output terminal of the first current mirror CM1 is electrically connected to the first terminal of the third resistor R3, the negative terminal of the sixth current source I6, and the voltage regulating module 400, respectively. The common terminal of the first current mirror CM1 is for electrical connection with the negative terminal of the first power supply, i.e., with the voltage VSS 1. The second end of the third resistor R3 is used for receiving the reference voltage V REF . The positive pole of the sixth current source I6 is used to be electrically connected to the positive pole of the first power supply, i.e. to the voltage VDD 1. The current supplied by the fifth current source I5 is equal in magnitude and same in direction as the current supplied by the sixth current source I6.
Specifically, the non-inverting input terminal of the third operational amplifier AMP3 receives the first signal V IP The source of the third fet M3 is locked due to the operational amplifier, so that the source of the third fet M3 tracks the first signal V IP And further one end of the current generation module 200 receives the first signal V IP 。
When the first logic block 100 is analyzed independently, the non-inverting input terminal of the third operational amplifier AMP3 receives the first signal V IP Due to the first signal V IP Certainly greater than the voltage VSS1, the third FET M3 can work normally, and the circuit structure is not influenced by the first signal V IP Must be greater than the reference voltage V REF The limit of (2). When the third fet M3 operates normally, the current provided by the fifth current source I5 flows out through the third fet M3 and then is copied through the first current mirror CM1, when the ratio of the first current mirror CM1 is 1: at 1, the right current of the first current mirror CM1 is the same as the left current, since the current provided by the fifth current source I5 is the same as the current provided by the sixth current source I6, no current flows through the third resistor R3, and the voltage output from the first end of the third resistor R3 is the reference voltage V REF 。
Illustratively, the third fet M3 is a P-type fet.
As shown in fig. 3, the second logic block 300 includes a fourth operational amplifier AMP4, a fourth field effect transistor M4, a seventh current source I7, an eighth current source I8, a second current mirror CM2, and a fourth resistor R4. The positive pole of the seventh current source I7 is used for connecting with the second current sourceThe positive pole of the power supply is electrically connected, i.e., to voltage VDD 2. The non-inverting input terminal of the fourth operational amplifier AMP4 is for receiving the second signal V IN . An inverting input terminal of the fourth operational amplifier AMP4 is electrically connected to the source of the fourth field effect transistor M4, the cathode of the seventh current source I7, and the current generating module 200, respectively. An output terminal of the fourth operational amplifier AMP4 is electrically connected to a gate of the fourth field effect transistor M4. The drain of the fourth fet M4 is electrically connected to the input of the second current mirror CM 2. The output terminal of the second current mirror CM2 is electrically connected to the first terminal of the fourth resistor R4, the negative terminal of the eighth current source I8, and the voltage regulating module 400, respectively. The common output terminal of the second current mirror CM2 is for electrical connection to the negative terminal of the second power supply, i.e., to the voltage VSS 2. The second end of the fourth resistor R4 is used for receiving the reference voltage V REF . The anode of the eighth current source I8 is used to be electrically connected to the anode of the second power supply, i.e. to the voltage VDD 2. The current provided by the seventh current source I7 and the current provided by the eighth current source I8 are equal in magnitude and same in direction as the current provided by the fifth current source I5.
Specifically, the non-inverting input terminal of the fourth operational amplifier AMP4 receives the second signal V IN Due to the action of the operational amplifier, the source of the fourth field effect transistor M4 is locked, so that the source of the fourth field effect transistor M4 tracks the second signal V IN And the other end of the current generation module 200 receives the second signal V IN 。
When the second logic module 300 is analyzed independently, the non-inverting input terminal of the fourth operational amplifier AMP4 receives the second signal V IN Due to the second signal V IN The voltage is certainly greater than the VSS2, the fourth field effect transistor M4 can work normally, and the circuit structure is not influenced by the second signal V IN Must be greater than the reference voltage V REF The limit of (2). When the fourth fet M4 operates normally, the current provided by the seventh current source I7 flows out through the fourth fet M4 and then is copied through the second current mirror CM2, when the ratio of the second current mirror CM2 is 1: at 1, the left current and the right current of the second current mirror CM2 are the same, and the current provided by the seventh current source I7, the current provided by the eighth current source I8 and the current provided by the fifth current source I5 are equal in magnitude and directionSimilarly, no current flows through the fourth resistor R4, and the voltage output from the first terminal of the fourth resistor R4 is the reference voltage V REF 。
Illustratively, the fourth fet M4 is a P-fet.
It should be noted that the third resistor R3 and the fourth resistor R4 in the embodiment of the present application are equal.
As shown in fig. 2 and 3, the current generating module 200 includes a fifth resistor R5. A first terminal of the fifth resistor R5 is electrically connected to the first logic block 100. A second terminal of the fifth resistor R5 is electrically connected to the second logic module 300.
Specifically, as shown in fig. 2, a first end of the fifth resistor R5 is electrically connected to the source of the first fet M1 in the first logic block 100. A second terminal of the fifth resistor R5 is electrically connected to the source of the second FET M2 in the second logic block 300.
When the first signal V IP And a second signal V IN When there is a dc offset between the first and second resistors, the dc offset is greater than 0, that is, the dc voltage at the first end of the fifth resistor R5 is greater than the dc voltage at the second end of the fifth resistor R5, so that a dc voltage drop occurs at the two ends of the fifth resistor R5, and an offset current is generated, and the direction of the offset current is from left to right. In conjunction with the above analysis and limitation, since the current provided by the first current source I1 is equal to the current provided by the second current source I2 in magnitude and same direction, and the current provided by the third current source I3 and the current provided by the fourth current source I4 are equal to the current provided by the first current source I1 in magnitude and same direction, when the offset current is generated in the fifth resistor R5, the currents from left to right are generated in the first resistor R1 and the second resistor R2, and therefore a voltage drop is generated in the first resistor R1, so that the first direct voltage output by the first logic module 100 is smaller than the reference voltage V REF . The second resistor R2 also generates a voltage drop, so that the second dc voltage outputted by the second logic module 300 is greater than the reference voltage V REF And a deviation exists between the first direct current voltage and the second direct current voltage, and the existence of the deviation can influence the normal operation of the amplifying circuit. The voltage regulating module 400 can always regulate the first DC voltage and the second DC voltage as long as there is a deviation between the first DC voltage and the second DC voltageThe first direct current voltage and the second direct current voltage are adjusted, and finally the first direct current voltage and the second direct current voltage are kept equal to the reference voltage, namely, the deviation between the first direct current voltage and the second direct current voltage is eliminated, so that the direct current deviation between the first signal and the second signal in the target differential signal is restrained, the output of the amplifying circuit is not saturated, and the useful small alternating current signal can be amplified.
When the first signal V IP And a second signal V IN When there is no dc offset, no dc voltage drop and no offset current are generated in the fifth resistor R5, and the first and second dc voltages and the reference voltage V do not generate an offset current REF Remain equal. When the first DC voltage and the second DC voltage are compared with the reference voltage V REF Remaining equal, the first signal V IP And a second signal V IN A differential current is generated in the fifth resistor R5, assuming that the differential current is (V) IP -V IN ) /R5, the direction of differential current is from left to right. At this time, the current source in fig. 2 is equivalent to an open circuit, so that the currents flowing through the first resistor R1 and the second resistor R2 are both differential currents and the directions of the currents are both from left to right. The voltage drop of the first resistor R1 is (V) IP -V IN ) R1/R5, such that a first voltage V of the differential voltage O1 Less than reference voltage V REF I.e. V O1 ＝V REF -(V IP -V IN ) R1/R5, the voltage drop of the second resistor R2 is (V) IP -V IN ) R2/R5, such that the second voltage V of the differential voltage O2 Greater than a reference voltage V REF I.e. V O2 ＝V REF +(V IP -V IN ) R2/R5, the first resistor R1 is equal to the second resistor R2, so the output AC voltage V is O ＝V O2 -V O1 ＝2(V IP -V IN ) R1/R5, the gain of the amplifier circuit is 2R 1/R5, therefore the output of the amplifier circuit is DC offset V REF Superposed with an AC voltage V O 。
As shown in fig. 2 and 3, the voltage regulating module 400 includes a first transconductance unit G m1 A second transconductance unit G m2 And a first capacitance C1. First transconductance unit G m1 Respectively with the second logic block 300 and the second transconductance cell G m2 Is electrically connected. First transconductance unit G m1 Respectively with the first logic block 100 and the second transconductance cell G m2 Is electrically connected. First transconductance unit G m1 With the positive output terminal of the first capacitor C1 and the positive electrode of the second transconductance unit G, respectively m2 Is electrically connected. First transconductance unit G m1 Respectively with the negative pole of the first capacitor C1 and the second transconductance unit G m2 Is electrically connected to the positive input terminal of the switch.
Specifically, as shown in FIG. 2, the first transconductance unit G m1 Respectively with the first terminal of the second resistor R2 and the second transconductance cell G m2 Is electrically connected. First transconductance unit G m1 Respectively with the first terminal of the first resistor R1 and the second transconductance cell G m2 Is electrically connected. First transconductance unit G m1 With the positive output terminal of the first capacitor C1 and the positive electrode of the second transconductance unit G, respectively m2 Is electrically connected. First transconductance unit G m1 Respectively with the negative pole of the first capacitor C1 and the second transconductance unit G m2 Is electrically connected to the positive input terminal of the switch.
From the above analysis, when the first signal V is detected IP And a second signal V IN When the dc deviation is greater than 0, the first dc voltage and the second dc voltage are also deviated, and the second dc voltage is greater than the first dc voltage. First transconductance unit G m1 Collecting a first direct current voltage and a second direct current voltage, wherein the second direct current voltage is greater than the first direct current voltage, and a first transconductance unit G m1 The positive output terminal outputs current and the negative output terminal inputs current, so that a voltage difference is formed on the first capacitor C1, wherein the voltage difference is positive left and negative right. Then the second transconductance cell G m2 Is less than the voltage at the negative input terminal, so that the second transconductance cell G m2 The positive output terminal outputs current, i.e. a current from right to left is provided for the first resistor R1, and a current from right to left is provided for the second resistor R2, fromThe voltage drop of the first resistor R1 and the voltage drop of the second resistor R2 are adjusted, and finally the deviation between the first direct current voltage and the second direct current voltage is close to 0 and is close to the reference voltage V REF Remain equal.
As shown in fig. 4, the first resistor R1, the second resistor R2 and the voltage regulation module 400 in fig. 2 are removed, and the remaining circuits are represented by a fully differential transconductance unit with a transconductance value G m0 1/R5, the voltage regulation module 400 is then equivalent to an inductance L, L — C1/(G) m1* G m2 ) The amplifier circuit can therefore be represented as a simplified system diagram on the right in fig. 4. The system transfer function may be expressed as
It can be seen that s is 0, i.e. in the dc state, the system transfer function is 0, and the amplifying circuit does not amplify the dc signal, and has a high-pass characteristic. When the frequency is high, the independent variable in the denominator is larger than the direct current quantity, and the function value of the system transfer function is constant and equal to the gain of the amplifying circuit. The pole of the-3 dB bandwidth of the high-pass filter characteristic corresponds to-2R 1/L. In wearable device application for detecting electrocardiosignals, the bandwidth needs to be set to be less than 1Hz, and the first transconductance unit G is considered m1 And a second transconductance cell G m2 The value of (a) requires a large capacitance to realize a large inductance, for example, R1 is 10M Ω, and L is required>3.2MH, first transconductance cell G m1 And a second transconductance cell G m2 Is equal to 0.1 mus, the capacitance of the first capacitor C1, C1>32 nF. Namely, the amplifying circuit uses one off-chip capacitor, and the direct current suppression characteristic of the fully differential signal is realized.
Due to the common 50Hz power frequency interference of a power supply network in the environment. And the human body can always generate a strong 50Hz signal under the coupling action of equivalent capacitance of the power supply line, and the signal is collected by the differential electrode and transmitted to the input end of the amplifier of the wearable device to be reflected as common-mode interference. Therefore, when the wearable device is collecting the differential signal, the common mode signal should be suppressed in addition to suppressing the dc offset existing in the target differential signal. As shown in fig. 2, regardless of the first signal V IP And a second signal V IN Whether there is a DC offset between them, when a common mode signal is input, a first signal V IP And a second signal V IN The voltage across the fifth resistor R5 changes simultaneously with the common mode signal, and no ac current is generated in the fifth resistor R5. Therefore, the output end of the amplifying circuit provided by the embodiment of the application has no common-mode interference signal, and the common-mode interference is well inhibited.
The application carries out simulation verification on the amplifying circuit, the high-pass broadband of the amplifying circuit is set to be 1Hz, the gain is set to be 20 times, the direct-current deviation is set to be 100mV, and a field effect tube is used for replacing a current source. As shown in fig. 5, which is a simulation result of the differential mode response of the amplifying circuit, it can be seen from fig. 5 that the low frequency signal is suppressed, i.e., the amplifying circuit suppresses the dc offset in the target differential signal. The-3 dB bandwidth of the high pass filter is 1Hz and the pass band gain is 26 dB. As shown in fig. 6, the simulation result of the common mode rejection characteristic of the amplifier circuit is shown. It can be seen from fig. 6 that the output rejection to the common mode input at 50Hz is 92dB, and the gain of the target differential signal corresponding to 50Hz is 26dB, so that the common mode rejection ratio CMRR is 118dB @50 Hz.
The embodiment of the application also provides a detection chip which comprises the amplifying circuit.
Specifically, when a direct current deviation exists in the acquired target differential signal, the current generation module in the amplifying circuit generates a deviation current from the direct current deviation, the deviation current enables the first logic module to generate a first direct current voltage and enables the second logic module to generate a second direct current voltage, and due to the existence of the direct current deviation, a deviation exists between the first direct current voltage and the second direct current voltage, as long as a deviation exists between the first direct current voltage and the second direct current voltage, the voltage regulation module can constantly regulate the first direct current voltage and the second direct current voltage, and finally the first direct current voltage and the second direct current voltage are kept equal to a reference voltage, namely the deviation existing between the first direct current voltage and the second direct current voltage is eliminated, so that the direct current deviation between the first signal and the second signal in the target differential signal is inhibited, and the output of the amplifying circuit is not saturated, useful ac small signals can be amplified. When the first direct-current voltage and the second direct-current voltage are equal to the reference voltage, the current generation module generates a differential current according to the first signal and the second signal, the differential current enables the first logic module to generate a first voltage in the differential voltage, and enables the second logic module to generate a second voltage in the differential voltage, namely the alternating-current small signal in the target differential signal is amplified. The amplified signal is transmitted to a detection chip for subsequent processing.
The embodiment of the application also provides wearable equipment, which comprises the detection chip.
The wearable device provided by the embodiment of the application inhibits the direct current deviation between the first signal and the second signal in the target differential signal, so that the output of the amplifying circuit is not saturated, and a useful alternating current small signal can be amplified.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. An amplifying circuit is characterized by comprising a first logic module, a second logic module, a current generation module and a voltage regulation module; the current generation module is electrically connected with the first logic module and the second logic module respectively, and the voltage regulation module is electrically connected with the first logic module and the second logic module respectively;
the first logic module is used for receiving a reference voltage and a first signal in a target differential signal and transmitting the first signal to the current generation module; the second logic module is configured to receive a second signal of the reference voltage and the target differential signal and transmit the second signal to the current generation module;
when the first signal and the second signal have a direct current deviation, the current generation module is used for generating a deviation current according to the direct current deviation, and the deviation current enables the first logic module to generate a first direct current voltage and enables the second logic module to generate a second direct current voltage;
the voltage regulation module is used for collecting the first direct-current voltage and the second direct-current voltage, and regulating the first direct-current voltage and the second direct-current voltage to enable the first direct-current voltage and the second direct-current voltage to be equal to the reference voltage.
2. The amplifying circuit according to claim 1, wherein the first logic block comprises a first operational amplifier, a first field effect transistor, a first current source, a second current source, and a first resistor;
the positive electrode of the first current source is used for being electrically connected with the positive electrode of a first power supply, the non-inverting input end of the first operational amplifier is used for receiving the first signal, the inverting input end of the first operational amplifier is respectively and electrically connected with the source electrode of the first field effect transistor, the negative electrode of the first current source and the current generation module, the output end of the first operational amplifier is electrically connected with the grid electrode of the first field effect transistor, the drain electrode of the first field effect transistor is respectively and electrically connected with the first end of the first resistor, the positive electrode of the second current source and the voltage regulation module, the second end of the first resistor is used for receiving the reference voltage, and the negative electrode of the second current source is used for being electrically connected with the negative electrode of the first power supply; the current provided by the first current source is equal to the current provided by the second current source in magnitude and direction.
3. The amplifying circuit according to claim 2, wherein the second logic block comprises a second operational amplifier, a second field effect transistor, a third current source, a fourth current source, and a second resistor;
the positive electrode of the third current source is used for being electrically connected with the positive electrode of a second power supply, the non-inverting input end of the second operational amplifier is used for receiving the second signal, the inverting input end of the second operational amplifier is respectively electrically connected with the source electrode of the second field effect transistor, the negative electrode of the third current source and the current generation module, the output end of the second operational amplifier is electrically connected with the grid electrode of the second field effect transistor, the drain electrode of the second field effect transistor is respectively electrically connected with the first end of the second resistor, the positive electrode of the fourth current source and the voltage regulation module, the second end of the second resistor is used for receiving the reference voltage, and the negative electrode of the fourth current source is used for being electrically connected with the negative electrode of the second power supply; the current provided by the third current source and the current provided by the fourth current source are equal in magnitude and same in direction as the current provided by the first current source.
4. The amplifier circuit of claim 3, wherein said first and second FETs are P-type FETs, said first and third current sources are P-type current sources, and said second and fourth current sources are N-type current sources.
5. The amplifying circuit according to claim 1, wherein the first logic block comprises a third operational amplifier, a third field effect transistor, a fifth current source, a sixth current source, a first current mirror, and a third resistor;
the positive electrode of the fifth current source is used for being electrically connected with the positive electrode of the first power supply, the non-inverting input end of the third operational amplifier is used for receiving the first signal, the inverting input end of the third operational amplifier is respectively and electrically connected with the source electrode of the third field effect transistor, the negative electrode of the fifth current source and the current generation module, the output end of the third operational amplifier is electrically connected with the grid electrode of the third field effect transistor, the drain electrode of the third field effect transistor is electrically connected with the input end of the first current mirror, the output end of the first current mirror is respectively and electrically connected with the first end of the third resistor, the negative electrode of the sixth current source and the voltage regulating module, the common end of the first current mirror is used for being electrically connected with the negative pole of the first power supply, the second end of the third resistor is used for receiving the reference voltage, and the positive pole of the sixth current source is used for being electrically connected with the positive pole of the first power supply; the current provided by the fifth current source is equal to the current provided by the sixth current source in magnitude and direction.
6. The amplifying circuit according to claim 5, wherein the second logic block comprises a fourth operational amplifier, a fourth field effect transistor, a seventh current source, an eighth current source, a second current mirror, and a fourth resistor;
the positive electrode of the seventh current source is used for being electrically connected with the positive electrode of a second power supply, the non-inverting input terminal of the fourth operational amplifier is used for receiving the second signal, the inverting input terminal of the fourth operational amplifier is respectively electrically connected with the source electrode of the fourth field effect transistor, the negative electrode of the seventh current source and the current generation module, the output terminal of the fourth operational amplifier is electrically connected with the gate electrode of the fourth field effect transistor, the drain electrode of the fourth field effect transistor is electrically connected with the input terminal of the second current mirror, the output terminal of the second current mirror is respectively electrically connected with the first terminal of the fourth resistor, the negative electrode of the eighth current source and the voltage regulation module, the common output terminal of the second current mirror is used for being electrically connected with the negative electrode of the second power supply, and the second terminal of the fourth resistor is used for receiving the reference voltage, the positive electrode of the eighth current source is used for being electrically connected with the positive electrode of the second power supply; the current provided by the seventh current source and the current provided by the eighth current source are equal in magnitude and same in direction as the current provided by the fifth current source.
7. The amplifying circuit according to any one of claims 1 to 6, wherein the current generating module comprises a fifth resistor; the first end of the fifth resistor is electrically connected with the first logic module, and the second end of the fifth resistor is electrically connected with the second logic module.
8. The amplifying circuit according to any one of claims 1-6, wherein the voltage regulating module comprises a first transconductance unit, a second transconductance unit and a first capacitor;
the positive input end of the first transconductance unit is electrically connected with the positive output ends of the second logic module and the second transconductance unit, the negative input end of the first transconductance unit is electrically connected with the negative output ends of the first logic module and the second transconductance unit, the positive output end of the first transconductance unit is electrically connected with the positive electrode of the first capacitor and the negative input end of the second transconductance unit, and the negative output end of the first transconductance unit is electrically connected with the negative electrode of the first capacitor and the positive input end of the second transconductance unit.
9. A detection chip comprising the amplification circuit according to any one of claims 1 to 8.
10. A wearable device comprising the detection chip of claim 9.
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| CN202210540297.5A CN114978073A (en) | 2022-05-18 | 2022-05-18 | Amplifying circuit, detection chip and wearable equipment |
| PCT/CN2022/137674 WO2023221465A1 (en) | 2022-05-18 | 2022-12-08 | Amplification circuit, detection chip, and wearable device |
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| CN202210540297.5A CN114978073A (en) | 2022-05-18 | 2022-05-18 | Amplifying circuit, detection chip and wearable equipment |
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| WO2023221465A1 (en) * | 2022-05-18 | 2023-11-23 | 深圳先进技术研究院 | Amplification circuit, detection chip, and wearable device |
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| CN102025667B (en) * | 2010-08-31 | 2013-11-20 | 上海南麟电子有限公司 | Circuit and method for eliminating direct current offset and radio frequency receiving chip |
| CN103441973B (en) * | 2013-09-11 | 2017-07-28 | 陈茂奎 | A kind of differential signal suppresses compensation method, apparatus and system |
| CN110755046B (en) * | 2019-10-30 | 2022-05-17 | 中国科学院深圳先进技术研究院 | Front-end analog circuit and front-end analog chip for neuroelectrophysiology detection |
| CN114978073A (en) * | 2022-05-18 | 2022-08-30 | 深圳先进技术研究院 | Amplifying circuit, detection chip and wearable equipment |
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| WO2023221465A1 (en) * | 2022-05-18 | 2023-11-23 | 深圳先进技术研究院 | Amplification circuit, detection chip, and wearable device |
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