KR20230130359A - Positive feedback loop and negative capacitance type input impedance amplifier circuit - Google Patents

Abstract

The present technology relates to an input impedance amplifier circuit of a positive feedback loop and a negative capacitance method. An amplifier for a biosignal sensor having the input impedance amplifier circuit of the present technology comprises: an amplifier section in which a first chopper, an input section, a bias section, a first amplifier, a second chopper, and a second amplifier are sequentially connected to receive a biosignal and amplify it and output it as an output signal; a feedback section implemented as a closed loop connected in series between the input section and the first amplifier and to the rear end of the second amplifier, and determining a circuit gain between the biosignal and the output signal; a positive feedback loop section implemented as a closed loop connected in parallel between the first chopper and the input section and to the rear end of the second amplifier, and generating a second current corresponding to the first current by the feedback section to increase the input impedance; and a negative capacitance circuit section connected in parallel to the rear end of the first chopper and the front end of the input section, and generating a third current corresponding to the difference between the first current and the second current to increase the input impedance. The present technology may provide an input impedance amplification circuit which may solve the PFL limitation, minimize the influence of input parasitic capacitance, and amplify the input impedance through a new NC method.

Description

Positive feedback loop and negative capacitance type input impedance amplifier circuit {Positive feedback loop and negative capacitance type input impedance amplifier circuit}

The present invention relates to a positive feedback loop and negative capacitance type input impedance amplification circuit. More specifically, an amplifier for a biological signal sensor having a positive feedback loop and a negative capacitance type input impedance amplification circuit that can be used as a sensor amplifier. It's about.

A biological signal sensor amplifies the voltage signal received from an electrode with a low-noise amplifier (LNA) and converts it into digital data through an analog-to-digital converter (ADC). At this time, in order to transmit the signal while minimizing attenuation of the voltage signal, the input impedance of the amplifier must be high.

Figure 1 shows an example of the configuration of a biosignal sensor. Biosignals (Vs) are collected through electrodes and transmitted to a low noise amplifier (LNA). Here, Zel represents the impedance of the electrode and Zin represents the input impedance of the low-noise amplifier. At this time, the voltage delivered to the low noise amplifier can be expressed as Equation 1 below.

Therefore, in order for most of the signals collected from the electrode to be transmitted to the low-noise amplifier, the input impedance of the low-noise amplifier must be high.

In biological signal sensors such as electroencephalograms (EEGs) and electrocardiograms (ECGs), small signals of 10 mV or less are collected through electrodes at low frequencies with a bandwidth of 10 kHz or less. Mainly used electrodes require an input impedance of 100MΩ or more for wet electrodes and 1GΩ or more for non-contact electrodes.

Figure 2 shows a capacitive feedback amplifier, a structure typically used in conventional low-noise amplifiers. At this time, the input impedance can be expressed as Equation 2 below.

And when the DC open-loop gain of the amplifier is A ₀ , the closed-loop gain of the amplifier can be expressed as Equation 3 below.

At this time, assuming that A ₀ is very large, G can be expressed as in Equation 4 below.

One of the input impedance amplification techniques is positive feedback loop (PFL). Figure 3 shows an amplifier circuit diagram to which a positive feedback loop (PFL) is applied. As shown in the equations below, when the current (Ipf) of the positive feedback loop is equal to the current (Ifb) by the feedback path, the currents cancel each other out and the input current (Iin) becomes 0. At this time, since the input impedance Zin = Vin / Iin, the input impedance is amplified as Iin becomes 0.

When the capacitance value of the PFL capacitor (Cpf) is set to be equal to the last term of Equation 5 above, the input impedance is infinitely amplified.

However, in actual circuits implemented in ICs, matching of capacitors must be considered. Therefore, it is very difficult to design Cpf as shown in Equation 5 above. Additionally, parasitic capacitance (Cp) exists in real circuits. The current (Ipf) due to the positive feedback loop changes due to the current (Ip) due to the parasitic capacitance (Cp) as shown in the equation below.

Therefore, even if Cpf is the same as the value derived from Equation 5 above, the current (Ipf) of the positive feedback loop and the current (Ifb) by the feedback path are not completely canceled due to the influence of the parasitic capacitance, so the input impedance of the amplifier is limited.

The inventor of the present invention completed the present invention after a long period of research and trial and error in order to solve this problem.

An embodiment of the present invention provides an input impedance amplification circuit that can solve the PFL limitation, minimize the effect of input parasitic capacitance, and amplify the input impedance through a new NC method.

Meanwhile, other unspecified purposes of the present invention will be additionally considered within the scope that can be easily inferred from the following detailed description and its effects.

An amplifier for a biological signal sensor having an input impedance amplification circuit according to an embodiment of the present invention includes a first chopper, an input unit, a bias unit, a first amplifier, and a second chopper to receive and amplify the biological signal and output it as an output signal. , and an amplifier unit to which a second amplifier is sequentially connected; a feedback unit implemented as a closed loop connected in series between the input unit and the first amplifier and at a rear end of the second amplifier, and determining a circuit gain between the biological signal and the output signal; A positive feedback loop that is implemented as a closed loop connected in parallel between the first chopper and the input unit and to the rear end of the second amplifier, and increases the input impedance by generating a second current corresponding to the first current by the feedback unit. wealth; And a negative capacitance circuit connected in parallel to the rear end of the first chopper and the front end of the input unit, and to increase the input impedance by generating a third current corresponding to the difference between the first current and the second current. You can.

The third current may have the same value as the difference between the first current and the second current.

The feedback unit may be configured by sequentially connecting a third chopper and a feedback capacitor.

The positive feedback loop unit may be configured by sequentially connecting a fourth chopper and an impedance boosting capacitor.

The negative capacitance circuitry may include a pair of cross-coupled NMOS transistors.

The negative capacitance circuit unit includes a first NMOS transistor gated in response to a first polarity of the biological signal; and a second NMOS transistor gated in response to the second polarity of the biological signal, wherein the gate of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the second NMOS transistor. It may be connected to the drain of the first NMOS transistor.

The negative capacitance circuit unit includes a first transistor and a second transistor each having a gate commonly connected to a first node and each having a source connected to a first power voltage; a third transistor and a fourth transistor whose source is connected to the drain of the first transistor and the drain of the second transistor at the second node and the third node, respectively, and which are cross-coupled with each other; and the drain of the third transistor and the drain of the fourth transistor at the fourth node where the voltage according to the first polarity of the biological signal is formed and the fifth node where the voltage according to the second polarity of the biological signal is formed, respectively. A fifth transistor and a sixth transistor are connected to the drain, have a gate commonly connected to the sixth node, and have a source connected to the second power voltage, respectively, and are connected between the second node and the third node. It may include a capacitor;

A voltage due to a second control input may be formed at the first node, and a voltage due to the first control input may be formed at the sixth node.

The negative capacitance circuitry may include a cross-coupled inverter pair.

The negative capacitance circuit unit includes a first inverter that generates a first inverting output in response to a first polarity of the biological signal; and a second inverter that generates a second inverting output in response to the second polarity of the biological signal, wherein the second inverting output is connected to the gate of the first inverter, and the first inverting output is connected to the gate of the first inverter. may be connected to the gate of the second inverter.

The negative capacitance circuit unit further includes a first resistor and a second resistor connected in series with each other, wherein one end of the first resistor is connected to the gate of the second inverter, and the other end of the second resistor is connected to the gate of the first inverter. It can be connected to the gate of .

The negative capacitance circuit unit includes a first transistor and a second transistor each having a gate commonly connected to a first node and each having a source connected to a first power voltage; a third transistor and a fourth transistor whose source is connected to the drain of the first transistor and the drain of the second transistor at the second node and the third node, respectively, and which are cross-coupled with each other; The gate of the third transistor and the gate of the fourth transistor are formed at the fourth node where the voltage according to the first polarity of the biological signal is formed and the fifth node where the voltage according to the second polarity of the biological signal is formed, respectively. a fifth transistor and a sixth transistor that are commonly connected and cross-coupled with each other; and a drain connected to the source of the fifth transistor and the source of the sixth transistor at each of the sixth and seventh nodes, and a gate commonly connected to the eighth node, and each source connected to a second power voltage. a seventh transistor and an eighth transistor; including a first and second resistor connected between the fourth node and the fifth node and connected in series with each other through a ninth node; a first capacitor connected between the second node and the third node; and a second capacitor connected between the sixth node and the seventh node.

The voltage formed at the first node, the voltage formed at the eighth node, and the voltage formed at the ninth node may be equal to each other.

The sizes of the first resistor and the second resistor may be the same.

The sizes of the first capacitor and the second capacitor may be the same.

This technology can solve the PFL limitation through a new NC method, minimize the effect of input parasitic capacitance, and provide an input impedance amplification circuit that can amplify the input impedance.

Additionally, this technology can provide a negative capacitance type input impedance amplification circuit that can be applied to various applications by amplifying the input impedance of an analog amplifier.

Figure 1 shows an example of the configuration of a biosignal sensor.
Figure 2 shows a capacitive feedback amplifier, which is a structure typically used in conventional low-noise amplifiers.
Figure 3 shows an amplifier circuit diagram to which a positive feedback loop is applied.
Figure 4 shows a negative capacitance type input impedance amplification circuit diagram.
Figure 5 shows an input impedance amplification circuit diagram combining the characteristics of negative capacitance with a positive feedback loop according to an embodiment of the present invention.
Figure 6 shows a block diagram for CCIA.
FIG. 7A shows a clock diagram of the chopper for the CCIA shown in FIG. 6.
Figure 7b shows the charging and discharging of Cin according to the clock phase shown in Figure 7a.
Figure 8 shows an implementation example of CCIA to which PFL is applied.
Figure 9 shows a circuit diagram as an example of the configuration of an NC according to an embodiment of the present invention, including a pair of cross-coupled NMOS transistors.
Figure 10 shows another configuration example of an NC circuit diagram according to an embodiment of the present invention, showing an NC circuit diagram including a cross-coupled inverter pair.
Figure 11 is a CCIA circuit diagram to which the PFL and NC described above in Figures 8 to 10 are applied, according to an embodiment of the present invention, and shows an amplifier for a biological signal sensor.
Figure 12 shows input impedance measurement results according to the input impedance amplification method for the comparative example and the inventive example.
The attached drawings are intended as reference for understanding the technical idea of the present invention, and are not intended to limit the scope of the present invention.

The above objects, other objects, features and advantages of the present invention will be easily understood through the following preferred embodiments related to the attached drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to enable the disclosed content to be more thorough and complete and to sufficiently convey the spirit of the present invention to those skilled in the art, without any intention other than to provide convenience of understanding.

In this specification, when it is mentioned that certain elements or lines are connected to the target element block, it includes not only direct connection but also indirect connection to the target element block through some other element.

In addition, the same or similar reference signs in each drawing indicate the same or similar components as much as possible. In some drawings, the connection relationships between elements and lines are only shown for effective explanation of technical content, and other elements or circuit blocks may be further provided.

Each embodiment described and illustrated herein may also include its complementary embodiment, and details regarding the general operation of input impedance amplification in a negative capacitance type and the circuitry or elements for performing such general operation are intended to summarize the gist of the present invention. Please note that this is not explained in detail to avoid ambiguity.

Figure 4 shows a negative capacitance (NC) type input impedance amplification circuit diagram.

It can be confirmed that the current (Ifb) due to the feedback path can be canceled by the current (I _NC ) generated by NC. Therefore, the input impedance can increase.

In detail, the voltage ( _V

When NC is applied, the input impedance Zin,boost can be expressed as follows.

From Equation 8 above, it can be seen that the input impedance is amplified.

Input impedance amplification through this NC method alleviates the limitations of input impedance amplification due to the effects of parasitic capacitance, enabling a higher level of input impedance amplification. Therefore, in a circuit where NC is applied, it is possible to have an input impedance amplified to the GΩ level.

As previously described in detail in FIG. 3, input impedance amplification using a PFL has a limitation in that the value of the current through the PFL changes due to the parasitic capacitance of the input terminal, thereby limiting the input impedance amplification. However, the input impedance through the NC described above works in a different way. First, as shown in Equation 8 above, the input impedance, which was previously 1/sCin, is amplified by α as shown in the equation below.

From Equation 9, it can be seen that the amplification degree (α) of the input impedance is determined by the open-loop gain (A(s)) of the amplifier, the input capacitance (Cin), the impedance (Zf) of the feedback loop, and the frequency (s). there is. Unlike PFL, which amplifies the input impedance solely through the size of the capacitance (Cpf) of the positive feedback loop, design flexibility is greatly improved when the NC method is applied. And generally, the open-loop gain (A(s)) of an amplifier is a very large value, so α has a very large value in the low-frequency region.

An embodiment of the present invention proposes a circuit that amplifies the input impedance by combining the characteristics of NC with PFL.

Figure 5 shows an input impedance amplification circuit diagram combining the characteristics of negative capacitance (NC) with a positive feedback loop (PFL) according to an embodiment of the present invention.

Due to the process limitations described above, the current (Ipf) generated by the PFL is amplified by matching the capacitance (Cpf) of the positive feedback loop with the capacitance (Cfb) of the feedback path to amplify the input impedance by the closed-loop gain (G). I do it. However, this has limitations that make it difficult to apply when the closed-loop gain is low. The lower the closed loop gain, the lower the amplification effect. For example, if the closed loop gain is 4, the input impedance only increases by about 4 times. In addition, due to the influence of the parasitic capacitance present in the input capacitance (Cin), the current (Ipf) of the PFL cannot be accurately matched to the current (Ifb) by the feedback path, which limits input impedance amplification. If the current changed by the parasitic capacitance is called Ipf_mod, Ipf_mod does not match Ifb.

At this time, the current of the PFL can be compensated by adding NC to the input of the instrumentation amplifier (IA). If the current by NC (I _NC ) is matched to Ifb-Ipf_mod, the input impedance theoretically becomes infinite. In other words, when NC is added, the current of the PFL is compensated and the amplification of the input impedance increases significantly. With these advantages, the NC method combined with PFL can be applied even when the closed-loop gain is low.

Hereinafter, as an example of an input impedance amplification method using NC, we will focus on CCIA to which NC is applied.

First, Figure 6 shows a block diagram of a capacitively-coupled chip instrumentation amplifier (CCIA). Chopping is a noise reduction technique that uses the principle of amplitude modulation (AM). It modulates the input signal corresponding to the chopping clock and moves it to the high frequency region to avoid noise at low frequencies, amplifies it, and then demodulates it again to return to the original frequency. This is a method of moving to an area. CCIA operates in a structure that amplifies the signal at the capacitor ratio, as shown in FIG. 6. In other words, the gain is determined by the ratio Cin/Cfb of Cin and Cfb in the form of capacitive feedback. Additionally, it has the advantage that the influence of 1/f noise is greatly reduced due to the chopping operation. Because it is composed of a capacitor, it is resistant to mismatch and does not consume DC power, making it advantageous for low-power design. However, there is a decrease in input impedance due to the chopper's switching operation.

And FIG. 7A shows a clock diagram of the chopper for CCIA shown in FIG. 6. Figure 7b shows the charging and discharging of Cin according to the clock phase shown in Figure 7a. During the chopping operation of FIG. 7A, the input capacitor Cin is switched between Vin+ and Vin-, and charging and discharging are repeated, as shown in FIG. 7B. In other words, the polarity changes depending on the chopper frequency, and the input capacitor (Cin) repeats charging and discharging as the polarity changes. At this time, since there is a relationship of Vcin = 2Vin = 1/(fchop*Cin)*Iin, the input impedance can be expressed as follows. fchop is the chopping frequency.

Next, Figure 8 shows an implementation example of CCIA to which PFL is applied. CCIA consists of a two-stage Miller-compensated opamp (Gm1 and Gm2), and Cm1 and Cm2 are Miller-compensation capacitors. The input signal Vin is amplified at CCIA and appears as output Vout. The DC bias of the CCIA is secured through bias resistors Rb1,2 connected to the reference voltage Vref. Cp1,2 represent the parasitic components of the input capacitor.

As shown in FIG. 8, a negative feedback loop (NFL) may be included in the main path through which the input signal (Vin) passes. The main path may refer to a path connected to an input terminal where the input signal (Vin) is input, a first OTA (OTA1), a second OTA (OTA2), and an output terminal where the output signal (Vout) is output. Specifically, the negative feedback loop (NFL) may be implemented as a closed loop in which Cfb and CHfb are connected in series between the input unit of the first OTA (OTA1) and the output unit of the second OTA (OTA2). The first OTA and the second OTA may be amplifiers that output the applied input voltage as an output current in proportion to the transconductance (Gm1 and Gm2, respectively). After setting the intrinsic gain through the first OTA and the second OTA, the overall circuit gain can be adjusted through a negative feedback loop. And the input impedance can be amplified by supplying the input current as the PFL current (Ipf1, 2).

As shown in Equation 6 above, even if the currents of Ipf1,2 and Ifb1,2 are set to be the same, Ipf1,2 changes due to parasitic capacitance. Therefore, as described above in FIG. 6, the input impedance can be amplified to a higher level by compensating the current generated by the NC to be equal to -(I'pf1,2-Ifb1,2). In other words, the input impedance can be amplified by connecting NC in parallel with Cin.

Figure 9 shows a circuit diagram including a cross-coupled NMOS transistor pair as an example of the configuration of an NC according to an embodiment of the present invention.

As shown in FIG. 9, the NC circuit (NC) is a cross circuit consisting of an NMOS transistor (M3) gated in response to the first polarity of the input signal and an NMOS transistor (M4) gated in response to the second polarity of the input signal. -Contains a pair of coupled NMOS transistors. At this time, the gate of the NMOS transistor M3 is connected to the drain of the NMOS transistor M4, and the gate of the NMOS transistor M4 is connected to the drain of the NMOS transistor M3.

In more detail, the first transistor M1 and the second transistor M2 have gates commonly connected to the first node N1, and their sources are each connected to the first power voltage VSS. The source of the third transistor M3 and the fourth transistor M4 is connected to the drain of the first transistor M1 and the drain of the second transistor M2 at the second node N2 and the third node N3, respectively. and are cross-linked with each other. The fifth transistor (M5) and the sixth transistor (M6) are a fourth node (N4) where a voltage according to the first polarity of the input signal is formed and a fifth node (N5) where a voltage according to the second polarity of the input signal is formed. ), each drain is connected to the drain of the third transistor (M3) and the drain of the fourth transistor (M4), each has a gate commonly connected to the sixth node, and each source is connected to the second power voltage (VDD). . And, the capacitor Cn is connected between the second node N2 and the third node N3.

A voltage due to the second control input (VB2) is formed at the first node (N1), and a voltage due to the first control input (VB1) is formed at the sixth node (N6).

The first to fourth transistors M1 to M4 may be NMOS transistors, and the fifth to sixth transistors M5 to M6 may be PMOS transistors.

Referring to the NC circuit diagram of FIG. 9, the output impedance (Znc) of NC can be expressed as follows.

At this time, the current generated by NC is as follows.

Figure 10 shows another configuration example of an NC circuit diagram according to an embodiment of the present invention, showing an NC circuit diagram including a cross-coupled inverter pair.

As shown in FIG. 10, a first inverter (INV1) generating a first inverting output in response to the first polarity of the input signal and a second inverting output in response to the second polarity of the input signal. 2 Includes inverter (INV2). At this time, the second inverting output is connected to the gate of the first inverter (INV1), and the first inverting output is connected to the gate of the second inverter (INV2).

And it further includes a first resistor (R1) and a second resistor (R2) connected in series with each other. One end of the first resistor (R1) is connected to the gate of the second inverter (INV2), and the other end of the second resistor (R2) is connected to the gate of the first inverter (INV1). The resistance values of the first resistor (R1) and the second resistor (R2) may be the same.

In more detail, the first transistor M1 and the second transistor M2 have gates commonly connected to the first node N1, and their sources are each connected to the first power voltage VSS. The source of the third transistor M3 and the fourth transistor M4 is connected to the drain of the first transistor M1 and the drain of the second transistor M2 at the second node N2 and the third node N3, respectively. and are cross-linked with each other. The fifth transistor (M5) and the sixth transistor (M6) are a fourth node (N4) where a voltage according to the first polarity of the input signal is formed and a fifth node (N5) where a voltage according to the second polarity of the input signal is formed. ), each gate is commonly connected to the gate of the third transistor (M3) and the gate of the fourth transistor (M4), and are cross-coupled with each other. The drains of the seventh transistor M7 and the eighth transistor M8 are connected to the source of the fifth transistor M5 and the source of the sixth transistor M6 at the sixth node M6 and the seventh node M7, respectively. It has a gate commonly connected to the eighth node (N8), and each source is connected to the second power voltage (VDD). Additionally, the first resistor R1 and the second resistor R2 are connected between the fourth node N4 and the fifth node N5 and are connected in series to each other through the ninth node N9. Additionally, the first capacitor C1 is connected between the second node N2 and the third node N3, and the second capacitor C2 is connected between the sixth node N6 and the seventh node N7. . The capacitance of the first capacitor C1 and the second capacitor C2 may be the same, and may have a value corresponding to half of the capacitance of the capacitor Cn of FIG. 9 described above.

The voltage formed at the first node N1, the voltage formed at the eighth node N8, and the voltage formed at the ninth node N9 may be equal to each other.

The first to fourth transistors M1 to M4 may be NMOS transistors, and the fifth to eighth transistors M5 to M8 may be PMOS transistors.

Compared to the above-described FIG. 9, the NC circuit shown in FIG. 10 senses the output common mode (output CM) voltage through the resistors (R1, R2) and can be configured without a separate bias circuit, which is advantageous for low-power design. The cross-coupled inverter structure can be thought of as a structure in which a cross-coupled NMOS transistor pair (M3, M4) and a cross-coupled PMOS transistor pair (M5, M6) are connected in parallel. By combining an NMOS transistor and a PMOS transistor, the Gm/Id index indicating current efficiency can be doubled compared to Figure 9 described above.

If gm5,6 and gm3,4 are assumed to be the same, the output impedance Zout of the circuit of FIG. 10 can be expressed as follows.

Figure 11 is a CCIA circuit diagram to which the PFL and NC described above in Figures 8 to 10 are applied, according to an embodiment of the present invention, and shows the amplifier 100 for a biological signal sensor. The amplifier 100 for a biological signal sensor includes an amplifier 110, a feedback unit 120, a positive feedback loop unit 130, and a negative capacitance circuit unit 140.

The amplification unit 110 includes a first chopper (CHin), an input unit (Cin1, 2), and a bias unit (Vref) sequentially connected to receive a biological signal, which is an input signal (Vin), amplify it, and output it as an output signal (Vout). , Rb1,2), a first amplifier (OTA1), a second chopper (CHout), and a second amplifier (OTA2). Corresponds to the CCIA described above.

The feedback unit 120 is implemented as a closed loop connected in series between the input units (Cin1, 2) and the first amplifier (OTA1) and the rear end of the second amplifier (OTA2), and determines the circuit gain between the biological signal and the output signal. . The feedback unit 120 may be configured by sequentially connecting a third chopper (CHfb) and feedback capacitors (Cfb1, 2). The feedback unit 120 corresponds to the NFL described above.

The positive feedback loop unit 130 is implemented as a closed loop connected in parallel between the first chopper (CHin) and the input units (Cp1, 2) and the rear end of the second amplifier (OTA2), and the first amplifier by the feedback unit 120 Second currents (Ipf1,2) corresponding to the currents (Ifb1,2) are generated to increase the input impedance (Zin). The positive feedback loop unit 130 may be configured by sequentially connecting the fourth chopper (CHpf) and the impedance boosting capacitors (Cpf1 and Cpf2). The positive feedback loop unit 130 corresponds to the PFL described above.

The negative capacitance circuit unit 140 is connected in parallel to the rear end of the first chopper (CHin) and the front end of the input unit (Cp1,2), and is connected in parallel to the difference between the first current (Ifb1,2) and the second current (Ipf1,2). A corresponding third current (I _NC ) is generated to increase the input impedance (Zin). Corresponds to the NC described above.

The third current (I _NC ) generated by the negative capacitance circuit unit 140 may have the same value as the difference between the first currents (Ifb1,2) and the second currents (Ipf1,2). As described above, the second current (Ipf1,2) has a changed value (I'pf1,2) due to the presence of the parasitic capacitance (Cp1,2, see FIG. 8). Therefore, as shown in the figure, if the amount of the third current (I _NC ) is equal to -(I'pf - Ifb), the input impedance (Zin) can be amplified to a very large value.

Previously, when boosting the input impedance through PFL, there was a problem that it was difficult to implement an accurate capacitance equal to the calculated value due to mismatch, so the impedance was boosted by the closed-loop gain by matching the unit size with the capacitor of the feedback loop. The way it was done was common. Additionally, there was a problem in that the Ipf value changed due to the influence of parasitic capacitance, reducing the effect of impedance boosting. Accordingly, in the impedance amplification circuit according to an embodiment of the present invention, an NC circuit to compensate for the PFL was additionally applied to overcome the fact that the input impedance boosting effect is very small when the PFL is applied to a PGA with a small closed-loop gain. . In other words, the NC circuit compensates for leakage current due to insufficient current and parasitic capacitance due to a capacitor size smaller than the capacitor required in the PFL.

Figure 12 shows input impedance measurement results according to the input impedance amplification method for the comparative example and the inventive example. In the case where input impedance amplification was not performed (No Zin Boost), the input impedance had a value of 150 MΩ (Comparative Example 1). Compared to Comparative Example 1, when the input impedance was amplified by PFL (PFL Only), the amplified input impedance had a value of 400 MΩ due to the influence of parasitic capacitance (Comparative Example 2). Compared to Comparative Example 1 and Comparative Example 2, it can be seen that in the case of the circuit to which PFL and NC are applied (NC+PFL), the input impedance is amplified to about 3.9GΩ (invention example). When only PFL is used, it is amplified by about 2.6 times, while when NC is applied, it is amplified by about 26 times, showing an input impedance amplification amount of about 10 times compared to when only PFL is used.

According to the above-described embodiment of the present invention, the input impedance can be amplified using an NC circuit capable of low-power operation in a small area. Embodiments of the present invention can be widely applied to circuits that transmit input signals to amplifiers, but can be more suitably applied to amplifiers for biological signal sensors. Additionally, it can be operated with low power and area in battery-powered sensor circuits. It is advantageous to receive signals by increasing the input impedance of the amplifier.

The term “unit” used in this document may mean, for example, a unit including one or a combination of two or more of hardware, software, or firmware. “Part” can be used interchangeably with terms such as, for example, module, unit, logic, logical block, component, or circuit. ) can be. A “part” may be the minimum unit of an integrated part or a part thereof. “Part” may be the minimum unit or part of one or more functions. The “part” may be implemented mechanically or electronically. For example, a “part” may be an application-specific integrated circuit (ASIC) chip, field-programmable gate arrays (FPGAs), or programmable-logic device, known or to be developed in the future, that performs certain operations. It can contain at least one.

As described above, the present invention has been described with specific details such as specific components and limited embodiments and drawings, but this is only provided to facilitate a more general understanding of the present invention, and the present invention is not limited to the above embodiments. , those skilled in the art can make various modifications and variations from this description. Accordingly, the spirit of the present invention should not be limited to the described embodiments, and the scope of the patent claims described below as well as all modifications that are equivalent or equivalent to the scope of this patent claim shall fall within the scope of the spirit of the present invention. .

100: Amplifier for biological signal sensor having an input impedance amplification circuit
110: Amplification unit
120: Feedback unit
130: positive feedback loop unit
140: Negative capacitance circuit part
PFL: Positive Feedback Loop
NFL: Negative Feedback Loop
NC: negative capacitance

Claims (15)

An amplification unit in which a first chopper, an input unit, a bias unit, a first amplifier, a second chopper, and a second amplifier are sequentially connected to receive a biological signal, amplify it, and output it as an output signal;
a feedback unit implemented as a closed loop connected in series between the input unit and the first amplifier and at a rear end of the second amplifier, and determining a circuit gain between the biological signal and the output signal;
A positive feedback loop that is implemented as a closed loop connected in parallel between the first chopper and the input unit and to the rear end of the second amplifier, and increases the input impedance by generating a second current corresponding to the first current by the feedback unit. wealth; and
A negative capacitance circuit unit connected in parallel to the rear end of the first chopper and the front end of the input unit and increasing the input impedance by generating a third current corresponding to the difference between the first current and the second current. An amplifier for a biological signal sensor comprising an input impedance amplification circuit. According to paragraph 1,
The third current has a value equal to the difference between the first current and the second current. According to paragraph 1,
An amplifier for a biological signal sensor having an input impedance amplification circuit, wherein the feedback unit is configured by sequential connection of a third chopper and a feedback capacitor. According to paragraph 1,
An amplifier for a biological signal sensor having an input impedance amplification circuit, wherein the positive feedback loop part is configured by sequential connection of a fourth chopper and an impedance boosting capacitor. According to paragraph 1,
An amplifier for a biosignal sensor having an input impedance amplification circuit, wherein the negative capacitance circuit part includes a pair of cross-coupled NMOS transistors. According to clause 5,
The negative capacitance circuit part is
a first NMOS transistor gated in response to a first polarity of the biological signal; and
A second NMOS transistor gated in response to the second polarity of the biological signal,
A living body having an input impedance amplification circuit, characterized in that the gate of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor. Amplifier for signal sensors. According to clause 5,
The negative capacitance circuit part is
a first transistor and a second transistor each having a gate commonly connected to a first node and each having a source connected to a first power voltage;
a third transistor and a fourth transistor whose source is connected to the drain of the first transistor and the drain of the second transistor at the second node and the third node, respectively, and which are cross-coupled with each other; and
The drain of the third transistor and the drain of the fourth transistor are respectively connected to the fourth node where the voltage according to the first polarity of the biological signal is formed and the fifth node where the voltage according to the second polarity of the biological signal is formed. A fifth transistor and a sixth transistor are connected to each other, have a gate commonly connected to the sixth node, and have a source connected to the second power supply voltage, respectively.
A capacitor connected between the second node and the third node. An amplifier for a biological signal sensor having an input impedance amplification circuit. In clause 7,
An amplifier for a biological signal sensor having an input impedance amplification circuit, wherein a voltage is formed in the first node by a second control input, and a voltage by a first control input is formed in the sixth node. According to paragraph 1,
An amplifier for a biological signal sensor having an input impedance amplification circuit, wherein the negative capacitance circuit part includes a cross-coupled inverter pair. According to clause 9,
The negative capacitance circuit part is
a first inverter generating a first inverting output in response to a first polarity of the biological signal; and
A second inverter generating a second inverting output in response to the second polarity of the biological signal,
The second inverting output is connected to the gate of the first inverter, and the first inverting output is connected to the gate of the second inverter. An amplifier for a biological signal sensor having an input impedance amplification circuit. . According to clause 10,
The negative capacitance circuit part is
It further includes a first resistor and a second resistor connected in series with each other,
An amplifier for a biosignal sensor having an input impedance amplification circuit, wherein one end of the first resistor is connected to the gate of the second inverter, and the other end of the second resistor is connected to the gate of the first inverter. . According to clause 9,
The negative capacitance circuit part is
a first transistor and a second transistor each having a gate commonly connected to a first node and each having a source connected to a first power voltage;
a third transistor and a fourth transistor whose source is connected to the drain of the first transistor and the drain of the second transistor at the second node and the third node, respectively, and which are cross-coupled with each other;
The gate of the third transistor and the gate of the fourth transistor are formed at the fourth node where the voltage according to the first polarity of the biological signal is formed and the fifth node where the voltage according to the second polarity of the biological signal is formed, respectively. a fifth transistor and a sixth transistor that are commonly connected and cross-coupled with each other; and
The drain is connected to the source of the fifth transistor and the source of the sixth transistor at the sixth node and the seventh node, respectively, has a gate commonly connected to the eighth node, and the source is connected to the second power voltage, respectively. 7 transistor and 8th transistor;
a first resistor and a second resistor connected between the fourth node and the fifth node and connected in series with each other through a ninth node;
a first capacitor connected between the second node and the third node; and
An amplifier for a biological signal sensor having an input impedance amplification circuit, comprising: a second capacitor connected between the sixth node and the seventh node. According to clause 12,
An amplifier for a biological signal sensor having an input impedance amplification circuit, wherein the voltage formed at the first node, the voltage formed at the eighth node, and the voltage formed at the ninth node are equal to each other. According to clause 12,
An amplifier for a biological signal sensor having an input impedance amplification circuit, wherein the first resistor and the second resistor have the same size. According to clause 12,
An amplifier for a biological signal sensor having an input impedance amplification circuit, wherein the first capacitor and the second capacitor have the same size.

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