CN111585531A

CN111585531A - Direct current coupling differential front-end amplifier circuit

Info

Publication number: CN111585531A
Application number: CN202010329210.0A
Authority: CN
Inventors: 张骏哲; 许小印
Original assignee: Shenzhen Xinsen Microelectronics Co ltd
Current assignee: Shenzhen Xinsen Microelectronics Co ltd
Priority date: 2020-04-23
Filing date: 2020-04-23
Publication date: 2020-08-25

Abstract

The invention discloses a direct current coupling differential front-end amplifier circuit, which comprises: the six-input differential amplifier circuit comprises a six-input differential amplifier circuit, a first loss regulation suppression circuit, a second direct current offset suppression circuit and a closed-loop gain circuit; the first direct current offset suppression circuit and the second direct current offset suppression circuit are used for suppressing direct current offset voltage; the closed-loop gain circuit serves as a negative feedback loop to provide closed-loop gain for the direct-current coupling differential front-end amplifier circuit. The invention is suitable for direct current coupling input, has certain direct current electrode disorder inhibition capability, and can effectively improve the signal-to-noise ratio and the anti-interference capability of weak bioelectricity signals, thereby improving the precision of the whole signal acquisition.

Description

Direct current coupling differential front-end amplifier circuit

Technical Field

The invention relates to the technical field of sensing technology and integrated circuits, in particular to a direct-current coupling differential front-end amplifier circuit.

Background

The front-end amplifier of the bioelectricity signal is a core module of the health information acquisition system. As the first circuit module for realizing signal acquisition by directly contacting the electrode of the whole acquisition system, the acquisition precision of the first circuit module directly influences the accuracy of the acquired health information. In the acquisition and measurement of weak bioelectric signals such as electrocardio, electroencephalogram and the like, skin cleanser and an electrode with conductor glue are generally used for reducing skin impedance and enhancing the conductivity between the electrode and the skin, however, the traditional electrode has a certain polarization voltage, which causes large input offset voltage of an acquisition amplifier to cause signal saturation distortion, and particularly, the polarization voltage of the electrode is larger under long-term measurement. In addition, the bioelectric signal has small amplitude and is extremely weak, so that the bioelectric signal is extremely easy to be interfered by environmental noise, electrode contact disturbance and circuit noise, and the problems are more serious in actual signal acquisition and measurement. Therefore, designing a front-end amplifier with offset voltage suppression, low noise and high energy efficiency is a key to creating a high-performance acquisition system, and particularly for the application trend of wearable health monitoring, more and more new technologies begin to emerge to meet the design requirements of the high-performance front-end amplifier. The current mainstream design method is to use AC coupling input, but the AC coupling has the disadvantage that a large coupling capacitor needs to be placed at the input end of the preamplifier, and the large capacitor cannot be integrated and has large input error caused by device mismatch. In order to solve the above problems, it is desirable to provide a new front-end amplifier circuit with a programmable high-pass cutoff frequency and amplification factor.

Disclosure of Invention

The present invention is directed to a dc-coupled differential front-end amplifier circuit, which is provided to overcome the drawbacks of the prior art.

The technical scheme adopted by the invention for solving the technical problems is as follows: constructing a dc-coupled differential front-end amplifier circuit comprising: a six-input differential amplifier circuit, a first DC offset suppression circuit, a second DC offset suppression circuit, and a closed-loop gain circuit,

the first dc dropout prevention circuit is connected between a first positive input terminal Vpp and a first negative input terminal Vpn of the six-input differential amplifier circuit, and a connection point of the first dc dropout prevention circuit and the first positive input terminal Vpp of the six-input differential amplifier circuit is an external signal positive differential input terminal Vip of the dc-coupled differential front-end amplifier circuit; the second dc offset suppression circuit is connected between the second positive input terminal Vnp and the second negative input terminal Vnn of the six-input differential amplifier circuit, and a connection point of the second dc offset suppression circuit and the second positive input terminal Vnp of the six-input differential amplifier circuit is an external signal negative differential input terminal Vin of the dc-coupled differential front-end amplifier circuit; a positive auxiliary input end Vpx of the six-input differential amplifier circuit and the closed-loop gain circuit both input a common-mode voltage Vcm, and a negative auxiliary input end Vnx of the six-input differential amplifier circuit is connected with an output end Vout of the six-input differential amplifier circuit through the closed-loop gain circuit;

the first direct current offset suppression circuit and the second direct current offset suppression circuit are used for suppressing direct current offset voltage; the closed-loop gain circuit serves as a negative feedback loop to provide closed-loop gain for the direct-current coupling differential front-end amplifier circuit.

Preferably, the six-input differential amplifier circuit includes: the circuit comprises a bias circuit, a multi-input stage circuit, a gain stage circuit and an output stage circuit; wherein the content of the first and second substances,

the bias circuit comprises PMOS tubes Mp1, Mp2 and a bias current source Ib; the source electrode of the PMOS tube Mp1 is connected with the positive power supply terminal Vdd, the drain electrode of the PMOS tube Mp1 is connected with the source electrode of the PMOS tube Mp2, and the source electrode of the PMOS tube Mp2 is connected with the negative power supply terminal Vss through the bias current source Ib; the grid electrode and the drain electrode of the PMOS tube Mp1 are in short circuit, and the grid electrode and the drain electrode of the PMOS tube Mp2 are in short circuit;

the multi-input stage circuit comprises PMOS tubes Mp3, Mp4, Mp5, Mp6, Mp7, Mp8, Mp15, Mp16, Mp17 and NMOS tubes Mn1 and Mn 3; the sources of the PMOS tubes Mp3, Mp6 and Mp15 are all connected with the positive power supply terminal Vdd, and the gates of the PMOS tubes Mp3, Mp6 and Mp15 are shorted and connected to the gate of the PMOS tube Mp 1; the gates of the PMOS transistors Mp7 and Mp8 are respectively used as a first positive input end Vpp and a first negative input end Vpn of the six-input differential amplifier circuit, the sources of the PMOS transistors Mp7 and Mp8 are connected to the drain of the PMOS transistor Mp6, the drain of the PMOS transistor Mp7 is connected to the drain of the NMOS transistor Mn3, and the drain of the PMOS transistor Mp8 is connected to the drain of the NMOS transistor Mn 1; the gates of the PMOS transistors Mp4 and Mp5 are respectively used as a second negative input end Vnn and a second positive input end Vnp of the six-input differential amplifier circuit, the sources of the PMOS transistors Mp4 and Mp5 are connected to the drain of the PMOS transistor Mp3, the drain of the PMOS transistor Mp4 is connected to the drain of the NMOS transistor Mn3, and the drain of the PMOS transistor Mp5 is connected to the drain of the NMOS transistor Mn 1; the gates of the PMOS transistors Mp16 and Mp17 are respectively used as a negative auxiliary input end Vnx and a positive auxiliary input end Vpx of the six-input differential amplifier circuit, the sources of the PMOS transistors Mp16 and Mp17 are connected to the drain of the PMOS transistor Mp15, the drain of the PMOS transistor Mp16 is connected to the drain of the NMOS transistor Mn1, and the drain of the PMOS transistor Mp17 is connected to the drain of the NMOS transistor Mn 3; the grid electrode of the NMOS transistor Mn1 is in short circuit with the drain electrode, the grid electrode of the NMOS transistor Mn3 is in short circuit with the drain electrode, and the source electrodes of the NMOS transistors Mn1 and Mn3 are both connected to the negative power supply terminal Vss;

the gain stage circuit comprises PMOS tubes Mp9, Mp10, Mp11, Mp12, Mp13 and NMOS tubes Mn2, Mn4, Mn5 and Mn 6; the PMOS tubes Mp9 and Mp10 form an active current mirror as a load, the grid electrode and the drain electrode of the PMOS tube Mp10 are connected with the grid electrode of the PMOS tube Mp9 after being in short circuit, the drain electrode of the PMOS tube Mp9 is connected with the drain electrode of the NMOS tube Mn4, and the drain electrode of the PMOS tube Mp10 is connected with the drain electrode of the NMOS tube Mn 2; the NMOS transistor Mn2 and an NMOS transistor Mn1 in the multi-input stage circuit form a current mirror circuit, the grid electrode of the NMOS transistor Mn2 is connected with the grid electrode of the NMOS transistor Mn1, and the source electrode of the NMOS transistor Mn2 is connected to the negative power supply terminal Vss; the NMOS transistor Mn4 and an NMOS transistor Mn3 in the multi-input stage circuit form a current mirror circuit, the grid electrode of the NMOS transistor Mn4 is connected with the grid electrode of the NMOS transistor Mn3, and the source electrode of the NMOS transistor Mn4 is connected to the negative power supply terminal Vss; the PMOS tubes Mp11, Mp12 and Mp13 and the NMOS tubes Mn5 and Mn6 form a first-order amplifier structure, the grid electrode of the PMOS tube Mp11 is connected with the grid electrode of the PMOS tube Mp1 in the bias circuit to form a current source, the grid electrodes of the PMOS tubes Mp12 and Mp13 are respectively connected with the drain electrodes of the PMOS tubes Mp9 and Mp10, the source electrodes of the PMOS tubes Mp12 and Mp13 are connected with the drain electrode of the PMOS tube Mp11, and the drain electrodes of the PMOS tubes Mp12 and Mp13 are respectively connected with the drain electrodes of the NMOS tubes Mn5 and Mn 6; the NMOS tubes Mn5 and Mn6 form an active current mirror as a load, the grid electrode and the drain electrode of the NMOS tube Mn5 are connected with the grid electrode of the NMOS tube Mn6 after being in short circuit, and the source electrodes of the NMOS tubes Mn5 and Mn6 are connected to the negative power supply terminal Vss;

the output stage circuit comprises a PMOS tube Mp14 and an NMOS tube Mn 7; the grid electrode of the PMOS tube Mp14 is connected with the grid electrode of a PMOS tube Mp1 in the bias circuit to form a mirror current source, the source electrode of the PMOS tube Mp14 is connected with a positive power supply terminal Vdd, and the drain electrode of the PMOS tube Mp14 is connected with the drain electrode of the NMOS tube Mn 7; the gate of the NMOS transistor Mn7 is connected with the drain of the NMOS transistor Mn6, and the source of the NMOS transistor Mn7 is connected to the negative power supply terminal Vss; the connection point of the drain of the PMOS tube Mp14 and the drain of the NMOS tube Mn7 is used as the output end Vout of the six-input differential amplifier circuit.

Preferably, the six-input differential amplifier circuit further comprises a miller compensation resistor-capacitor circuit;

the Miller compensation resistor-capacitor circuit comprises a resistor R and a capacitor C, wherein the resistor R and the capacitor C are connected between the grid of the PMOS tube Mp13 and the output end Vout of the six-input differential amplifier circuit in series;

the miller compensation resistor-capacitor circuit provides phase margin compensation for the six-input differential amplifier circuit.

Preferably, the first dc offset suppression circuit and the second dc offset suppression circuit each include a PMOS transistor M1 and a PMOS transistor M2;

the grid electrode of the PMOS tube M1 is connected with the grid electrode of the PMOS tube M2, the drain electrode of the PMOS tube M1 is connected with the drain electrode of the PMOS tube M2, and the grid electrode connection points of the PMOS tubes M1 and M2 are connected with the drain electrode connection points of the PMOS tubes M1 and M2; in the first constant current dimming suppression circuit, the source and the substrate of the PMOS transistor M1 are connected to the external signal positive differential input end Vip after being shorted, and the source and the substrate of the PMOS transistor M2 are connected to the first negative input end Vpn of the six-input differential amplifier circuit after being shorted; in the second direct current offset suppression circuit, the source and the substrate of the PMOS transistor M1 are short-circuited and then connected to the external signal negative differential input terminal Vin, and the source and the substrate of the PMOS transistor M2 are short-circuited and then connected to the second negative input terminal Vnn of the six-input differential amplifier circuit.

Furthermore, the high-pass cut-off frequency of the first direct current offset suppression circuit and the second direct current offset suppression circuit is adjustable; the first direct current offset suppression circuit and the second direct current offset suppression circuit respectively comprise a PMOS (P-channel metal oxide semiconductor) transistor M1 and a PMOS transistor M2;

the grid electrode of the PMOS tube M1 and the grid electrode of the PMOS tube M2 are in short circuit and are connected with a bias voltage Vb, the PMOS tube M1 is connected with the drain electrode of the PMOS tube M2, and the PMOS tube M1 and the substrate of the PMOS tube M2 are connected together and are connected to the drain electrode connection point of the PMOS tube M1 and the PMOS tube M2; in the first constant current drop suppression circuit, the source of the PMOS transistor M1 is connected to the external signal positive differential input terminal Vip, and the source of the PMOS transistor M2 is connected to the first negative input terminal Vpn of the six-input differential amplifier circuit; in the second dc offset suppression circuit, the source of the PMOS transistor M1 is connected to the external signal negative differential input terminal Vin, and the source of the PMOS transistor M2 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit; the bias voltage Vb is generated by a bias voltage generating circuit;

and adjusting the high-pass cut-off frequency of the first direct current offset suppression circuit and the second direct current offset suppression circuit by adjusting the magnitude of the bias voltage Vb.

Preferably, the dc-coupled differential front-end amplifier circuit further comprises a first fast recovery circuit and a second fast recovery circuit;

the first fast recovery circuit is connected between an external signal positive differential input end Vip of the direct-current coupling differential front-end amplifier circuit and a first negative input end Vpn of the six-input differential amplifier circuit; the second fast recovery circuit is connected between an external signal negative differential input terminal Vin of the dc-coupled differential front-end amplifier circuit and a second negative input terminal Vnn of the six-input differential amplifier circuit;

the first fast recovery circuit and the second fast recovery circuit are used for improving the response speed of the direct-current coupling differential front-end amplifier circuit under the condition that an external signal input lead wire is disconnected and reconnected.

Preferably, the first fast recovery circuit comprises a MOS transistor M3, and the second fast recovery circuit comprises a MOS transistor M4;

the source electrode of the MOS tube M3 is connected with the external signal negative differential input end Vip of the direct current coupling differential front-end amplifier circuit, and the drain electrode of the MOS tube M3 is connected with the first negative input end Vpn of the six-input differential amplifier circuit; the source of the MOS transistor M4 is connected to the external signal negative differential input terminal Vin of the dc-coupled differential front-end amplifier circuit, and the drain of the MOS transistor M4 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit; the grid electrode of the MOS transistor M3 and the grid electrode of the MOS transistor M4 are both controlled by a control signal SW;

when the external signal input lead wire is disconnected and reconnected, the control signal SW controls the MOS tube M3 and the MOS tube M4 to be conducted, and external signals are transmitted to the six-input differential amplifier circuit in a low-impedance mode.

Preferably, the closed-loop gain circuit is a variable closed-loop gain circuit that provides an adjustable closed-loop gain for the dc-coupled differential front-end amplifier circuit.

Optionally, the variable closed-loop gain circuit comprises a variable resistor array network Rf and a fixed resistor Rg;

one end of the fixed resistor Rg is connected with a negative auxiliary input end Vnx of the six-input differential amplifier circuit, and the other end of the fixed resistor Rg is connected with an output end Vout of the six-input differential amplifier circuit; the variable resistor array network Rf is composed of a plurality of resistors with different resistance values, one ends of the resistors with different resistance values are connected and connected with a common mode voltage Vcm, and the other ends of the resistors with different resistance values are connected to a connection point of the fixed resistor Rg and a negative auxiliary input end Vnx of the six-input differential amplifier circuit through a selection switch; the selection switch is controlled by a digital control circuit;

the digital control circuit selects the resistance value of the variable resistor array network Rf accessed to the variable closed-loop gain circuit by controlling a selection switch, so that the direct-current coupling differential front-end amplifier circuit realizes different closed-loop gains.

Optionally, the variable closed-loop gain circuit comprises a fixed resistor Rf and a variable resistor Rg;

one end of the variable resistor Rg is connected with a negative auxiliary input end Vnx of the six-input differential amplifier circuit, and the other end of the variable resistor Rg is connected with an output end Vout of the six-input differential amplifier circuit; one end of the fixed resistor Rf receives the common-mode voltage Vcm, and the other end of the fixed resistor Rf is connected to a connection point of the variable resistor Rg and a negative auxiliary input end Vnx of the six-input differential amplifier circuit;

the direct-current coupling differential front-end amplifier circuit can realize different closed-loop gains by changing the resistance value of the variable resistor Rg connected into the variable closed-loop gain circuit.

The technical scheme of the invention has the following beneficial effects: the circuit has certain amplification factor adjusting capability and can improve the transmission signal-to-noise ratio of weak signals. Meanwhile, the electrode polarization offset voltage suppression device has certain electrode polarization offset voltage suppression capability, so that direct current coupling input can be adopted without causing system saturation distortion. By introducing the quick recovery circuit, the problem of low response speed of the amplifier under the condition that the input signal lead wire is disconnected and reconnected can be solved. Therefore, the invention can effectively enhance the sensing and collecting effect of weak bioelectric signals. In addition, the circuit of the invention adopts a single operational amplifier structure, has small system volume and low power consumption, and is easy to integrate and realize under the standard CMOS process.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a schematic structural diagram of a first embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a second embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of a DC offset suppression circuit according to an embodiment of the present invention;

FIG. 4 is a circuit schematic of an embodiment of the invention;

fig. 5 is a circuit schematic of a six input differential difference amplifier circuit in an embodiment of the invention.

Detailed Description

For a more clear understanding of the technical features, objects and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

as shown in fig. 1, the dc-coupled differential front-end amplifier circuit of the present invention includes: a six-input differential amplifier circuit 10, a first DC offset suppression circuit 20, a second DC offset suppression circuit 30, and a closed-loop gain circuit 40, wherein,

the first dc dropout prevention circuit 20 is connected between the first positive input terminal Vpp and the first negative input terminal Vpn of the six-input differential amplifier circuit 10, and a connection point of the first dc dropout prevention circuit 20 and the first positive input terminal Vpp of the six-input differential amplifier circuit 10 is an external signal positive differential input terminal Vip of the dc-coupled differential front-end amplifier circuit; the second dc offset suppression circuit 30 is connected between the second positive input terminal Vnp and the second negative input terminal Vnn of the six-input differential amplifier circuit 10, and a connection point of the second dc offset suppression circuit 30 and the second positive input terminal Vnp of the six-input differential amplifier circuit 10 is an external signal negative differential input terminal Vin of the dc-coupled differential front-end amplifier circuit; the positive auxiliary input end Vpx of the six-input differential amplifier circuit 10 and the closed-loop gain circuit 40 both input a common-mode voltage Vcm, and the negative auxiliary input end Vnx of the six-input differential amplifier circuit 10 is connected with the output end Vout of the six-input differential amplifier circuit 10 through the closed-loop gain circuit 40;

the first dc offset suppression circuit 20 and the second dc offset suppression circuit 30 are used for suppressing the dc offset voltage; the closed-loop gain circuit 40 acts as a negative feedback loop to provide closed-loop gain for the dc-coupled differential front-end amplifier circuit.

The common mode voltage Vcm is a preset dc common mode voltage, and is generally half of the power supply voltage.

The advantages of the inventive solution are illustrated below by comparison with several existing front-end amplifier solutions:

the first scheme is as follows: the front-end unity gain amplification buffer is cascaded and combined with a plurality of amplifiers. The unit gain amplifier is used for providing high input impedance and low output impedance to realize the function of impedance conversion, and the post amplifier realizes the signal amplification of the electrophysiological signals. The amplifier generally employs a conventional two-stage operational amplifier.

The second scheme is as follows: the instrument operational amplifier provides high common mode rejection ratio capability by adopting a three-operational amplifier design structure, and realizes amplification and acquisition of signals.

In the third scheme: the amplifier with larger gain realizes higher gain by adopting resistance feedback of a traditional amplifier or eliminates offset voltage by the aid of a digital circuit.

A fourth scheme: the design of the AC coupling differential input front-end amplifier is the current mainstream design method. Generally, an input capacitance pair mode is adopted to realize alternating current signal coupling input, and a virtual resistor is introduced to a feedback loop to realize high pass of low cut-off frequency so as to eliminate electrode offset voltage.

The four front-end amplifier schemes described above suffer from the following drawbacks:

in the first scheme, the combination of the unity gain buffer and the plurality of amplifiers has the following main technical disadvantages: on the one hand, since the signals are differential inputs, a double buffer is required. This has a very high matching requirement for the buffer and is therefore difficult to do. On the other hand, the combination of a plurality of amplifiers causes problems of an excessive chip area and an excessive power consumption.

In the second scheme, although the instrumentation operational amplifier has very high common mode noise rejection performance, the three-operational amplifier structure usually requires very good operational amplifier matching effect. Off-chip trimming techniques are usually required to achieve better circuit matching, and laser trimming techniques and circuit trimming techniques are generally adopted. The later cost of the chip is higher, and the three-operational amplifier structure circuit is complicated.

In the third scheme, the operational amplifier with a large gain is easily saturated due to the existence of a large direct-current offset voltage in the human electrophysiological signal. Offset voltage cancellation in larger gain amplifiers by the introduction of digital circuitry typically complicates system design and the integration of digital circuitry introduces additional circuit noise.

In the fourth scheme, the amplifier in the scheme is usually implemented in a capacitive feedback mode, and the structure can better eliminate the direct-current offset voltage but has low input impedance and weak signal sensing capability. Meanwhile, the linearity performance of the virtual resistor used on the feedback loop is poor. In addition, monolithic integration is generally not possible due to the large capacitance used when extremely low high-pass cut-off frequencies are achieved.

The front-end amplifier circuit can realize pre-amplification of the electrode sensing signal and can inhibit a certain electrode offset voltage, so that signal distortion caused by the electrode offset voltage cannot occur in the process of pre-amplifying the signal. Based on the front-end amplifier, the bioelectricity signal acquisition system can realize direct current coupling input and has higher input impedance. The anti-interference capability of the bioelectricity signal acquisition system can be effectively improved. The circuit can be further applied to an electric signal acquisition system based on the dry electrode, and meanwhile, the circuit has lower power consumption and low noise performance.

as shown in fig. 2, the dc-coupled differential front-end amplifier circuit of this embodiment further includes a first fast recovery circuit 50 and a second fast recovery circuit 60 on the basis of the first embodiment;

the first fast recovery circuit 50 is connected between the external signal positive differential input terminal Vip of the dc-coupled differential front-end amplifier circuit and the first negative input terminal Vpn of the six-input differential amplifier circuit 10; the second fast recovery circuit 60 is connected between the external signal negative differential input terminal Vin of the dc-coupled differential front-end amplifier circuit and the second negative input terminal Vnn of the six-input differential amplifier circuit 10;

the first fast recovery circuit 50 and the second fast recovery circuit 60 are used to increase the response speed of the dc-coupled differential front-end amplifier circuit in case the external signal input lead is disconnected and reconnected.

as shown in fig. 3, the first dc offset suppression circuit 20 and the second dc offset suppression circuit 30 each include a PMOS transistor M1 and a PMOS transistor M2;

the grid electrode of the PMOS tube M1 is connected with the grid electrode of the PMOS tube M2, the drain electrode of the PMOS tube M1 is connected with the drain electrode of the PMOS tube M2, and the grid electrode connection points of the PMOS tubes M1 and M2 are connected with the drain electrode connection points of the PMOS tubes M1 and M2; in the first constant current leakage suppression circuit 20, the source and the substrate of the PMOS transistor M1 are short-circuited and then connected to the external signal positive differential input terminal Vip, and the source and the substrate of the PMOS transistor M2 are short-circuited and then connected to the first negative input terminal Vpn of the six-input differential amplifier circuit 10; in the second dc offset suppression circuit 30, the source and the substrate of the PMOS transistor M1 are shorted and connected to the negative differential input terminal Vin of the external signal, and the source and the substrate of the PMOS transistor M2 are shorted and connected to the second negative input terminal Vnn of the six-input differential amplifier circuit 10.

FIG. 4 is a circuit schematic of an embodiment of the invention;

as shown in fig. 4, the present invention further provides a circuit structure of the first dc offset suppression circuit 20 and the second dc offset suppression circuit 30 with adjustable high-pass cut-off frequency; in this embodiment, the first dc offset suppression circuit 20 and the second dc offset suppression circuit 30 each include a PMOS transistor M1 and a PMOS transistor M2;

the grid of the PMOS tube M1 is in short circuit with the grid of the PMOS tube M2 and is connected with a bias voltage Vb, the PMOS tube M1 is connected with the drain of the PMOS tube M2, the PMOS tube M1 and the substrate of the PMOS tube M2 are connected together and are connected with the drain connection point of the PMOS tube M1 and the PMOS tube M2; in the first constant current drop suppression circuit 20, the source of the PMOS transistor M1 is connected to the positive differential input terminal Vip of the external signal, and the source of the PMOS transistor M2 is connected to the first negative input terminal Vpn of the six-input differential amplifier circuit 10; in the second dc offset suppression circuit 30, the source of the PMOS transistor M1 is connected to the negative differential input terminal Vin of the external signal, and the source of the PMOS transistor M2 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit 10; the bias voltage Vb is generated by a bias voltage generating circuit;

by adjusting the magnitude of the bias voltage Vb, the high-pass cutoff frequency of the first dc offset suppression circuit 20 and the second dc offset suppression circuit 30 is adjusted.

As shown in fig. 4, the first fast recovery circuit 50 of the present invention includes a MOS transistor M3, and the second fast recovery circuit 60 includes a MOS transistor M4;

the source of the MOS transistor M3 is connected to the negative differential input Vip of the external signal of the dc-coupled differential front-end amplifier circuit, and the drain of the MOS transistor M3 is connected to the first negative input Vpn of the six-input differential amplifier circuit 10; the source of the MOS transistor M4 is connected to the external signal negative differential input terminal Vin of the dc-coupled differential front-end amplifier circuit, and the drain of the MOS transistor M4 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit 10; the grid electrode of the MOS tube M3 and the grid electrode of the MOS tube M4 are both controlled by a control signal SW;

when the external signal input lead wire is disconnected and reconnected, the control signal SW controls the MOS transistor M3 and the MOS transistor M4 to be turned on, and the external signal is transmitted to the six-input differential amplifier circuit 10 with low impedance.

The working principle of the fast recovery circuit is explained in detail below:

the invention realizes the quick discharge of the charges of the high-impedance nodes Vpn and Vnn in the circuit of the invention by introducing two MOS switches controlled by the control signal SW. When the input signal lead wire falls off and then the input of the amplifier is reconnected, the amplifier needs a longer time to realize the stabilization of the output signal due to the existence of the two high-impedance nodes. Therefore, when the above situation is detected, the control signal SW controls the MOS transistors M3 and M4 to be turned on, so that the signals input from the external signal positive differential input terminal Vip and the external signal negative differential input terminal Vin are transmitted to the input terminal of the operational amplifier with low impedance, and the response delay effect caused by the virtual resistance high impedance is avoided, so that the output of the amplifier circuit can be quickly responded and output and is stable.

Further, the closed loop gain circuit 40 of the present invention is a variable closed loop gain circuit that provides an adjustable closed loop gain for the dc-coupled differential front-end amplifier circuit.

As shown in fig. 4, the variable closed-loop gain circuit includes a variable resistor array network Rf and a fixed resistor Rg;

one end of the fixed resistor Rg is connected with the negative auxiliary input end Vnx of the six-input differential amplifier circuit 10, and the other end of the fixed resistor Rg is connected with the output end Vout of the six-input differential amplifier circuit 10; the variable resistor array network Rf is composed of a plurality of resistors with different resistance values, one ends of the plurality of resistors with different resistance values are connected to the common mode voltage Vcm, and the other ends of the plurality of resistors with different resistance values are connected to a connection point of the fixed resistor Rg and the negative auxiliary input end Vnx of the six-input differential amplifier circuit 10 through the selection switch; the selection switch is controlled by a digital control circuit;

the digital control circuit selects the resistance value of the variable resistor array network Rf accessed to the variable closed-loop gain circuit by controlling the selection switch, so that the direct-current coupling differential front-end amplifier circuit realizes different closed-loop gains.

As can be seen from the above circuit configuration, the variable gain of the front-end amplifier of the present invention is realized by the variable feedback resistance network Rf. The scheme is realized by positive and negative auxiliary input ends Vpx and Vnx of a six-input differential amplifier. Vcm is a system common mode level and is connected with positive and negative auxiliary negative input ends Vnx and Vpx of the six-input differential amplifier. Vpx and Vnx are connected with the resistor Rg in series and then are connected with the output end Vout of the six-input differential amplifier to form a system negative feedback loop. The resistor network Rf is connected in series between the negative auxiliary input terminal Vnx and Vcm. The Rg resistance value in the feedback loop is fixed, the resistance Rf can be realized by the resistance array network with different resistance values, and different system amplification factors can be realized by selecting different Rf resistance values through the digital control circuit. The closed loop gain of the system is expressed as:

further, the variable closed-loop gain circuit may also include a fixed resistor Rf and a variable resistor Rg;

one end of the variable resistor Rg is connected with a negative auxiliary input end Vnx of the six-input differential amplifier circuit 10, and the other end of the variable resistor Rg is connected with an output end Vout of the six-input differential amplifier circuit 10; one end of a fixed resistor Rf receives the common mode voltage Vcm, and the other end of the fixed resistor Rf is connected to a connection point of a variable resistor Rg and a negative auxiliary input end Vnx of the six-input differential amplifier circuit 10;

As shown in fig. 5, the six-input differential amplifier circuit 10 includes: the circuit comprises a bias circuit, a multi-input stage circuit, a gain stage circuit and an output stage circuit; wherein the content of the first and second substances,

the bias circuit comprises PMOS tubes Mp1, Mp2 and a bias current source Ib; the source electrode of the PMOS tube Mp1 is connected with the positive power supply terminal Vdd, the drain electrode of the PMOS tube Mp1 is connected with the source electrode of the PMOS tube Mp2, and the source electrode of the PMOS tube Mp2 is connected with the negative power supply terminal Vss through a bias current source Ib; the grid electrode of the PMOS tube Mp1 is in short circuit with the drain electrode, and the grid electrode of the PMOS tube Mp2 is in short circuit with the drain electrode;

the multi-input stage circuit comprises PMOS tubes Mp3, Mp4, Mp5, Mp6, Mp7, Mp8, Mp15, Mp16, Mp17 and NMOS tubes Mn1 and Mn 3; the sources of the PMOS tubes Mp3, Mp6 and Mp15 are all connected with a positive power supply terminal Vdd, and the gates of the PMOS tubes Mp3, Mp6 and Mp15 are in short circuit and connected to the gate of the PMOS tube Mp 1; gates of PMOS transistors Mp7 and Mp8 are respectively used as a first positive input end Vpp and a first negative input end Vpn of the six-input differential amplifier circuit 10, sources of the PMOS transistors Mp7 and Mp8 are connected to a drain of the PMOS transistor Mp6, a drain of the PMOS transistor Mp7 is connected to a drain of the NMOS transistor Mn3, and a drain of the PMOS transistor Mp8 is connected to a drain of the NMOS transistor Mn 1; the gates of the PMOS transistors Mp4 and Mp5 are respectively used as a second negative input end Vnn and a second positive input end Vnp of the six-input differential amplifier circuit 10, the sources of the PMOS transistors Mp4 and Mp5 are connected to the drain of the PMOS transistor Mp3, the drain of the PMOS transistor Mp4 is connected to the drain of the NMOS transistor Mn3, and the drain of the PMOS transistor Mp5 is connected to the drain of the NMOS transistor Mn 1; the gates of the PMOS transistors Mp16 and Mp17 are respectively used as a negative auxiliary input end Vnx and a positive auxiliary input end Vpx of the six-input differential amplifier circuit 10, the sources of the PMOS transistors Mp16 and Mp17 are connected to the drain of the PMOS transistor Mp15, the drain of the PMOS transistor Mp16 is connected to the drain of the NMOS transistor Mn1, and the drain of the PMOS transistor Mp17 is connected to the drain of the NMOS transistor Mn 3; the grid electrode of the NMOS transistor Mn1 is in short circuit with the drain electrode, the grid electrode of the NMOS transistor Mn3 is in short circuit with the drain electrode, and the source electrodes of the NMOS transistors Mn1 and Mn3 are both connected to the negative power supply terminal Vss;

the gain stage circuit comprises PMOS tubes Mp9, Mp10, Mp11, Mp12, Mp13 and NMOS tubes Mn2, Mn4, Mn5 and Mn 6; the PMOS tubes Mp9 and Mp10 form an active current mirror as a load, the grid electrode and the drain electrode of the PMOS tube Mp10 are connected with the grid electrode of the PMOS tube Mp9 after being in short circuit, the drain electrode of the PMOS tube Mp9 is connected with the drain electrode of the NMOS tube Mn4, and the drain electrode of the PMOS tube Mp10 is connected with the drain electrode of the NMOS tube Mn 2; the NMOS transistor Mn2 and the NMOS transistor Mn1 in the multi-input stage circuit form a current mirror circuit, the grid electrode of the NMOS transistor Mn2 is connected with the grid electrode of the NMOS transistor Mn1, and the source electrode of the NMOS transistor Mn2 is connected to the negative power supply terminal Vss; the NMOS transistor Mn4 and the NMOS transistor Mn3 in the multi-input stage circuit form a current mirror circuit, the grid electrode of the NMOS transistor Mn4 is connected with the grid electrode of the NMOS transistor Mn3, and the source electrode of the NMOS transistor Mn4 is connected to the negative power supply terminal Vss; PMOS tubes Mp11, Mp12 and Mp13 and NMOS tubes Mn5 and Mn6 form a first-order amplifier structure, the grid electrode of the PMOS tube Mp11 is connected with the grid electrode of a PMOS tube Mp1 in a bias circuit to form a current source, the grid electrodes of the PMOS tubes Mp12 and Mp13 are respectively connected with the drain electrodes of the PMOS tubes Mp9 and Mp10, the source electrodes of the PMOS tubes Mp12 and Mp13 are connected with the drain electrode of the PMOS tube Mp11, and the drain electrodes of the PMOS tubes Mp12 and Mp13 are respectively connected with the drain electrodes of the NMOS tubes Mn5 and Mn 6; an active current mirror is formed by the NMOS tubes Mn5 and Mn6 and serves as a load, the grid electrode and the drain electrode of the NMOS tube Mn5 are connected with the grid electrode of the NMOS tube Mn6 after being in short circuit, and the source electrodes of the NMOS tubes Mn5 and Mn6 are connected to the negative end Vss of a power supply;

the output stage circuit comprises a PMOS tube Mp14 and an NMOS tube Mn 7; the grid electrode of the PMOS tube Mp14 is connected with the grid electrode of the PMOS tube Mp1 in the bias circuit to form a mirror current source, the source electrode of the PMOS tube Mp14 is connected with the positive end Vdd of a power supply, and the drain electrode of the PMOS tube Mp14 is connected with the drain electrode of the NMOS tube Mn 7; the grid electrode of the NMOS tube Mn7 is connected with the drain electrode of the NMOS tube Mn6, and the source electrode of the NMOS tube Mn7 is connected to the negative power supply terminal Vss; the connection point of the drain of the PMOS transistor Mp14 and the drain of the NMOS transistor Mn7 serves as the output terminal Vout of the six-input differential amplifier circuit 10.

As can be seen from the above circuit configuration of the six-input differential amplifier circuit 10, the circuit is characterized by a multistage amplifier having six input terminals and one output. Just because of its six inputs, three equivalent subtractors (Vpn-Vpp, Vnp-Vnn, Vpx-Vnx) can be constructed for implementing the dc offset voltage suppression scheme and the adjustable system feedback gain scheme in the scheme of the present invention.

It is understood that the NMOS transistor and the PMOS transistor in the six-input differential amplifier circuit 10 can be used in a completely reversed manner, for example, the input transistor in the circuit can use an NMOS transistor input, and the PMOS current source can use an NMOS mirror current source in a reversed manner.

Further, the six-input differential amplifier circuit 10 further includes a miller compensation resistance-capacitance circuit 101;

the miller compensation resistor-capacitor circuit 101 comprises a resistor R and a capacitor C, wherein the resistor R and the capacitor C are connected in series between the gate of the PMOS transistor Mp13 and the output terminal Vout of the six-input differential amplifier circuit 10;

the miller compensation rc circuit 101 provides phase margin compensation for the six-input differential amplifier circuit 10, further improving the stability of the system.

The operation principle of the dc offset suppression circuit 20 and the second dc offset suppression circuit 30 in the circuit of the present invention will be described in detail with reference to fig. 4 and 5.

The PMOS transistors M1 and M2 in fig. 4 form a virtual resistor Rp in a diode connection manner, and the virtual resistor Rp has a very large equivalent resistance, such as a resistance of one G ohm, several G ohms, or even several tens of G ohms. The first negative input terminal Vpn of the six-input differential amplifier circuit 10 employs a MOS transistor (for example, a PMOS transistor Mp8 in fig. 5) having a parasitic capacitance Cg. The virtual resistor formed by the PMOS transistors M1 and M2 and the parasitic capacitor Cg of the PMOS transistor Mp8 form an equivalent integrating circuit, i.e. an equivalent low-pass filter circuit. The equivalent integral constant is tau-R_pC_g. The first positive and negative input terminals Vpp and Vpn of the six-input differential amplifier circuit 10 form a differential subtractor, i.e., Vpp-Vpn, by which the input signals Vip and Vip are subtracted from each other through a virtual resistor Rp formed by PMOS transistors M1 and M2, thereby implementing a high-pass filter with a cut-off frequency of τ -R_pC_gDetermine the frequency of

Since the equivalent resistance value of the dummy resistance Rp is extremely large, the input stage of the six-input differential amplifier circuit 10 can obtain a high-pass filter characteristic with an extremely low cutoff frequency as low as mHz. By using the circuit structure, the DC offset voltage can be filtered by the equivalent high-pass filtering functionTherefore, the suppression of the direct-current offset voltage is realized.

Further, the principle of the high-pass cut-off frequency adjustable scheme of the invention is as follows: by setting different bias voltages Vb, the magnitude of the virtual resistor Rp formed by the PMOS transistors M1 and M2 can be adjusted, and therefore the integral constant τ R can be adjusted_pC_gSo as to adjust the high-pass cut-off frequency for filtering the direct-current offset voltage.

The invention realizes adjustable amplification factor through the closed-loop gain circuit 40 with variable closed-loop gain, and improves the transmission signal-to-noise ratio of weak signals; electrode polarization offset voltage suppression is achieved by the first and second dc offset

suppression circuits

20 and 30, and thus dc-coupled input can be used without causing system saturation distortion. The problem of slow amplifier response in the event of an input signal lead drop reconnect is solved by first and second

fast recovery circuits

50 and 60. Therefore, the invention can effectively enhance the sensing and collecting effect of weak bioelectric signals. In addition, the six-input differential amplifier circuit 10 with the single operational amplifier structure has the advantages of smaller size, lower power consumption, easy integration and realization in a standard CMOS process, small occupied chip area and low cost. The method can be applied to an analog front-end chip of a multi-channel signal.

It should be further noted that although the present invention is provided in the context of bioelectrical signal acquisition, the circuit structure of the present invention is not limited to the field of bioelectrical signal acquisition. The design method and the circuit structure can also be applied to other sensing circuits and signal acquisition systems of weak electric signals.

While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A dc-coupled differential front-end amplifier circuit, comprising: a six-input differential amplifier circuit (10), a first DC offset suppression circuit (20), a second DC offset suppression circuit (30), and a closed-loop gain circuit (40),

the first loss modulation suppression circuit (20) is connected between a first positive input end Vpp and a first negative input end Vpn of the six-input differential amplifier circuit (10), and a connection point of the first loss modulation suppression circuit (20) and the first positive input end Vpp of the six-input differential amplifier circuit (10) is an external signal positive differential input end Vip of the dc-coupled differential front-end amplifier circuit; the second dc offset suppression circuit (30) is connected between the second positive input terminal Vnp and the second negative input terminal Vnn of the six-input differential amplifier circuit (10), and a connection point of the second dc offset suppression circuit (30) and the second positive input terminal Vnp of the six-input differential amplifier circuit (10) is an external signal negative differential input terminal Vin of the dc-coupled differential front-end amplifier circuit; a common-mode voltage Vcm is input to a positive auxiliary input end Vpx of the six-input differential amplifier circuit (10) and the closed-loop gain circuit (40), and a negative auxiliary input end Vnx of the six-input differential amplifier circuit (10) is connected with an output end Vout of the six-input differential amplifier circuit (10) through the closed-loop gain circuit (40);

the first direct current offset suppression circuit (20) and the second direct current offset suppression circuit (30) are used for suppressing direct current offset voltage; the closed-loop gain circuit (40) serves as a negative feedback loop to provide closed-loop gain for the direct-current coupling differential front-end amplifier circuit.

2. The dc-coupled differential front-end amplifier circuit according to claim 1, wherein the six-input differential amplifier circuit (10) comprises: the circuit comprises a bias circuit, a multi-input stage circuit, a gain stage circuit and an output stage circuit; wherein the content of the first and second substances,

the multi-input stage circuit comprises PMOS tubes Mp3, Mp4, Mp5, Mp6, Mp7, Mp8, Mp15, Mp16, Mp17 and NMOS tubes Mn1 and Mn 3; the sources of the PMOS tubes Mp3, Mp6 and Mp15 are all connected with the positive power supply terminal Vdd, and the gates of the PMOS tubes Mp3, Mp6 and Mp15 are shorted and connected to the gate of the PMOS tube Mp 1; the gates of the PMOS transistors Mp7 and Mp8 are respectively used as a first positive input end Vpp and a first negative input end Vpn of the six-input differential amplifier circuit (10), the sources of the PMOS transistors Mp7 and Mp8 are connected to the drain of the PMOS transistor Mp6, the drain of the PMOS transistor Mp7 is connected to the drain of the NMOS transistor Mn3, and the drain of the PMOS transistor Mp8 is connected to the drain of the NMOS transistor Mn 1; the gates of the PMOS transistors Mp4 and Mp5 are respectively used as a second negative input end Vnn and a second positive input end Vnp of the six-input differential amplifier circuit (10), the sources of the PMOS transistors Mp4 and Mp5 are connected to the drain of the PMOS transistor Mp3, the drain of the PMOS transistor Mp4 is connected to the drain of the NMOS transistor Mn3, and the drain of the PMOS transistor Mp5 is connected to the drain of the NMOS transistor Mn 1; the gates of the PMOS tubes Mp16 and Mp17 are respectively used as a negative auxiliary input end Vnx and a positive auxiliary input end Vpx of the six-input differential amplifier circuit (10), the sources of the PMOS tubes Mp16 and Mp17 are connected to the drain of the PMOS tube Mp15, the drain of the PMOS tube Mp16 is connected with the drain of the NMOS tube Mn1, and the drain of the PMOS tube Mp17 is connected with the drain of the NMOS tube Mn 3; the grid electrode of the NMOS transistor Mn1 is in short circuit with the drain electrode, the grid electrode of the NMOS transistor Mn3 is in short circuit with the drain electrode, and the source electrodes of the NMOS transistors Mn1 and Mn3 are both connected to the negative power supply terminal Vss;

the output stage circuit comprises a PMOS tube Mp14 and an NMOS tube Mn 7; the grid electrode of the PMOS tube Mp14 is connected with the grid electrode of a PMOS tube Mp1 in the bias circuit to form a mirror current source, the source electrode of the PMOS tube Mp14 is connected with a positive power supply terminal Vdd, and the drain electrode of the PMOS tube Mp14 is connected with the drain electrode of the NMOS tube Mn 7; the gate of the NMOS transistor Mn7 is connected with the drain of the NMOS transistor Mn6, and the source of the NMOS transistor Mn7 is connected to the negative power supply terminal Vss; the connection point of the drain of the PMOS tube Mp14 and the drain of the NMOS tube Mn7 is used as the output end Vout of the six-input differential amplifier circuit (10).

3. The dc-coupled differential front-end amplifier circuit according to claim 2, wherein the six-input differential amplifier circuit (10) further comprises a miller-compensated resistor-capacitor circuit;

the Miller compensation resistor-capacitor circuit comprises a resistor R and a capacitor C, wherein the resistor R and the capacitor C are connected between the grid of the PMOS tube Mp13 and the output end Vout of the six-input differential amplifier circuit (10) in series;

the miller compensation rc circuit provides phase margin compensation for the six-input differential amplifier circuit (10).

4. The dc-coupled differential front-end amplifier circuit according to claim 1, wherein the first dc offset suppression circuit (20) and the second dc offset suppression circuit (30) each comprise a PMOS transistor M1, a PMOS transistor M2;

the grid electrode of the PMOS tube M1 is connected with the grid electrode of the PMOS tube M2, the drain electrode of the PMOS tube M1 is connected with the drain electrode of the PMOS tube M2, and the grid electrode connection points of the PMOS tubes M1 and M2 are connected with the drain electrode connection points of the PMOS tubes M1 and M2; in the first constant current drain suppression circuit (20), the source and the substrate of the PMOS transistor M1 are connected to the external signal positive differential input end Vip after being short-circuited, and the source and the substrate of the PMOS transistor M2 are connected to the first negative input end Vpn of the six-input differential amplifier circuit (10) after being short-circuited; in the second direct current offset suppression circuit (30), the source and the substrate of the PMOS transistor M1 are connected to the external signal negative differential input terminal Vin after being short-circuited, and the source and the substrate of the PMOS transistor M2 are connected to the second negative input terminal Vnn of the six-input differential amplifier circuit (10) after being short-circuited.

5. The dc-coupled differential front-end amplifier circuit according to claim 1, wherein the high-pass cut-off frequency of the first dc offset suppression circuit (20) and the second dc offset suppression circuit (30) is adjustable; the first direct current offset suppression circuit (20) and the second direct current offset suppression circuit (30) both comprise a PMOS tube M1 and a PMOS tube M2;

the grid electrode of the PMOS tube M1 and the grid electrode of the PMOS tube M2 are in short circuit and are connected with a bias voltage Vb, the PMOS tube M1 is connected with the drain electrode of the PMOS tube M2, and the PMOS tube M1 and the substrate of the PMOS tube M2 are connected together and are connected to the drain electrode connection point of the PMOS tube M1 and the PMOS tube M2; in the first constant current drop suppression circuit (20), the source of the PMOS transistor M1 is connected to the external signal positive differential input terminal Vip, and the source of the PMOS transistor M2 is connected to the first negative input terminal Vpn of the six-input differential amplifier circuit (10); in the second dc offset suppression circuit (30), the source of the PMOS transistor M1 is connected to the external signal negative differential input terminal Vin, and the source of the PMOS transistor M2 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit (10); the bias voltage Vb is generated by a bias voltage generating circuit;

and adjusting the high-pass cut-off frequency of the first direct current offset suppression circuit (20) and the second direct current offset suppression circuit (30) by adjusting the magnitude of the bias voltage Vb.

6. The dc-coupled differential front-end amplifier circuit according to claim 1, further comprising a first fast recovery circuit (50) and a second fast recovery circuit (60);

the first fast recovery circuit (50) is connected between an external signal positive differential input terminal Vip of the dc-coupled differential front-end amplifier circuit and a first negative input terminal Vpn of the six-input differential amplifier circuit (10); the second fast recovery circuit (60) is connected between the external signal negative differential input Vin of the dc-coupled differential front-end amplifier circuit and the second negative input Vnn of the six-input differential amplifier circuit (10);

the first fast recovery circuit (50) and the second fast recovery circuit (60) are used for improving the response speed of the direct current coupling differential front-end amplifier circuit under the condition that an external signal input lead wire is disconnected and reconnected.

7. The dc-coupled differential front-end amplifier circuit according to claim 6, wherein the first fast recovery circuit (50) comprises a MOS transistor M3, and the second fast recovery circuit (60) comprises a MOS transistor M4;

the source electrode of the MOS tube M3 is connected with the external signal negative differential input end Vip of the direct current coupling differential front-end amplifier circuit, and the drain electrode of the MOS tube M3 is connected with the first negative input end Vpn of the six-input differential amplifier circuit (10); the source electrode of the MOS tube M4 is connected with the external signal negative differential input end Vin of the DC coupling differential front-end amplifier circuit, and the drain electrode of the MOS tube M4 is connected with the second negative input end Vnn of the six-input differential amplifier circuit (10); the grid electrode of the MOS transistor M3 and the grid electrode of the MOS transistor M4 are both controlled by a control signal SW;

when the external signal input lead wire is disconnected and reconnected, the control signal SW controls the MOS tube M3 and the MOS tube M4 to be conducted, and external signals are transmitted to the six-input differential amplifier circuit (10) in a low-impedance mode.

8. The dc-coupled differential front-end amplifier circuit according to claim 1, wherein the closed-loop gain circuit (40) is a variable closed-loop gain circuit that provides an adjustable closed-loop gain for the dc-coupled differential front-end amplifier circuit.

9. The dc-coupled differential front-end amplifier circuit of claim 8, wherein the variable closed-loop gain circuit comprises a variable resistor array network Rf and a fixed resistor Rg;

one end of the fixed resistor Rg is connected with a negative auxiliary input end Vnx of the six-input differential amplifier circuit (10), and the other end of the fixed resistor Rg is connected with an output end Vout of the six-input differential amplifier circuit (10); the variable resistor array network Rf is composed of a plurality of resistors with different resistance values, one ends of the resistors with different resistance values are connected and connected with a common mode voltage Vcm, and the other ends of the resistors with different resistance values are connected to a connection point of the fixed resistor Rg and a negative auxiliary input end Vnx of the six-input differential amplifier circuit (10) through a selection switch; the selection switch is controlled by a digital control circuit;

10. The dc-coupled differential front-end amplifier circuit of claim 8, wherein the variable closed-loop gain circuit comprises a fixed resistor Rf and a variable resistor Rg;

one end of the variable resistor Rg is connected with a negative auxiliary input end Vnx of the six-input differential amplifier circuit (10), and the other end of the variable resistor Rg is connected with an output end Vout of the six-input differential amplifier circuit (10); one end of the fixed resistor Rf receives the common-mode voltage Vcm, and the other end of the fixed resistor Rf is connected to a connection point of the variable resistor Rg and a negative auxiliary input end Vnx of the six-input differential amplifier circuit (10);