CN110755046B - Front-end analog circuit and front-end analog chip for neuroelectrophysiology detection - Google Patents
Front-end analog circuit and front-end analog chip for neuroelectrophysiology detection Download PDFInfo
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/25—Bioelectric electrodes therefor
- A61B5/279—Bioelectric electrodes therefor specially adapted for particular uses
- A61B5/291—Bioelectric electrodes therefor specially adapted for particular uses for electroencephalography [EEG]
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/25—Bioelectric electrodes therefor
- A61B5/279—Bioelectric electrodes therefor specially adapted for particular uses
- A61B5/296—Bioelectric electrodes therefor specially adapted for particular uses for electromyography [EMG]
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/30—Input circuits therefor
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
- A61B5/7203—Signal processing specially adapted for physiological signals or for diagnostic purposes for noise prevention, reduction or removal
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
- A61B5/7225—Details of analog processing, e.g. isolation amplifier, gain or sensitivity adjustment, filtering, baseline or drift compensation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
Abstract
The utility model belongs to the technical field of the detection of neuro-electrophysiology, a front end analog circuit and front end analog chip for the detection of neuro-electrophysiology are provided, amplify the processing through the signal of a plurality of signal detection passageway to the signal of detecting electrode input, the synchronous detection of a plurality of channel signals has been realized, and generate lead shielded wire drive signal and right leg drive signal based on the common mode signal among a plurality of signal detection passageways through right leg drive module, thereby realize the suppression to common mode noise, the noise that has solved current detection of neuro-electrophysiology circuit existence is higher, the complicated scheduling problem of structure.
Description
Technical Field
The application belongs to the technical field of neuro-electrophysiology detection, and particularly relates to a front-end analog circuit and a front-end analog chip for neuro-electrophysiology detection.
Background
Electroencephalogram (EEG) signals and electromyogram signals (EMG) are common human neuroelectrophysiological signals, for example, the EEG signals are mainly used for identifying the consciousness state of the brain of a human, the electromyogram signals (EMG) are the superposition of a Motor Unit Action Potential (MUAP) in a plurality of muscle fibers on time and space, and surface electromyogram Signals (SEMG) are the comprehensive effect of electrical activity on the skin surface of superficial muscle EMG and nerve trunk, and can reflect the activity of the neuromuscular to a certain extent. Therefore, the neuroelectrophysiological signals have important practical values in clinical medicine, human-computer efficiency, rehabilitation medicine, sports science and the like.
However, the existing neuroelectrophysiological signal detection circuit does not have a special chip, has the problems of high noise, complex structure and the like, and greatly influences the wearable application of the detection system.
Disclosure of Invention
The application aims to provide a front-end analog circuit and a front-end analog chip for neuroelectrophysiology detection, and aims to solve the problems of high noise, complex structure and the like of the existing neuroelectrical signal detection circuit.
The embodiment of the application provides a front end analog circuit, with a plurality of detection electrode and right leg electrode connection, front end analog circuit includes:
the signal detection channels are connected with the detection electrodes in a one-to-one correspondence mode and used for amplifying signals input by the detection electrodes;
the right leg driving module is connected with the signal detection channels and is used for generating a lead shielding line driving signal and a right leg driving signal according to a common-mode signal in the signal detection channels; and
the power supply management module is connected with the plurality of signal detection channels and the right leg driving module and is used for supplying power to the signal detection circuit;
the right leg driving signal is fed back to the surface of the skin of the human body through the right leg electrode so as to inhibit common mode noise.
Optionally, the signal detection channel includes:
an input buffer circuit for providing an input impedance to a port connected to the detection electrode;
a preamplifier circuit for performing differential amplification processing on the signal output by the input buffer circuit;
the gain adjustable amplifier circuit is used for amplifying the differential signal output by the preamplifier circuit and converting the differential signal from a double-end differential form into a single-end output signal;
the band-pass filter circuit is used for filtering low-frequency signals and high-frequency interference noise in the single-ended output signals;
and the output buffer circuit is used for providing output driving capability for the signal output by the band-pass filter circuit.
Optionally, the front-end analog circuit further includes a plurality of gain control signal sources, which are used to adjust the amplification factor of the gain-adjustable amplifier circuit.
Optionally, the band-pass filter circuit includes a first capacitor and a low-pass filter, and the first capacitor is disposed between the low-pass filter and the gain-adjustable amplifier circuit;
the first capacitor is used for filtering low-frequency interference noise in the single-ended output signal; the low-pass filter is used for filtering high-frequency interference noise in the single-ended output signal.
Optionally, a programmable gain amplifier circuit is further disposed between the band-pass filter circuit and the output buffer circuit, and the programmable gain amplifier circuit amplifies the single-ended output signal based on an external control signal.
Optionally, the power management module includes a bandgap reference circuit for providing a reference voltage signal and a reference current signal, a low dropout regulator, a first switching tube, a first resistor, and a second resistor;
the reference voltage output end of the band-gap reference circuit is connected with the first input end of the low-dropout linear voltage regulator, the output end of the low-dropout linear voltage regulator is connected with the control end of the first switch tube, the current input end of the first switch tube is connected with an external voltage source, the current output end of the first switch tube and the first end of the first resistor are connected together to serve as the power supply voltage output end of the power supply management module, the second end of the first resistor and the first end of the second resistor are connected together to the second input end of the low-dropout linear voltage regulator, and the second end of the second resistor is grounded.
Optionally, the preamplifier circuit includes: the transconductance operational amplifier, the second switching tube, the third switching tube, the fourth switching tube, the fifth switching tube, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor;
the first end of the second capacitor is connected to the first output end of the input buffer circuit, the second end of the second capacitor, the first end of the third capacitor, the first input end of the transconductance operational amplifier, the control end of the second switch tube and the current output end of the second switch tube are connected in common, the current input end of the second switch tube, the current output end of the third switch tube and the control end of the third switch tube are connected in common, the current input end of the third switch tube, the second end of the third capacitor and the first output end of the transconductance operational amplifier are connected in common to the first input end of the gain-adjustable amplifier circuit, the first end of the fourth capacitor is connected to the second output end of the input buffer circuit, the second end of the fourth capacitor, the first end of the fifth capacitor, the second input end of the transconductance operational amplifier, The control end of the fourth switching tube and the current output end of the fourth switching tube are connected in common, the current input end of the fourth switching tube, the control end of the fifth switching tube and the current output end of the fifth switching tube are connected in common, and the current input end of the fifth switching tube, the second end of the fifth capacitor and the second output end of the transconductance operational amplifier are connected in common to the second input end of the gain-adjustable amplifier circuit.
Optionally, the gain-adjustable amplifier circuit includes: the power amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a sixth switching tube, a seventh switching tube, an eighth switching tube and a ninth switching tube;
a first end of the third resistor is connected to a first output end of the preamplifier circuit, a first end of the fourth resistor is connected to a second output end of the preamplifier circuit, a second end of the third resistor, a first input end of the power amplifier, a first end of the fifth resistor, a first end of the sixth resistor, and a first end of the seventh resistor are connected in common, a second end of the fifth resistor is connected to a current output end of the sixth switching tube, a control end of the sixth switching tube is connected to the gain control signal source, a second end of the sixth resistor is connected to a current output end of the seventh switching tube, a control end of the seventh switching tube is connected to the gain control signal source, a current input end of the sixth switching tube, a current input end of the seventh switching tube, a second end of the seventh resistor, and an output end of the power amplifier are connected in common to an input end of the band-pass filter circuit, the second end of the fourth resistor, the first end of the eighth resistor, the first end of the ninth resistor and the first end of the tenth resistor are connected to the second input end of the power amplifier, the second end of the ninth resistor is connected to the current output end of the eighth switch tube, the second end of the tenth resistor is connected to the current output end of the ninth switch tube, the control end of the eighth switch tube is connected to the gain control signal source, the control end of the ninth switch tube is connected to the gain control signal source, and the current input end of the eighth switch tube, the current input end of the ninth switch tube and the second end of the eighth resistor are connected to the power management module.
Optionally, the right leg driving module is composed of a buffer and an inverting amplifier circuit, where the buffer generates a lead shielding line driving signal according to a common-mode signal provided by the plurality of signal detection channels, and the inverting amplifier circuit performs inverting amplification filtering processing on the lead shielding line driving common-mode signal to generate a right leg driving signal.
The embodiment of the application also provides a front-end analog chip for neuroelectrophysiology detection, which comprises a plurality of detection electrodes, a right leg electrode and the front-end analog circuit, wherein the front-end analog circuit is respectively connected with a plurality of pairs of the detection electrodes and the right leg electrode.
In the front-end analog circuit and the front-end analog chip provided by the application, signals input by the detection electrodes are amplified through the multiple signal detection channels, synchronous detection of the multiple channel signals is realized, lead shielding line driving signals and right leg driving signals are generated through the right leg driving module based on common-mode signals in the multiple signal detection channels, inhibition of common-mode noise is realized, and the problems that the existing nerve electrical signal detection circuit is high in noise, complex in structure and the like are solved.
Drawings
Fig. 1 is a schematic circuit diagram of a front-end analog circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic circuit diagram of a signal detection channel according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of another signal detection channel according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of another signal detection channel according to an embodiment of the present disclosure;
fig. 5 is a schematic circuit diagram of a power management module according to an embodiment of the present disclosure;
FIG. 6 is a schematic circuit diagram of a preamplifier circuit according to an embodiment of the present application;
fig. 7 is a schematic circuit diagram of a gain adjustable amplifier circuit according to an embodiment of the present application;
fig. 8 is a schematic diagram of EEG signal detection using a front-end analog chip according to an embodiment of the present application;
fig. 9 is a schematic diagram of EMG signal detection using a front-end analog chip according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
The embodiment of the application provides a front end analog circuit, this front end analog circuit and a plurality of detecting electrode and right leg electrode connection, front end analog circuit includes: the signal detection channels are connected with the detection electrodes in a one-to-one correspondence mode and used for amplifying signals input by the detection electrodes; the right leg driving module is connected with the signal detection channels and used for generating lead shielding line driving signals and right leg driving signals according to common-mode signals in the signal detection channels; the power management module is connected with the plurality of signal detection channels and the right leg driving module and is used for supplying power to the signal detection circuit; the right leg driving signal is fed back to the surface of the skin of the human body through the right leg electrode so as to inhibit common mode noise.
In this embodiment, the front-end analog circuit in this embodiment adopts a plurality of signal detection channels to amplify signals provided by a plurality of detection electrodes, so as to implement synchronous detection of signals of the plurality of channels, and the amplification factor in each signal detection channel may be set based on user needs, for example, the amplification factor of each signal detection channel is adjusted by increasing a gain control signal. Further, in this embodiment, the lead shielding line driving common mode signal and the right leg driving signal are generated by the right leg driving circuit, and the right leg driving signal is fed back to the skin surface of the user by the right leg driving electrode, so as to suppress the common mode noise.
In this embodiment, the right leg driving circuit generates the lead shielding line driving signal, which can also reduce the leakage current between the lead wire and the shielding line, ensure the safety of the patient, and improve the input impedance of the circuit. Because distributed capacitance exists between the lead wire and the shielding wire, capacitance reactance presented to 50Hz signals is several megaohms, if the shielding wire is directly grounded, the capacitance reactance and the input impedance of the input circuit are in a parallel state, the input impedance of the whole machine is greatly reduced, leakage current from a human body to the ground is increased, and the safety factor is reduced. The lead shielding line is used for driving a signal to provide higher input impedance, so that the equipotential between the shielding line and a signal ground is ensured, and the shielding ground is skillfully isolated from the signal ground, thereby keeping the advantage that an input circuit has high input impedance.
In this embodiment, when the front-end analog circuit is integrated in a chip, the input mode of the chip may be set by a control signal provided outside the chip, when the input mode is a single-electrode mode, each channel is connected to only one detection electrode and is connected to an input positive terminal, a common-mode signal output by the signal detection channel is generated by a signal collected by the positive terminal, and the common-mode signal is connected to an input negative terminal of the chip through outside the chip; when the input mode is a double-electrode mode, each channel is connected with two detection electrodes and respectively connected with the positive and negative ends, and the common-mode signal is generated by signals collected by the positive and negative ends.
In an embodiment, fig. 1 is a schematic structural diagram of a front-end analog circuit provided in this embodiment, and referring to fig. 1, the front-end analog circuit in this embodiment includes four signal detection channels 10, where each signal detection channel 10 is connected to an external control signal source, and sets a gain multiple of the signal detection channel based on an external control signal SEL _ PGA provided by the external control signal source. The leg driving module RLD generates a common mode signal CM _ DRV, a lead shielding line driving signal SHLD _ DRV and a right leg driving signal RLD _ DRV based on the signals collected by the four signal detection channels 10, and feeds back the right leg driving signal RLD _ DRV to the skin surface of the user through the right leg driving electrode, thereby suppressing the common mode noise. Meanwhile, the source of the common-mode signal is set through an external control signal SEL _ CM, and when the common-mode signal is provided by an input anode end and an input cathode end, the chip is in a double-electrode input mode; when the common-mode signal is only provided by the input positive terminal, the chip is in a single-electrode input mode. The power management module 20 is used for providing a power voltage, a reference voltage and a reference current for the four signal detection channels 10.
In one embodiment, the right leg driving module RLD is composed of a buffer and an inverting amplifier circuit, wherein the buffer generates a lead shielding line driving signal according to a common mode signal provided by a plurality of signal detection channels, and the inverting amplifier circuit performs an inverting amplification filtering process on the lead shielding line driving signal to generate a right leg driving signal.
For example, in one embodiment, referring to fig. 1, the right leg driving module RLD includes: eight current-limiting resistors R0, a buffer BUF1, an eleventh resistor R11, a twelfth resistor R12, a fifth capacitor C5 and an inverting amplifier IA; first ends of the eight current-limiting resistors R0 are respectively connected to a plurality of signal detection channels in a one-to-one correspondence manner, second ends of the eight current-limiting resistors R0 are commonly connected to an input end of the buffer BUF1 and serve as a common-mode signal output end CM _ DRV, an output end of the buffer BUF1 and a first end of the eleventh resistor R11 are commonly connected to serve as a lead shielded line driving signal output end SHLD _ DRV of the front-end analog circuit, a second end of the eleventh resistor R11, a first end of the twelfth resistor R12 and a first end of the fifth capacitor C5 are commonly connected to a first input end of the inverting amplifier IA, a second input end of the inverting amplifier IA is externally connected, and a second end of the fifth capacitor C5 and a second end of the twelfth resistor R12 and an output end of the inverting amplifier IA are commonly connected to serve as a right leg driving signal output end d _ DRV of the front-end analog circuit.
In the present embodiment, each channel is connected to a pair of detection electrodes for collecting a neuroelectrophysiological signal, such as an electroencephalogram (EEG) signal and an Electromyogram (EMG) signal. Meanwhile, the source of the common mode signal CM _ DRV is set through the external control signal SEL _ CM, for example, the switch K1 is controlled through the external control signal SEL _ CM, when the external control signal SEL _ CM controls the switch K1 to be closed, the common mode signal CM _ DRV is provided by the input positive and negative terminals of the channel, and at this time, the input mode of the chip is a dual-electrode input mode; when the external control signal SEL _ CM controls the switch K1 to be turned off, the input mode of the chip is the single-electrode input mode when the common-mode signal CM _ DRV is provided only by the input positive terminal.
In one embodiment, referring to fig. 2, the signal detection channel 10 comprises: an input buffer circuit 11 for providing an input impedance to a port connected to the detection electrode; a preamplifier circuit 12 for performing differential amplification processing on the signal output from the input buffer circuit 11; the gain adjustable amplifier circuit 13 is configured to amplify the differential signal output by the preamplifier circuit 12, and convert the differential signal from a double-ended differential form to a single-ended output signal; a band-pass filter circuit 14 for filtering low-frequency signals and high-frequency interference noise in the single-ended output signal; and an output buffer circuit 15 for providing an output driving capability to the signal output from the band pass filter circuit 14.
In the present embodiment, the circuit structures of the plurality of signal detection channels 10 are the same, and as shown in fig. 2, the input buffer circuit 11, the preamplifier circuit 12, the gain adjustable amplifier circuit 13, the band pass filter circuit 14 and the output buffer circuit 15 in each signal detection channel 10 are connected in sequence, wherein the input buffer circuit 11 provides a high input impedance for the port connected to the detection electrode, the preamplifier circuit 12 performs a differential amplification process on the signal output by the input buffer circuit 11, the gain adjustable amplifier circuit 13 performs an amplification process on the differential signal output by the preamplifier circuit 12 and converts the differential signal from a double-ended differential form into a single-ended output signal, then the band pass filter circuit 14 filters low-frequency and high-frequency interference noise in the single-ended output signal, and finally the output buffer circuit 15 provides an output driving capability for the signal output by the band pass filter circuit 14, therefore, signal acquisition and signal amplification of each signal detection channel are realized.
In one embodiment, the front-end analog circuit further includes a plurality of gain control signal sources for adjusting the amplification factor of the gain-adjustable amplifier circuit 13. In this embodiment, the gain-adjustable amplifier circuit 13 may be implemented by a high-gain operational amplifier resistor negative feedback form, and the resistance value of the feedback resistor is adjusted by the gain control signals generated by the plurality of gain control signal sources, so as to adjust the amplification factor of the gain-adjustable amplifier circuit 13.
For example, in an embodiment, fig. 3 is a schematic diagram of the signal detection channel 1 provided in this embodiment, and referring to fig. 3, the gain adjustable amplifier circuit 13 receives the gain control signals provided by the gain control signal source ENA and the gain control signal source ENB to adjust the resistance of the feedback resistor, so as to adjust the amplification factor thereof, the input buffer circuit 11 includes two buffers BUF, the input terminals of the two buffers BUF are respectively connected to the detection electrodes, and provide high input impedance for the ports VN1 and VP1 connected to the detection electrodes, the input buffer circuit 11 can be implemented by an operational amplifier unit negative feedback form, in which the output terminals of the two buffers BUF are respectively connected to the two input terminals of the preamplifier circuit 12, for example, the output terminals of the two buffers BUF are respectively connected to the two input terminals of the amplifier PA in the preamplifier circuit 12, further, the output terminals VN1 'and VP 1' of the two buffers BUF are also connected to the right leg driving circuit RLD, and provide the common mode signal CM _ DRV to the right leg driving circuit RLD, so that the right leg driving circuit RLD generates the corresponding right leg driving signal RLD _ DRV.
In one embodiment, the preamplifier circuit 12 differentially amplifies the output signal of the input buffer BUF, for example, the amplification factor may be set to 5 times, specifically, the preamplifier circuit 12 may be implemented by a negative feedback form of a capacitor of the high-gain operational amplifier PA, and a pair of PMOS transistors is used to form a pseudo resistor to provide a bias voltage for the input, and further, an input field effect transistor inside the operational amplifier PA may be a large-sized PMOS structure, so as to reduce the noise at the input end.
In one embodiment, the gain-adjustable amplifier circuit 13 may be composed of a gain-adjustable amplifier PGA, for example, a high-gain operational amplifier implemented by using a resistor negative feedback form, and the amplification factor of the gain-adjustable amplifier circuit 13 may be adjusted between 10, 20 and 50 by controlling the overall resistance value of the feedback resistor through the gain control signals ENA and ENB provided by the gain control signal source ENA and the gain control signal source ENB. And converts the differential signal output by the preamplifier circuit 12 from a double-ended differential form to a single-ended output signal PRE _ OUT.
In one embodiment, the gain of each channel is adjusted by the gain adjustable amplifier 13, and the total gain of each channel can be between 100 and 500 times. At this time, referring to fig. 4, the circuit structure diagram of the front-end analog circuit is configured to set gain control signal source ports ENA and ENB on the chip for receiving external gain control signals, where the gain control signal source ports ENA and ENB are respectively connected to each signal detection channel for controlling the channel gain thereof.
In one embodiment, the band pass filter circuit 14 includes a first capacitor C1 and a low pass filter LPF, and the first capacitor C1 is disposed between the low pass filter LPF and the gain adjustable amplifier circuit 13; the first capacitor C1 is configured to filter low-frequency interference noise in the single-ended output signal, and the low-pass filter LPF is configured to filter high-frequency interference noise in the single-ended output signal PRE _ OUT.
In this embodiment, the first capacitor C1 may be an off-chip capacitor, the gain adjustable amplifier circuit 13 and the low pass filter LPF are both formed in a chip, and two ends of the first capacitor C1 are respectively connected to the output terminal PRE _ OUT of the gain adjustable amplifier circuit 13 and the input terminal of the low pass filter LPF. The single-ended output signal PRE _ OUT1 passes through the first capacitor C1, enters the chip CHP1 signal port, and then enters the low pass filter LPF, and at this time, the first capacitor C1 and the low pass filter LPF form a band pass filter BPF, so that low-frequency and high-frequency interference noise of the single-ended output signal PRE _ OUT1 is filtered.
In one embodiment, the capacitance of the first capacitor C1 may be 100nF, and the high pass bandwidth is set to 10Hz, and the bandwidth of the low pass filter LPF may be 1KHz, and further, the high pass bandwidth of the band pass filter circuit 14 may be adjusted by adjusting the capacitance value of the first capacitor C1.
Further, the positions of the first capacitor C1 and the low pass filter LPF may be interchanged, that is, the low frequency interference noise of the single-ended output signal PRE _ OUT1 is filtered first, and then the high frequency interference noise is filtered.
In one embodiment, the output buffer circuit 15 is formed by a buffer BUF for providing an output driving capability for the amplified and filtered signal to be output off-chip.
In this embodiment, the schematic structure of the signal detecting channel 10 can be as shown in fig. 4, in this case, a fixed gain amplifier FGA can be disposed in the gain adjustable amplifier circuit 13, the amplification factor of the fixed gain amplifier FGA can be set to 20 times, and the differential signal output by the preamplifier circuit 12 is converted from a double-ended differential form into a single-ended output signal PRE _ OUT1, specifically, the fixed gain amplifier FGA can be implemented by a high-gain operational amplifier resistor negative feedback form.
In one embodiment, referring to fig. 4, a programmable gain amplifier circuit 16 is further disposed between the band-pass filter circuit 14 and the output buffer circuit 15, and the programmable gain amplifier circuit 16 amplifies the single-ended output signal based on an external control signal.
In this embodiment, a programmable gain amplifier circuit 16 is provided between the bandpass filter circuit 14 and the output buffer circuit 15, so that the signal detection channel can be formed into a three-stage amplification structure, and thus the EEG small signal can be amplified, and at this time, the programmable gain amplifier circuit 16 amplifies the signal after low-pass filtering in the previous stage again. The programmable gain amplifier circuit 16 may be composed of a gain amplifier PGA, the amplification factor of the amplifier PGA may be selected by an external control signal SEL _ PGA, and when SEL _ PGA is equal to 0, the gain of the amplifier PGA is 15 times, so that the total channel gain is 1500 times; when SEL _ PGA is 1, the gain of the amplifier PGA is 7.5 times, so that the total channel gain is 750 times.
In one embodiment, referring to fig. 5, the power management module 20 includes a BandGap Reference circuit (BandGap Reference) for providing a Reference voltage signal and a Reference current signal, a low dropout linear regulator LDI, a first switch transistor M1, a first resistor R1, and a second resistor R2; reference voltage output end V _ ref of band-gap reference circuit with low dropout regulator LDI's first input is connected, band-gap reference circuit's reference current output end I _ ref provides the reference current signal, low dropout regulator LDI's output with first switch tube M1's control end is connected, first switch tube M1's current input end is connected with external voltage source VCC, first switch tube M1's current output end and first resistance R1's first end connect altogether as power management module 20's mains voltage output end VDD, first resistance R1's second end with second resistance R2's first end connect altogether in low dropout regulator LDI's second input, second resistance R2's second end ground connection.
In this embodiment, external voltage source VCC can be for battery power supply, and the working power supply that obtains reference voltage and reference current and front-end analog circuit is handled through the power supply to the battery, provides more convenient scheme for front-end analog circuit is applied to wearable equipment.
In this embodiment, the first switch transistor M1 may be a P-type MOS transistor, a drain of the P-type MOS transistor is a current input terminal of the first switch transistor M1, a source of the P-type MOS transistor is a current output terminal of the first switch transistor M1, and a gate of the P-type MOS transistor is a control terminal of the first switch transistor M1.
In one embodiment, referring to FIG. 6, the preamplifier circuit 12 comprises: the transconductance operational amplifier OTA, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5; a first end of the second capacitor C2 is connected to the first output end of the input buffer circuit 11, a second end of the second capacitor C2, a first end of the third capacitor C3, a first input end of the transconductance operational amplifier OTA, a control end of the second switch tube M2 and a current output end of the second switch tube M2 are connected in common, a current input end of the second switch tube M2, a current output end of the third switch tube M3 and a control end of the third switch tube M3 are connected in common, a current input end of the third switch tube M3, a second end of the third capacitor C3 and a first output end of the transconductance operational amplifier OTA are connected in common to the first input end of the gain-adjustable amplifier circuit 13, a first end of the fourth capacitor C4 is connected to the second output end of the input buffer circuit 11, a second end of the fourth capacitor C4, a first end of the transconductance operational amplifier OTA, The first end of the fifth capacitor C5, the second input end of the transconductance operational amplifier OTA, the control end of the fourth switch tube M4 and the current output end of the fourth switch tube M4 are connected in common, the current input end of the fourth switch tube M4, the control end of the fifth switch tube M5 and the current output end of the fifth switch tube M5 are connected in common, and the current input end of the fifth switch tube M5, the second end of the fifth capacitor C5 and the second output end of the transconductance operational amplifier OTA are connected in common to the second input end of the gain-adjustable amplifier circuit 13.
In one embodiment, referring to fig. 7, the gain-adjustable amplifier circuit 13 includes: the power amplifier AMP, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the sixth switching tube M6, the seventh switching tube M7, the eighth switching tube M8 and the ninth switching tube M9; a first end of the third resistor R3 is connected to a first output end of the preamplifier circuit 12, a first end of the fourth resistor R4 is connected to a second output end of the preamplifier circuit 12, a second end of the third resistor R3, a first input end of the power amplifier AMP, a first end of the fifth resistor R5, a first end of the sixth resistor R6, and a first end of the seventh resistor R7 are commonly connected, a second end of the fifth resistor R5 is connected to a current output end of the sixth switching tube M6, a control end of the sixth switching tube M6 is connected to the gain control signal source ENB, a second end of the sixth resistor R6 is connected to a current output end of the seventh switching tube M7, a control end of the seventh switching tube M7 is connected to the gain control signal source ENA, a current input end of the sixth switching tube M6, and a current input end of the seventh switching tube M7 are connected to the gain control signal source ENA, A second terminal of the seventh resistor R7 and an output terminal of the power amplifier AMP are commonly connected to an input terminal of the band-pass filter circuit 14, a second terminal of the fourth resistor R4, a first terminal of the eighth resistor R8, a first terminal of the ninth resistor R9 and a first terminal of the tenth resistor R10 are commonly connected to a second input terminal of the power amplifier AMP, a second end of the ninth resistor R9 is connected to a current output end of the eighth switch tube M8, a second terminal of the tenth resistor R10 is connected to the current output terminal of the ninth switch transistor M9, the control end of the eighth switching tube M8 is connected to the gain control signal source ENA, the control end of the ninth switching tube M9 is connected to the gain control signal source ENB, the current input terminal of the eighth switch transistor M8, the current input terminal of the ninth switch transistor M9, and the second terminal of the eighth resistor R8 are commonly connected to the power management module 20.
In this embodiment, the power management module 20 is configured to provide a reference voltage signal VREF for the gain adjustable amplifier circuit 13, so that the front end analog circuit can operate under a stable voltage and current even under the condition of battery power supply.
The embodiment of the application also provides a front-end analog chip for neuroelectrophysiology detection, which comprises a plurality of detection electrodes, a right leg electrode and the front-end analog circuit, wherein the front-end analog circuit is respectively connected with a plurality of pairs of the detection electrodes and the right leg electrode.
In this embodiment, fig. 8 is a schematic diagram of a test result of the front-end analog chip in this embodiment for testing and verifying a human brain wave signal, and as shown in fig. 8, an electroencephalogram (EEG) signal of a tester when watching a horror video is compared with an electroencephalogram signal in a process from eye closing to eye opening in a calm state, respectively, so as to accurately detect a change in a voltage level of the electroencephalogram signal.
Fig. 9 is a schematic diagram of a test result of detecting muscle movement of an upper limb of a human body, wherein a frame is a human body Electromyography (EMG) signal, and through the front-end analog chip, a motion state of the human body muscle can be identified through a plurality of detection electrodes, and further, the motion of the artificial limb can be controlled through identifying the EMG signal in the frame, so that the artificial limb has a wider application prospect.
In the front-end analog circuit and the front-end analog chip provided by the application, signals input by the detection electrodes are amplified through the multiple signal detection channels, synchronous detection of the multiple channel signals is realized, lead shielding line driving signals and right leg driving signals are generated through the right leg driving module based on common-mode signals in the multiple signal detection channels, inhibition of common-mode noise is realized, and the problems that the existing nerve electrical signal detection circuit is high in noise, complex in structure and the like are solved.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (9)
1. A front-end analog circuit for neuroelectrophysiological detection, connected to a plurality of detection electrodes and a right leg electrode, the front-end analog circuit comprising:
the signal detection channels are connected with the detection electrodes in a one-to-one correspondence mode and used for amplifying signals input by the detection electrodes;
the right leg driving module is connected with the signal detection channels and used for generating lead shielding line driving signals and right leg driving signals according to common-mode signals in the signal detection channels; and
the power supply management module is connected with the plurality of signal detection channels and the right leg driving module and is used for supplying power to the signal detection circuit;
the right leg driving signal is fed back to the surface of the skin of the human body through the right leg electrode so as to inhibit common-mode noise;
the front-end analog circuit is integrated on a chip, an input mode of the chip is set through an external control signal provided outside the chip, when the external control signal controls the switch to be switched off, the input mode of the chip is a single-electrode input mode, each channel is only connected with one detection electrode and is connected to an input positive terminal, a common-mode signal output by the signal detection channel is only generated by a signal collected by the positive terminal, and the common-mode signal is connected to an input negative terminal of the chip through the outside of the chip; when the external control signal controls the switching switch to be closed, the input mode of the chip is a double-electrode input mode, each channel is connected with two detection electrodes and respectively connected with a positive electrode end and a negative electrode end, and a common-mode signal is generated by signals collected by the positive electrode end and the negative electrode end;
the right leg driving module is composed of a buffer and an inverting amplifying circuit, wherein the buffer generates a lead shielding line driving signal according to a common mode signal provided by a plurality of signal detection channels, and the inverting amplifying circuit performs inverting amplification filtering processing on the lead shielding line driving signal to generate a right leg driving signal.
2. The front-end analog circuit of claim 1, wherein the signal detection channel comprises:
an input buffer circuit for providing an input impedance to a port connected to the detection electrode;
a preamplifier circuit for performing differential amplification processing on the signal output by the input buffer circuit;
the gain adjustable amplifier circuit is used for amplifying the differential signal output by the preamplifier circuit and converting the differential signal from a double-end differential form into a single-end output signal;
the band-pass filter circuit is used for filtering low-frequency and high-frequency interference noise in the single-ended output signal;
and the output buffer circuit is used for providing output driving capability for the signal output by the band-pass filter circuit.
3. The front-end analog circuit of claim 2, wherein the front-end analog circuit further comprises a plurality of gain control signal sources for adjusting the amplification of the gain adjustable amplifier circuit.
4. The front-end analog circuit of claim 2, wherein the band-pass filter circuit comprises a first capacitor and a low-pass filter, the first capacitor being disposed between the low-pass filter and the gain-tunable amplifier circuit;
the first capacitor is used for filtering low-frequency interference noise in the single-ended output signal, and the low-pass filter is used for filtering high-frequency interference noise in the single-ended output signal.
5. The front-end analog circuit of claim 2, wherein a programmable gain amplifier circuit is further disposed between the band-pass filter circuit and the output buffer circuit, and the programmable gain amplifier circuit amplifies the single-ended output signal based on an external control signal.
6. The front-end analog circuit of claim 1, wherein the power management module comprises a bandgap reference circuit for providing a reference voltage signal and a reference current signal, a low dropout linear regulator, a first switching tube, a first resistor, and a second resistor;
band gap reference circuit's reference voltage output with low dropout linear regulator's first input is connected, low dropout linear regulator's output with the control end of first switch tube is connected, the current input end of first switch tube is connected with external voltage source, the current output end of first switch tube and the first end of first resistance connects the conduct altogether the power supply voltage output of power management module, the second of first resistance end with the first end of second resistance connects in altogether the second input of low dropout linear regulator, the second end ground connection of second resistance.
7. The front-end analog circuit of claim 2, wherein the preamplifier circuit comprises: the transconductance operational amplifier, the second switching tube, the third switching tube, the fourth switching tube, the fifth switching tube, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor;
the first end of the second capacitor is connected to the first output end of the input buffer circuit, the second end of the second capacitor, the first end of the third capacitor, the first input end of the transconductance operational amplifier, the control end of the second switch tube and the current output end of the second switch tube are connected in common, the current input end of the second switch tube, the current output end of the third switch tube and the control end of the third switch tube are connected in common, the current input end of the third switch tube, the second end of the third capacitor and the first output end of the transconductance operational amplifier are connected in common to the first input end of the gain-adjustable amplifier circuit, the first end of the fourth capacitor is connected to the second output end of the input buffer circuit, the second end of the fourth capacitor, the first end of the fifth capacitor, the second input end of the transconductance operational amplifier, The control end of the fourth switching tube and the current output end of the fourth switching tube are connected in common, the current input end of the fourth switching tube, the control end of the fifth switching tube and the current output end of the fifth switching tube are connected in common, and the current input end of the fifth switching tube, the second end of the fifth capacitor and the second output end of the transconductance operational amplifier are connected in common to the second input end of the gain-adjustable amplifier circuit.
8. The front-end analog circuit of claim 3, wherein the gain-adjustable amplifier circuit comprises: the power amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a sixth switching tube, a seventh switching tube, an eighth switching tube and a ninth switching tube;
a first end of the third resistor is connected to a first output end of the preamplifier circuit, a first end of the fourth resistor is connected to a second output end of the preamplifier circuit, a second end of the third resistor, a first input end of the power amplifier, a first end of the fifth resistor, a first end of the sixth resistor, and a first end of the seventh resistor are connected in common, a second end of the fifth resistor is connected to a current output end of the sixth switching tube, a control end of the sixth switching tube is connected to the gain control signal source, a second end of the sixth resistor is connected to a current output end of the seventh switching tube, a control end of the seventh switching tube is connected to the gain control signal source, a current input end of the sixth switching tube, a current input end of the seventh switching tube, a second end of the seventh resistor, and an output end of the power amplifier are connected in common to an input end of the band-pass filter circuit, the second end of the fourth resistor, the first end of the eighth resistor, the first end of the ninth resistor and the first end of the tenth resistor are connected to the second input end of the power amplifier, the second end of the ninth resistor is connected to the current output end of the eighth switch tube, the second end of the tenth resistor is connected to the current output end of the ninth switch tube, the control end of the eighth switch tube is connected to the gain control signal source, the control end of the ninth switch tube is connected to the gain control signal source, and the current input end of the eighth switch tube, the current input end of the ninth switch tube and the second end of the eighth resistor are connected to the power management module.
9. A front-end analog chip for neuroelectrophysiological examination, comprising a plurality of detection electrodes and a right leg electrode, and a front-end analog circuit according to any one of claims 1 to 8, the front-end analog circuit being connected to a plurality of pairs of the detection electrodes and the right leg electrode, respectively.
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| CN114978073A (en) * | 2022-05-18 | 2022-08-30 | 深圳先进技术研究院 | Amplifying circuit, detection chip and wearable equipment |
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| CN202776292U (en) * | 2012-09-19 | 2013-03-13 | 长沙爱康电子有限公司 | Circuit structure of electrocardiosignal acquisition module |
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