CN104000575A - Electrocardiosignal acquisition device - Google Patents

Electrocardiosignal acquisition device Download PDF

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Publication number
CN104000575A
CN104000575A CN201410183074.3A CN201410183074A CN104000575A CN 104000575 A CN104000575 A CN 104000575A CN 201410183074 A CN201410183074 A CN 201410183074A CN 104000575 A CN104000575 A CN 104000575A
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circuit
resistor
operational amplifier
connected
output terminal
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CN201410183074.3A
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杨佩璐
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山东中医药大学
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Abstract

An electrocardiosignal acquisition device comprises an electrocardiogram lead circuit, a preamplifier circuit, a level uplift circuit, a band-pass filter circuit, a 50 HZ trap circuit, an AD conversion circuit, a lead falling detection and alarm circuit and a central processor. The electrocardiogram lead circuit is used for leading in a detected electrocardiosignal. After amplification, level uplift, filtering, trapping, analog-digital conversion and other processing operations are performed on the electrocardiosignal through the preamplifier circuit, the level uplift circuit, the band-pass filter circuit, the 50 HZ trap circuit and the AD conversion circuit in sequence, the electrocardiosignal is sent to the central processor. The central processor performs feature point recognition on the processed electrocardiosignal. The lead falling detection and alarm circuit is used for performing lead falling detection on the electrocardiosignal. The reliability and flexibility of system design are improved, and the situation that filter characteristics are inconsistent due to the difference between resistance and capacitance, and then distortion of the electrocardiosignal is caused is avoided. Besides, the electrocardiosignal acquisition device has the advantages of being good in performance, high in accuracy, small in size, lower in energy consumption and the like.

Description

一种心电信号采集装置 A cardiac signal sampling means

技术领域 FIELD

[0001 ] 本发明涉及信号采集技术领域,具体地说是一种心电信号采集装置。 [0001] The present invention relates to signal acquisition technologies, and in particular to an ECG acquisition device.

背景技术 Background technique

[0002] 心脏病已成为危害人类健康的主要疾病之一。 [0002] heart disease has become a major disease hazard to human health. 据统计,心血管疾病是威胁人类生命的主要疾病,世界上心脏病的死亡率仍占首位。 According to statistics, cardiovascular disease is the main threat to human life, heart disease mortality in the first place in the world still. 因此,对心血管疾病的诊断、治疗一直被世界各国医学界所重视,准确地进行心电信号提取,为医生提供有效的辅助分析手段是重要而有意义的课题。 Therefore, the diagnosis of cardiovascular disease, the treatment has been valued by the world medical community countries, accurately ECG extraction, provide an effective means for the physician-assisted analysis is an important and meaningful issue. 随着电子技术的迅速发展,医用电子监护系统近年来己在临床诊断中逐渐应用。 With the rapid development of electronic technology, electronic medical monitoring system in recent years has been gradually applied in clinical diagnosis.

[0003] 心电图是人体最重要的生物电信息之一。 [0003] ECG is one of the most important human bio-electrical information. 心电信号是一种周期性的电生理信号,经人体组织传到体表,在体表产生电位差。 ECG signal is a periodic electrophysiological signals, transmitted through human tissue surface, a potential difference at the body surface. 临床上,可以用各种仪器和设备将体表产生的电位差测量出来并描绘成曲线,以形成心电图。 Clinically, the potential difference can be measured by a variety of instruments and equipment to produce the surface and depicted as curve out to form an electrocardiogram. 体表的心电信号测量方法通常是采用贴在体表特定位置的电极获取微弱的心电信号,并通过心电导联线将上述微弱的心电信号送入心电预处理电路进行处理后,经A/D数字化转化为数字信号,并送入MCU,由MCU进行心电图特征点的识别和处理,最后将处理和识别后的心电信号传送给上位机进行显示。 The method of measuring cardiac electrical signal is typically a body surface electrodes to the surface of a specific position weak ECG signal acquisition, and through the above-described ECG lead ECG weak ECG preprocessing circuit into treatment, a / D-converted into a digital signal digitized and sent to MCU, and recognition processing by the feature point ECG MCU, and finally transfer the processed ECG signal for display, and identification to the host computer.

[0004] 传统的心电图采集系统和装置采用了分立的元器件对心电信号进行采集,主要包括了前级保护电路、电刀抑制电路、前端阻抗匹配电路、导联脱落识别电路、主放大电路、起搏检测电路、高通滤波电路、二级放大电路、低通滤波电路、右腿驱动电路、A/D转换电路以及MCU电路组成。 [0004] The conventional ECG acquisition system and apparatus of the discrete components of the ECG signal acquisition, including a pre-stage protection circuit electrically knife suppression circuit, the impedance matching circuit leading end, lead off recognition circuit, the main amplifier circuit , pacing detecting circuit, a high pass filter circuit, two amplifying circuit, the low pass filter circuit, right leg drive circuit, A / D conversion circuit and MCU circuit. 由于采用的分立元器件来实现,无可避免的运用了大量的集成电路、电阻和电容等元器件,造成该装置的体积大、功耗高、设计复杂灵活性低等缺点,由于集成电路、电阻和电容元器件个体的差异性,造成了心电图各个导联的参数和指标具有差异性(典型的如共模抑制比、输入阻抗等),电阻和电容差异性过大还容易造成前端滤波电路滤波特性的变化,滤掉了心电图的有用信号,失去了心电图信号的诊断价值。 As a result of the discrete components to implement, inevitable use of a large integrated circuit components such as resistors and capacitors, resulting in a large volume of the apparatus, high power consumption, design complexity, flexibility and low defects, since the integrated circuit, resistance and capacitance components of individual differences, causing metrics for each parameter and having lead electrocardiogram difference (such as the typical common mode rejection ratio, input impedance, etc.), differences in resistance and capacitance also easily lead to too large a front end filter circuit changes in filter characteristics, filter out the useful signal ECG, lost the diagnostic value of ECG signals.

发明内容 SUMMARY

[0005] 针对上述不足,本发明提供了一种具有较高精度及信噪比的心电信号采集装置。 [0005] In view of the above insufficiency, the present invention provides an ECG signal acquisition device having high accuracy and signal to noise ratio.

[0006] 本发明解决其技术问题所采用的技术方案是:一种心电信号采集装置,其特征是,包括心电导联电路、前置放大电路、电平抬升电路、带通滤波电路、50HZ陷波电路、AD转换电路、导联脱落检测报警电路和中央处理器, [0006] aspect of the present invention to solve the technical problem is: A ECG acquisition device, characterized in that the circuit comprises ECG preamplifier circuit, a level raising circuit, a bandpass filter circuit, 50HZ trap circuit, the AD conversion circuit, leadoff detection alarm circuit and a central processor,

所述心电导联电路用于导入所检测的心电信号,并依次经过前置放大电路、电平抬升电路、带通滤波电路、50HZ陷波电路和AD转换电路对所述心电信号进行放大、电平抬升、滤波、陷波和模数转换等处理后发送给中央处理器,所述中央处理器对处理后的心电信号进行特征点识别,所述导联脱落检测报警电路的输入端与所述前置放大电路的输出端连接,输出端与中央处理器连接,用于对所述心电信号进行导联脱落检测; The ECG circuitry for introducing the detected ECG, and sequentially passes through the preamplifier circuit, the level lifting circuit, a bandpass filter circuit, 50HZ trap circuit and the AD converter circuit for amplifying said ECG signal after raising the level, filtering, notch processing and analog-digital conversion is sent to the central processor, the central processor for processing the ECG signal to identify the feature points, the lead off alarm detecting circuit input terminal an output terminal of the preamplifier circuit is connected, an output terminal connected to the central processor, for the ECG signal leads off detection;

所述心电导联电路包括右胸上电极、左腹下电极、右腹下电极、缓冲放大电路和右腿驱动电路,所述的右胸上电极及左腹下电极为心电信号采样电极,右胸上电极和左腹下电极分别经过缓冲放大电路与前置放大电路连接,用于对心电信号进行隔离;所述右腹下电极为右腿驱动电极,右腹下电极经过右腿驱动电路与前置放大电路连接,用于消除在心电检测时形成的交流干扰,降低人体的共模电压,提高信噪比。 The circuit includes a ECG lead electrodes on the right chest, left web lower electrode, the lower right ventral electrode, the buffer amplifier and the right leg drive circuit on the right breast and the left web electrode lower electrode ECG sampling electrode, upper right chest electrodes and lower electrodes are left web through a buffer amplifier circuit connected to the preamplifier circuit, for isolating ECG signal; lower right leg drive electrode of the right web electrode, the lower right web through a right leg driver electrode circuit and preamplifier circuit, for eliminating AC interference is formed when ECG detection, reducing the common mode voltage of the body, improve the SNR.

[0007] 作为优选,所述前置放大电路包括双端输入、双端输出的差分放大电路,共模取样驱动电路,阻容耦合电路,以及双端输入、单端输出的差分放大电路;所述双端输入、双端输出的差分放大电路的双输入端与生物体接触电极连接,双输入端依次经过共模取样驱动电路和阻容耦合电路与双端输入、单端输出的差分放大电路的双输入端连接。 [0007] Advantageously, the preamplifier circuit comprises a double-ended input, differential double-ended output amplifier circuit, the common-mode sampling circuit driving the differential amplifier circuit, RC coupling circuit, and a double-ended input, single-ended output; the said double-ended differential input, differential output end of the dual two-input amplifier circuit electrically connected in contact with the living body, two-input common mode sequentially through the driving circuit and the sampling circuit and the resistance-capacitance coupled double-ended input single-ended output amplifier circuit dual input connected.

[0008] 作为优选,所述双端输入、双端输出的差分放大电路包括第一运算放大器U1、第二运算放大器U2、电阻R1、电阻R2和电阻R3,所述共模取样驱动电路包括第三运算放大器U3、电阻R4和电阻R5,所述阻容耦合电路包括电容Cl、电容C2、电阻R6和电阻R7,所述双端输入、单端输出的差分放大电路包括仪表放大器Al和压敏电阻R8 ;所述第一运算放大器Ul和第二运算放大器U2的正向输入端分别与生物体接触电极连接,反向输入端之间串联电阻R3,第一运算放大器Ul和第二运算放大器U2的反向输入端与输出端之间分别串联电阻Rl和电阻R2 ;所述第一运算放大器Ul的输出端串联电容Cl后与仪表放大器Al的反向输入端连接,所述第二运算放大器U2的输出端串联电容C2后与仪表放大器Al的正向输入端连接;所述第三运算放大器U3的正向输入端分别经过电阻R4和电阻R5与第一运算放大 [0008] Advantageously, the double-ended input, the differential amplifier circuit comprises a double-ended output of the first operational amplifier U1, a second operational amplifier U2, resistor R1, resistor R2 and the resistor R3, the common mode sampling circuit includes a first driver three operational amplifier U3, resistors R4 and the resistor R5, the circuit comprises a resistance-capacitance coupled capacitor Cl, capacitor C2, resistor R6 and the resistor R7, the double-ended input single-ended output differential amplifying circuit comprises an instrumentation amplifier and a pressure-sensitive Al resistor R8; Ul of the first operational amplifier and the inverting input of the second operational amplifier U2 is connected to the contact electrodes respectively organism, a series resistor R3 connected between an inverting input terminal of the first operational amplifier Ul and a second operational amplifier U2 respectively connected in series between the inverting input terminal and an output terminal of the resistor Rl and resistor R2; the output terminal of the first operational amplifier Ul is connected in series with the inverting input terminal of the instrumentation amplifier Al through capacitor Cl, a second operational amplifier U2 the output terminal of the series capacitor C2 is connected to the positive input of the instrumentation amplifier Al; inverting input terminal of the third operational amplifier U3, respectively, through the resistor R4 and the resistor R5 and the first operational amplifier Ul和第二运算放大器U2的输出端连接,反相输入端与输出端连接,输出端分别经过电阻R6和电阻R7与仪表放大器Al的反向输入端和正向输入端连接;所述压敏电阻R8为仪表放大器Al的外接增益调节电阻。 Ul and the output terminal of the second operational amplifier U2 is connected to the inverting input terminal and an output terminal connected, respectively, through the output terminal and the inverting input terminal of a resistor R6 and a resistor R7 and the Al-amp positive input terminal; a varistor R8 is Al external instrumentation amplifier gain adjustment resistor.

[0009] 作为优选,所述带通滤波电路包括高通滤波电路和低通滤波电路,所述的高通滤波电路和低通滤波电路串联连接; [0009] Advantageously, the bandpass filter circuit comprises a high pass filter circuit and a low pass filter circuit, the highpass filter circuit and a low pass filter circuit connected in series;

所述高通滤波电路包括第四运算放大器U4、电阻R9和电容C3,所述第四运算放大器U4的正向输入端经过电阻R9接地,同时经过电容C3与前置放大电路的输出端连接,反相输入端与输出端连接; The high pass filter circuit comprising a fourth operational amplifier U4, capacitor C3 and resistor R9, the positive input terminal of the fourth operational amplifier U4 through resistor R9 to ground, while the output terminal through the capacitor C3 is connected to the preamplifier, trans inverting input terminal and an output terminal;

所述低通滤波电路包括第五运算放大器U5、电阻R10、电阻R11、电容C4和电容C5,所述第五运算放大器U5的正向输入端经过电容C4接地,同时依次串联电阻Rll和电阻RlO后与第四运算放大器U4的的输出端连接,反相输入端与输出端连接,第五运算放大器U5的输出端串联电容C5后连接于电阻RlO和电阻Rll之间。 The low pass filter circuit includes a fifth operational amplifier U5, resistor R10, resistor R11, capacitor C4 and capacitor C5, the positive input of the fifth operational amplifier U5 is grounded through capacitor C4, and a resistor in series and a resistor RlO Rll after connected to the output of the fourth operational amplifier U4, the inverting input terminal and an output terminal connected to the output terminal of the fifth operational amplifier U5 is connected in series between the capacitor C5 and the resistor RlO resistor Rll.

[0010] 作为优选,所述电平抬升电路包括第六运算放大器U6、电阻R12、电阻R13、电阻R14、电阻R15和第一可调电阻RWl,所述第六运算放大器U6的正向输入端经过电阻R15接地,反相输入端串联电阻R12后与带通滤波电路的输出端连接,同时经过电阻R14与第一可调电阻RWl的可调端连接,所述第一可调电阻RWl的两端分别与正、负电压端连接,反相输入端与输出端之间串联电阻Rl3。 [0010] Advantageously, said level lifting circuit comprises a sixth operational amplifier U6, resistors R12, a resistor R13, a resistor R14, a resistor R15 and a first adjustable resistor RWL, the positive input terminal of the sixth operational amplifier U6 after R15 is connected to ground, an inverting input end of the resistor series resistor R12 to the output terminal of the band pass filter circuit, while passing through the adjustable resistor R14 and a first end of the adjustable resistor is connected RWl, RWl the first two adjustable resistor terminal connected to the positive and negative voltage terminal, Rl3 series resistor between the inverting input terminal and the output terminal.

[0011] 作为优选,所述50HZ陷波电路包括第七运算放大器U7、第八运算放大器U8、电阻R16、电阻R17、电阻R18、电阻R19、电阻R20、电阻R21、电容C6、电容C7、电容C8和电容C9 ;所述第七运算放大器U7的正向输入端经过并联电路与电平抬升电路的输出端连接,所述并联电路由电阻R16、电阻R17的串联电路与电容C6、电容C7的串联电路并联而成,第七运算放大器U7的反相输入端与输出端连接;所述第八运算放大器U8的正向输入端经过电阻R20与第七运算放大器U7的输出端连接,同时经过电阻R21接地,反相输入端与输出端连接,输出端经过电阻R18和电阻R19的并联电路连接于电容C6和电容C7之间,同时经过电容C8和电容C9的并联电路连接于电阻R16与电阻R17之间。 [0011] Advantageously, the seventh 50HZ notch circuit comprising an operational amplifier U7, the eighth operational amplifier U8, resistors R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, capacitors C6, capacitor C7, the capacitor capacitors C8 and C9; seventh output terminal of the operational amplifier inverting input terminal of U7 via the parallel circuit of the level raising circuit, the parallel circuit of a resistor R16, a series circuit of resistor R17 and capacitor C6, the capacitor C7 series circuit formed by the inverting input terminal and the output terminal of the operational amplifier U7 is connected to the seventh; eighth-inverting input of the operational amplifier U8 via the resistor R20 and the seventh output terminal of the operational amplifier U7 is connected through a resistor at the same time R21 to ground, an inverting input terminal and an output terminal connected to an output terminal through the parallel circuit of the resistor R18 and the resistor R19 is connected between capacitor C6 and capacitor C7, while passing through the parallel circuit of capacitor C8 is connected to a capacitor C9 and resistor R16 and resistor R17 between.

[0012] 作为优选,所述AD转换电路采用ADC0809芯片。 [0012] Advantageously, the AD conversion circuit using ADC0809 chip.

[0013] 作为优选,所述导联脱落检测报警电路包括差分放大电路、窗口比较器电路和报警电路,所述差分放大电路的输入端与所述前置放大电路的输出端连接,输出端与窗口比较器电路的输入端连接,所述窗口比较器电路的输出端与报警电路连接,所述报警电路与中央处理器连接,用于对所述心电信号进行导联脱落检测,并根据导联脱落检测处理向所述中央处理器提供导联脱落检测信号。 [0013] Advantageously, the lead off alarm detection circuit includes a differential amplifier circuit, the window comparator circuit and alarm circuit, the input terminal of the differential amplifier circuit connected to the output of the preamplifier circuit, and an output terminal input of the window comparator circuit, the output of the window comparator circuit connected to the alarm circuit, the alarm circuit is connected to the central processor, for the ECG signal leads off detection, in accordance with the guide and off detection process to provide lead-off detection signal to the central processor.

[0014] 作为优选,所述差分放大电路包括第九运算放大器U9,所述窗口比较器电路包括第十运算放大器U10、第十一运算放大器U11、第二可调电阻RW2、第三可调电阻RW3、第一二极管Dl和第二二极管D2,所述报警电路包括第四可调电阻RW4、发光二极管D3和与门Gl ;所述第九运算放大器U9的正向输入端与前置放大电路的输出端连接,输出端分别与第九运算放大器U9的反向输入端、第十运算放大器UlO的正向输入端和第十一运算放大器Ull的反向输入端连接;第十运算放大器Uio的反向输入端和第^ 运算放大器Uii的正向输入端分别与第二可调电阻RW2的可调端和第三可调电阻RW3的可调端连接,所述第二可调电阻RW2和第三可调电阻RW3形成串联电路,串联电路两端分别接正负电压且在第二可调电阻RW2和第三可调电阻RW3之间连接有等电位;第十运算放大器UlO的输出端和第十一运 [0014] Advantageously, the differential amplifier circuit includes a ninth operational amplifier U9, said window comparator circuit includes an operational amplifier U10 tenth, eleventh operational amplifier U11, RW2, a second adjustable resistor, the third adjustable resistor RW3, the first diode Dl, a second diode D2, the alarm circuit comprises a fourth adjustable resistor RW4, the light emitting diode D3 and a gate of Gl; the non-inverting input of the operational amplifier U9 ninth front of preamplifier circuit output terminal is connected to the output terminal of the operational amplifier U9 respectively ninth inverting input, the inverting input of the operational amplifier positive input terminal of tenth and eleventh operational amplifier UlO Ull is connected; a tenth operation Uio inverting input terminal of the amplifier and the positive input terminal of the operational amplifier Uii ^ are connected to the second end of the adjustable variable resistor RW2 and RW3 third adjustable adjustable end of the resistor, said second adjustable resistor RW2 and RW3 third adjustable resistor form a series circuit, connected across the series circuits between the positive and negative voltage, and a second adjustable resistor RW2 and RW3 third adjustable resistor connected to equipotential; a tenth of the output of the operational amplifier UlO end and an eleventh op 放大器Ull的输出端分别串联第一二极管Dl和第二二极管D2后与第四可调电阻RW4的一端连接;所述第四可调电阻RW4的另一端连接等电位,可调端与与门Gl的输入端连接,所述与门Gl的输出端串联发光二极管D3后与中央处理器连接。 The output of amplifier Ull are serially connected to one end of a fourth adjustable resistor RW4 after a first diode Dl, a second diode D2 of; the other terminal of the fourth adjustable resistor RW4 equipotential connection, adjustable end and the inputs of the gate Gl is connected, after the light emitting diode D3 connected in series with the central processor and the output of aND gate Gl.

[0015] 作为优选,所述缓冲放大电路包括电阻R22和第十二运算放大器U12,所述电阻R22 —端与右胸上电极或左腹下电极的输出端连接,另一端与第十二运算放大器U12的正向输入端连接,所述第十二运算放大器U12的反相输入端与输出端连接;所述右腿驱动电路包括电阻R23、电阻R24、电容ClO和第十三运算放大器U13,所述电阻R23 —端与右腹下电极的输出端连接,另一端与第十二运算放大器U12的反相输入端连接,所述第十二运算放大器U12的反相输入端与输出端之间串联有电阻R24与电容ClO的并联电路,第十二运算放大器U12的正向输入端接地。 [0015] Advantageously, the buffer amplifier circuit including a resistor R22 and a twelfth operational amplifier U12, a resistor R22 - terminal connected to the output electrode of the lower electrode or upper right chest left web, the other end of the twelfth operation the positive input of the amplifier U12 is connected to an inverting input terminal and the output terminal of the twelfth operational amplifier U12 is connected; the right leg drive circuit includes a resistor R23, a resistor R24, and a thirteenth capacitor ClO operational amplifier U13, the resistor R23 - and output ends of the lower right ventral electrode connected to the inverting input terminal and the other terminal of the twelfth operational amplifier U12 is connected to an inverting input terminal and the output terminal of the twelfth operational amplifier U12 between resistor R24 ​​connected in series with the parallel circuit of capacitor ClO, twelfth operational amplifier U12 positive input is grounded.

[0016] 本发明具有以下突出的有益效果:由于心电信号是微弱信号,所以本发明设置了前置放大电路来放大心电信号;为了抑制基线漂移和消除高频谐波的严重干扰,设置了由高通滤波电路和低通滤波电路诸城的带通滤波电路;为了心电信号不失真,设计了电平抬升电路;为了消除50 Hz工频干扰,设置了50HZ陷波电路,最后设置了AD转换电路,使信号频率达到采样要求。 [0016] The present invention has the following outstanding advantages: Since the ECG signal is weak, the present invention is provided to amplify the ECG preamplifier circuit; severe interference in order to suppress high-frequency harmonics to eliminate baseline wander, and is provided by the band pass filter circuit a high-pass filter circuit and a low pass filter circuit the cities; to ECG signal distortion, designed level raising circuit; to eliminate the 50 Hz power frequency interference, provided 50HZ trap circuit, and finally provided AD conversion circuit, a signal frequency of sampling requirements. 本发明通过对心电信号进行进行放大、电平抬升、滤波、陷波和模数转换等处理,增加了系统设计的可靠性以及灵活性,避免了由于电阻和电容差异造成滤波特性不一致而引起的心电信号的失真,具有性能好、精度高、体积小以及能耗更低等特点。 The present invention ECG signal is amplified, the level of uplift, filtering, and analog to digital notch conversion process, increasing the reliability and flexibility of the system design, avoids the resistance and capacitance caused by differences in the filtering characteristics due to inconsistency ECG signal distortion, with good performance, high accuracy, small size and lower energy consumption characteristics.

附图说明 BRIEF DESCRIPTION

[0017]下面结合附图对本发明作进一步说明: [0017] DRAWINGS The present invention is further described:

图1是本发明的原理框图; FIG. 1 is a block diagram of the present invention;

图2是本发明所述前置放大电路的电路图;图3是本发明所述高通滤波电路的电路图; FIG 2 is a circuit diagram of the preamplifier of the present invention; FIG. 3 is a circuit diagram of the high pass filter circuit of the present invention;

图4是本发明所述低通滤波电路的电路图; FIG 4 is a circuit diagram of the low pass filter circuit of the present invention;

图5是本发明所述电平抬升电路的电路图; FIG 5 is a circuit diagram of the present invention said level lifting circuit;

图6是本发明所述50HZ陷波电路的电路图; The present invention FIG. 6 is a circuit diagram 50HZ trap;

图7是本发明所述导联脱落检测报警电路的电路图; FIG 7 is a circuit diagram of the present invention, the lead off detection circuit of the alarm;

图8是本发明所述缓冲放大电路的电路图; FIG 8 that the present invention is a circuit diagram of the buffer amplifier circuit;

图9是本发明所述右腿驱动电路的电路图。 FIG 9 is a circuit diagram of the driving circuit of the present invention, the right leg. 具体实施方式 Detailed ways

[0018] 下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。 [0018] The following disclosure provides many different embodiments or examples to achieve different structures of the present invention. 为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。 To simplify the disclosure of the present invention, be described hereinafter and the members of the specific examples provided. 此外,本发明可以在不同例子中重复参考数字和/或字母。 Further, the present disclosure may repeat reference numerals and / or letters in the various examples. 这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。 This repetition is for the purpose of simplicity and clarity, and does not indicate a relationship between the embodiments and / or arrangements being discussed. 应当注意,在附图中所图示的部件不一定按比例绘制。 It should be noted that, in the member illustrated in the drawings are not necessarily drawn to scale. 本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。 Descriptions of the present invention will be omitted and processing techniques are well-known components and processes in order to avoid unnecessarily limiting the present invention.

[0019] 如图1所示,本发明的一种心电信号采集装置,它包括心电导联电路、前置放大电路、电平抬升电路、带通滤波电路、50HZ陷波电路、AD转换电路、导联脱落检测报警电路和中央处理器,所述心电导联电路用于导入所检测的心电信号,并依次经过前置放大电路、电平抬升电路、带通滤波电路、50HZ陷波电路和AD转换电路对所述心电信号进行放大、电平抬升、滤波、陷波和模数转换等处理后发送给中央处理器,所述中央处理器对处理后的心电信号进行特征点识别,所述导联脱落检测报警电路的输入端与所述前置放大电路的输出端连接,输出端与中央处理器连接,用于对所述心电信号进行导联脱落检测。 [0019] FIG An ECG signal acquisition device according to the present invention shown in FIG. 1, which comprises ECG circuitry, the preamplifier circuit, the level lifting circuit, a bandpass filter circuit, 50HZ trap circuit, the AD conversion circuit , leadoff detection alarm circuit and a central processor, the ECG circuit for introducing the detected ECG, and sequentially passes through the preamplifier circuit, the level lifting circuit, a bandpass filter circuit, 50HZ trap circuit after the AD conversion circuit and amplifies the level of uplift, filtering, notch, etc., and analog to digital conversion process on the ECG signal to a central processor, said central processor for processing the ECG signal feature point recognition the alarm detecting circuit leadoff input terminal of the preamplifier circuit is connected to an output terminal, an output terminal connected to the central processor, for the ECG signal leads off detection.

[0020] 所述心电导联电路包括右胸上电极、左腹下电极、右腹下电极、缓冲放大电路和右腿驱动电路,所述的右胸上电极及左腹下电极为心电信号采样电极,右胸上电极和左腹下电极分别经过缓冲放大电路与前置放大电路连接,用于对心电信号进行隔离;所述右腹下电极为右腿驱动电极,右腹下电极经过右腿驱动电路与前置放大电路连接,用于消除在心电检测时形成的交流干扰,降低人体的共模电压,提高信噪比。 [0020] The circuit includes a ECG lead electrodes on the right chest, left web lower electrode, the lower right ventral electrode, the buffer amplifier and the right leg drive circuit, the electrode on the right chest and left web ECG electrodes sampling electrode, and the upper right chest electrodes are left web through the lower electrode and the buffer amplifier circuit connected to preamplifier circuit for ECG signal isolation; lower right leg drive electrode of the right web electrode, the lower electrode through the right ventral right leg drive circuit and preamplifier circuit, for eliminating AC interference is formed when ECG detection, reducing the common mode voltage of the body, improve the SNR.

[0021] 由于心电信号是微弱信号,所以本发明设置了前置放大电路来放大心电信号。 [0021] Since the ECG signal is weak, the present invention is provided to a preamplifier circuit amplifies the ECG signal. 所述前置放大电路包括双端输入、双端输出的差分放大电路,共模取样驱动电路,阻容耦合电路,以及双端输入、单端输出的差分放大电路;所述双端输入、双端输出的差分放大电路的双输入端与生物体接触电极连接,双输入端依次经过共模取样驱动电路和阻容耦合电路与双端输入、单端输出的差分放大电路的双输入端连接。 The preamplifier circuit comprises a double-ended input, differential double-ended output amplifier circuit, sampling the common-mode drive circuit RC coupling circuit, and a double-ended input single-ended output differential amplifier circuit; a double-ended input, bis an output terminal of the differential amplifier circuit of the two-input is connected with the living body contact electrode, sequentially through two-input common-mode driving circuit and a sampling circuit coupled to the RC double-ended input, two-input differential amplifier circuit is connected to the single-ended output.

[0022] 图2是本发明所述前置放大电路的电路图,如图2所示,所述双端输入、双端输出的差分放大电路包括第一运算放大器U1、第二运算放大器U2、电阻R1、电阻R2和电阻R3,所述共模取样驱动电路包括第三运算放大器U3、电阻R4和电阻R5,所述阻容耦合电路包括电容Cl、电容C2、电阻R6和电阻R7,所述双端输入、单端输出的差分放大电路包括仪表放大器Al和压敏电阻R8 ;所述第一运算放大器Ul和第二运算放大器U2的正向输入端分别与生物体接触电极连接,反向输入端之间串联电阻R3,第一运算放大器Ul和第二运算放大器U2的反向输入端与输出端之间分别串联电阻Rl和电阻R2 ;所述第一运算放大器Ul的输出端串联电容Cl后与仪表放大器Al的反向输入端连接,所述第二运算放大器U2的输出端串联电容C2后与仪表放大器Al的正向输入端连接;所述第三运算放大器U3的正向输入 [0022] FIG. 2 is a circuit diagram of the present invention, the preamplifier circuit, shown in Figure 2, the double-ended input, double-ended output of the differential amplifier circuit comprises a first operational amplifier U1, a second operational amplifier U2, resistor R1, a resistor R2 and a resistor R3, the common mode sampling circuit includes a third drive an operational amplifier U3, resistors R4 and the resistor R5, the circuit comprises a resistance-capacitance coupled capacitor Cl, capacitor C2, resistor R6 and the resistor R7, the bis ended input single-ended output of the differential amplifying circuit comprises an instrumentation amplifier Al and varistor R8; Ul of the first operational amplifier and the inverting input of the second operational amplifier U2 is connected to the contact electrodes respectively organism inverting input terminal series between the resistor R3, a resistor Rl are connected in series between the resistor R2 and the operational amplifier Ul and a first inverting input terminal and the output terminal of the second operational amplifier U2; the output of said first operational amplifier Ul and a series capacitance Cl inverting input of the instrumentation amplifier Al is connected to the output terminal of the second operational amplifier U2 is connected in series to the positive input of the instrumentation amplifier Al after capacitor C2; positive input of said third operational amplifier U3, 分别经过电阻R4和电阻R5与第一运算放大器Ul和第二运算放大器U2的输出端连接,反相输入端与输出端连接,输出端分别经过电阻R6和电阻R7与仪表放大器Al的反向输入端和正向输入端连接;所述压敏电阻R8为仪表放大器Al的外接增益调节电阻。 Respectively through the resistor R4 and the resistor R5 and the output terminal of the first operational amplifier Ul and a second operational amplifier U2 is connected to the inverting input terminal and an output terminal connected to an output terminal respectively through resistor R6 and the resistor R7 and the inverting input of the instrumentation amplifier Al and a non-inverting input terminal is connected; R8 is a varistor external instrumentation amplifier gain adjusting resistor Al. 前置放大是整个信号放大最关键的环节,关系到整个模拟采集部分的工作性能。 Signal amplifying preamplified entire most critical link, related to the performance of the entire analog acquisition portion.

[0023] 为了抑制基线漂移和消除高频谐波的严重干扰,设置了带通滤波电路。 [0023] In order to suppress severe interference and baseline drift eliminate high frequency harmonics, the band pass filter circuit is provided. 所述带通滤波电路包括闻通滤波电路和低通滤波电路,所述的闻通滤波电路和低通滤波电路串联连接; The bandpass filter circuit comprises a filter circuit and a smell through a low-pass filter circuit, said filter circuit and smell through a low-pass filter circuit connected in series;

图3是本发明所述高通滤波电路的电路图;如图3所示,所述高通滤波电路包括第四运算放大器U4、电阻R9和电容C3,所述第四运算放大器U4的正向输入端经过电阻R9接地,同时经过电容C3与前置放大电路的输出端连接,反相输入端与输出端连接; Figure 3 is a circuit diagram of the present invention, the high-pass filter circuit; As shown, the high pass filter circuit comprising a fourth operational amplifier U4, resistors R9 and a C3 capacitor 3, the positive input terminal of the fourth operational amplifier U4 through resistor R9 is grounded, while the output terminal through the capacitor C3 is connected to the preamplifier circuit, an inverting input terminal and an output terminal;

图4是本发明所述低通滤波电路的电路图。 FIG 4 is a circuit diagram of the low pass filter circuit of the present invention. 如图4所示,所述低通滤波电路包括第五运算放大器U5、电阻R10、电阻Rl 1、电容C4和电容C5,所述第五运算放大器U5的正向输入端经过电容C4接地,同时依次串联电阻Rll和电阻RlO后与第四运算放大器U4的的输出端连接,反相输入端与输出端连接,第五运算放大器U5的输出端串联电容C5后连接于电阻RlO和电阻Rll之间。 As shown, the low pass filter circuit includes a fifth operational amplifier U5, the resistor R10, the resistor Rl 1, capacitor C4 and capacitor C5 4, the positive input terminal of the fifth operational amplifier U5 is grounded via a capacitor C4, while after sequentially connecting the series resistor Rll resistor RlO and the output terminal of the fourth operational amplifier U4, the inverting input terminal and an output terminal connected to the output terminal of the fifth operational amplifier U5 is connected to capacitor C5 in series between the resistor RlO and the resistor Rll .

[0024] 为了心电信号不失真,设计了电平抬升电路。 [0024] In order distortion ECG signal, the circuit design of the level lift. 如图5所示,所述电平抬升电路包括第六运算放大器U6、电阻R12、电阻R13、电阻R14、电阻R15和第一可调电阻RWl,所述第六运算放大器U6的正向输入端经过电阻R15接地,反相输入端串联电阻R12后与带通滤波电路的输出端连接,同时经过电阻R14与第一可调电阻RWl的可调端连接,所述第一可调电阻RH的两端分别与正、负电压端连接,反相输入端与输出端之间串联电阻R13。 5, the level raising circuit comprises a sixth operational amplifier U6, resistors R12, a resistor R13, a resistor R14, a resistor R15 and a first adjustable resistor RWL, the positive input terminal of the sixth operational amplifier U6 after R15 is connected to ground, an inverting input end of the resistor series resistor R12 to the output terminal of the band pass filter circuit, while passing through the adjustable resistor R14 and a first end of the adjustable resistor is connected RWl, the first adjustable resistor RH for two terminal connected to the positive and negative voltage terminal, a resistor R13 connected in series between the inverting input terminal and the output terminal.

[0025] 为了消除50 Hz工频干扰,设置了50HZ陷波电路。 [0025] In order to eliminate the 50 Hz power frequency interference, provided the trap circuit 50HZ. 如图6所示,所述50HZ陷波电路包括第七运算放大器U7、第八运算放大器U8、电阻R16、电阻R17、电阻R18、电阻R19、电阻R20、电阻R21、电容C6、电容C7、电容C8和电容C9 ;所述第七运算放大器U7的正向输入端经过并联电路与电平抬升电路的输出端连接,所述并联电路由电阻R16、电阻R17的串联电路与电容C6、电容C7的串联电路并联而成,第七运算放大器U7的反相输入端与输出端连接;所述第八运算放大器U8的正向输入端经过电阻R20与第七运算放大器U7的输出端连接,同时经过电阻R21接地,反相输入端与输出端连接,输出端经过电阻R18和电阻R19的并联电路连接于电容C6和电容C7之间,同时经过电容C8和电容C9的并联电路连接于电阻R16与电阻R17之间。 6, the seventh 50HZ notch circuit comprising an operational amplifier U7, the eighth operational amplifier U8, resistors R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, capacitors C6, capacitor C7, the capacitor capacitors C8 and C9; seventh output terminal of the operational amplifier inverting input terminal of U7 via the parallel circuit of the level raising circuit, the parallel circuit of a resistor R16, a series circuit of resistor R17 and capacitor C6, the capacitor C7 series circuit formed by the inverting input terminal and the output terminal of the operational amplifier U7 is connected to the seventh; eighth-inverting input of the operational amplifier U8 via the resistor R20 and the seventh output terminal of the operational amplifier U7 is connected through a resistor at the same time R21 to ground, an inverting input terminal and an output terminal connected to an output terminal through the parallel circuit of the resistor R18 and the resistor R19 is connected between capacitor C6 and capacitor C7, while passing through the parallel circuit of capacitor C8 is connected to a capacitor C9 and resistor R16 and resistor R17 between.

[0026] 为了使信号频率达到采样要求,本发明最后还设置了AD转换电路,所述AD转换电路采用ADC0809芯片。 [0026] In order to make the signal frequency of the sampling requirement, the present invention is finally provided with the AD conversion circuit, the AD conversion circuit using ADC0809 chip. ADC0809是采样分辨率为8位的、以逐次逼近原理进行模一数转换的器件。 ADC0809 sampling resolution of 8-bit, successive approximation principle to analog-digital conversion device. 其内部有一个8通道多路开关,它可以根据地址码锁存译码后的信号,只选通8路模拟输入信号中的一个进行A/D转换。 Which has an internal 8-channel multiplexer, which can latch address code signal decoding, channel 8 through only a selected analog input signal is A / D-conversion. ADC0809的工作过程为:首先输入3位地址,并使ALE=I,将地址存入地址锁存器中。 ADC0809 working process is: firstly three input address and ALE = I, the address stored in the address latch. 此地址经译码选通8路模拟输入之一到比较器。 This coded address strobe one of eight analog input to the comparator. START上升沿将逐次逼近寄存器复位。 The rising edge of the START successive approximation register is reset. 下降沿启动A / D转换,之后EOC输出信号变低,指示转换正在进行。 Falling start A / D conversion, then the output signal EOC becomes low, indicating conversion is in progress. 直到A / D转换完成,EOC变为高电平,指示A / D转换结束,结果数据已存入锁存器,这个信号可用作中断申请。 Until the A / D conversion is complete, EOC goes high, indicating the end of A / D conversion result data has been stored in the latch, the interrupt request signal may be used. 当OE输入高电平时,输出三态门打开,转换结果的数字量输出到数据总线上。 When the OE input is high, the output of tri-state gate is opened, the digital output to the data bus of the conversion. [0027] 为了能够快速判断导联脱落并进行报警,从而保证心电监测装置诊断结果的可靠性,本发明设置了导联脱落检测报警电路。 [0027] In order to be able to quickly determine the lead off alarm and to ensure the reliability of the diagnosis result ECG monitoring device, the present invention is provided a lead-off detection alarm circuit. 所述导联脱落检测报警电路包括差分放大电路、窗口比较器电路和报警电路,所述差分放大电路的输入端与所述前置放大电路的输出端连接,输出端与窗口比较器电路的输入端连接,所述窗口比较器电路的输出端与报警电路连接,所述报警电路与中央处理器连接,用于对所述心电信号进行导联脱落检测,并根据导联脱落检测处理向所述中央处理器提供导联脱落检测信号。 The lead-off alarm detection circuit includes a differential amplifier circuit, the window comparator circuit and alarm circuit, the input terminal of the differential amplifier circuit connected to the output of the preamplifier circuit, the input and output of the window comparator circuit terminal is connected, the output of the window comparator circuit connected to the alarm circuit, the alarm circuit is connected to the central processor, for the ECG signal leads off detection, and the detection process according to leadoff to the said central processor provides leadoff detection signal. 所述中央处理器根据导联脱落检测信号确定是否出现导联脱落,并在确定出现了导联脱落时发送导联脱落标志信号,并进行显示。 The central processing unit according to a detection signal leadoff determine if lead off, and determines that a transmission flag leadoff lead-off signal, and displayed.

[0028] 图7是本发明所述导联脱落检测报警电路的电路图。 [0028] FIG. 7 of the present invention is a detecting circuit diagram of the lead-off of the alarm circuit. 如图7所示,所述差分放大电路包括第九运算放大器U9,所述窗口比较器电路包括第十运算放大器U10、第十一运算放大器U11、第二可调电阻RW2、第三可调电阻RW3、第一二极管Dl和第二二极管D2,所述报警电路包括第四可调电阻RW4、发光二极管D3和与门Gl ;所述第九运算放大器U9的正向输入端与前置放大电路的输出端连接,输出端分别与第九运算放大器U9的反向输入端、第十运算放大器Uio的正向输入端和第^ 运算放大器Uii的反向输入端连接;第十运算放大器UlO的反向输入端和第十一运算放大器Ull的正向输入端分别与第二可调电阻RW2的可调端和第三可调电阻RW3的可调端连接,所述第二可调电阻RW2和第三可调电阻RW3形成串联电路,串联电路两端分别接正负电压且在第二可调电阻RW2和第三可调电阻RW3之间连接有等电位;第十运算放大器UlO的输出端和第十一运算放大 7, the differential amplifier circuit includes a ninth operational amplifier U9, said window comparator circuit includes an operational amplifier U10 tenth, eleventh operational amplifier U11, RW2, a second adjustable resistor, the third adjustable resistor RW3, the first diode Dl, a second diode D2, the alarm circuit comprises a fourth adjustable resistor RW4, the light emitting diode D3 and a gate of Gl; the non-inverting input of the operational amplifier U9 ninth front of preamplifier circuit output terminal is connected to the output terminal of the operational amplifier U9 respectively ninth inverting input terminal of the operational amplifier positive input terminal of the tenth and first Uio ^ Uii operational amplifier inverting input terminal; a tenth of the operational amplifier UlO inverting input terminal and the positive input terminal of the eleventh operational amplifier Ull are connected to a second end of the adjustable variable resistor RW2 and RW3 third adjustable adjustable end of the resistor, said second adjustable resistor RW2 and RW3 third adjustable resistor form a series circuit, connected across the series circuits between the positive and negative voltage, and a second adjustable resistor RW2 and RW3 third adjustable resistor connected to equipotential; a tenth of the output of the operational amplifier UlO end and eleventh operational amplifier 器Ull的输出端分别串联第一二极管Dl和第二二极管D2后与第四可调电阻RW4的一端连接;所述第四可调电阻RW4的另一端连接等电位,可调端与与门Gl的输入端连接,所述与门Gl的输出端串联发光二极管D3后与中央处理器连接。 Ull output terminal is connected to one end of the resistor in series to a fourth adjustable RW4 after a first diode Dl, a second diode D2 of; the other terminal of the fourth adjustable resistor RW4 equipotential connection, adjustable end and the inputs of the gate Gl is connected, after the light emitting diode D3 connected in series with the central processor and the output of aND gate Gl.

[0029] 图8是本发明所述缓冲放大电路的电路图。 [0029] FIG 8 that the present invention is a circuit diagram of the buffer amplifier circuit. 如图8所示,所述缓冲放大电路包括电阻R22和第十二运算放大器U12,所述电阻R22—端与右胸上电极或左腹下电极的输出端连接,另一端与第十二运算放大器U12的正向输入端连接,所述第十二运算放大器U12的反相输入端与输出端连接,用以将输入电极信号进行隔离。 8, the buffer amplifier circuit including a resistor R22 and a twelfth operational amplifier U12, a resistor R22- and output ends of the lower electrode or upper electrode of the left web right chest, and the other end of the twelfth operation the positive input of the amplifier U12 is connected to the inverting input terminal and the output terminal of a twelfth operational amplifier U12 is connected to the input electrode of the signal isolation. 缓冲放大电路是心电采集输入电路的重要部分,实际上是一个阻抗转换器,在电路中起隔离作用。 A buffer amplifier circuit is an important part of the acquired ECG input circuit, an impedance converter is actually, in the circuit isolated from the role.

[0030] 为了降低位移电流,在心电导联电路中设计了右腿驱动电路。 [0030] In order to reduce the displacement current, the circuit design of the ECG lead right leg drive circuit. 如图9所示,所述右腿驱动电路包括电阻R23、电阻R24、电容ClO和第十三运算放大器U13,所述电阻R23 —端与右腹下电极的输出端连接,另一端与第十二运算放大器U12的反相输入端连接,所述第十二运算放大器U12的反相输入端与输出端之间串联有电阻R24与电容ClO的并联电路,第十二运算放大器U12的正向输入端接地。 As shown, the right leg drive circuit includes a resistor R23, a resistor R24, and a thirteenth capacitor ClO operational amplifier U13, a resistor R23 9 - terminal connected to the output electrode of the lower right ventral, the other end of the tenth two inverting input terminal of the operational amplifier U12 is connected in series with a parallel circuit of resistor R24 ​​and capacitor ClO between the inverting input terminal and the output terminal of the twelfth operational amplifier U12, U12 twelfth positive input of the operational amplifier grounded. 由于人体在通常情况下通过各种渠道拾取50Hz交流电压,这样就会在心电检测时,在信号中形成交流干扰,常在几伏以上,为了消除这种干扰,通常采用右腿驱动电路。 Since the human body pickup 50Hz AC voltage under normal circumstances, through various channels, which would detect when the ECG, alternating interference signal is formed, often more than a few volts, in order to eliminate such interference, usually the right leg drive circuit. 右腿驱动电路的工作原理是将由人体体表获得的共模电压通过负反馈放大的方式输回人体,从而达到抵消共模干扰的作用,从根本上抑制共模电压。 Working principle of the right leg drive circuit common-mode voltage is obtained by the human body through negative feedback reinfusion human enlarged manner, so as to achieve cancellation of common mode interference suppressing common-mode voltage fundamental. 接线时电极经过电阻与放大器接地端相连,能大大降低人体的共模电压。 When the wiring electrode is connected via a resistor to the ground terminal of the amplifier, it can greatly reduce the common mode voltage of the human body. 右腿驱动是心电信号提取中必需的一个环节,把混杂于原始心电信号中的共模噪声提取出来,经过一级倒相放大后,再返回到人体,使它们相互叠加,从而减小人体共模干扰的绝对值,提高信噪比,它能够将50Hz的工频干扰降低到1%—下,而且不会将心电信号中的50Hz有用信号除去,与右腿接地的方法比较,右腿驱动技术对抑制交流干扰效果更好。 A driving part of the right leg ECG is necessary for extraction, the mixed raw ECG signal to common mode noise is extracted, after an inverted amplified, and then returned to the body, so that they are superposed on each other, thereby reducing the absolute value of the body common mode interference, improve the SNR, it is possible to reduce frequency interference 50Hz to 1% - under and 50Hz useful signal will not be removed ECG signal, compared with the method of the grounded right leg, right leg drive AC interference suppressing technology to better effect. [0031 ] 上述实施方式中,本发明所涉及到的所有运算放大器均可采用LM324集成电路,仪表放大器Al可以米用AD620放大器。 [0031] The above-described embodiment, the present invention relates to the use of all available LM324 operational amplifier integrated circuit, amp meter may be used AD620 amplifier Al.

[0032] 以上所述只是本发明的优选实施方式,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也被视为本发明的保护范围。 [0032] The above are only preferred embodiments of the present invention, those of ordinary skill in the art, in the present invention without departing from the principles of the premise, can make various improvements and modifications, improvements and modifications are also the protection scope of the present invention.

Claims (10)

1.一种心电信号采集装置,其特征是,包括心电导联电路、前置放大电路、电平抬升电路、带通滤波电路、50HZ陷波电路、AD转换电路、导联脱落检测报警电路和中央处理器, 所述心电导联电路用于导入所检测的心电信号,并依次经过前置放大电路、电平抬升电路、带通滤波电路、50HZ陷波电路和AD转换电路对所述心电信号进行放大、电平抬升、滤波、陷波和模数转换等处理后发送给中央处理器,所述中央处理器对处理后的心电信号进行特征点识别,所述导联脱落检测报警电路的输入端与所述前置放大电路的输出端连接,输出端与中央处理器连接,用于对所述心电信号进行导联脱落检测; 所述心电导联电路包括右胸上电极、左腹下电极、右腹下电极、缓冲放大电路和右腿驱动电路,所述的右胸上电极及左腹下电极为心电信号采样电极,右胸上电极和左 An ECG acquisition device, characterized in that the circuit comprises ECG preamplifier circuit, a level raising circuit, a bandpass filter circuit, 50HZ trap circuit, the AD conversion circuit, an alarm detection circuit leadoff and a central processor, the ECG circuit for introducing the detected ECG, and sequentially passes through the preamplifier circuit, the level lifting circuit, a bandpass filter circuit, 50HZ trap circuit and the AD conversion circuit sent to the central processor, the central processor ECG after post-processing feature point recognition ECG signal amplification, level lift, filtering, notch processing and analog-digital conversion, the detection leadoff alarm circuit input terminal and an output terminal connected to the preamplifier circuit, an output terminal connected to the central processor, for the ECG signal leads off detection; said circuitry comprises ECG electrodes on the right chest , Zuofu lower electrode, the lower right ventral electrode, the buffer amplifier and the right leg drive circuit, the electrode on the right chest and left web sample electrode ECG electrodes on the right chest and left electrode 腹下电极分别经过缓冲放大电路与前置放大电路连接,用于对心电信号进行隔离;所述右腹下电极为右腿驱动电极,右腹下电极经过右腿驱动电路与前置放大电路连接,用于消除在心电检测时形成的交流干扰,降低人体的共模电压,提高信噪比。 Hypogastric electrodes through a buffer amplifier circuit connected to the preamplifier circuit, for isolating ECG signal; right leg drive electrode to the lower right ventral electrode, the lower electrode through the right ventral right leg drive circuit and preamplifier circuit connection, for eliminating AC interference is formed when ECG detection, reducing the common mode voltage of the body, improve the SNR.
2.根据权利要求1所述的一种心电信号采集装置,其特征是,所述前置放大电路包括双端输入、双端输出的差分放大电路,共模取样驱动电路,阻容耦合电路,以及双端输入、单端输出的差分放大电路;所述双端输入、双端输出的差分放大电路的双输入端与生物体接触电极连接,双输入端依次经过共模取样驱动电路和阻容耦合电路与双端输入、单端输出的差分放大电路的双输入端连接。 2. According to an ECG acquisition device according to claim 1, wherein said preamplifier circuit comprises a double-ended input, double-ended output differential amplifier circuit, sampling the common-mode drive circuit RC coupling circuit and a double-ended input single-ended output differential amplifier circuit; a double-ended input, differential output amplifier circuit of the double-ended dual biometric input terminal connected to the contact electrode, two-input common mode sequentially through the sampling circuit driving resistance and two-input capacitance coupled with the double-ended input circuit, a differential amplifier circuit is connected to single-ended output.
3.根据权利要求2所述的一种心电信号采集装置,其特征是,所述双端输入、双端输出的差分放大电路包括第一运算放大器U1、第二运算放大器U2、电阻R1、电阻R2和电阻R3,所述共模取样驱动电路包括第三运算放大器U3、电阻R4和电阻R5,所述阻容耦合电路包括电容Cl、电容C2、电阻R6和电阻R7,所述双端输入、单端输出的差分放大电路包括仪表放大器Al和压敏电阻R8 ;所述第一运算放大器Ul和第二运算放大器U2的正向输入端分别与生物体接触电极连接,反向输入端之间串联电阻R3,第一运算放大器Ul和第二运算放大器U2的反向输入端与输出端之间分别串联电阻Rl和电阻R2 ;所述第一运算放大器Ul的输出端串联电容Cl后与仪表放大器Al的反向输入端连接,所述第二运算放大器U2的输出端串联电容C2后与仪表放大器Al的正向输入端连接;所述第三运算放大器U3的正向输入 3. According to an ECG acquisition device according to claim 2, characterized in that the double-ended input, double-ended output of the differential amplifier circuit comprises a first operational amplifier U1, a second operational amplifier U2, resistor R1, resistors R2 and R3, the common mode sampling circuit includes a third drive an operational amplifier U3, resistors R4 and the resistor R5, the circuit comprises a resistance-capacitance coupled capacitor Cl, capacitor C2, resistor R6 and the resistor R7, the double-ended input between the positive input of the first operational amplifier Ul and a second operational amplifier U2 are respectively connected to the contact electrode organism, the inverting input; single-ended output of the differential amplifying circuit comprises an instrumentation amplifier Al R8 and varistors series resistor R3, a resistor Rl are connected in series between the resistor R2 and the operational amplifier Ul and a first inverting input terminal and the output terminal of the second operational amplifier U2; the output of said first operational amplifier Ul series capacitor Cl and amp Al inverting input connected to the output terminal of the second operational amplifier U2 is connected in series to the positive input of the instrumentation amplifier Al after capacitor C2; positive input of said third operational amplifier U3, 分别经过电阻R4和电阻R5与第一运算放大器Ul和第二运算放大器U2的输出端连接,反相输入端与输出端连接,输出端分别经过电阻R6和电阻R7与仪表放大器Al的反向输入端和正向输入端连接;所述压敏电阻R8为仪表放大器Al的外接增益调节电阻。 Respectively through the resistor R4 and the resistor R5 and the output terminal of the first operational amplifier Ul and a second operational amplifier U2 is connected to the inverting input terminal and an output terminal connected to an output terminal respectively through resistor R6 and the resistor R7 and the inverting input of the instrumentation amplifier Al and a non-inverting input terminal is connected; R8 is a varistor external instrumentation amplifier gain adjusting resistor Al.
4.根据权利要求1所述的一种心电信号采集装置,其特征是,所述带通滤波电路包括闻通滤波电路和低通滤波电路,所述的闻通滤波电路和低通滤波电路串联连接; 所述高通滤波电路包括第四运算放大器U4、电阻R9和电容C3,所述第四运算放大器U4的正向输入端经过电阻R9接地,同时经过电容C3与前置放大电路的输出端连接,反相输入端与输出端连接; 所述低通滤波电路包括第五运算放大器U5、电阻R10、电阻R11、电容C4和电容C5,所述第五运算放大器U5的正向输入端经过电容C4接地,同时依次串联电阻Rll和电阻RlO后与第四运算放大器U4的的输出端连接,反相输入端与输出端连接,第五运算放大器U5的输出端串联电容C5后连接于电阻RlO和电阻Rll之间。 4. According to an ECG acquisition device according to claim 1, characterized in that said filter circuit includes a bandpass filter circuit and smell through a low-pass filter circuit, the smell-pass filter circuit and a low pass filter circuit connected in series; the high pass filter circuit comprising a fourth operational amplifier U4, capacitor C3 and resistor R9, the positive input terminal of the fourth operational amplifier U4 is grounded through a resistor R9, while a capacitor C3 through the preamplifier circuit and an output terminal connected, an inverting input terminal and an output terminal; a low pass filter circuit includes a fifth operational amplifier U5, resistor R10, resistor R11, capacitor C4 and capacitor C5, the positive input of the fifth operational amplifier U5 through capacitor after C4 ground connection, while sequentially resistor RlO series resistor Rll and the output terminal of the fourth operational amplifier U4, the inverting input terminal and an output terminal connected to the output terminal of the fifth operational amplifier U5 is connected in series to a capacitor C5 and resistor RlO between resistors Rll.
5.根据权利要求1所述的一种心电信号采集装置,其特征是,所述电平抬升电路包括第六运算放大器U6、电阻R12、电阻R13、电阻R14、电阻R15和第一可调电阻RWl,所述第六运算放大器U6的正向输入端经过电阻R15接地,反相输入端串联电阻R12后与带通滤波电路的输出端连接,同时经过电阻R14与第一可调电阻RWl的可调端连接,所述第一可调电阻RH的两端分别与正、负电压端连接,反相输入端与输出端之间串联电阻R13。 5. According to an ECG acquisition device according to claim 1, characterized in that said level lifting circuit comprises a sixth operational amplifier U6, resistors R12, a resistor R13, a resistor R14, a resistor R15 and a first adjustable resistance RWL, the positive input terminal of the sixth operational amplifier U6 through R15 to ground, an inverting input end of the resistor series resistor R12 connected to the output of the band pass filter circuit, while passing through the first resistor R14 and the variable resistor RWL adjustable end is connected to both ends of the first resistor RH is connected to the adjustable positive and negative voltage terminal, a resistor R13 connected in series between the inverting input terminal and the output terminal.
6.根据权利要求1所述的一种心电信号采集装置,其特征是,所述50HZ陷波电路包括第七运算放大器U7、第八运算放大器U8、电阻R16、电阻R17、电阻R18、电阻R19、电阻R20、电阻R21、电容C6、电容C7、电容C8和电容C9 ;所述第七运算放大器U7的正向输入端经过并联电路与电平抬升电路的输出端连接,所述并联电路由电阻R16、电阻R17的串联电路与电容C6、电容C7的串联电路并联而成,第七运算放大器U7的反相输入端与输出端连接;所述第八运算放大器U8的正向输入端经过电阻R20与第七运算放大器U7的输出端连接,同时经过电阻R21接地,反相输入端与输出端连接,输出端经过电阻R18和电阻R19的并联电路连接于电容C6和电容C7之间,同时经过电容C8和电容C9的并联电路连接于电阻R16与电阻R17之间。 6. According to an ECG acquisition device according to claim 1, characterized in that said notch circuit comprises a seventh 50HZ an operational amplifier U7, the eighth operational amplifier U8, resistors R16, resistor R17, resistor R18, resistor R19, ​​resistor R20, resistor R21, capacitors C6, capacitor C7, the capacitor C8 and capacitor C9; the positive output terminal of said seventh input terminal of the operational amplifier U7 via the parallel circuit of the level raising circuit, the parallel circuit comprising resistor R16, a series circuit of resistor R17 and capacitor C6, C7 of the capacitor series circuit of the parallel connection, the inverting input terminal and the output terminal of the operational amplifier U7 is connected to the seventh; eighth-inverting input of the operational amplifier U8 through a resistor R20 and the seventh output terminal of the operational amplifier U7 is connected through resistor R21 to ground while the inverting input terminal and an output terminal connected to an output terminal through the parallel circuit of the resistor R18 and the resistor R19 is connected between capacitor C6 and capacitor C7, while passing capacitor C8 and capacitor C9 is connected between the parallel circuit of resistor R16 and the resistor R17.
7.根据权利要求1所述的一种心电信号采集装置,其特征是,所述AD转换电路采用ADC0809 芯片。 7. According to an ECG acquisition device according to claim 1, characterized in that, the AD conversion circuit using ADC0809 chip.
8.根据权利要求1所述的一种心电信号采集装置,其特征是,所述导联脱落检测报警电路包括差分放大电路、窗口比较器电路和报警电路,所述差分放大电路的输入端与所述前置放大电路的输出端连接,输出端与窗口比较器电路的输入端连接,所述窗口比较器电路的输出端与报警电路连接,所述报警电路与中央处理器连接,用于对所述心电信号进行导联脱落检测,并根据导联脱落检测处理向所述中央处理器提供导联脱落检测信号。 An ECG signal acquisition device according to claim 1, characterized in that the lead-off detection alarm circuit includes a differential amplifier circuit, the window comparator circuit and alarm circuit, an input terminal of the differential amplifying circuit connected to the output of the preamplifier circuit, an input terminal and an output terminal connected to a window comparator circuit, the output of the window comparator circuit connected to the alarm circuit, the alarm circuit is connected to the central processor, for the ECG signal leads off detection, and provides a leadoff detection signal to the central processor in accordance with the lead off detection process.
9.根据权利要求8所述的一种心电信号采集装置,其特征是,所述差分放大电路包括第九运算放大器U9,所述窗口比较器电路包括第十运算放大器U10、第十一运算放大器U11、第二可调电阻RW2、第三可调电阻RW3、第一二极管Dl和第二二极管D2,所述报警电路包括第四可调电阻RW4、发光二极管D3和与门Gl ;所述第九运算放大器U9的正向输入端与前置放大电路的输出端连接,输出端分别与第九运算放大器U9的反向输入端、第十运算放大器UlO的正向输入端和第十一运算放大器Ull的反向输入端连接;第十运算放大器UlO的反向输入端和第十一运算放大器Ull的正向输入端分别与第二可调电阻RW2的可调端和第三可调电阻RW3的可调端连接,所述第二可调电阻RW2和第三可调电阻RW3形成串联电路,串联电路两端分别接正负电压且在第二可调电阻RW2和第三可调电阻RW3之间连接有等电 An ECG signal acquisition device according to claim 8, characterized in that the differential amplifier circuit includes a ninth operational amplifier U9, said window comparator circuit includes an operational amplifier U10 tenth, eleventh operation amplifier U11, a second adjustable resistor RW2, the third adjustable resistor RW3, a first diode Dl, a second diode D2, the alarm circuit comprises a fourth adjustable resistor RW4, the light emitting diode D3 and a gate Gl ; output of the ninth-inverting input of the operational amplifier and the preamplifier circuit U9 is connected to an output terminal of the operational amplifier U9 respectively ninth inverting input, the positive input terminal and the tenth operational amplifier UlO eleven inverting input terminal of the operational amplifier is connected Ull; positive input of the operational amplifier inverting input terminal of tenth and eleventh operational amplifier UlO Ull are adjustable resistor RW2 second and third adjustable end adjusting the adjustable resistor RW3 end is connected to the second adjustable resistor RW2 and RW3 third adjustable resistor form a series circuit, connected across the series circuit of the positive and negative voltages, respectively and in a second and third adjustable resistor adjustable RW2 a resistor connected between the other electrically RW3 位;第十运算放大器UlO的输出端和第十一运算放大器Ull的输出端分别串联第一二极管Dl和第二二极管D2后与第四可调电阻RW4的一端连接;所述第四可调电阻RW4的另一端连接等电位,可调端与与门Gl的输入端连接,所述与门Gl的输出端串联发光二极管D3后与中央处理器连接。 Bit; UlO output terminal of the operational amplifier of a tenth and an eleventh output terminal of the operational amplifier Ull are serially connected to one end of a fourth adjustable resistor RW4 after a first diode Dl, a second diode D2 of; the first the other end of adjustable resistor RW4 four equipotential connection, and the adjustable end is connected to the input terminal of the gate Gl, after the light emitting diode D3 connected in series with the central processor and the output of aND gate Gl.
10.根据权利要求1-9任一项所述的一种心电信号采集装置,其特征是,所述缓冲放大电路包括电阻R22和第十二运算放大器U12,所述电阻R22 —端与右胸上电极或左腹下电极的输出端连接,另一端与第十二运算放大器U12的正向输入端连接,所述第十二运算放大器U12的反相输入端与输出端连接;所述右腿驱动电路包括电阻R23、电阻R24、电容ClO和第十三运算放大器U13,所述电阻R23 —端与右腹下电极的输出端连接,另一端与第十二运算放大器U12的反相输入端连接,所述第十二运算放大器U12的反相输入端与输出端之间串联有电阻R24与电容ClO的并联电路,第十二运算放大器U12的正向输入端接地。 An ECG data acquisition device according to any one of claims 1-9, wherein said buffer amplifier circuit includes a resistor R22 and a twelfth operational amplifier U12, a resistor R22 - the right end chest electrode or the lower electrode output terminal connected to the left web, the other positive input terminal of the twelfth operational amplifier U12 is connected to an inverting input terminal connected to the output terminal of a twelfth operational amplifier U12; of the right leg driving circuit includes a resistor R23, a resistor R24, and a thirteenth capacitor ClO operational amplifier U13, a resistor R23 - terminal connected to the output electrode of the lower right ventral, an inverting input terminal and the other end of the twelfth operational amplifier U12 is connected in series with a parallel circuit of resistor R24 ​​and capacitor ClO between the inverting input terminal and the output terminal of the twelfth operational amplifier U12, U12 twelfth operational amplifier positive input is grounded.
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