WO2023221465A1

WO2023221465A1 - Amplification circuit, detection chip, and wearable device

Info

Publication number: WO2023221465A1
Application number: PCT/CN2022/137674
Authority: WO
Inventors: 安奇; 王怡珊; 李烨
Original assignee: 深圳先进技术研究院
Priority date: 2022-05-18
Filing date: 2022-12-08
Publication date: 2023-11-23
Also published as: CN114978073A

Abstract

The present application is applicable to the technical field of electronic circuits, and provides an amplification circuit, a detection chip, and a wearable device. A first logic module in the amplification circuit is configured to receive a reference voltage and a first signal in target differential signals, and transmit the first signal to a current generation module. A second logic module is configured to receive the reference voltage and a second signal in the target differential signals, and transmit the second signal to the current generation module. When a direct current deviation exists between the first signal and the second signal, the current generation module is configured to generate a deviation current according to the direct current deviation, so that the deviation current enables the first logic module to generate a first direct current voltage, and enables the second logic module to generate a second direct current voltage. A voltage adjustment module is configured to collect the first direct current voltage and the second direct current voltage, and adjust the first direct current voltage and the second direct current voltage to keep the first direct current voltage and the second direct current voltage equal to a reference voltage. The amplification circuit provided in the present application can suppress the direct current deviation in the target differential signals.

Description

Amplification circuits, detection chips and wearable devices

Technical field

This application belongs to the field of electronic circuit technology, and in particular relates to an amplification circuit, a detection chip and a wearable device.

Background technique

As people pay more attention to their own health, wearable devices such as smart bracelets have been widely used. ECG signals are an important reference for human health, and detecting ECG signals is an important function of wearable devices. The current basic working principle of detecting ECG signals is to collect differential signals through differential electrodes, and transmit the collected differential signals to the ECG signal detection chip. The ECG signal detection chip amplifies, filters, and quantifies the electrical signals. However, there are the following problems during the processing: after the differential electrode comes into contact with the human body, the differential signal is transmitted to the amplifier input end of the ECG signal detection chip. Due to the DC deviation in the differential signal, the output of the amplifier is saturated and cannot provide useful AC signals. Small signals are amplified.

Contents of the invention

The embodiments of the present application provide an amplification circuit, a detection chip and a wearable device, which can solve the problem in wearable devices that due to the DC deviation in the collected differential signals, the output of the amplifier is saturated and useful AC small signals cannot be amplified. question.

In a first aspect, embodiments of the present application provide an amplification circuit, including a first logic module, a second logic module, a current generation module and a voltage adjustment module; the current generation module is connected to the first logic module and the voltage adjustment module respectively. The second logic module is electrically connected, and the voltage adjustment module is electrically connected to the first logic module and the second logic module respectively;

The first logic module is used to receive a reference voltage and a first signal in a target differential signal, and transmit the first signal to the current generation module; the second logic module is used to receive the reference voltage and a second signal in the target differential signal, and transmit the second signal to the current generation module;

When there is a DC deviation between the first signal and the second signal, the current generation module is configured to generate a deviation current according to the DC deviation, and the deviation current causes the first logic module to generate a first DC voltage, causing the second logic module to generate a second DC voltage;

The voltage adjustment module is used to collect the first DC voltage and the second DC voltage, and adjust the first DC voltage and the second DC voltage so that the first DC voltage and the second DC voltage are The two DC voltages remain equal to the reference voltage.

In a possible implementation of the first aspect, the first logic module includes a first operational amplifier, a first field effect transistor, a first current source, a second current source and a first resistor;

The positive electrode of the first current source is used to be electrically connected to the positive electrode of the first power supply, the non-inverting input terminal of the first operational amplifier is used to receive the first signal, and the inverting input terminal of the first operational amplifier is respectively The source of the first field effect transistor, the negative electrode of the first current source and the current generation module are electrically connected. The output terminal of the first operational amplifier is electrically connected to the gate of the first field effect transistor. connection, the drain of the first field effect transistor is electrically connected to the first end of the first resistor, the positive electrode of the second current source and the voltage adjustment module respectively, and the second end of the first resistor Used to receive the reference voltage, the negative electrode of the second current source is used to be electrically connected to the negative electrode of the first power source; the current provided by the first current source is equal to the current provided by the second current source And the direction is the same.

In a possible implementation of the first aspect, the second logic module includes a second operational amplifier, a second field effect transistor, a third current source, a fourth current source and a second resistor;

The positive electrode of the third current source is used to be electrically connected to the positive electrode of the second power supply, the non-inverting input terminal of the second operational amplifier is used to receive the second signal, and the inverting input terminal of the second operational amplifier is respectively The source of the second field effect transistor, the negative electrode of the third current source and the current generation module are electrically connected. The output terminal of the second operational amplifier is electrically connected to the gate of the second field effect transistor. connection, the drain of the second field effect transistor is electrically connected to the first end of the second resistor, the positive electrode of the fourth current source and the voltage adjustment module respectively, and the second end of the second resistor used to receive the reference voltage, the negative electrode of the fourth current source is used to be electrically connected to the negative electrode of the second power supply; the current provided by the third current source, the current provided by the fourth current source and the The currents provided by the first current sources are equal in magnitude and direction.

In a possible implementation of the first aspect, the first field effect transistor and the second field effect transistor are P-type field effect transistors, and the first current source and the third current source are P-type field effect transistors. Type current source, the second current source and the fourth current source are N-type current sources.

In a possible implementation of the first aspect, the first logic module includes a third operational amplifier, a third field effect transistor, a fifth current source, a sixth current source, a first current mirror and a third resistor;

The positive electrode of the fifth current source is used to be electrically connected to the positive electrode of the first power supply, the non-inverting input terminal of the third operational amplifier is used to receive the first signal, and the inverting input terminal of the third operational amplifier is respectively The source of the third field effect transistor, the negative electrode of the fifth current source and the current generation module are electrically connected. The output terminal of the third operational amplifier is electrically connected to the gate of the third field effect transistor. connection, the drain of the third field effect transistor is electrically connected to the input end of the first current mirror, and the output end of the first current mirror is respectively connected to the first end of the third resistor and the sixth The negative electrode of the current source is electrically connected to the voltage adjustment module, the common end of the first current mirror is used to be electrically connected to the negative electrode of the first power supply, and the second end of the third resistor is used to receive the reference voltage, the positive electrode of the sixth current source is used to be electrically connected to the positive electrode of the first power supply; the current provided by the fifth current source is equal in magnitude and direction to the current provided by the sixth current source.

In a possible implementation of the first aspect, the second logic module includes a fourth operational amplifier, a fourth field effect transistor, a seventh current source, an eighth current source, a second current mirror and a fourth resistor;

The positive electrode of the seventh current source is used to be electrically connected to the positive electrode of the second power supply, the non-inverting input terminal of the fourth operational amplifier is used to receive the second signal, and the inverting input terminal of the fourth operational amplifier is respectively The source of the fourth field effect transistor, the negative electrode of the seventh current source and the current generation module are electrically connected. The output terminal of the fourth operational amplifier is electrically connected to the gate of the fourth field effect transistor. connection, the drain of the fourth field effect transistor is electrically connected to the input end of the second current mirror, and the output end of the second current mirror is respectively connected to the first end of the fourth resistor and the eighth The negative electrode of the current source is electrically connected to the voltage adjustment module, the common output end of the second current mirror is used to be electrically connected to the negative electrode of the second power supply, and the second end of the fourth resistor is used to receive the Reference voltage, the positive electrode of the eighth current source is used to be electrically connected to the positive electrode of the second power supply; the current provided by the seventh current source, the current provided by the eighth current source and the fifth current source The currents supplied are equal in magnitude and direction.

In a possible implementation of the first aspect, the current generating module includes a fifth resistor; a first end of the fifth resistor is electrically connected to the first logic module, and a second end of the fifth resistor is electrically connected to the first logic module. The terminal is electrically connected to the second logic module.

In a possible implementation of the first aspect, the voltage adjustment module includes a first transconductance unit, a second transconductance unit and a first capacitor;

The positive input terminal of the first transconductance unit is electrically connected to the second logic module and the positive output terminal of the second transconductance unit respectively, and the negative input terminal of the first transconductance unit is respectively connected to the third transconductance unit. A logic module is electrically connected to the negative output terminal of the second transconductance unit, and the positive output terminal of the first transconductance unit is respectively connected to the positive electrode of the first capacitor and the negative input terminal of the second transconductance unit. Electrically connected, the negative output terminal of the first transconductance unit is electrically connected to the negative electrode of the first capacitor and the positive input terminal of the second transconductance unit respectively.

In a second aspect, embodiments of the present application provide a detection chip, including the amplification circuit described in any one of the first aspects.

In a third aspect, embodiments of the present application provide a wearable device, including the detection chip described in the second aspect.

Compared with the prior art, the beneficial effects of the embodiments of the present application are:

An embodiment of the present application provides an amplification circuit, including a first logic module, a second logic module, a current generation module and a voltage adjustment module. The current generating module is electrically connected to the first logic module and the second logic module respectively, and the voltage adjustment module is electrically connected to the first logic module and the second logic module respectively. The first logic module receives the reference voltage and the first signal of the target differential signal, and transmits the first signal to the current generation module. The second logic module receives the reference voltage and the second signal of the target differential signal, and transmits the second signal to the current generation module. When there is a DC deviation between the first signal and the second signal in the collected target differential signal, the current generation module generates a deviation current according to the DC deviation. The deviation current causes the first logic module to generate a first DC voltage, causing the second logic module to generate a third DC voltage. Two DC voltages. Due to the existence of DC deviation, there will be a deviation between the first DC voltage and the second DC voltage. As long as there is a deviation between the first DC voltage and the second DC voltage, the voltage adjustment module will always adjust the first DC voltage. The DC voltage and the second DC voltage finally make the first DC voltage and the second DC voltage equal to the reference voltage, that is, the deviation existing between the first DC voltage and the second DC voltage is eliminated, thus suppressing the target differential signal. The DC deviation between the first signal and the second signal prevents the output of the amplifier circuit from being saturated and can amplify useful small AC signals. When the first DC voltage and the second DC voltage remain equal to the reference voltage, the current generation module generates a differential current according to the first signal and the second signal, and the differential current causes the first logic module to generate the first voltage in the differential voltage, so that the The second logic module generates the second voltage in the differential voltage, that is, amplifies the AC small signal in the target differential signal.

It can be understood that the beneficial effects of the above second to third aspects can be referred to the relevant descriptions in the above first aspect, and will not be described again here.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of the present application. For some embodiments, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a functional block diagram of an amplifier circuit provided by an embodiment of the present application;

Figure 2 is a schematic circuit connection diagram of an amplifier circuit provided by an embodiment of the present application;

Figure 3 is a schematic circuit connection diagram of an amplifier circuit provided by another embodiment of the present application;

Figure 4 is a system equivalent diagram of an amplifier circuit provided by an embodiment of the present application;

Figure 5 is a schematic diagram of the differential mode response of an amplifier circuit provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of the common mode suppression characteristics of an amplifier circuit provided by an embodiment of the present application.

In the figure: 100, first logic module; 200, current generation module; 300, second logic module; 400, voltage adjustment module.

Detailed ways

In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures and technologies are provided to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and/or components but does not exclude one or more other The presence or addition of features, integers, steps, operations, elements, components and/or collections thereof.

It will also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, to mean "once determined" or "in response to a determination" or "once the [described condition or event] is detected ]" or "in response to detection of [the described condition or event]".

In addition, in the description of this application and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

Reference in the specification of this application to "one embodiment" or "some embodiments" or the like means that a particular feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Therefore, the phrases "in one embodiment", "in some embodiments", "in other embodiments", "in other embodiments", etc. appearing in different places in this specification are not necessarily References are made to the same embodiment, but rather to "one or more but not all embodiments" unless specifically stated otherwise. The terms “including,” “includes,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized.

Wearable devices such as smart bracelets have been widely used. The electrocardiogram signal detection chip used in wearable devices such as smart bracelets should ensure that the electrocardiogram signal detection chip detects small AC signals in the collected differential signals without saturation of the amplifier. to zoom in. Existing amplifiers use a fully differential structure composed of dual operational amplifiers, but this structure has no suppression effect on the DC deviation present in the differential signal. When the DC deviation is small, the amplifier will not saturate. When the DC deviation is large, the output of the amplifier will be saturated, making it impossible to amplify the small AC signal in the differential signal.

In order to solve the above problem, as shown in FIG. 1 , an embodiment of the present application provides an amplification circuit, including a first logic module 100 , a second logic module 300 , a current generation module 200 and a voltage adjustment module 400 . The current generating module 200 is electrically connected to the first logic module 100 and the second logic module 300 respectively. The voltage adjustment module 400 is electrically connected to the first logic module 100 and the second logic module 300 respectively.

Specifically, the first logic module 100 receives the first signal among the reference voltage and the target differential signal, and transmits the first signal to the current generation module 200 . The second logic module 300 receives the reference voltage and the second signal in the target differential signal, and transmits the second signal to the current generation module 200 .

When there is a DC deviation between the first signal and the second signal, the current generation module 200 generates a deviation current according to the DC deviation. The deviation current causes the first logic module 100 to generate a first DC voltage, and the second logic module 300 to generate a second DC voltage. Due to the existence of DC deviation, there is also a deviation between the first DC voltage and the second DC voltage. In order to eliminate the deviation between the first DC voltage and the second DC voltage, the voltage adjustment module 400 collects the first DC voltage and the second DC voltage. two DC voltages, and adjust the first DC voltage and the second DC voltage so that the first DC voltage and the second DC voltage remain equal to the reference voltage, that is, the difference between the first DC voltage and the second DC voltage is eliminated. Deviation, thus suppressing the DC deviation between the first signal and the second signal in the target differential signal, so that the output of the amplifier circuit will not be saturated, and useful AC small signals can be amplified.

When the first DC voltage and the second DC voltage remain equal to the reference voltage, the current generating module 200 generates a differential current according to the first signal and the second signal. The differential current causes the first logic module 100 to generate the first differential voltage. voltage, so that the second logic module 300 generates the second voltage in the differential voltage, that is, amplifies the AC small signal in the target differential signal.

It should be noted that the DC deviation is the DC voltage difference between the first signal and the second signal.

As shown in FIG. 2 , the first logic module 100 includes a first operational amplifier AMP1, a first field effect transistor M1, a first current source I1, a second current source I2 and a first resistor R1. The positive electrode of the first current source I1 is used to be electrically connected to the positive electrode of the first power supply, that is, to be electrically connected to the voltage VDD1. The non-inverting input terminal of the first operational amplifier AMP1 is used to receive the first signal V _IP . The inverting input terminal of the first operational amplifier AMP1 is electrically connected to the source of the first field effect transistor M1 , the negative electrode of the first current source I1 and the current generation module 200 respectively. The output terminal of the first operational amplifier AMP1 is electrically connected to the gate of the first field effect transistor M1. The drain of the first field effect transistor M1 is electrically connected to the first end of the first resistor R1, the anode of the second current source I2 and the voltage adjustment module 400 respectively. The second terminal of the first resistor R1 is used to receive the reference voltage _VREF . The negative electrode of the second current source I2 is used to be electrically connected to the negative electrode of the first power source, that is, to be electrically connected to the voltage VSS1. The current provided by the first current source I1 and the current provided by the second current source I2 are equal in magnitude and direction.

Specifically, the non-inverting input terminal of the first operational amplifier AMP1 receives the first signal V _IP . Due to the action of the operational amplifier, the source of the first field effect transistor M1 is locked, so that the source of the first field effect transistor M1 tracks the first signal V IP. Signal V _IP , thereby causing one end of the current generation module 200 to receive the first signal V _IP .

When analyzing the first logic module 100 independently, the second terminal of the first resistor R1 receives the reference voltage V _REF . The non-inverting input terminal of the first operational amplifier AMP1 receives the first signal V _IP . In order to make the first field effect transistor M1 work normally, the source voltage of the first field effect transistor M1 should be greater than the drain voltage. Therefore, only when the first signal V When _IP is greater than the reference voltage V _REF , the first field effect transistor M1 will work normally. When the first field effect transistor M1 operates normally, the current provided by the first current source I1 flows out through the first field effect transistor M1. Since the current provided by the first current source I1 and the current provided by the second current source I2 are equal in magnitude and direction, The same, so no current will be generated on the first resistor R1, and the voltage output by the first terminal of the first resistor R1 is the reference voltage _VREF .

As shown in FIG. 2 , the second logic module 300 includes a second operational amplifier AMP2, a second field effect transistor M2, a third current source I3, a fourth current source I4, and a second resistor R2. The positive electrode of the third current source I3 is used to be electrically connected to the positive electrode of the second power supply, that is, to be electrically connected to the voltage VDD2. The non-inverting input terminal of the second operational amplifier AMP2 is used to receive the second signal V _IN . The inverting input terminal of the second operational amplifier AMP2 is electrically connected to the source of the second field effect transistor M2 , the negative electrode of the third current source I3 and the current generation module 200 respectively. The output terminal of the second operational amplifier AMP2 is electrically connected to the gate of the second field effect transistor M2. The drain of the second field effect transistor M2 is electrically connected to the first end of the second resistor R2, the positive electrode of the fourth current source I4 and the voltage adjustment module 400 respectively. The second terminal of the second resistor R2 is used to receive the reference voltage _VREF . The negative electrode of the fourth current source I4 is used to be electrically connected to the negative electrode of the second power source, that is, to be electrically connected to the voltage VSS2. The current provided by the third current source I3 and the current provided by the fourth current source I4 are equal in magnitude and direction to the current provided by the first current source I1.

Specifically, the non-inverting input terminal of the second operational amplifier AMP2 receives the second signal V _IN . Due to the action of the operational amplifier, the source of the second field effect transistor M2 is locked, so that the source of the second field effect transistor M2 tracks the second signal V IN. The signal V _IN causes the other end of the current generation module 200 to receive the second signal V _IN .

When analyzing the second logic module 300 independently, the second terminal of the second resistor R2 receives the reference voltage V _REF . The non-inverting input terminal of the second operational amplifier AMP2 receives the second signal V _IN . In order to make the second field effect transistor M2 work normally, the source voltage of the second field effect transistor M2 should be greater than the drain voltage. Therefore, only when the second signal V When _IN is greater than the reference voltage V _REF , the second field effect transistor M2 will work normally. When the second field effect transistor M2 operates normally, the current provided by the third current source I3 flows out through the second field effect transistor M2. Since the current provided by the third current source I3, the current provided by the fourth current source I4 and the first current The currents provided by the source I1 are equal in magnitude and direction, so no current is generated on the second resistor R2, and the voltage output by the first terminal of the second resistor R2 is the reference voltage _VREF .

For example, the first field effect transistor M1 and the second field effect transistor M2 are P-type field effect transistors. The first current source I1 and the third current source I3 are P-type current sources, and the second current source I2 and the fourth current source I4 are N-type current sources.

It should be noted that the first resistor R1 and the second resistor R2 in the embodiment of the present application are equal. The first power supply and the second power supply in the embodiment of the present application may be the same power supply, or they may be two different power supplies.

As shown in FIG. 3 , the first logic module 100 includes a third operational amplifier AMP3, a third field effect transistor M3, a fifth current source I5, a sixth current source I6, a first current mirror CM1 and a third resistor R3. The positive electrode of the fifth current source I5 is used to be electrically connected to the positive electrode of the first power supply, that is, to be electrically connected to VDD1. The non-inverting input terminal of the third operational amplifier AMP3 is used to receive the first signal V _IP . The inverting input end of the third operational amplifier AMP3 is electrically connected to the source of the third field effect transistor M3, the negative electrode of the fifth current source I5 and the current generation module 200 respectively. The output terminal of the third operational amplifier AMP3 is electrically connected to the gate of the third field effect transistor M3. The drain of the third field effect transistor M3 is electrically connected to the input terminal of the first current mirror CM1. The output terminal of the first current mirror CM1 is electrically connected to the first terminal of the third resistor R3, the negative electrode of the sixth current source I6 and the voltage adjustment module 400 respectively. The common terminal of the first current mirror CM1 is used to be electrically connected to the negative electrode of the first power supply, that is, to be electrically connected to the voltage VSS1. The second terminal of the third resistor R3 is used to receive the reference voltage _VREF . The positive electrode of the sixth current source I6 is used to be electrically connected to the positive electrode of the first power supply, that is, to be electrically connected to the voltage VDD1. The current provided by the fifth current source I5 and the current provided by the sixth current source I6 are equal in magnitude and in the same direction.

Specifically, the non-inverting input terminal of the third operational amplifier AMP3 receives the first signal V _IP . Due to the action of the operational amplifier, the source of the third field effect transistor M3 is locked, so that the source of the third field effect transistor M3 tracks the first signal V IP. Signal V _IP , thereby causing one end of the current generation module 200 to receive the first signal V _IP .

When analyzing the first logic module 100 independently, the non-inverting input terminal of the third operational amplifier AMP3 receives the first signal V _IP . Since the first signal V _IP must be greater than the voltage VSS1, the third field effect transistor M3 can work normally. This circuit structure It is not restricted by the fact that the first signal V _IP must be greater than the reference voltage V _REF . When the third field effect transistor M3 operates normally, the current provided by the fifth current source I5 flows out through the third field effect transistor M3, and then is copied through the first current mirror CM1. When the ratio of the first current mirror CM1 is 1:1 When , the current on the right side of the first current mirror CM1 is the same as the current on the left side. Since the current provided by the fifth current source I5 and the current provided by the sixth current source I6 are equal in magnitude and direction, there is no current flowing on the third resistor R3. However, the voltage output by the first terminal of the third resistor R3 is the reference voltage _VREF .

For example, the third field effect transistor M3 is a P-type field effect transistor.

As shown in FIG. 3 , the second logic module 300 includes a fourth operational amplifier AMP4, a fourth field effect transistor M4, a seventh current source I7, an eighth current source I8, a second current mirror CM2 and a fourth resistor R4. The positive electrode of the seventh current source I7 is used to be electrically connected to the positive electrode of the second power supply, that is, to be electrically connected to the voltage VDD2. The non-inverting input terminal of the fourth operational amplifier AMP4 is used to receive the second signal V _IN . The inverting input end of the fourth operational amplifier AMP4 is electrically connected to the source of the fourth field effect transistor M4, the negative electrode of the seventh current source I7 and the current generation module 200 respectively. The output terminal of the fourth operational amplifier AMP4 is electrically connected to the gate of the fourth field effect transistor M4. The drain of the fourth field effect transistor M4 is electrically connected to the input terminal of the second current mirror CM2. The output terminal of the second current mirror CM2 is electrically connected to the first terminal of the fourth resistor R4, the negative electrode of the eighth current source I8 and the voltage adjustment module 400 respectively. The common output terminal of the second current mirror CM2 is used to be electrically connected to the negative electrode of the second power supply, that is, to be electrically connected to the voltage VSS2. The second terminal of the fourth resistor R4 is used to receive the reference voltage _VREF . The positive electrode of the eighth current source I8 is used to be electrically connected to the positive electrode of the second power supply, that is, to be electrically connected to the voltage VDD2. The current provided by the seventh current source I7, the current provided by the eighth current source I8 and the current provided by the fifth current source I5 are equal in magnitude and direction.

Specifically, the non-inverting input terminal of the fourth operational amplifier AMP4 receives the second signal V _IN . Due to the action of the operational amplifier, the source of the fourth field effect transistor M4 is locked, so that the source of the fourth field effect transistor M4 tracks the second signal. The signal V _IN causes the other end of the current generation module 200 to receive the second signal V _IN .

When the second logic module 300 is independently analyzed, the non-inverting input terminal of the fourth operational amplifier AMP4 receives the second signal V _IN . Since the second signal V _IN must be greater than the voltage VSS2, the fourth field effect transistor M4 can operate normally. This circuit The structure is not limited by the fact that the second signal V _IN must be greater than the reference voltage V _REF . When the fourth field effect transistor M4 works normally, the current provided by the seventh current source I7 flows out through the fourth field effect transistor M4, and then is copied through the second current mirror CM2. When the ratio of the second current mirror CM2 is 1:1 When , the current on the left side of the second current mirror CM2 is the same as the current on the right side. Since the current provided by the seventh current source I7, the current provided by the eighth current source I8 and the current provided by the fifth current source I5 are equal in magnitude and direction, Therefore, no current flows through the fourth resistor R4, and the voltage output by the first terminal of the fourth resistor R4 is the reference voltage _VREF .

For example, the fourth field effect transistor M4 is a P-type field effect transistor.

It should be noted that the third resistor R3 and the fourth resistor R4 in the embodiment of the present application are equal.

As shown in Figures 2 and 3, the current generation module 200 includes a fifth resistor R5. The first end of the fifth resistor R5 is electrically connected to the first logic module 100 . The second end of the fifth resistor R5 is electrically connected to the second logic module 300 .

Specifically, as shown in FIG. 2 , the first end of the fifth resistor R5 is electrically connected to the source of the first field effect transistor M1 in the first logic module 100 . The second end of the fifth resistor R5 is electrically connected to the source of the second field effect transistor M2 in the second logic module 300 .

When there is a DC deviation between the first signal V _IP and the second signal V _IN and the DC deviation is greater than 0, that is, the DC voltage on the first end of the fifth resistor R5 is greater than the DC voltage on the second end of the fifth resistor R5 , therefore a DC voltage drop will be generated at both ends of the fifth resistor R5, thereby generating a deviation current, and the direction of the deviation current is from left to right. Combined with the above analysis and limitation, since the current provided by the first current source I1 and the current provided by the second current source I2 are equal in magnitude and direction, and the current provided by the third current source I3 and the current provided by the fourth current source I4 The current provided by the first current source I1 is equal in magnitude and direction. When a deviation current is generated on the fifth resistor R5, it will cause currents from left to right to be generated on both the first resistor R1 and the second resistor R2. Therefore, the first A voltage drop will occur on the resistor R1, so that the first DC voltage output by the first logic module 100 is less than the reference voltage _VREF . A voltage drop will also occur on the second resistor R2, causing the second DC voltage output by the second logic module 300 to be greater than the reference voltage V _REF , resulting in a deviation between the first DC voltage and the second DC voltage. The existence of this deviation will affect The amplifier circuit works normally. As long as there is a deviation between the first DC voltage and the second DC voltage, the voltage adjustment module 400 will continue to adjust the first DC voltage and the second DC voltage, and finally keep the first DC voltage and the second DC voltage equal to the reference voltage. That is, the deviation existing between the first DC voltage and the second DC voltage is eliminated, thereby suppressing the DC deviation between the first signal and the second signal in the target differential signal, so that the output of the amplifier circuit will not be saturated, which can be useful for The small AC signal is amplified.

When there is no DC deviation between the first signal V _IP and the second signal V _IN , no DC voltage drop will occur on the fifth resistor R5, and no deviation current will occur. The first DC voltage and the second DC voltage are different from the reference Voltage V _REF remains equal. When the first DC voltage and the second DC voltage remain equal to the reference voltage V _REF , the first signal V _IP and the second signal V _IN will generate a differential current in the fifth resistor R5. Assume that the differential current is (V _IP -V _IN )/R5, the direction of the differential current is from left to right. At this time, the current source in Figure 2 is equivalent to an open circuit, so the currents flowing through the first resistor R1 and the second resistor R2 are both differential currents and the current directions are from left to right. Then the voltage drop of the first resistor R1 is (V _IP -V _IN )*R1/R5, so that the first voltage V _O1 in the differential voltage is less than the reference voltage V _REF , that is, V _O1 =V _REF -(V _IP -V _IN )*R1/R5, the voltage drop of the second resistor R2 is (V _IP -V _IN )*R2/R5, so that the second voltage V _O2 in the differential voltage is greater than the reference voltage V _REF , that is, V _O2 =V _REF +( V _IP -V _IN )*R2/R5, since the first resistor R1 and the second resistor R2 are equal, the output AC voltage V _O =V _O2 -V _O1 =2(V _IP -V _IN )*R1/R5, It can be obtained that the gain of the amplifier circuit is 2*R1/R5, so the output of the amplifier circuit is the AC voltage V _O superimposed on the DC bias V _REF .

As shown in FIGS. 2 and 3 , the voltage adjustment module 400 includes a first transconductance unit G _m1 , a second transconductance unit G _m2 and a first capacitor C1 . The positive input terminal of the first transconductance unit G _m1 is electrically connected to the second logic module 300 and the positive output terminal of the second transconductance unit G _m2 respectively. The negative input terminal of the first transconductance unit G _m1 is electrically connected to the negative output terminals of the first logic module 100 and the second transconductance unit G _m2 respectively. The positive output terminal of the first transconductance unit G _m1 is electrically connected to the positive electrode of the first capacitor C1 and the negative input terminal of the second transconductance unit G _m2 respectively. The negative output terminal of the first transconductance unit G _m1 is electrically connected to the negative electrode of the first capacitor C1 and the positive input terminal of the second transconductance unit G _m2 respectively.

Specifically, as shown in FIG. 2 , the positive input end of the first transconductance unit G _m1 is electrically connected to the first end of the second resistor R2 and the positive output end of the second transconductance unit G _m2 respectively. The negative input terminal of the first transconductance unit G _m1 is electrically connected to the first terminal of the first resistor R1 and the negative output terminal of the second transconductance unit G _m2 respectively. The positive output terminal of the first transconductance unit G _m1 is electrically connected to the positive electrode of the first capacitor C1 and the negative input terminal of the second transconductance unit G _m2 respectively. The negative output terminal of the first transconductance unit G _m1 is electrically connected to the negative electrode of the first capacitor C1 and the positive input terminal of the second transconductance unit G _m2 respectively.

According to the above analysis, it can be seen that when there is a DC deviation between the first signal V _IP and the second signal V _IN and the DC deviation is greater than 0, there will be a deviation between the first DC voltage and the second DC voltage and the second DC voltage will greater than the first DC voltage. The first transconductance unit G _m1 collects a first DC voltage and a second DC voltage, where the second DC voltage is greater than the first DC voltage. The positive output terminal of the first transconductance unit G _m1 outputs a current, and the negative output terminal inputs a current, so that A voltage difference is formed on the first capacitor C1, and the voltage difference is positive on the left and negative on the right. Then the voltage on the positive input terminal of the second transconductance unit G _m2 is less than the voltage on the negative input terminal, so that the negative output terminal of the second transconductance unit G _m2 outputs a current and the positive output terminal inputs a current, which is the first resistor R1 A current from right to left is provided, and a current from right to left is provided for the second resistor R2, thereby adjusting the voltage drop on the first resistor R1 and the second resistor R2, and finally making the first DC voltage equal to the second resistor R2. The deviation between DC voltages is close to 0 and remains equal to the reference voltage V _REF .

As shown in Figure 4, except for the first resistor R1, the second resistor R2 and the voltage adjustment module 400 in Figure 2, the remaining circuit is represented by a fully differential transconductance unit, and the transconductance value is G _m0 =1/R5, and then The voltage adjustment module 400 is equivalent to an inductor L, L=C1/(G _m1 *G _m2 ), so the amplification circuit can be represented as the simplified system diagram on the right side of Figure 4 . The system transfer function can be expressed as

It can be seen that s=0, that is, in the DC state, the system transfer function is equal to 0, and the amplifier circuit does not amplify the DC signal and has high-pass characteristics. When the frequency is higher, the independent variable in the denominator is greater than the DC amount, and the function value of the system transfer function is constant and equal to the gain of the amplifier circuit. The pole of the high-pass filter characteristic -3dB bandwidth corresponds to s=-2R1/L. In the application of wearable devices that detect ECG signals, the bandwidth needs to be set to less than 1Hz. Considering the values of the first transconductance unit G _m1 and the second transconductance unit G _m2 , a larger capacitor needs to be used to achieve a larger The inductance, for example, R1=10MΩ, requires L>3.2MH. The transconductance value of the first transconductance unit G _m1 and the second transconductance unit G _m2 is equal to 0.1μS, then the capacitance C1 of the first capacitor C1>32nF. That is, the amplifier circuit uses an off-chip capacitor to achieve the DC suppression characteristics of the fully differential signal.

Because the 50Hz power frequency interference of the power supply network is prevalent in the environment. The coupling effect with the equivalent capacitance of the power supply line causes the human body to always have a strong 50Hz signal. This signal is collected by the differential electrode and transmitted to the amplifier input end of the wearable device, which is reflected as common mode interference. Therefore, when a wearable device collects differential signals, in addition to suppressing the DC deviation present in the target differential signal, the common mode signal should also be suppressed. As shown in Figure 2, regardless of whether there is a DC offset between the first signal V _IP and the second signal V _IN , when a common mode signal is input, the first signal V _IP and the second signal V _IN will synchronize with the common mode signal. changes, causing the voltages at both ends of the fifth resistor R5 to change simultaneously, and no AC current will be generated on the fifth resistor R5. Therefore, there is no common-mode interference signal at the output end of the amplifier circuit provided by the embodiment of the present application, and the common-mode interference is well suppressed.

This application simulates and verifies the amplifier circuit. The high-pass broadband of the amplifier circuit is set to 1Hz, the gain is set to 20 times, the DC deviation is set to 100mV, and a field effect tube is used instead of the current source. As shown in Figure 5, it is the simulation result of the differential mode response of the amplifier circuit. From Figure 5, we can see that the low-frequency signal is suppressed, that is, the amplifier circuit suppresses the DC deviation in the target differential signal. The high-pass filter has a -3dB bandwidth of 1Hz and a passband gain of 26dB. As shown in Figure 6, it is the simulation result of the common mode rejection characteristics of the amplifier circuit. It can be seen from Figure 6 that the output suppression of the common-mode input is 92dB at 50Hz. The gain of the target differential signal corresponding to 50Hz is 26dB, so the common-mode rejection ratio CMRR = 118dB@50Hz.

An embodiment of the present application also provides a detection chip, including the above-mentioned amplification circuit.

Specifically, when there is a DC deviation in the collected target differential signal, the current generation module in the amplifier circuit generates a deviation current from the DC deviation. The deviation current causes the first logic module to generate a first DC voltage, and causes the second logic module to generate a second DC voltage. DC voltage, due to the existence of DC deviation, there will be a deviation between the first DC voltage and the second DC voltage. As long as there is a deviation between the first DC voltage and the second DC voltage, the voltage adjustment module will always adjust the first DC voltage. voltage and the second DC voltage, ultimately keeping the first DC voltage and the second DC voltage equal to the reference voltage, that is, eliminating the deviation existing between the first DC voltage and the second DC voltage, thus suppressing the target differential signal. The DC deviation between the first signal and the second signal prevents the output of the amplifier circuit from being saturated and can amplify useful small AC signals. When the first DC voltage and the second DC voltage remain equal to the reference voltage, the current generation module generates a differential current according to the first signal and the second signal, and the differential current causes the first logic module to generate the first voltage in the differential voltage, so that the The second logic module generates the second voltage in the differential voltage, that is, amplifies the AC small signal in the target differential signal. The amplified signal will be transmitted to the detection chip for subsequent processing.

An embodiment of the present application also provides a wearable device, including the above detection chip.

The wearable device provided by the embodiment of the present application suppresses the DC deviation between the first signal and the second signal in the target differential signal, so that the output of the amplifier circuit will not be saturated, and can amplify useful AC small signals. Specific working principle Please refer to the description of the working principles of the detection chip and amplifier circuit mentioned above, which will not be described again here.

In the above embodiments, each embodiment is described with its own emphasis. For parts that are not detailed or documented in a certain embodiment, please refer to the relevant descriptions of other embodiments.

The above-described embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still implement the above-mentioned implementations. The technical solutions described in the examples are modified, or some of the technical features are equivalently replaced; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in the embodiments of this application, and should be included in within the protection scope of this application.

Claims

An amplifier circuit, characterized in that it includes a first logic module, a second logic module, a current generation module and a voltage adjustment module; the current generation module is electrically connected to the first logic module and the second logic module respectively. , the voltage adjustment module is electrically connected to the first logic module and the second logic module respectively;

The first logic module is used to receive a reference voltage and a first signal in a target differential signal, and transmit the first signal to the current generation module; the second logic module is used to receive the reference voltage and a second signal in the target differential signal, and transmit the second signal to the current generation module;

When there is a DC deviation between the first signal and the second signal, the current generation module is configured to generate a deviation current according to the DC deviation, and the deviation current causes the first logic module to generate a first DC voltage, causing the second logic module to generate a second DC voltage;

The voltage adjustment module is used to collect the first DC voltage and the second DC voltage, and adjust the first DC voltage and the second DC voltage so that the first DC voltage and the second DC voltage are The two DC voltages remain equal to the reference voltage.
The amplifier circuit according to claim 1, wherein the first logic module includes a first operational amplifier, a first field effect transistor, a first current source, a second current source and a first resistor;

The positive electrode of the first current source is used to be electrically connected to the positive electrode of the first power supply, the non-inverting input terminal of the first operational amplifier is used to receive the first signal, and the inverting input terminal of the first operational amplifier is respectively The source of the first field effect transistor, the negative electrode of the first current source and the current generation module are electrically connected. The output terminal of the first operational amplifier is electrically connected to the gate of the first field effect transistor. connection, the drain of the first field effect transistor is electrically connected to the first end of the first resistor, the positive electrode of the second current source and the voltage adjustment module respectively, and the second end of the first resistor Used to receive the reference voltage, the negative electrode of the second current source is used to be electrically connected to the negative electrode of the first power source; the current provided by the first current source is equal to the current provided by the second current source And the direction is the same.
The amplifier circuit according to claim 2, wherein the second logic module includes a second operational amplifier, a second field effect transistor, a third current source, a fourth current source and a second resistor;

The positive electrode of the third current source is used to be electrically connected to the positive electrode of the second power supply, the non-inverting input terminal of the second operational amplifier is used to receive the second signal, and the inverting input terminal of the second operational amplifier is respectively The source of the second field effect transistor, the negative electrode of the third current source and the current generation module are electrically connected. The output terminal of the second operational amplifier is electrically connected to the gate of the second field effect transistor. connection, the drain of the second field effect transistor is electrically connected to the first end of the second resistor, the positive electrode of the fourth current source and the voltage adjustment module respectively, and the second end of the second resistor used to receive the reference voltage, the negative electrode of the fourth current source is used to be electrically connected to the negative electrode of the second power supply; the current provided by the third current source, the current provided by the fourth current source and the The currents provided by the first current sources are equal in magnitude and direction.
The amplifier circuit according to claim 3, wherein the first field effect transistor and the second field effect transistor are P-type field effect transistors, and the first current source and the third current source are P-type field effect transistors. P-type current source, the second current source and the fourth current source are N-type current sources.
The amplifier circuit according to claim 1, wherein the first logic module includes a third operational amplifier, a third field effect transistor, a fifth current source, a sixth current source, a first current mirror and a third resistor. ;

The positive electrode of the fifth current source is used to be electrically connected to the positive electrode of the first power supply, the non-inverting input terminal of the third operational amplifier is used to receive the first signal, and the inverting input terminal of the third operational amplifier is respectively The source of the third field effect transistor, the negative electrode of the fifth current source and the current generation module are electrically connected. The output terminal of the third operational amplifier is electrically connected to the gate of the third field effect transistor. connection, the drain of the third field effect transistor is electrically connected to the input end of the first current mirror, and the output end of the first current mirror is respectively connected to the first end of the third resistor and the sixth The negative electrode of the current source is electrically connected to the voltage adjustment module, the common end of the first current mirror is used to be electrically connected to the negative electrode of the first power supply, and the second end of the third resistor is used to receive the reference voltage, the positive electrode of the sixth current source is used to be electrically connected to the positive electrode of the first power supply; the current provided by the fifth current source is equal in magnitude and direction to the current provided by the sixth current source.
The amplifier circuit according to claim 5, wherein the second logic module includes a fourth operational amplifier, a fourth field effect transistor, a seventh current source, an eighth current source, a second current mirror and a fourth resistor. ;

The positive electrode of the seventh current source is used to be electrically connected to the positive electrode of the second power supply, the non-inverting input terminal of the fourth operational amplifier is used to receive the second signal, and the inverting input terminal of the fourth operational amplifier is respectively The source of the fourth field effect transistor, the negative electrode of the seventh current source and the current generation module are electrically connected. The output terminal of the fourth operational amplifier is electrically connected to the gate of the fourth field effect transistor. connection, the drain of the fourth field effect transistor is electrically connected to the input end of the second current mirror, and the output end of the second current mirror is respectively connected to the first end of the fourth resistor and the eighth The negative electrode of the current source is electrically connected to the voltage adjustment module, the common output end of the second current mirror is used to be electrically connected to the negative electrode of the second power supply, and the second end of the fourth resistor is used to receive the Reference voltage, the positive electrode of the eighth current source is used to be electrically connected to the positive electrode of the second power supply; the current provided by the seventh current source, the current provided by the eighth current source and the fifth current source The currents supplied are equal in magnitude and direction.
The amplifier circuit according to any one of claims 1 to 6, wherein the current generating module includes a fifth resistor; a first end of the fifth resistor is electrically connected to the first logic module, and the The second end of the fifth resistor is electrically connected to the second logic module.
The amplifier circuit according to any one of claims 1 to 6, wherein the voltage adjustment module includes a first transconductance unit, a second transconductance unit and a first capacitor;

The positive input terminal of the first transconductance unit is electrically connected to the second logic module and the positive output terminal of the second transconductance unit respectively, and the negative input terminal of the first transconductance unit is respectively connected to the third transconductance unit. A logic module is electrically connected to the negative output terminal of the second transconductance unit, and the positive output terminal of the first transconductance unit is respectively connected to the positive electrode of the first capacitor and the negative input terminal of the second transconductance unit. Electrically connected, the negative output terminal of the first transconductance unit is electrically connected to the negative electrode of the first capacitor and the positive input terminal of the second transconductance unit respectively.
A detection chip, characterized by comprising the amplification circuit according to any one of claims 1-8.
A wearable device, characterized by comprising the detection chip according to claim 9.