CN114927526A - Ferroelectric memory, ferroelectric capacitor and preparation method thereof - Google Patents
Ferroelectric memory, ferroelectric capacitor and preparation method thereof Download PDFInfo
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- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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Abstract
The invention discloses a ferroelectric memory, a ferroelectric capacitor and a preparation method thereof, belonging to the field of semiconductor memory devices. According to the invention, the antiferroelectric dielectric layer is introduced before the growth of the ferroelectric dielectric layer in the ferroelectric capacitor, and when the antiferroelectric layer is used as a seed layer, a crystallization template is provided for the ferroelectric dielectric layer, so that the ferroelectric phase ratio is increased, the remanent polarization is improved, and a storage window is further improved; meanwhile, when the antiferroelectric layer is used as the interface layer, the interface layer has lower surface energy and more stable electrode contact interface than other phases, so that the interface defects and leakage current are reduced, the oxygen vacancy concentration is reduced, the generation of oxygen vacancies in the electrical cycle process is inhibited, the durability is improved, and the reliability of the memory is improved. The method is beneficial to the application of the ferroelectric random access memory with low power consumption, high performance and high reliability.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a ferroelectric memory with a high storage window and high reliability.
Background
In recent years, the integrated circuit industry has been developing ways from the "moore's law era" into the "post-moore's law era" and "beyond the moore's law era". This means that the goal of microelectronic technology development has shifted from being centered on feature size reduction to being centered on reducing power consumption and increasing computational effort; and the improvement of the focusing integration degree is converted into the integration and the lateral expansion of the focusing system function.
In a conventional computing architecture, a three-tier architecture is used for storage in the system in order to balance performance and cost. As the distance from the computing unit increases, memory goes from high speed Static Random Access Memory (SRAM) to Dynamic Random Access Memory (DRAM) to high density Flash memory (Flash). However, with the rapid improvement of the performance of the computing unit and the rapid development of applications such as the internet of things and wearable devices, the original memory system has bottlenecks in performance and power consumption. Therefore, more new types of memory need to replace or supplement the original three-tier memory architecture. The ferroelectric memory has the advantages of non-volatility, low power consumption and high speed, and is expected to partially replace or supplement the existing memory technology.
However, the traditional perovskite ferroelectric material has the defects of incompatibility of CMOS (complementary metal oxide semiconductor) process, difficult integration and the like, so that the development of ferroelectric devices is restricted. Until 2011, researchers found hafnium oxide (HfO) that can be grown using atomic layer deposition 2 ) The ferroelectric material has ferroelectricity under specific doping, stress and annealing conditions, and the excellent CMOS process compatibility of the ferroelectric material fills new activity for the research of ferroelectric devices such as FeRAM and the like. Among different kinds of hafnium oxide based ferroelectric memories, a ferroelectric memory (FeRAM) composed of a selection transistor and a ferroelectric capacitor (1T1C) has a structure and operation mode similar to those of a DRAM, can read and write data at high speed and has better retention and lower power consumption, and is expected to become a substitute of a conventional DRAM. However, as further research shows, the hafnium oxide based ferroelectric material has residual polarization (P) compared with the traditional ferroelectric material r ) The FeRAM has low storage charge capacity, so that the read voltage difference is small, and the size of a storage window of the ferroelectric memory is directly influenced; in addition, the hafnium oxide-based ferroelectric material has larger coercive field and is influenced by factors such as leakage current and oxygen vacancy introduced by the interface layerThus, the hafnium oxide-based FeRAM has a problem of poor durability. Therefore, there is a need for a ferroelectric memory that achieves high endurance while ensuring high remanent polarization and high reliability while achieving a high memory window.
Disclosure of Invention
The invention aims to provide a ferroelectric memory, a ferroelectric capacitor and a preparation method thereof.
The specific technical scheme of the invention is as follows:
a ferroelectric memory includes a ferroelectric capacitor and a cell selection transistor; the bottom electrode of the ferroelectric capacitor is connected with a memory plate line, and the top electrode of the ferroelectric capacitor is connected with the source end of the unit selection transistor; the unit selection transistor is characterized in that an antiferroelectric medium layer is inserted between a ferroelectric medium layer and a bottom electrode of the ferroelectric capacitor, and the antiferroelectric medium layer adopts an antiferroelectric material with dominant T phase or an antiferroelectric material with dominant phase with lowest surface energy.
The core of the invention is that in the ferroelectric capacitor of the ferroelectric memory, an antiferroelectric medium layer is inserted between the ferroelectric medium layer and the bottom electrode, and the antiferroelectric medium layer adopts an antiferroelectric material with dominant T phase or an antiferroelectric material with dominant phase with lowest surface energy. The ferroelectric dielectric layer is used as a storage dielectric layer, the antiferroelectric dielectric layer is used as a contact interface layer between the ferroelectric dielectric layer and the bottom electrode, and meanwhile, the antiferroelectric dielectric layer is also used as a seed layer of the ferroelectric dielectric layer in preparation. The antiferroelectric dielectric material improves the remnant polarization of the ferroelectric layer by guiding the grain growth of the hafnium oxide based ferroelectric dielectric layer and improving the orthogonal phase (O phase) proportion in the ferroelectric layer dielectric, thereby improving the ferroelectricity of the ferroelectric material, inhibiting the generation of a monoclinic phase (M phase) in the ferroelectric layer dielectric, reducing the M phase proportion, reducing the growth rate of oxygen vacancy concentration caused by M phase transformation, and improving the durability; as an optimized contact interface layer, since it has a lower surface energy and a more stable electrode contact interface than other phases, it is possible to reduce the initial oxygen vacancy concentration at the interface, and to suppress the growth of oxygen vacancies in the electrical cycle test, achieving effective improvement in durability.
The antiferroelectric dielectric layer may be selected from pure ZrO 2 HfZrO and PbZrO with Zr content greater than Hf content 3 Or NH 4 H 2 PO 4 (ADP) type, (NH) 4 ) 2 SO 4 Type, (NH4) 2 H 3 O 6 Type, perovskite type and RbNO 3 And (c) an antiferroelectric material of type (la).
The thickness of the antiferroelectric dielectric layer can be below 10 nm.
The ferroelectric dielectric layer can be selected from a traditional perovskite ferroelectric material, a ferroelectric polymer or a novel ferroelectric material based on HfO2, wherein the ferroelectric material generates ferroelectricity under the doping, stress and annealing treatment.
The thickness of the ferroelectric dielectric layer may be 30nm or less.
The bottom electrode and the top electrode of the ferroelectric capacitor can be selected from Ti, TiN, TiSi, TiAlN, TaN, TaCN, TaSi, W, WSi, WN, Al, Ru, RuO 2 、Re、Pt、Mo、Ir、IrO 2 、In 2 O3, SnO, ZnO, Ti, Ni, Nb, Ga, GaN, GeSi, doped Si, SiC, GeSi, or combinations thereof.
A method for preparing a ferroelectric capacitor of a ferroelectric memory comprises the following steps:
1) preparing a bottom electrode on the surface of the silicon substrate;
2) growing an antiferroelectric dielectric layer on the bottom electrode, wherein the antiferroelectric dielectric layer adopts an antiferroelectric material with dominant T phase or an antiferroelectric material with dominant phase with lowest surface energy, and the antiferroelectric dielectric layer is used as a seed layer of the ferroelectric dielectric layer;
3) growing a ferroelectric dielectric layer on the surface of the antiferroelectric dielectric layer;
4) growing a top electrode on the surface of the ferroelectric dielectric layer;
5) defining the area of the capacitor by photoetching, and removing other materials by a wet etching or dry etching method to expose the bottom electrode;
6) under the same annealing condition, the growth temperature of the antiferroelectric medium layer in the step 2) is adjusted to realize that the material of the ferroelectric medium layer is in an orthogonal phase and the material of the antiferroelectric medium layer is in a T-phase dominant phase or a phase with the lowest surface energy is dominant.
The invention has the technical effects that:
the ferroelectric memory of the invention is based on the ferroelectric capacitor inserted into the antiferroelectric dielectric layer, and has the advantages of high storage window and high reliability:
1. in the preparation method of the ferroelectric capacitor, the antiferroelectric material with dominant T phase or the antiferroelectric material with dominant phase with lowest surface energy is used as a seed layer to grow the ferroelectric dielectric layer, so that the proportion of O phase in the crystal phase of the ferroelectric dielectric layer is higher, the ferroelectric polarization is improved, and the storage window is further improved; meanwhile, the proportion of the M phase is reduced, the generation of oxygen vacancy is inhibited, and the durability is improved.
The antiferroelectric dielectric layer is used as a seed layer, and the antiferroelectric dielectric layer guides the growth of grains of the material of the ferroelectric dielectric layer in the annealing and crystallization process, so that the activation energy of crystallization to a ferroelectric phase when the material of the ferroelectric dielectric layer is crystallized is reduced, ferroelectric phase crystallization with a larger proportion is generated in the material of the ferroelectric dielectric layer, the proportion of the ferroelectric phase in the ferroelectric dielectric layer is increased, the overall ferroelectricity of the material is improved, the ferroelectric residual polarization strength is improved under the condition of unchanged thickness, and the storage window of the memory is further improved; meanwhile, the generation of an M phase in the ferroelectric medium layer is inhibited, so that the proportion of the M phase is reduced, the growth rate of oxygen vacancy concentration caused by M phase transformation is reduced, and the durability is improved. Taking the results of the specific examples as an example, compared with the conventional ferroelectric capacitor, the ferroelectric phase of the ferroelectric dielectric layer of the invention is improved by about 10%; the ferroelectric capacitance M phase accounts for as low as 3.7%, and the ferroelectric capacitance M phase accounts for 6% less than that of the ferroelectric capacitance without the introduction of the antiferroelectric dielectric layer.
2. The anti-ferroelectric material with dominant T phase or the anti-ferroelectric material with dominant phase with the lowest surface energy is adopted as the interface layer contacting with the bottom electrode, and the interface layer has lower surface energy and more stable electrode contact interface than other phases, thereby realizing effective improvement of durability and improving reliability.
The antiferroelectric dielectric layer is used as an interface layer which is in contact with the bottom electrode, and has lower surface energy and a more stable electrode contact interface compared with other phases, so that the interface defect is reduced, the leakage current is reduced, the oxygen vacancy concentration is reduced, the generation of oxygen vacancies in the electrical cycle process is inhibited, the initial oxygen vacancy concentration at the interface is reduced, the effective improvement of the durability is realized, and the reliability of the memory is improved. Taking the results of the specific examples as an example, the interface defects are reduced by about 12% compared with the ferroelectric capacitor without the antiferroelectric dielectric layer
Drawings
Fig. 1 is a schematic diagram of a ferroelectric memory according to an embodiment of the present invention.
In the figure:
1-Word Line, WL 2-Bit Line, BL
3-Plate Line, PL 4-cell select transistor (nMOSFET)
5-ferroelectric capacitor C with antiferroelectric dielectric layer FE/DE
6-equivalent bit line load capacitance C BL 7-sensitive regenerative amplifier SA
Fig. 2 is a schematic cross-sectional view of a ferroelectric capacitor fabricated in accordance with an embodiment of the present invention.
In the figure:
8-top electrode (TaN) 9-ferroelectric dielectric layer (Hf) 0.5 Zr 0.5 O 2 )
10-antiferroelectric dielectric layer (T-phase dominated ZrO) 2 ) 11-bottom electrode (TaN)
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings.
As shown in FIG. 1, the present embodiment provides a high-reliability ferroelectric memory with a high memory window, comprising a cell selection transistor T1, a ferroelectric capacitor C with an antiferroelectric dielectric layer FE/DE Equivalent bit line load capacitance C BL And a sense regenerative amplifier SA. Wherein the cell selection transistor T1 is an n-type MOSFET device for realizingThe current unit selection control is carried out, wherein a source end is connected with the top electrode of the asymmetric ferroelectric capacitor, and a drain end is connected with a bit line; ferroelectric capacitor made of TaN/Hf 0.5 Zr 0.5 O 2 /ZrO 2 a/TaN composition, wherein the ferroelectric dielectric layer Hf 0.5 Zr 0.5 O 2 For storing data, an antiferroelectric dielectric layer ZrO 2 The bottom electrode TaN is connected with the plate line and positioned between the ferroelectric dielectric layer and the bottom electrode, when the ferroelectric polarization direction of the ferroelectric capacitor faces to the bottom electrode, the storage state is 1, and otherwise, the storage state is 0; the sensitive regeneration amplifier is used for amplifying bit line differential signals so as to realize data reading and writing back, the input end of the sensitive regeneration amplifier is connected with the bit line, and the reference end of the sensitive regeneration amplifier is connected with the virtual unit. When logic "0" and "1" states are written, or the memory state of the cell is read, the Word Line (WL) is selected to access the storage capacitance. When reading data, PL is set to high level, and WL and PL are selected simultaneously. When FeRAM stores data 0 or 1, the polarization state of the ferroelectric capacitor is P r+ Or P r- When reading, different reading currents are generated according to the ferroelectric polarization state, so that the BL voltage is increased to different degrees, and the data reading is completed after the BL voltage is amplified by the sensitive regenerative amplifier. After each read operation, the memory cell needs to be initialized.
The core of the invention is that the ferroelectric capacitor of the ferroelectric memory, the ferroelectric medium layer is a storage medium; an antiferroelectric dielectric layer between the ferroelectric dielectric layer and the bottom electrode, the antiferroelectric dielectric layer being a layer of T-phase dominated antiferroelectric material or a layer of lowest surface energy dominated antiferroelectric material, respectively being T-phase dominated ZrO 2 Or HfZrO with a Zr proportion larger than a Hf proportion dominated by the T phase; low surface energy PbZrO 3 Type NH 4 H 2 PO 4 (ADP) type, (NH) 4 ) 2 SO 4 Type (NH) 4 ) 2 H 3 O 6 Perovskite type and RbNO 3 And (c) an antiferroelectric material of type (la).
As shown in FIG. 2, the ferroelectric capacitor is made of TaN/Hf 0.5 Zr 0.5 O 2 /ZrO 2 For example, the composition of TaN, the CMOS process compatible preparation method of the ferroelectric capacitor of the invention is as follows:
(1) magnetron sputtering a bottom layer tantalum nitride (TaN) metal plate.
(2) Atomic Layer Deposition (ALD) grown ZrO 2 A film. ZrO growth by tuning ALD 2 The ALD growth temperature of the thin film enables the growth of the HZO of the orthorhombic phase and the antiferroelectric ZrO dominated by the T phase with the lowest surface energy under the same annealing condition 2 . The idea of this special treatment is that by adjusting the ALD growth temperature of ZrO2 and HZO and the subsequent annealing temperature conditions synergistically, only one annealing is needed to generate the antiferroelectric ZrO2 and the orthorhombic HZO during the preparation process. The advantage of doing so is: the process steps are simplified, and defects or pollution caused by multiple annealing is reduced. The specific steps are that the thermal oxide atomic layer deposition prepares ZrO with the thickness of 2nm 2 A film. Specifically, TEMAZ as a Zr precursor source, H 2 O as an O precursor source. The growth temperature range is 200-250 ℃, Zr source with the carrier gas flow of 50sccm and 100sccm O source are alternately and circularly introduced, and the ZrO is finished 2 And (5) growing the thin film.
(3) And moving the silicon wafer into a vacuum pipeline to be isolated from the ALD reaction chamber, heating the ALD reaction chamber to 300 ℃ for the growth of the ferroelectric medium layer, and moving the silicon wafer into the ALD reaction chamber after the temperature in the ALD device reaction chamber is stabilized at 300 ℃. Ensuring that the whole process is in a vacuum environment.
(4) And growing the HZO thin film by Atomic Layer Deposition (ALD). HZO was prepared to a thickness of 8 nm. Specifically, TEMAH was used as the Hf precursor source, TEMAZ was used as the Zr precursor source, H 2 O as an O precursor source. The reaction chamber temperature was controlled at 300 deg.f. Introducing a Zr source and an O source with a carrier gas flow rate of 50sccm at first and 100sccm at second, and introducing the Zr source and the O source with a carrier gas flow rate of 50sccm at first and 100sccm at second, so that HZO (Hf) with a component ratio of 1:1:4 can be generated by alternate circulation 0.5 Zr 0.5 O 2 ) A film.
(5) Magnetron sputtering a top layer tantalum nitride (TaN) metal plate.
(6) And (6) photoetching and patterning.
(7) And (5) etching. And removing the top tantalum nitride (TaN) and the ferroelectric oxide.
(8) Rapid thermal annealing at 400-600 deg.C for 30-90 s to achieve orthogonal HZO and HZOAntiferroelectric ZrO dominated by T phase with lowest surface energy 2 。
The beneficial effects of the invention are illustrated by the specific embodiment:
1. when the ferroelectric memory is normally operated, the storage window is the polarization turnover quantity difference of the ferroelectric capacitor when different states are read, and the polarization turnover quantity difference is in direct proportion to the residual polarization quantity of the ferroelectric capacitor; antiferroelectric ZrO in ferroelectric capacitor containing low surface energy T-phase dominant antiferroelectric dielectric layer in the invention 2 When the layer is used as a seed layer, the induced HZO ferroelectric layer crystals have a ferroelectric phase with a higher proportion, so that the residual polarization amount of the ferroelectric is improved under other conditions such as no change of thickness and the like, the proportion of the M phase is reduced, the growth rate of the oxygen vacancy concentration caused by the transformation of the M phase is reduced, and the durability is improved; in conclusion, the high-reliability ferroelectric memory based on the ferroelectric capacitor with the anti-ferroelectric dielectric layer dominated by the T phase with low surface energy enhances the ferroelectric remanent polarization and improves the storage window of the ferroelectric memory; the durability is improved and the reliability is improved.
2. When the ferroelectric memory is normally operated, after a plurality of operations, the oxygen vacancies of the ferroelectric capacitor are increased, the leakage current is increased, and the interface defects are increased, so that the ferroelectric memory is fatigued, broken down and fails. T-phase dominant antiferroelectric ZrO in ferroelectric capacitor containing low surface energy T-phase dominant antiferroelectric dielectric layer in the invention 2 Layer as optimized interface layer, T-phase ZrO 2 Is ZrO 2 The phase with the lowest surface energy is most stable, and can reduce the oxygen vacancy concentration at the interface, inhibit the generation of oxygen vacancies and reduce the interface defects and leakage current in the multiple electrical cycle processes, so that the durable electrical cycle times of the ferroelectric capacitor of the antiferroelectric dielectric layer with the T phase with low surface energy dominating are improved by multiple orders of magnitude, and the durability is improved; in conclusion, the high-reliability ferroelectric memory based on the ferroelectric capacitor with the antiferroelectric dielectric layer dominated by the T phase with low surface energy enhances the durability and improves the reliability of the ferroelectric memory.
Finally, it is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.
Claims (10)
1. A ferroelectric memory comprises a ferroelectric capacitor and a unit selection transistor, wherein the ferroelectric capacitor comprises a top electrode, a ferroelectric dielectric layer and a bottom electrode; the cell selection transistor has a gate connected to a memory word line and a drain connected to a memory bit line, and is characterized in that an antiferroelectric dielectric layer is interposed between the ferroelectric dielectric layer and the bottom electrode, and the antiferroelectric dielectric layer is made of an antiferroelectric material having a dominant T phase or an antiferroelectric material having a dominant phase with a lowest surface energy.
2. The ferroelectric memory of claim 1, wherein the antiferroelectric dielectric layer is selected from the group consisting of pure ZrO 2 HfZrO and PbZrO with Zr content greater than Hf content 3 Or NH 4 H 2 PO 4 (ADP) type, (NH) 4 ) 2 SO 4 Type, (NH4) 2 H 3 O 6 Perovskite type and RbNO 3 Type antiferroelectric material.
3. The ferroelectric memory of claim 1, wherein the thickness of the antiferroelectric dielectric layer is less than 10 nm.
4. The ferroelectric memory of claim 1, wherein the antiferroelectric dielectric layer is selected from the group consisting of pure ZrO 2 HfZrO and PbZrO with Zr content greater than Hf content 3 Or NH 4 H 2 PO 4 (ADP) type, (NH) 4 ) 2 SO 4 Type, (NH4) 2 H 3 O 6 Perovskite type and RbNO 3 And (c) an antiferroelectric material of type (la).
5. The ferroelectric memory of claim 1, wherein the ferroelectric dielectric layer is selected from a conventional perovskite-type ferroelectric material, a ferroelectric polymer, or a novel ferroelectric material based on HfO2 that produces ferroelectricity upon doping, stress, annealing.
6. The ferroelectric memory of claim 1, wherein the thickness of the ferroelectric dielectric layer is below 30 nm.
7. The ferroelectric memory of claim 1, wherein the bottom or top electrode of the ferroelectric capacitor is selected from Ti, TiN, TiSi, TiAlN, TaN, TaCN, TaSi, W, WSi, WN, Al, Ru, RuO 2 、Re、Pt、Mo、Ir、IrO 2 、In 2 O3, SnO, ZnO, Ti, Ni, Nb, Ga, GaN, GeSi, doped Si, SiC, GeSi, or combinations thereof.
8. A ferroelectric capacitor of a ferroelectric memory is characterized in that the ferroelectric capacitor comprises a top electrode, a ferroelectric medium layer and a bottom electrode, an antiferroelectric medium layer is inserted between the ferroelectric medium layer and the bottom electrode, the antiferroelectric medium layer adopts an antiferroelectric material with dominant T phase or an antiferroelectric material with dominant phase with lowest surface energy, the ferroelectric medium layer is used as a storage medium layer, and the antiferroelectric medium layer is used as a contact interface layer between the ferroelectric medium layer and the bottom electrode.
9. A method for preparing a ferroelectric capacitor of a ferroelectric memory comprises the following steps:
1) preparing a bottom electrode on the surface of the silicon substrate;
2) growing an antiferroelectric dielectric layer on the bottom electrode, wherein the antiferroelectric dielectric layer is made of an antiferroelectric material with dominant T phase or an antiferroelectric material with dominant phase with lowest surface energy, and the antiferroelectric dielectric layer is used as a seed layer of the ferroelectric dielectric layer;
3) growing a ferroelectric dielectric layer on the surface of the antiferroelectric dielectric layer;
4) growing a top electrode on the surface of the ferroelectric dielectric layer;
5) defining the area of the capacitor by photoetching, and removing other materials by a wet etching or dry etching method to expose the bottom electrode;
6) under the same annealing condition, the growth temperature of the antiferroelectric dielectric layer in the step 2) is adjusted to realize that the material of the ferroelectric dielectric layer is in an orthogonal phase and the material of the antiferroelectric dielectric layer is in a phase with dominant T phase or dominant phase with lowest surface energy.
10. A method of manufacturing a ferroelectric capacitor of a ferroelectric memory as in claim 9, wherein said antiferroelectric dielectric layer has a thickness of 10nm or less.
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| PCT/CN2023/073667 WO2023231430A1 (en) | 2022-06-02 | 2023-01-29 | Ferroelectric memory and ferroelectric capacitor thereof and preparation method therefor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116209258A (en) * | 2022-11-01 | 2023-06-02 | 北京超弦存储器研究院 | Memory structure of memory unit and preparation method |
| CN116209259A (en) * | 2022-11-01 | 2023-06-02 | 北京超弦存储器研究院 | Memory cell array structure and preparation method |
| WO2023231430A1 (en) * | 2022-06-02 | 2023-12-07 | 北京超弦存储器研究院 | Ferroelectric memory and ferroelectric capacitor thereof and preparation method therefor |
| WO2024055688A1 (en) * | 2022-09-14 | 2024-03-21 | 华为技术有限公司 | Ferroelectric memory array, manufacturing method therefor, memory and electronic device |
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| CN100550391C (en) * | 2007-04-12 | 2009-10-14 | 复旦大学 | A kind of ferroelectric condenser and ferroelectric field effect pipe and manufacture method thereof |
| US10468495B2 (en) * | 2015-08-11 | 2019-11-05 | Alacrity Semiconductors, Inc. | Integrated circuit including ferroelectric memory cells and methods for manufacturing |
| KR20190001455A (en) * | 2017-06-27 | 2019-01-04 | 에스케이하이닉스 주식회사 | Ferroelectric Memory Device |
| CN110165053A (en) * | 2019-05-28 | 2019-08-23 | 肇庆市华师大光电产业研究院 | A kind of ALD preparation Hf towards ferroelectric memory application0.5Zr0.5O2The method of ferroelectric thin film |
| US20220122995A1 (en) * | 2020-10-16 | 2022-04-21 | Ferroelectric Memory Gmbh | Memory cell and methods thereof |
| CN113871386A (en) * | 2021-09-13 | 2021-12-31 | 北京大学 | Ferroelectric capacitor based on asymmetric lamination, low-voltage high-speed ferroelectric memory and preparation method |
| CN114927526A (en) * | 2022-06-02 | 2022-08-19 | 北京超弦存储器研究院 | Ferroelectric memory, ferroelectric capacitor and preparation method thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023231430A1 (en) * | 2022-06-02 | 2023-12-07 | 北京超弦存储器研究院 | Ferroelectric memory and ferroelectric capacitor thereof and preparation method therefor |
| WO2024055688A1 (en) * | 2022-09-14 | 2024-03-21 | 华为技术有限公司 | Ferroelectric memory array, manufacturing method therefor, memory and electronic device |
| CN116209258A (en) * | 2022-11-01 | 2023-06-02 | 北京超弦存储器研究院 | Memory structure of memory unit and preparation method |
| CN116209259A (en) * | 2022-11-01 | 2023-06-02 | 北京超弦存储器研究院 | Memory cell array structure and preparation method |
| CN116209259B (en) * | 2022-11-01 | 2024-03-15 | 北京超弦存储器研究院 | Memory cell array structure and preparation method |
| CN116209258B (en) * | 2022-11-01 | 2024-03-29 | 北京超弦存储器研究院 | Memory structure of memory unit and preparation method |
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