WO2024055688A1 - Ferroelectric memory array, manufacturing method therefor, memory and electronic device - Google Patents

Abstract

The present application relates to the technical field of semiconductors. Provided are a ferroelectric memory array, a manufacturing method therefor, a memory and an electronic device, which aim to improve uniformity and reliability of the performance of memories. The ferroelectric memory array may be of a two-dimensional structure or may also be of a three-dimensional structure, and comprises a plurality of memory units arranged in an array mode; each memory unit comprises a ferroelectric capacitor and a transistor; each ferroelectric capacitor comprises a first electrode and a second electrode which are oppositely arranged, and a ferroelectric film arranged between the first electrode and the second electrode; the crystal phase of the ferroelectric films comprises a tetragonal phase; and each ferroelectric film comprises a first layer and a second layer which are in contact with each other, at least one of the first layer and the second layer comprising a ferroelectric material, and the lattice constant of the first layer being different from the lattice constant of the second layer. The ferroelectric memory array can be used for ferroelectric memories, ferroelectric field-effect transistor memories or ferroelectric tunnel junction memories, so as to read and write data.

Description

Ferroelectric memory array and preparation method thereof, memory, electronic equipment

This application requires the priority of the Chinese patent application submitted to the State Intellectual Property Office on September 14, 2022, with the application number 202211115524.6 and the application name "Ferroelectric memory array and its preparation method, memory, and electronic equipment", and its entire content incorporated herein by reference.

Technical field

The present application relates to the field of semiconductor technology, and in particular to a ferroelectric memory array and its preparation method, memory, and electronic equipment.

Background technique

At present, Ferroelectric Random Access Memory (Ferroelectric Random Access Memory, English abbreviation: FeRAM, Chinese abbreviation: Ferroelectric Memory) has received widespread attention in the field due to its high integration and low power consumption.

Generally, a ferroelectric memory has a plurality of memory cells, and each memory cell includes a ferroelectric capacitor. The ferroelectric capacitor includes two electrodes disposed oppositely, and a ferroelectric film disposed between the two electrodes. That is, the ferroelectric capacitor The capacitor has a metal-ferroelectric film-metal (Metal-Ferroelectric-Metal, MFM) structure. The ferroelectric film has a ferroelectric effect. The electric field generated by the two electrodes is applied to the ferroelectric film. The ferroelectric domains in the ferroelectric film form polarized charges under the action of the electric field. When the electric field is reversed, the ferroelectric domain undergoes directional flipping. The polarization charge energy formed by the ferroelectric domain before and after the electric field is reversed is different. This binary stable state (positive and negative polarization state) will make the ferroelectric domain The capacitor is charged and discharged, and can be recognized by the external sense amplifier to determine whether the ferroelectric memory is in the storage state of "0" or "1".

However, using the Atomic Layer Deposition (ALD) process, the ferroelectric thin film prepared exhibits a polycrystalline structural state, and the crystalline phase and crystal orientation of the ferroelectric thin film cannot be unified. For example, ferroelectric thin films include orthorhombic phase (O-phase, also called ferroelectric phase), tetragonal phase (T-phase, also called antiferroelectric phase), and monoclinic phase (Monoclinic phase, M-phase, also known as non-ferroelectric phase), in which only orthorhombic phase crystals have good ferroelectric effects, which will affect the performance uniformity and reliability of ferroelectric memory.

Contents of the invention

Embodiments of the present application provide a ferroelectric memory array and its preparation method, memory, and electronic equipment, aiming to improve the uniformity and reliability of memory performance.

In order to achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In the first aspect, a ferroelectric memory array is provided. The ferroelectric memory array can have a two-dimensional structure or a three-dimensional structure. Moreover, the ferroelectric memory array can be applied to ferroelectric memory, ferroelectric field effect transistor memory, or ferroelectric tunnel junction memory to achieve reading and writing of data.

The above-mentioned ferroelectric memory array includes a plurality of memory cells arranged in an array. Each memory cell includes a ferroelectric capacitor and a transistor. The ferroelectric capacitor includes a first electrode and a second electrode arranged oppositely, and is arranged between the first electrode and the second electrode. ferroelectric film between two electrodes. Wherein, the crystal phase of the ferroelectric film includes a tetragonal phase, the ferroelectric film includes a first layer and a second layer in contact with each other, at least one of the first layer and the second layer includes a ferroelectric material, and the crystal phase of the first layer The lattice constant is different from that of the second layer.

In the ferroelectric capacitor provided by the above embodiments of the present application, the first layer of the ferroelectric film is in contact with the second layer. Since the lattice constant of the first layer is different from the lattice constant of the second layer, there is a gap between them. A lattice mismatch will occur, causing stress to be generated between the first layer and the second layer. This stress will act on the crystals of the tetragonal phase, causing lattice distortion of the crystals of the tetragonal phase, forming a "strained tetragonal phase".

Compared with the "intrinsic tetragonal phase" whose crystal lattice is not distorted, the "strained tetragonal phase" has a larger residual polarization intensity, which can improve the distinction between positive and negative polarization states of the ferroelectric film and improve the ferroelectric memory. The storage window improves the accuracy of reading and writing data in ferroelectric memory.

Moreover, compared with the orthorhombic phase, the lowest potential barrier for oxygen vacancy migration in the strained tetragonal phase is larger, and the oxygen vacancies are less likely to migrate, which can improve the polarization fatigue phenomenon of the ferroelectric film and reduce the probability of breakdown of the ferroelectric capacitor, thus It can improve the service life and durability of ferroelectric memory.

In addition, the strained tetragonal phase has better thermal stability, which can improve the thermal stability of ferroelectric capacitors and thereby improve the thermal stability of ferroelectric memories.

In some embodiments, the unit cell of the tetragonal phase in the ferroelectric film includes oxygen ions that are offset relative to the center of symmetry of the unit cell.

In the above embodiments, the tetragonal phase undergoes lattice distortion to form a strained tetragonal phase. The oxygen ions in the unit cell of the strained tetragonal phase are shifted relative to the symmetry center of the unit cell, causing it to have a larger residual polarization intensity, thereby improving the ferroelectricity. The distinction between the positive and negative polarization states of the film improves the storage window of the ferroelectric memory and improves the accuracy of reading and writing data in the ferroelectric memory.

In some embodiments, both the first layer and the second layer include ferroelectric materials, the crystal phases of the first layer and the second layer both include a tetragonal phase, and the proportion of the tetragonal phase in the first layer and the second layer ranges from 30 %~100%.

In the above embodiment, when both the first layer and the second layer include a ferroelectric material, and the lattice constant of the first layer is different from the lattice constant of the second layer, the surface of the first layer in contact with the second layer Lattice mismatch can be formed, causing stress between the first layer and the second layer. This stress acts on the tetragonal phase crystals in the first layer and the second layer, causing lattice distortion of the tetragonal phase crystals, thus A strained tetragonal phase is formed in both the first and second layers.

In some embodiments, the first layer includes hafnium oxide, the second layer includes zirconium oxide, and the hafnium oxide has a lattice constant different from the lattice constant of zirconium oxide.

In some embodiments, both the first layer and the second layer include hafnium zirconium oxygen, the number ratio of hafnium atoms in the first layer is different from the number ratio of hafnium atoms in the second layer, and the zirconium atoms in the first layer The number ratio is different from the number ratio of zirconium atoms in the second layer, so that the lattice constant of the first layer is different from the lattice constant of the second layer.

In some embodiments, a plurality of first layers and a plurality of second layers are alternately provided.

In the above embodiment, since the lattice constant of the first layer is different from the lattice constant of the second layer, by arranging multiple first layers and multiple second layers alternately, the multiple first layers and the multiple second layers are arranged alternately. The surfaces in contact can form lattice mismatches, which can increase the stress between the first layer and the second layer. This stress acts on the crystals of the tetragonal phase, causing lattice distortion of the crystals of the tetragonal phase, which is conducive to the formation of Strain tetragonal phase.

In some embodiments, the first layer includes ferroelectric material and the second layer includes non-ferroelectric material. The ferroelectric film includes a plurality of first layers and at least one second layer. The first layers and the second layers are alternately arranged, and the second layer is not in contact with the first electrode and the second electrode. The crystal phase of the first layer includes a tetragonal phase, and the proportion of the tetragonal phase in the first layer ranges from 30% to 100%.

In the above embodiment, when the first layer includes ferroelectric material, the second layer includes non-ferroelectric material, and the lattice constant of the first layer is different from the lattice constant of the second layer, by setting the first layer and The second layers are alternately arranged. The surfaces in contact with the first layer and the second layer can form lattice mismatches, causing stress between the first layer and the second layer. This stress acts on the tetragonal phase crystals in the first layer. This will cause lattice distortion in the crystals of the tetragonal phase, thus forming a strained tetragonal phase in the first layer.

Moreover, since the second layer includes non-ferroelectric material, by arranging the second layer not to contact the first electrode and the second electrode, it is possible to prevent the first electrode or the second electrode from contacting the non-ferroelectric material, thereby avoiding damage to the ferroelectric memory. Performance is negatively affected.

In some embodiments, the first layer includes hafnium zirconium oxide and the second layer includes metal oxide.

In some embodiments, the second layer includes at least one of titanium oxide, lanthanum oxide, and magnesium oxide.

In some embodiments, the number proportion of hafnium atoms in the ferroelectric film is smaller than the number proportion of zirconium atoms. In the process of preparing the ferroelectric film, it is beneficial to generate a tetragonal phase in the ferroelectric film.

In some embodiments, the ratio of the number of hafnium atoms in the ferroelectric film to the sum of the numbers of hafnium atoms and zirconium atoms ranges from 0.1 to 0.45; the ratio of the number of zirconium atoms to the sum of the numbers of hafnium atoms and zirconium atoms The range is 0.55~0.9%.

In some embodiments, the ratio of the number of oxygen atoms in the ferroelectric film to the sum of the number of hafnium atoms and zirconium atoms ranges from 1.3 to 1.9. By reducing the proportion of oxygen atoms in the ferroelectric film, the ferroelectricity can be increased. The number of oxygen vacancies in the film is conducive to the generation of tetragonal phase in the ferroelectric film.

In some embodiments, the thickness of the ferroelectric film ranges from 4 nm to 8 nm.

In the above embodiments, the thickness of the ferroelectric film is small. By reducing the thickness of the ferroelectric film, it is beneficial to generate a tetragonal phase in the ferroelectric film during the process of preparing the ferroelectric film.

In some embodiments, the first electrode has a thermal expansion coefficient that is different from the second electrode.

In the above embodiments, the process of preparing the ferroelectric capacitor needs to be carried out in a high-temperature environment. Since the thermal expansion coefficient of the first electrode is different from that of the second electrode, the volume expansion rate of the first electrode is different from the volume of the second electrode. Different expansion rates cause stress to be generated between the first electrode and the second electrode. This stress acts on the tetragonal phase crystal of the ferroelectric film, causing lattice distortion of the tetragonal phase crystal to form a strained tetragonal phase.

In some embodiments, the crystal phase of the ferroelectric film also includes an orthorhombic phase. The orthorhombic phase can also generate residual polarization intensity, which can further improve High uniformity and reliability of ferroelectric memory improve the storage window of ferroelectric memory.

In some embodiments, both the first electrode and the second electrode are planar electrodes, and the first electrode, the first layer, the second layer and the second electrode are stacked. That is, the structure of the ferroelectric capacitor is a two-dimensional planar structure, which is simple and easy to prepare.

In some embodiments, the first electrode is a planar electrode, the second electrode is a columnar electrode, the second electrode penetrates the first electrode, and the first layer and the second layer are arranged around the second electrode.

In the above embodiments, the ferroelectric capacitor adopts a three-dimensional vertical structural design, which can reduce its occupied area in the plane, thereby increasing the number of ferroelectric capacitors per unit area in the plane, so as to increase the efficiency of the memory unit per unit area. Setting the number will help improve the storage density of the memory.

In some embodiments, both the first electrode and the second electrode are planar electrodes, and one of the first electrode and the second electrode is electrically connected to the transistor to form a memory cell. Or, the first electrode is a planar electrode, the second electrode is a columnar electrode, and the second electrode is electrically connected to the transistor to form a memory cell.

In a second aspect, a method for preparing a ferroelectric memory array is provided, which method includes sequentially forming a first electrode, a ferroelectric film, and a second electrode. The ferroelectric film includes a first layer and a second layer, at least one of the first layer and the second layer includes a ferroelectric material, and the first layer has a lattice constant different from that of the second layer. and/or, the thermal expansion coefficient of the first electrode is different from the thermal expansion coefficient of the second electrode. After forming the second electrode, the method further includes: rapidly heat treating the ferroelectric film to form a tetragonal phase.

The preparation method provided by the above embodiments of the present application sequentially forms a first electrode, a ferroelectric film and a second electrode. After forming the second electrode, the ferroelectric film is rapidly heat treated to form a square in the ferroelectric film. Mutually.

Moreover, since the lattice constant of the first layer is different from the lattice constant of the second layer, a lattice mismatch will occur between the two, causing stress to be generated between the first layer and the second layer, and this stress will act on the tetragonal phase. On the crystal, the crystal of the tetragonal phase will produce lattice distortion, forming a strained tetragonal phase.

In some embodiments, the temperature of the rapid thermal treatment ranges from 450°C to 650°C.

Compared with the related art, the orthorhombic phase is formed through rapid heat treatment at a higher temperature. In the above embodiment, by lowering the temperature of the rapid heat treatment, it is beneficial to form the tetragonal phase in the ferroelectric film.

In a third aspect, a memory is provided, which includes the ferroelectric memory array described in any of the above embodiments, and a controller electrically connected to the ferroelectric memory array.

In the fourth aspect, an electronic device is provided. The electronic device is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. The electronic device includes a circuit board and the memory described in the above embodiment. The memory is disposed on the circuit board and is electrically connected to the circuit board.

It can be understood that the beneficial effects that can be achieved by the memory and electronic devices provided by the above embodiments of the present application can be referred to the beneficial effects of the ferroelectric memory array mentioned above, which will not be described again here.

Description of drawings

In order to explain the technical solutions in the present application more clearly, the drawings required to be used in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only appendices to some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of the present application.

Figure 1 is an architectural diagram of an electronic device according to some embodiments;

Figure 2 is an exploded view of an electronic device according to some embodiments;

Figure 3 is an architectural diagram of a ferroelectric memory according to some embodiments;

Figure 4 is a circuit diagram of a memory cell according to some embodiments;

Figure 5 is a structural diagram of a ferroelectric capacitor in the related art;

Figure 6 is the electron energy loss spectrum of the oxygen vacancy content in the ferroelectric film;

Figure 7 is a structural diagram of a ferroelectric capacitor according to some embodiments;

Figure 8 is a crystal structure diagram of the strained tetragonal phase in the ferroelectric film;

Figure 9 is the atomic coordinate diagram of the strained tetragonal phase and orthorhombic phase unit cells in the ferroelectric film;

Figure 10 is the atomic coordinate diagram of oxygen ions in the strained tetragonal phase and orthorhombic phase unit cells in the ferroelectric film;

Figure 11 is a graph of the electric hysteresis loop of the ferroelectric film;

Figure 12 is the electron energy loss spectrum of the oxygen vacancy content in the ferroelectric film;

Figure 13 is a histogram of the lowest potential barrier for oxygen vacancy migration in the orthorhombic phase, monoclinic phase and strained tetragonal phase;

Figure 14 is a structural diagram of another ferroelectric capacitor according to some embodiments;

Figure 15 is a structural diagram of another ferroelectric capacitor according to some embodiments;

Figure 16 is a structural diagram of yet another ferroelectric capacitor according to some embodiments;

Figure 17 is a structural diagram of yet another ferroelectric capacitor according to some embodiments;

Figures 18A to 18D are diagrams of steps for preparing a ferroelectric capacitor according to some embodiments;

Figure 19 is a three-dimensional vertical structural diagram of a ferroelectric capacitor according to some embodiments;

Figures 20A to 20D are diagrams of steps for preparing a ferroelectric capacitor according to some embodiments;

Figure 21 is another three-dimensional vertical structure diagram of a ferroelectric capacitor according to some embodiments.

Detailed ways

The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art fall within the scope of protection of this application.

In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", The orientations or positional relationships indicated by "top", "bottom", "inner", "outside", etc. are based on the orientations or positional relationships shown in the drawings. They are only for the convenience of describing the present application and simplifying the description, and are not indicated or implied. Reference is made to devices or elements having a specific orientation, being constructed and operating in a specific orientation, and therefore should not be construed as limiting the application.

Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted in an open, inclusive sense, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" and the like are intended to indicate specific features associated with the embodiment or example. , structures, materials or characteristics are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

Hereinafter, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

In describing some embodiments, expressions "coupled" and "connected" and their derivatives may be used. For example, some embodiments may be described using the term "connected" to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments claimed herein are not necessarily limited to the contents herein.

"At least one of A, B and C" has the same meaning as "at least one of A, B or C" and includes the following combinations of A, B and C: A only, B only, C only, A Combinations with B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

"A and/or B" includes the following three combinations: A only, B only, and a combination of A and B.

The use of "configured to" in this document implies open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" is meant to be open and inclusive in that a process, step, calculation or other action "based on" one or more stated conditions or values may in practice be based on additional conditions or beyond the stated values.

As used herein, "approximately" includes the stated value as well as an average within an acceptable range of deviations from the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the relationship between Determined by the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system).

In the context of this application, the meanings of "on,""above," and "over" are to be construed in the broadest manner, such that "on" does not only mean "directly on something" ”, but also includes the meaning of “on something” with intermediate features or layers in between, and “above” or “on” not only means “above” or “on” something, but also includes the meaning of “on something” with no middle in between The meaning of a feature or layer being "above" or "on" something (i.e., directly on something).

Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.

The technical terms involved in some embodiments of this application are as follows:

Grains: Grains are small, irregular-shaped crystals that make up polycrystals.

Crystal: A structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.

Crystal lattice: The atoms inside the crystal are arranged according to certain geometric rules. The spatial grid in which the atoms are arranged regularly is called a crystal lattice.

Unit cell: The most basic geometric unit that constitutes a crystal. Its shape and size are the same as the parallelepiped units of the space lattice, retaining all the characteristics of the entire crystal lattice.

Ferroelectric materials: They can maintain spontaneous polarization by aligning their internal electric dipole moments with an applied electric field, even when the externally applied electric field is removed. In other words, a ferroelectric is a material in which the polarization value (or electric field) remains semi-permanently, even after a constant voltage is applied and the voltage returns to zero volts.

Some embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (Personal Digital Assistant, PDA), a television, or a smart wearable product (for example, a smart watch, a smart bracelet) , virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, charging small household appliances (such as soy milk machines, sweeping robots), drones, radar, aerospace equipment and vehicle-mounted equipment, etc. Type of user equipment or terminal equipment; the electronic equipment can also be network equipment such as base stations. The embodiments of the present application do not place any special restrictions on the specific form of the electronic device.

Figure 1 is an architectural diagram of an electronic device according to some embodiments.

As shown in FIG. 1 , the electronic device 1 includes: a storage device 11 , a processor 12 , an input device 13 , an output device 14 and other components. Those skilled in the art can understand that the architecture of the electronic device 1 shown in Figure 1 does not constitute a limitation on the electronic device 1, and the electronic device 1 may include more or less components than those shown in Figure 1 , or some of the components shown in Figure 1 may be combined, or may be arranged differently from the components shown in Figure 1 .

Among them, the storage device 11 is used to store software programs and modules. The storage device 11 mainly includes a storage program area and a storage data area, wherein the storage program area can store and back up an operating system, at least one application program required for a function (such as a sound playback function, an image playback function, etc.), etc.; the storage data area can store Data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.) and the like are stored. Furthermore, the storage device 11 includes an external memory 111 and an internal memory 112 . Data stored in the external memory 111 and the internal memory 112 can be transferred to each other. The external memory 111 may include, for example, a hard disk, a USB disk, a floppy disk, etc. The internal memory 112 may include, for example, a random access memory (Random Access Memory, RAM), a read-only memory (Read-Only Memory, ROM), etc., wherein the random access memory may include, for example, a ferroelectric memory, a phase change memory, or a magnetic memory. wait.

The processor 12 is the control center of the electronic device 1, using various interfaces and lines to connect various parts of the entire electronic device 1, by running or executing software programs and/or modules stored in the storage device 11, and by calling the software programs and/or modules stored in the storage device 11. The data in the device 11 executes various functions of the electronic device 1 and processes data, thereby overall monitoring the electronic device 1 . Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (Application Processor, AP), a modem processor, a graphics processor (Graphics Processing Unit, GPU), etc. Among them, different processing units can be independent devices or integrated in one or more processors. For example, the processor 12 can integrate an application processor and a modem processor, where the application processor mainly processes operating systems, user interfaces, application programs, etc., and the modem processor mainly processes wireless communications. It can be understood that the above-mentioned modem processor may not be integrated into the processor 12 . The above-mentioned application processor may be, for example, a central processing unit (Central Processing Unit, CPU). In FIG. 1 , the processor 12 is a CPU as an example. The CPU may include a calculator 121 and a controller 122 . The arithmetic unit 121 obtains the data stored in the internal memory 112 and processes the data stored in the internal memory 112. The processed result is usually sent back to the internal memory 112. The controller 122 can control the arithmetic unit 121 to process data, and the controller 122 can also control the external memory 111 and the internal memory 112 to read or write data.

The input device 13 is used to receive input numeric or character information, and to generate user settings and function controls of the electronic device. related key signal input. By way of example, the input device 13 may include a touch screen and other input devices. The touch screen, also known as the touch panel, can collect the user's touch operations on or near the touch screen (such as the user's operations on or near the touch screen using fingers, stylus, or any suitable objects or accessories), and perform operations based on preset settings. The program drives the corresponding connection device. The controller 122 in the above-mentioned processor 12 can also control the input device 13 to receive the input signal or not to receive the input signal. In addition, the input numeric or character information received by the input device 13 and the key signal input generated related to user settings and function control of the electronic device may be stored in the internal memory 112 .

The output device 14 is used to output the input of the input device 13 and store signals corresponding to the data in the internal memory 112 . For example, the output device 14 outputs a sound signal or a video signal. The controller 122 in the above-mentioned processor 12 can also control the output device 14 to output a signal or not to output a signal.

It should be noted that the thick arrows in Figure 1 are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, a single arrow between the input device 13 and the internal memory 112 indicates that data received by the input device 13 is transmitted to the internal memory 112 . For another example, the double arrow between the operator 121 and the internal memory 112 indicates that the data stored in the internal memory 112 can be transferred to the operator 121 , and the data processed by the operator 121 can be transferred to the internal memory 112 . The thin arrows in Figure 1 indicate components that controller 122 can control. For example, the controller 122 can control the external memory 111, the internal memory 112, the operator 121, the input device 13, the output device 14, and the like.

In order to facilitate further description of the structure of the electronic device 1 , the following is an exemplary introduction taking the electronic device 1 as a mobile phone.

Figure 2 is an exploded view of an electronic device according to some embodiments.

Referring to FIG. 2 , the electronic device 1 may also include a middle frame 15 , a rear case 16 and a display screen 17 . The back shell 16 and the display screen 17 are respectively located on opposite sides of the middle frame 15 , and the middle frame 15 and the display screen 17 are disposed in the back shell 16 . The middle frame 15 includes a bearing plate 150 for bearing the display screen 17 and a frame 151 surrounding the bearing plate 150 .

Continuing to refer to FIG. 2 , the electronic device 1 may further include a circuit board 18 , which is disposed on a side of the carrier plate 150 close to the rear case 16 . The internal memory 112 in the electronic device 1 may be disposed on the circuit board 18 . The memory 112 is electrically connected to the circuit board 18 .

At present, ferroelectric memory, as a new type of memory, is widely used in internal devices due to its characteristics of non-volatile data storage, fast access rate, low read and write voltage, low power consumption, small device size, good cycle performance and radiation resistance. in memory. The internal memory 112 involved in this application is not limited to ferroelectric memory. It may also be a ferroelectric field-effect transistor (Ferroelectric Field-Effect-Transistor, FeFET) memory or a ferroelectric tunnel junction (Ferroelectric Tunnel Junction, FTJ) memory.

The following embodiments are introduced by taking the internal memory 112 as a ferroelectric memory as an example. FIG. 3 is an architectural diagram of a ferroelectric memory according to some embodiments.

Referring to FIG. 3 , the internal memory 112 includes a ferroelectric memory array 210 , a decoder 220 , a driver 230 , a controller (timing controller) 240 , a buffer 250 and an input/output interface 260 . The ferroelectric memory array 210 includes a plurality of memory cells 200 arranged in an array.

Figure 4 is a circuit diagram of a memory cell according to some embodiments.

Referring to Figure 4, the memory unit 200 includes a circuit architecture based on a ferroelectric capacitor. The memory unit 200 has a 1T1C (1-Transistor-1-Capacitor) structure, that is, the memory unit 200 includes a transistor T and a ferroelectric capacitor C. The transistor T The source is electrically connected to the bit line (Bit Line, BL), the drain is electrically connected to one electrode of the ferroelectric capacitor C, the gate is electrically connected to the word line (Word Line, WL), and the other electrode of the ferroelectric capacitor C Electrically connected to a Plate Line (PL), the circuit architecture of the memory unit 200 in the embodiment of the present application is not limited to this.

Based on this, the above-described decoder 220 can decode according to the received address to determine the memory unit 200 in the ferroelectric memory array 210 that needs to be accessed. The driver 230 is used to generate a control signal according to the decoding result output by the decoder 220. The control signal is transmitted to the gate of the transistor T in the memory unit 200 through the word line WL to control the transistor T to turn on or off, thereby achieving the specified Access to storage unit 200. The buffer 250 receives the data signal output by the memory unit 200 through the board line PL, and is used to buffer the data signal. For example, First-In First-Out (FIFO) may be used for buffering. The timing controller 240 is used to control the timing of the buffer 250 and control the driver 230 to drive the ferroelectric memory array 210 . The input/output interface 260 is used to transmit data signals, such as receiving data signals or sending data signals.

The above ferroelectric memory array 210, decoder 220, driver 230, timing controller 240, buffer 250 and input and output The interface 260 can be integrated into one chip, or can be integrated into multiple chips.

The following is an introduction to the working principle of ferroelectric memory based on the structure of ferroelectric capacitors.

FIG. 5 is a structural diagram of a ferroelectric capacitor in the related art.

Referring to Figure 5, the ferroelectric capacitor C' includes a first electrode 01' and a second electrode 02' arranged oppositely, and a ferroelectric film 03' disposed between the first electrode 01' and the second electrode 02'. The ferroelectric capacitor C' has an MFM structure. The ferroelectric film 03' includes ferroelectric material, and the ferroelectric material has spontaneous polarization characteristics.

Specifically, the ferroelectric material has orthogonal phase crystals. When the first electrode 01' and the second electrode 02' receive a voltage signal and generate an electric field, the electric field is applied to the ferroelectric film 03'. The ferroelectric material The central atom of the unit cell of the orthorhombic phase moves along the electric field and stops in a low energy state, which may be, for example, a "0" storage state.

It should be noted that a large number of central atoms move and couple in the unit cell to form ferroelectric domains, and ferroelectric domains will form polarization charges under the action of an electric field.

When the electric field generated by the first electrode 01' and the second electrode 02' is reversed, the central atom moves in the unit cell along the direction of the electric field and stops in another low energy state. This state can be, for example, "1 "The storage state, that is, the ferroelectric domain flips directionally under the action of the reversing electric field.

It should be noted that the polarization charge energy formed by the ferroelectric domain before and after the electric field reversal is different. This positive and negative polarization state will cause the ferroelectric capacitor C' to charge and discharge, which can then be detected by the external sense amplifier. Recognition is used to determine whether the storage unit 200 is in the storage state of "0" or "1", thereby realizing the reading or writing of data in the ferroelectric memory.

Usually, the above-mentioned ferroelectric film 03' is prepared using an atomic layer deposition process. The ferroelectric film 03' exhibits a polycrystalline structural state, and the crystal phase and crystal orientation cannot be unified. For example, the ferroelectric film 03' includes orthorhombic phase (also called ferroelectric phase), tetragonal phase (also called antiferroelectric phase), and monoclinic phase (also called non-ferroelectric phase). Among them, the orthorhombic phase represents ferroelectric phase. Electrical properties, the tetragonal phase exhibits antiferroelectric properties, the monoclinic phase exhibits dielectric properties, and the content of the orthorhombic phase is low. The presence of the tetragonal phase and monoclinic phase will affect the uniformity and reliability of the performance of the ferroelectric memory. sex.

Figure 6 is the electron energy loss spectrum of the oxygen vacancy content in the ferroelectric film 03'. Combining Figures 5 and 6, the "abscissa" is the detection distance of the ferroelectric film 03' along the first direction X, and the "vertical coordinate" is the detection distance of the ferroelectric film 03' along the first direction "Coordinates" is the oxygen vacancy content at the position corresponding to the detection distance.

In the ferroelectric film 03', the oxygen vacancy content in the orthorhombic phase, tetragonal phase and monoclinic phase has a large difference. Among them, the oxygen vacancy content in the orthorhombic phase and tetragonal phase is higher, while the oxygen vacancy content in the monoclinic phase is higher. The content is low. Moreover, the inventor of the present application found through experiments that there is only one enrichment peak of oxygen vacancies inside the grains of each orthorhombic phase and each tetragonal phase. Therefore, the phase statistics can be calculated based on the enrichment peak of oxygen vacancies. type and number of grains.

As shown in Figure 6, each oxygen vacancy enrichment peak represents an orthorhombic phase. Within the detection distance of 270nm, the ferroelectric film 03' has 3 grains, and the 3 grains include 1 orthorhombic phase. and 2 monoclinic phases, and the length of the monoclinic phase is relatively large, indicating that the content of the orthorhombic phase in the ferroelectric film 03' is low, resulting in poor performance uniformity and reliability of the ferroelectric memory.

Moreover, as the ferroelectric memory becomes smaller in size, since the ferroelectric film 03' exhibits a polycrystalline structural state, the threshold voltage for editing and erasing of the ferroelectric memory is close to each other, resulting in a reduction in the distinction between editing and erasing. , which in turn causes the memory window (Memory Window, MW) to decrease.

In addition, with the cyclic changes of the electric field generated by the first electrode 01' and the second electrode 02', the oxygen vacancies in the ferroelectric film 03' will migrate, and the oxygen vacancies will migrate to the ferroelectric film 03' close to the first electrode. 01' or the surface of the second electrode 02', which reduces the content of oxygen vacancies inside the ferroelectric film 03'. In this case, the orthorhombic phase crystals in the ferroelectric film 03' will undergo a phase change and transform into a monoclinic phase. crystal.

In the ferroelectric film 03', the migration of oxygen vacancies will cause pinning of the domain walls of the ferroelectric domain, resulting in polarization fatigue (fatigue). "Polarization fatigue" refers to the phenomenon that the polarization intensity of ferroelectric domains decreases after multiple directional flips. Specifically, the ferroelectric memory will perform a large number of editing/erasing operations when reading and writing data. The ferroelectric domains in the ferroelectric film 03' are constantly flipped. After many cycles, the remaining ferroelectric domains in the ferroelectric film 03' The polarization intensity decreases, the coercive field increases, and the two states of "0" or "1" get closer and closer, resulting in a decrease in the distinction between the positive and negative polarization states of the ferroelectric film 03', and finally it becomes difficult to distinguish, and the ferroelectric film 03' becomes difficult to distinguish. The storage window of the memory is reduced, which increases the error rate of reading and writing data in the ferroelectric memory.

Moreover, in the ferroelectric film 03', the concentration of oxygen vacancy migration gradually decreases from close to the electrodes (first electrode 01' and second electrode 02') to the inside, and the gradual accumulation of oxygen vacancies will also form conductive filaments, making the ferroelectric film 03'. The increase in leakage current in the capacitor C' may easily lead to breakdown of the ferroelectric capacitor C', which in turn will reduce the service life and durability of the ferroelectric memory.

Based on this, how to improve the storage window of ferroelectric memory and improve the uniformity, reliability and durability of its performance have become urgent problems in the field.

Some embodiments of the present application provide a ferroelectric capacitor, and FIG. 7 is a structural diagram of a ferroelectric capacitor according to some embodiments.

Referring to Figure 7, the ferroelectric capacitor C includes a first electrode 01 and a second electrode 02 arranged oppositely, and a ferroelectric film 03 located between the first electrode 01 and the second electrode 02. The crystal phase of the ferroelectric film 03 includes tetragonal Mutually.

For example, an electron microscope can be used to directly analyze the phase structure of the ferroelectric film 03 , and it is found that the crystal phase of the ferroelectric film 03 includes a tetragonal phase. Alternatively, X-ray diffraction (XRD) is used to perform X-ray diffraction on the ferroelectric film 03. By analyzing its diffraction pattern, it is concluded that the crystal phase of the ferroelectric film 03 includes a tetragonal phase. In the ferroelectric capacitor C shown in FIG. 7 , the part where the ferroelectric film 03 is located in the “solid line frame” is the tetragonal phase.

Continuing to refer to FIG. 7 , the ferroelectric film 03 includes a first layer 031 and a second layer 032 in contact, at least one of the first layer 031 and the second layer 032 includes a ferroelectric material, and the crystal lattice of the first layer 031 The constant is different from the lattice constant of the second layer 032.

In the ferroelectric capacitor C provided by the above embodiment of the application, the first layer 031 of the ferroelectric film 03 is in contact with the second layer 032. Since the lattice constant of the first layer 031 and the lattice constant of the second layer 032 Different, a lattice mismatch will occur between the two, causing stress to be generated between the first layer 031 and the second layer 032. This stress will act on the crystals of the tetragonal phase, causing lattice distortion of the crystals of the tetragonal phase, forming "Strained tetragonal phase", Figure 8 is a crystal structure diagram of the strained tetragonal phase in ferroelectric film 03.

Figure 9 is the atomic coordinate diagram of the strained tetragonal phase and orthorhombic phase unit cells in the ferroelectric film 03. The "abscissa" is the number of unit cells, and the "ordinate" is the interplanar spacing of the unit cell. Combined with Figure 8 and As shown in Figure 9, compared with the "intrinsic tetragonal phase" where the crystal lattice is not distorted, the crystal plane spacing of the strained tetragonal phase in ferroelectric film 03 increases, and the crystal plane spacing of the strained tetragonal phase is smaller than that of the orthorhombic phase. , indicating that stress acting on the unit cell of the tetragonal phase will cause lattice distortion of the unit cell of the tetragonal phase, forming a strained tetragonal phase. It can be understood that, based on the range of interplanar spacing values of the unit cell in FIG. 9 , it can also be judged that the ferroelectric film 03 includes strained tetragonal phase and orthorhombic phase unit cells.

As shown in Figure 8, the oxygen ions in the "strained tetragonal phase" are offset from the symmetry center of the unit cell, giving it a large residual polarization intensity, which can improve the distinction between positive and negative polarization states of the ferroelectric film 03 , improve the storage window of ferroelectric memory, and improve the accuracy of reading and writing data in ferroelectric memory.

Figure 10 is the atomic coordinate diagram of oxygen ions in the unit cells of the strained tetragonal phase and orthorhombic phase in the ferroelectric film 03. The "abscissa" is the number of unit cells, and the "ordinate" is the offset of the oxygen ions in the unit cell. distance, it can be seen that the oxygen ions in the strained tetragonal phase and orthorhombic phase unit cells are offset, and the offset of the oxygen ions in the strained tetragonal phase is about 30pm.

Figure 11 is a graph of the hysteresis loop of the ferroelectric film 03, in which the "abscissa" is the voltage applied to the ferroelectric film 03, and the "ordinate" is the residual polarization intensity of the ferroelectric film 03. At the voltage When the voltage is -1.36V, the residual polarization intensity is -18.58μC/cm ² ; when the voltage is 1.7V, the residual polarization intensity is 18.48μC/cm ² ; when the voltage is 0, the ferroelectric The 2-fold remanent polarization intensity of film 03 is approximately 37 μC/cm ² , indicating that the strained tetragonal phase has a large remnant polarization intensity.

Compared with related technologies, the orthorhombic phase in the ferroelectric film generates residual polarization intensity, and the content of the orthorhombic phase in the ferroelectric film is low. However, this application generates residual polarization intensity by straining the tetragonal phase, and the ferroelectric film 03 The content of the medium-strain tetragonal phase is relatively high, which can improve the uniformity and reliability of the ferroelectric memory using the ferroelectric capacitor C.

Figure 12 is the electron energy loss spectrum of the oxygen vacancy content in the ferroelectric film 03. Each oxygen vacancy enrichment peak represents an orthorhombic phase or a strained tetragonal phase. Within the detection distance of 270nm, the ferroelectric film 03 has 7 grains, the number of grains is larger, the spacing between grains is small and the grains are closely arranged. Among them, 7 grains include 3 orthorhombic phases and 4 strained tetragonal phases. The length of the strained tetragonal phase is relatively large, indicating that the content of the strained tetragonal phase in ferroelectric film 03 is higher, which can improve the uniformity of the ferroelectric memory. performance and reliability. In addition, the content of the orthorhombic phase in the ferroelectric film 03 is also relatively high, and the orthorhombic phase can also generate residual polarization intensity, which can further improve the uniformity and reliability of the ferroelectric memory.

Figure 13 is a histogram of the lowest potential barrier for oxygen vacancy migration in the orthorhombic phase, monoclinic phase and strained tetragonal phase. Among them, the lowest potential barrier for oxygen vacancy migration in the orthorhombic phase is 1.883eV, and the lowest potential barrier for oxygen vacancy migration in the monoclinic phase The lowest potential barrier is 1.768eV, and the lowest potential barrier for oxygen vacancy migration in the strained tetragonal phase is 2.424eV.

It can be seen that the lowest potential barrier for oxygen vacancy migration in the strained tetragonal phase is the largest, indicating that the oxygen vacancies in the strained tetragonal phase are not easy to migrate, which can improve the polarization fatigue phenomenon of ferroelectric film 03 and reduce the probability of breakdown of ferroelectric capacitor C, thereby improving Ferroelectric memory longevity, durability.

For example, for the ferroelectric capacitor C provided in the above embodiment of the present application, the operating voltage applied to the first electrode 01 and the second electrode 02 is 3MV/cm. In this case, the electric field of the ferroelectric capacitor C can cycle for 1 ×10 ¹² times, indicating the use of ferroelectric memory Longer service life and better durability.

In addition, the strained tetragonal phase has good thermal stability, which can improve the thermal stability of the ferroelectric capacitor C, thereby improving the thermal stability of the ferroelectric memory.

In some embodiments, as shown in FIG. 7 , both the first layer 031 and the second layer 032 of the ferroelectric film 03 include ferroelectric materials. In this case, the crystal phases of the first layer 031 and the second layer 032 are uniform. The tetragonal phase is included, and the proportion of the tetragonal phase in the first layer 031 and the second layer 032 ranges from 30% to 100%. For example, the proportion of the tetragonal phase in the first layer 031 and the second layer 032 is 30%, 50%, 65%, 80% or 100%.

It can be understood that, in the case where both the first layer 031 and the second layer 032 include ferroelectric materials, and the lattice constant of the first layer 031 is different from the lattice constant of the second layer 032, the first layer 031 and the second layer 032 have different lattice constants. The contact surfaces of the second layer 032 may form a lattice mismatch, causing stress to be generated between the first layer 031 and the second layer 032. This stress acts on the tetragonal crystals in the first layer 031 and the second layer 032, causing The crystal of the tetragonal phase produces lattice distortion, thereby forming a strained tetragonal phase in both the first layer 031 and the second layer 032 .

Illustratively, the first layer 031 includes hafnium oxide, the second layer 032 includes zirconium oxide, and the lattice constant of hafnium oxide is different from the lattice constant of zirconium oxide.

Illustratively, both the first layer 031 and the second layer 032 include hafnium zirconium oxygen (chemical formula: Hf _x Zr _1-x O _y , referred to as HZO). The number of hafnium atoms in the first layer 031 is proportional to that of the second layer. The number proportions of hafnium atoms in 032 are different, and the number proportions of zirconium atoms in the first layer 031 are different from the number proportions of zirconium atoms in the second layer 032, so that the lattice constant of the first layer 031 is different from that of the second layer 031. The lattice constant of layer 032 is different.

Figure 14 is a structural diagram of another ferroelectric capacitor according to some embodiments.

Referring to Figure 14, the ferroelectric film 03 includes a plurality of first layers 031 and a plurality of second layers 032. The first layers 031 and the second layers 032 both include ferroelectric materials, and the crystals of the first layer 031 and the second layer 032 are Each phase includes a tetragonal phase, and a plurality of first layers 031 and a plurality of second layers 032 are alternately arranged.

It can be understood that since the lattice constant of the first layer 031 is different from the lattice constant of the second layer 032, by arranging multiple first layers 031 and multiple second layers 032 alternately, the multiple first layers 031 and the second layer 032 are arranged alternately. The surfaces in contact with multiple second layers 032 can form lattice mismatches, which can increase the stress between the first layer 031 and the second layer 032. This stress acts on the tetragonal phase crystals, causing the tetragonal phase crystals to The lattice distortion is produced, which is conducive to the formation of strained tetragonal phase.

FIG. 15 is a structural diagram of another ferroelectric capacitor according to some embodiments; FIG. 16 is a structural diagram of yet another ferroelectric capacitor according to some embodiments.

Referring to Figure 15, the ferroelectric film 03 includes a plurality of first layers 031 and at least one second layer 032. The first layer 031 includes a ferroelectric material, the second layer 032 includes a non-ferroelectric material, and the crystal phase of the first layer 031 Including the tetragonal phase, the proportion of the tetragonal phase in the first layer 031 ranges from 30% to 100%. For example, the proportion of the tetragonal phase in the first layer 031 is 30%, 50%, 65%, 80% or 100%.

Continuing to refer to FIG. 15 , the first layer 031 and the second layer 032 are alternately arranged, and the second layer 032 is not in contact with the first electrode 01 and the second electrode 02 .

It can be understood that in the case where the first layer 031 includes a ferroelectric material, the second layer 032 includes a non-ferroelectric material, and the lattice constant of the first layer 031 is different from the lattice constant of the second layer 032, by setting The first layer 031 and the second layer 032 are alternately arranged. The contact surfaces of the first layer 031 and the second layer 032 may form a lattice mismatch, causing stress to be generated between the first layer 031 and the second layer 032. This stress acts on The tetragonal phase crystal in the first layer 031 will cause lattice distortion of the tetragonal phase crystal, thereby forming a strained tetragonal phase in the first layer 031 .

Moreover, since the second layer 032 includes non-ferroelectric material, by arranging the second layer 032 not to contact the first electrode 01 and the second electrode 02, the first electrode 01 or the second electrode 02 can be prevented from contacting the non-ferroelectric material, Avoid negatively affecting the performance of ferroelectric memory.

For example, as shown in Figure 15, the ferroelectric film 03 includes two first layers 031 and a second layer 032, which is equivalent to a second layer 032 being inserted between the two first layers 031, which can avoid the first layer 031. The second layer 032 is in contact with the first electrode 01 and the second electrode 02 .

Illustratively, as shown in Figure 16, the ferroelectric film 03 includes a plurality of first layers 031 and a plurality of second layers 032, which is equivalent to a plurality of second layers 032 inserted between the plurality of first layers 031. A plurality of first layers 031 and a plurality of second layers 032 are arranged alternately. The surfaces in contact with the plurality of first layers 031 and the plurality of second layers 032 can form lattice mismatch, thereby improving the relationship between the first layer 031 and the second layer 032 . The stress between the two layers of 032 is conducive to the formation of a strained tetragonal phase.

Illustratively, first layer 031 includes hafnium zirconium oxide and second layer 032 includes metal oxide. For example, second layer 032 may include At least one of titanium oxide, lanthanum oxide, and magnesium oxide, that is, the second layer 032 may include one or more of titanium oxide, lanthanum oxide, and magnesium oxide.

In some embodiments, where the first layer 031 of the ferroelectric film 03 includes hafnium oxide and the second layer 032 includes zirconium oxide, or where both the first layer 031 and the second layer 032 include hafnium zirconium oxide. or, in the case where the first layer 031 includes hafnium zirconium oxygen and the second layer 032 includes non-ferroelectric material, the number proportion of hafnium atoms in the ferroelectric film 03 is smaller than the number proportion of zirconium atoms, so that in In the process of preparing the ferroelectric film 03, it is beneficial to generate a tetragonal phase in the ferroelectric film 03.

It can be understood that in the case where both the first layer 031 and the second layer 032 include hafnium zirconium oxide (chemical formula: Hf _x Zr _1-x O _y ), x<1-x.

For example, the ratio of the number of hafnium atoms in the ferroelectric film 03 to the sum of the numbers of hafnium atoms and zirconium atoms ranges from 0.1 to 0.45, that is, 0.1≤x≤0.45. For example, the ratio of the number of hafnium atoms to the sum of the numbers of hafnium atoms and zirconium atoms is 0.1, 0.2, 0.275, 0.3, or 0.45.

For example, the ratio of the number of zirconium atoms in the ferroelectric film 03 to the sum of the numbers of hafnium atoms and zirconium atoms ranges from 0.55 to 0.9, that is, 0.55≤1-x≤0.9. For example, the ratio of the number of zirconium atoms to the sum of the numbers of hafnium atoms and zirconium atoms is 0.55, 0.6, 0.725, 0.8 or 0.9.

In some embodiments, where the first layer 031 of the ferroelectric film 03 includes hafnium oxide and the second layer 032 includes zirconium oxide, or where both the first layer 031 and the second layer 032 include hafnium zirconium oxide. or, in the case where the first layer 031 includes hafnium zirconium oxygen and the second layer 032 includes non-ferroelectric material, the ratio range of the number of oxygen atoms in the ferroelectric film 03 to the sum of the numbers of hafnium atoms and zirconium atoms It is 1.3~1.9.

It can be understood that in the case where both the first layer 031 and the second layer 032 include hafnium zirconium oxide (chemical formula: Hf _x Zr _1-x O _y ), 1.3≤y≤1.9. For example, the ratio of the number of oxygen atoms to the sum of the numbers of hafnium atoms and zirconium atoms is 1.3, 1.5, 1.6, 1.8 or 1.9.

Compared with hafnium zirconium oxygen (chemical formula: Hf _x Zr _1-x O ₂ ), y=2, in the above embodiments of the present application, by reducing the proportion of oxygen atoms in the ferroelectric film 03, the ferroelectric film can be increased The number of oxygen vacancies in 03 is conducive to the generation of tetragonal phase in the ferroelectric film 03.

In some embodiments, the thickness of the ferroelectric film 03 ranges from 4 nm to 8 nm. For example, the thickness of the ferroelectric film 03 is 4 nm, 5 nm, 6 nm, 7 nm or 8 nm.

The thickness of the ferroelectric film in the related art is usually greater than 10 nm, but in the above embodiments of the present application, the thickness of the ferroelectric film 03 is smaller. By reducing the thickness of the ferroelectric film 03, in the process of preparing the ferroelectric film 03, there are It is beneficial to generate the tetragonal phase in the ferroelectric film 03.

Figure 17 is a structural diagram of yet another ferroelectric capacitor according to some embodiments.

Referring to Figure 17, the thermal expansion coefficient of the first electrode 01 of the ferroelectric capacitor C is different from the thermal expansion coefficient of the second electrode 02. In the process of preparing the ferroelectric capacitor C, it needs to be carried out in a high temperature environment. Due to the thermal expansion of the first electrode 01 The coefficient of thermal expansion is different from that of the second electrode 02, and the volume expansion rate of the first electrode 01 is different from that of the second electrode 02, causing stress to be generated between the first electrode 01 and the second electrode 02, and this stress acts on the iron The tetragonal phase crystal of the electric film 03 will cause lattice distortion of the tetragonal phase crystal, forming a strained tetragonal phase.

Exemplarily, the materials of the first electrode 01 and the second electrode 02 may include any of TiN, TaN, Ir, _IrOx , Ti, TiCN, TiSiN, WSiN, TiAlN, TaAlN, TiAlCN, W, Pt, Au, and Al There are two types, and the thermal expansion coefficients of the two materials are different.

For example, as shown in FIG. 17 , the material of the first electrode 01 includes W, and the material of the second electrode 02 includes TiN.

In some embodiments, the ferroelectric capacitor C may further include a third electrode 04 , and the third electrode 04 may be located on a side of the second electrode 02 away from the ferroelectric film 03 .

For example, the material of the third electrode 04 may be the same as the material of the first electrode 01 .

Exemplarily, the material of the third electrode 04 may include any one of TiN, TaN, Ir, IrOx, Ti, TiCN, TiSiN, WSiN, TiAlN, TaAlN, TiAlCN, W, Pt, Au, and Al, for example, The material of the three electrodes 04 may include W.

The structure of the ferroelectric capacitor C provided by the embodiment of the present application may be a two-dimensional planar structure. For example, see FIG. 7 and FIG. 14 to FIG. 17 . The first electrode 01 and the second electrode 02 are both planar electrodes. An electrode 01, the first layer 031, the second layer 032 and the second electrode 02 of the ferroelectric film 03 are stacked. The ferroelectric capacitor C has a simple structure and is easy to prepare.

Exemplarily, the memory unit 200 includes a ferroelectric capacitor C and a transistor T. The first electrode 01 and the second electrode 02 of the ferroelectric capacitor C are planar electrodes. In this case, the first electrode 01 and the second electrode 02 are planar electrodes. One of the electrodes 02 is electrically connected to the transistor T to form the memory cell 200 .

Some embodiments of the present application provide a method for preparing the ferroelectric capacitor C shown in FIG. 17 , and FIGS. 18A to 18D are diagrams of steps for preparing the ferroelectric capacitor according to some embodiments.

As shown in FIG. 18A, the first electrode 01 is formed.

For example, a physical vapor deposition (Physical Vapor Deposition, PVD) process can be used to form the first electrode 01 .

As shown in Fig. 18B, ferroelectric film 03 is formed.

For example, an atomic layer deposition (ALD) process can be used to sequentially form the second layer 032 and the first layer 031 on the first electrode 01 to obtain the ferroelectric film 03. At least one of the first layer 031 and the second layer 032 includes a ferroelectric material, and the first layer 031 has a lattice constant different from that of the second layer 032 .

As shown in FIG. 18C , a second electrode 02 is formed, and the second electrode 02 is located on a side of the ferroelectric film 03 away from the first electrode 01 .

For example, an atomic layer deposition process may be used to form the second electrode 02 .

For example, as shown in FIG. 18D , after the second electrode 02 is formed, a third electrode 04 may also be formed on a side of the second electrode 02 away from the ferroelectric film 03 .

For example, a physical vapor deposition process may be used to form the third electrode 04 .

After the second electrode 02 is formed, the ferroelectric film 03 is subjected to rapid thermal processing (RTP) to form a tetragonal phase.

The preparation method provided by the above embodiments of the present application sequentially forms the first electrode 01, the ferroelectric film 03 and the second electrode 02. After the second electrode 02 is formed, the ferroelectric film 03 is rapidly heat treated to form a ferroelectric layer. A tetragonal phase is formed in the electric film 03 .

Moreover, since the lattice constant of the first layer 031 is different from the lattice constant of the second layer 032, a lattice mismatch will occur between them, causing stress to be generated between the first layer 031 and the second layer 032. This stress Acting on the crystals of the tetragonal phase will cause lattice distortion of the crystals of the tetragonal phase, forming a strained tetragonal phase.

In some embodiments, the ferroelectric film 03 is subjected to rapid heat treatment, and the temperature of the rapid heat treatment ranges from 450°C to 650°C. For example, the temperature of the rapid heat treatment is 450°C, 500°C, 550°C, 600°C, or 650°C.

Compared with the related art, where the orthorhombic phase is formed through rapid heat treatment at a relatively high temperature (greater than 700° C.), the above-mentioned embodiments of the present application facilitate the formation of a tetragonal phase in the ferroelectric film 03 by lowering the temperature of the rapid heat treatment.

The structure of the ferroelectric capacitor C provided in the embodiments of the present application can also be a three-dimensional vertical structure. Figure 19 is a three-dimensional vertical structure diagram of a ferroelectric capacitor according to some embodiments.

Referring to Figure 19, the first electrode 01 of the ferroelectric capacitor C is a planar electrode, the second electrode 02 is a columnar electrode, the second electrode 02 penetrates the first electrode 01, and the first layer 031 and the second layer 032 of the ferroelectric film 03 Disposed around the second electrode 02 to separate the first electrode 01 from the second electrode 02 .

The ferroelectric capacitor C adopts the above-mentioned three-dimensional vertical structural design, which can reduce its occupied area in the X-Y plane, thereby increasing the number of ferroelectric capacitors C per unit area in the X-Y plane, thereby increasing the memory unit 200 per unit area. The number of settings is beneficial to improving the storage density of ferroelectric memory.

Exemplarily, the memory unit 200 includes a ferroelectric capacitor C and a transistor T. The first electrode 01 of the ferroelectric capacitor C is a planar electrode, and the second electrode 02 is a columnar electrode. In this case, the second electrode 02 and The transistor T is electrically connected, that is, the columnar electrode of the ferroelectric capacitor C is electrically connected to the transistor T to form the memory cell 200 .

Some embodiments of the present application provide a method for preparing the ferroelectric capacitor C shown in Figure 19. Figures 20A to 20D are diagrams of steps for preparing the ferroelectric capacitor according to some embodiments.

As shown in FIG. 20A , a stacked layer is formed. The stacked layer includes alternately arranged first electrodes 01 (planar electrodes) and a dielectric layer 06 . The dielectric layer 06 can separate two first electrodes 01 that are adjacent along the direction Z. , so as to insulate between two adjacent first electrodes 01 .

As shown in FIG. 20B , a via H is formed that penetrates the stacked layer, and the via H penetrates the first electrode 01 and the dielectric layer 06 in the stacked layer.

As shown in FIG. 20C , the second layer 032 and the first layer 031 of the ferroelectric film 03 are formed on the side walls of the via hole H.

As shown in FIG. 20D , the second electrode 02 is formed inside the ferroelectric film 03 .

The above preparation method of the present application forms a ferroelectric capacitor C with a three-dimensional vertical structure.

Figure 21 is another three-dimensional vertical structure diagram of a ferroelectric capacitor according to some embodiments.

Referring to Figure 21, a trench H is opened in the first electrode 01 of the ferroelectric capacitor C. The second layer 032 of the ferroelectric film 03 is disposed on the inner wall of the trench H. The first layer 031 is disposed inside the second layer 032. . The second electrode 02 is disposed inside the second layer 032, And the second electrode 02 fills the trench H. The ferroelectric capacitor C using this structure is also called a trench capacitor.

The above-mentioned three-dimensional vertical structural design of the ferroelectric capacitor C can also reduce its occupied area in the X-Y plane, thereby increasing the number of ferroelectric capacitors C per unit area in the X-Y plane to increase the memory unit per unit area. The setting number of 200 is conducive to improving the storage density of ferroelectric memory.

The memory and electronic equipment provided by some embodiments of the present application include the ferroelectric capacitor C provided by any of the above embodiments. The beneficial effects it can achieve can be referred to the beneficial effects of the ferroelectric capacitor C mentioned above, which are not mentioned here. Again.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention. should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (22)

1. A ferroelectric memory array, characterized in that it includes a plurality of memory cells arranged in an array, and the memory cells include ferroelectric capacitors and transistors;

   The ferroelectric capacitor includes:

   A first electrode and a second electrode arranged oppositely;

   A ferroelectric film disposed between the first electrode and the second electrode;

   Wherein, the crystal phase of the ferroelectric film includes a tetragonal phase;

   The ferroelectric film includes a first layer and a second layer in contact, at least one of the first layer and the second layer includes a ferroelectric material, and the first layer has a lattice constant consistent with the The lattice constant of the second layer is different.
2. The ferroelectric memory array according to claim 1, wherein the unit cell of the tetragonal phase in the ferroelectric film includes oxygen ions, and the oxygen ions are offset relative to the center of symmetry of the unit cell.
3. The ferroelectric memory array according to claim 1 or 2, wherein the first layer and the second layer each comprise a ferroelectric material;

   The crystal phase of the first layer and the second layer both includes a tetragonal phase, and the proportion of the tetragonal phase in the first layer and the second layer ranges from 30% to 100%.
4. The ferroelectric memory array of claim 3, wherein the first layer includes hafnium oxide and the second layer includes zirconium oxide.
5. The ferroelectric memory array of claim 3, wherein the first layer and the second layer each include hafnium zirconium oxide;

   The number proportion of hafnium atoms in the first layer is different from the number proportion of hafnium atoms in the second layer;

   The number ratio of zirconium atoms in the first layer is different from the number ratio of zirconium atoms in the second layer.
6. The ferroelectric memory array according to any one of claims 3 to 5, wherein a plurality of first layers and a plurality of second layers are alternately arranged.
7. The ferroelectric memory array according to claim 1 or 2, wherein the first layer includes ferroelectric material, and the second layer includes non-ferroelectric material;

   The ferroelectric film includes a plurality of the first layers and at least one second layer, the first layers and the second layers are alternately arranged, and the second layer is not connected with the first electrode and the second layer. the second electrode contacts;

   The crystal phase of the first layer includes a tetragonal phase, and the proportion of the tetragonal phase in the first layer ranges from 30% to 100%.
8. The ferroelectric memory array of claim 7, wherein the first layer includes hafnium zirconium oxide and the second layer includes metal oxide.
9. The ferroelectric memory array of claim 8, wherein the second layer includes at least one of titanium oxide, lanthanum oxide, and magnesium oxide.
10. The ferroelectric memory array according to any one of claims 4, 5, 8 and 9, characterized in that the number proportion of hafnium atoms in the ferroelectric film is smaller than the number proportion of zirconium atoms.
11. The ferroelectric memory array according to claim 10, wherein the ratio of the number of hafnium atoms in the ferroelectric film to the sum of the numbers of hafnium atoms and zirconium atoms ranges from 0.1 to 0.45;

    The ratio of the number of zirconium atoms to the sum of the numbers of hafnium atoms and zirconium atoms ranges from 0.55 to 0.9.
12. The ferroelectric memory array according to claim 10 or 11, wherein the ratio of the number of oxygen atoms in the ferroelectric film to the sum of the number of hafnium atoms and zirconium atoms ranges from 1.3 to 1.9.
13. The ferroelectric memory array according to any one of claims 1 to 12, wherein the thickness of the ferroelectric film ranges from 4 nm to 8 nm.
14. The ferroelectric memory array according to any one of claims 1 to 13, wherein the thermal expansion coefficient of the first electrode is different from the thermal expansion coefficient of the second electrode.
15. The ferroelectric memory array according to any one of claims 1 to 14, wherein the crystal phase of the ferroelectric film further includes an orthorhombic phase.
16. The ferroelectric memory array according to any one of claims 1 to 15, wherein the first electrode and the second electrode are planar electrodes, and the first electrode, the first layer , the second layer and the second electrode are stacked.
17. The ferroelectric memory array according to any one of claims 1 to 15, wherein the first electrode is a planar electrode and the second electrode is a columnar electrode;

    The second electrode penetrates the first electrode, and the first layer and the second layer are arranged around the second electrode.
18. The ferroelectric memory array according to any one of claims 1 to 17, wherein the first electrode and the second electrode are planar electrodes, and the first electrode and the second electrode are planar electrodes. One of them is electrically connected to the transistor; or,

    The first electrode is a planar electrode, the second electrode is a columnar electrode, and the second electrode is electrically connected to the transistor.
19. A method for preparing a ferroelectric memory array, which is characterized by including:

    A first electrode, a ferroelectric film and a second electrode are formed in sequence; the ferroelectric film includes a first layer and a second layer, at least one of the first layer and the second layer includes a ferroelectric material, and The lattice constant of the first layer is different from the lattice constant of the second layer; and/or the thermal expansion coefficient of the first electrode is different from the thermal expansion coefficient of the second electrode;

    Wherein, after forming the second electrode, the method further includes:

    The ferroelectric film is subjected to rapid heat treatment to form a tetragonal phase.
20. The preparation method according to claim 19, characterized in that the temperature range of the rapid heat treatment is 450°C to 650°C.
21. A memory, characterized in that it includes:

    The ferroelectric memory array according to any one of claims 1 to 18;

    A controller electrically connected to the ferroelectric memory array.
22. An electronic device, characterized by including:

    circuit board;

    The memory of claim 21, wherein the memory is disposed on the circuit board and electrically connected to the circuit board.