WO2023179394A1

WO2023179394A1 - Ferroelectric memory and forming method therefor, and electronic device

Info

Publication number: WO2023179394A1
Application number: PCT/CN2023/081044
Authority: WO
Inventors: 王贺; 李家晨; 殷月伟; 李晓光; 唐文涛; 赵俊峰; 罗时江
Original assignee: 华为技术有限公司; 中国科学技术大学
Priority date: 2022-03-23
Filing date: 2023-03-13
Publication date: 2023-09-28
Also published as: CN116867286A

Abstract

Embodiments of the present application provide a ferroelectric memory and a forming method therefor, and an electronic device. In each of the storage units of the ferroelectric memory provided by the embodiments of the present application, a ferroelectric tunnel junction used for storing charges comprises an insulating barrier intercalation stacked between at least one electrode of a first electrode and a second electrode, and a ferroelectric barrier layer, or the insulating barrier intercalation stacked between adjacent ferroelectric barrier layers. When electrons are migrated between the adjacent ferroelectric barrier layers, the electrons need to pass through the insulating barrier intercalation, and the insulating barrier intercalation can destroy the continuity of a crystal boundary between the adjacent ferroelectric barrier layers, and weaken the migration of the electrons between the adjacent ferroelectric barrier layers; similarly, the electrons are migrated between the ferroelectric barrier layer and at least one electrode of the first electrode and the second electrode, and when the electrons need to pass through the insulating barrier intercalation, the insulating barrier intercalation can weaken the migration of the electrons, and correspondingly, the leakage current generated due to the migration of the electrons is reduced.

Description

Ferroelectric memory, method of forming the same, and electronic equipment

This application requests the priority of the Chinese patent application submitted to the State Intellectual Property Office on March 23, 2022, with the application number: 202210295574.0, and the application name is "Ferroelectric memory and its formation method, electronic equipment", the entire content of which is incorporated by reference incorporated in this application.

Technical field

The present application relates to the field of storage technology, and in particular to ferroelectric memory, its formation method, and electronic equipment.

Background technique

As a new type of memory, ferroelectric random access memory (FeRAM) is more traditional than traditional dynamic random access memory (DRAM) or flash memory because it is non-volatile and highly efficient. Advantages such as speed, low power consumption, and high number of reads and writes are increasingly being used.

Usually, FeRAM includes a substrate and a plurality of memory cells formed on the substrate. The core component of the memory cell is a ferroelectric tunnel junction (FTJ); Figure 1 shows a process structure diagram of the ferroelectric tunnel junction. . Among them, the FTJ includes a stacked first electrode 01 and a second electrode 02, and a ferroelectric barrier layer 03 formed between the first electrode 01 and the second electrode 02. The potential barrier for electrons in the ferroelectric barrier layer 03 can be switched between a high value and a low value through polarization reversal. When the potential barrier of electrons in ferroelectric barrier layer 03 is at a high value, FTJ exhibits a high resistance state; when the potential barrier of electrons in ferroelectric barrier layer 03 is at a low value, FTJ exhibits a low resistance state. The high-resistance state and low-resistance state of FTJ can correspond to "1" and "0" representing the logic state, and are recorded in FeRAM.

The unit cell of hafnium oxide itself is a symmetrical unit cell. The treated hafnium oxide unit cell changes from a symmetrical unit cell to an asymmetrical hafnium oxide unit cell. The positive and negative charge centers of the corresponding hafnium oxide unit cells do not overlap, generating electric charges. The dipole forms a spontaneous polarization, and the potential barrier of the electrons in the hafnium oxide switches between high and low values through polarization reversal under the action of an external electric field. The treatment may be doping silicon. Therefore, hafnium oxide can be used as a preparation material for the ferroelectric barrier layer 03 and applied to FTJ.

The process of forming an FTJ containing hafnium oxide includes: forming a first electrode 01 on a substrate; forming a hafnium oxide base material on the first electrode 01; forming a second electrode 02 on the hafnium oxide base material; annealing and crystallizing the hafnium oxide base material Obtain FTJ for ferroelectric barrier layer 03. There is a problem in the existing process of forming FTJ, that is, hafnium oxide will produce a large number of grain boundaries during the annealing and crystallization process, which results in the prepared FTJ having a high leakage current. The leakage current is when the FeRAM is in the writing state, and the FeRAM An electric field is applied to the internal FTJ, and the electrons migrate in a directional manner to form a current. Specifically, when an electric field is applied to the FTJ, electrons migrate directionally between the first electrode 01, the ferroelectric barrier layer 03 and the second electrode 02; since there are a large number of grain boundaries in the ferroelectric barrier layer 03, atoms at the grain boundaries appear inconsistently. Regularly arranged, the structure at the grain boundary is sparse, the electrons at the grain boundary have higher energy, and the electrons can easily migrate through the grain boundary.

Contents of the invention

Embodiments of the present application provide a ferroelectric memory, a method of forming the same, and electronic equipment. The main purpose is to provide a method that can weaken the migration of electrons between adjacent ferroelectric barrier layers, or the migration of electrons between at least one of the first electrode and the second electrode and the ferroelectric barrier layer, so that the ferroelectric barrier layer can be weakened. The memory has low leakage current.

In order to achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In a first aspect, the application provides a ferroelectric memory, which is a ferroelectric random access memory (FeRAM). The ferroelectric memory includes: a substrate; a plurality of Memory cells are formed on a substrate, each memory cell includes a ferroelectric tunnel junction; wherein the ferroelectric tunnel junction includes: a first electrode; at least one ferroelectric barrier layer, the ferroelectric barrier layer includes a ferroelectric oxide Hafnium-based material; a second electrode, a ferroelectric barrier layer stacked between the first electrode and the second electrode; at least one insulating barrier intercalation layer, at least one of the first electrode and the second electrode and the ferroelectric barrier layer There is an insulating barrier intercalation layer between them, or there is an insulating barrier intercalation layer between adjacent ferroelectric barrier layers.

In the memory unit of the ferroelectric memory provided by this application, the ferroelectric tunnel junction used to store charges not only includes a first electrode, a second electrode, and a ferroelectric barrier layer stacked between the first electrode and the second electrode, Also included is an insulating barrier interlayer stacked between at least one of the first electrode and the second electrode and the ferroelectric barrier layer, or an insulating barrier interlayer stacked between adjacent ferroelectric barrier layers. . Since the insulating barrier intercalation has a low dielectric constant, it can weaken electron migration. When electrons migrate between adjacent ferroelectric barrier layers, the electrons need to pass through the insulating barrier intercalation. The insulating barrier intercalation can break the continuity of the grain boundaries between adjacent ferroelectric barrier layers and weaken the electrons. Migration between adjacent ferroelectric barrier layers; similarly, electrons migrate between the ferroelectric barrier layer and at least one of the first electrode and the second electrode, when the electrons need to pass through the insulating barrier intercalation layer , the insulating barrier intercalation can weaken the migration of electrons; the migration of electrons is weakened, and the leakage current caused by electron migration is correspondingly reduced. Therefore, the ferroelectric memory obtained by the embodiment of the present application has a lower leakage current.

In a possible implementation of the first aspect, at least one of the first electrode and the second electrode is a pinch electrode, the ferroelectric barrier layer is in contact with the pinch electrode, and the pinch electrode is the absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide. Electrodes less than the difference threshold.

In this implementation, the tensile stress released during the annealing and crystallization process of the holding electrode helps to convert the unit cell of hafnium oxide in the ferroelectric barrier layer from symmetry to asymmetry. Using pinched electrodes can obtain more asymmetric hafnium oxide unit cells; the more asymmetric hafnium oxide unit cells, the stronger the ferroelectricity of the ferroelectric barrier layer. Therefore, the ferroelectricity of the ferroelectric barrier layer is higher, correspondingly The ferroelectric tunnel junction has higher ferroelectricity.

In a possible implementation of the first aspect, the hafnium oxide-based material includes hafnium oxide and a doping element, and the doping element is an element that converts the unit cell of the hafnium oxide from symmetry to asymmetry and has ferroelectricity.

In this implementation, during the annealing and crystallization process, the doping elements help the unit cell of hafnium oxide convert from symmetry to asymmetry. Therefore, adding doping elements to hafnium oxide-based materials can produce more asymmetric hafnium oxide unit cells; the more asymmetric hafnium oxide unit cells, the stronger the ferroelectricity of the ferroelectric barrier layer. Therefore, the ferroelectric barrier layer The ferroelectricity is higher, and the corresponding ferroelectric tunnel junction has higher ferroelectricity.

In a possible implementation of the first aspect, the doping elements include: zirconium, yttrium, aluminum, silicon, gadolinium, strontium, lanthanum, nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium At least one of gallium, calcium and carbon.

In a possible implementation of the first aspect, the ferroelectric barrier layer includes a first ferroelectric barrier layer and a second ferroelectric barrier layer, and there is an insulating barrier intercalation layer between the first ferroelectric barrier layer and the second ferroelectric barrier layer. ; The first electrode is a holding electrode; the first ferroelectric barrier layer is in contact with the first electrode; the thickness of the first ferroelectric barrier layer is greater than the thickness of the second ferroelectric barrier layer.

The tensile stress generated during the annealing and crystallization process of the clamped electrode can act on the hafnium oxide in the ferroelectric barrier layer in contact with it. In this implementation, the thickness of the first ferroelectric barrier layer is greater than the thickness of the second ferroelectric barrier layer, and the first ferroelectric barrier layer contains more hafnium oxide than the second ferroelectric barrier layer; the holding electrode Contact with the first ferroelectric barrier layer containing more hafnium oxide; during the annealing and crystallization process, the tensile stress generated by the holding electrode can act on more hafnium oxide, converting the unit cell of hafnium oxide from symmetry to asymmetry sex, so you can get more The asymmetry of the hafnium oxide unit cell. The more asymmetric hafnium oxide unit cells, the stronger the ferroelectricity of the ferroelectric barrier layer. Therefore, the ferroelectricity of the ferroelectric barrier layer is higher, and the corresponding ferroelectric tunnel junction has higher ferroelectricity.

In a possible implementation manner of the first aspect, the distance between the first electrode and the second electrode in the stacking direction is less than or equal to 5 nm.

The smaller the distance between the first electrode and the second electrode, the smaller the thickness of the insulating barrier intercalation layer and the ferroelectric barrier layer stacked between the first electrode and the second electrode. Correspondingly, the electrons pass through the insulating barrier intercalation layer and The smaller the resistance of the ferroelectric barrier layer, the better the conductivity of the ferroelectric tunnel junction. In this implementation, the distance between the first electrode and the second electrode is less than or equal to 5 nm, the resistance of electrons passing through the insulating barrier intercalation layer and the ferroelectric barrier layer is small, and the corresponding ferroelectric tunnel junction has high conductivity.

In a possible implementation manner of the first aspect, the insulating barrier interlayer includes at least one of silicon oxide and aluminum oxide.

The wider the band gap, the more difficult it is for electrons of a material to transition from one energy level to a higher energy level, and accordingly the material is more difficult to penetrate. In this implementation, alumina has a wider band gap, so the alumina has a strong anti-breakdown ability, and correspondingly, the ferroelectric tunnel junction containing alumina has a strong anti-breakdown ability. In the same way, silicon oxide has a wide band gap, silicon oxide has a strong resistance to breakdown, and correspondingly, a ferroelectric tunnel junction containing silicon oxide has a strong resistance to breakdown.

In a possible implementation of the first aspect, the number of insulation barrier intercalation layers is less than or equal to 3.

Introducing an insulating barrier intercalation into the ferroelectric tunnel junction can reduce the leakage current of the ferroelectric tunnel junction. In order to further reduce the leakage current of the ferroelectric tunnel junction, multiple layers of insulating barrier intercalations can be introduced into the ferroelectric tunnel junction. However, if the number of insulation barrier intercalation layers is large, the volume of the ferroelectric tunnel junction will be correspondingly increased, which is not conducive to the high-density integration of the ferroelectric tunnel junction. Therefore, in order to take into account the characteristics of small leakage current and small volume, in this implementation, the number of insulation barrier intercalation layers is less than or equal to 3.

In a second aspect, embodiments of the present application provide a method for forming a ferroelectric memory, including: forming a first electrode on a substrate; forming at least one ferroelectric barrier layer and at least one ferroelectric barrier layer on a side of the first electrode away from the substrate. An insulating barrier intercalation layer, the ferroelectric barrier layer includes a ferroelectric hafnium oxide-based material; forming a second electrode, so that the first electrode, the second electrode, the ferroelectric barrier layer and the insulating barrier intercalation layer form a memory unit A ferroelectric tunnel junction; wherein, there is a ferroelectric barrier layer between the first electrode and the second electrode, and there is an insulating barrier intercalation layer between at least one of the first electrode and the second electrode and the ferroelectric barrier layer, or , there is an insulating barrier intercalation layer between adjacent ferroelectric barrier layers.

In the method for forming a ferroelectric memory given in this application, not only the first electrode, the second electrode, and the ferroelectric barrier layer stacked between the first electrode and the second electrode are produced, but also the ferroelectric barrier layer stacked on the first electrode is produced. and an insulating barrier intercalation between at least one of the second electrodes and the ferroelectric barrier layer, or an insulating barrier intercalation stacked between adjacent ferroelectric barrier layers. Since the insulating barrier intercalation has a low dielectric constant, it can weaken electron migration. When electrons migrate between adjacent ferroelectric barrier layers, the electrons need to pass through the insulating barrier intercalation. The insulating barrier intercalation can break the continuity of the grain boundaries between adjacent ferroelectric barrier layers and weaken the electrons. Migration between adjacent ferroelectric barrier layers; similarly, electrons migrate between the ferroelectric barrier layer and at least one of the first electrode and the second electrode, when the electrons need to pass through the insulating barrier intercalation layer , the insulating barrier intercalation can weaken the migration of electrons; because the migration of electrons is weakened, the leakage current caused by electron migration is correspondingly reduced. Therefore, the ferroelectric memory obtained by the embodiment of the present application has a lower leakage current.

In a possible implementation of the second aspect, forming the first electrode and the second electrode includes: using a material whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than a difference threshold to form the first electrode and the second electrode. of at least one electrode.

In this implementation, the electrode is formed from a material whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold. The tensile stress released by the electrode during the annealing and crystallization process contributes to the formation of hafnium oxide in the ferroelectric barrier layer. The unit cell switches from symmetry to asymmetry. Therefore, more asymmetric hafnium oxide unit cells can be obtained. The more asymmetric hafnium oxide unit cells, the stronger the ferroelectricity of the ferroelectric barrier layer. Therefore, the ferroelectricity of the ferroelectric barrier layer is higher, and the corresponding ferroelectric tunnel junction has higher ferroelectricity.

In a possible implementation manner of the second aspect, forming the ferroelectric barrier layer includes: forming at least one layer of hafnium oxide-based material; and annealing and crystallizing the hafnium oxide-based material to form the ferroelectric barrier layer.

In a possible implementation of the second aspect, after the step of forming at least one layer of hafnium oxide-based material and before annealing the crystallized hafnium oxide-based material, a second electrode is formed, and the second electrode is formed by a thermal expansion coefficient of the hafnium oxide thermal expansion coefficient. A material whose absolute value of the difference is less than the difference threshold is formed.

In this implementation, the second electrode is formed of a material whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold. The tensile stress released by the second electrode during the annealing and crystallization process contributes to the internalization of the ferroelectric barrier layer. The unit cell of hafnium oxide is converted from symmetry to asymmetry, so more asymmetric hafnium oxide unit cells can be obtained. The more asymmetric hafnium oxide unit cells, the stronger the ferroelectricity of the ferroelectric barrier layer. Therefore, the ferroelectricity of the ferroelectric barrier layer is higher, and the corresponding ferroelectric tunnel junction has higher ferroelectricity.

In a possible implementation manner of the second aspect, after the step of annealing the crystallized hafnium oxide-based material to convert it into the ferroelectric barrier layer, a second electrode is formed, and the second electrode is an electrode away from the substrate.

In a possible implementation of the second aspect, after the step of forming at least one layer of hafnium oxide-based material, a clamping material is used to form an intermediate electrode, the intermediate electrode is in contact with the hafnium oxide-based material, and the intermediate electrode is composed of a thermal expansion coefficient and a thermal expansion coefficient of hafnium oxide. A material whose absolute value of the difference is less than the difference threshold is formed; after the step of forming the intermediate electrode, the annealed crystallized hafnium oxide-based material is converted into a ferroelectric barrier layer; the intermediate electrode is removed; and a second electrode is formed, the second electrode having specific properties better than the middle electrode The specific properties of the electrode include at least one of electrical conductivity, hardness, and thermal conductivity.

In this implementation, the middle electrode is made of a material whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold. The tensile stress released by the middle electrode during the annealing and crystallization process contributes to the hafnium oxide in the ferroelectric barrier layer. The unit cell is converted from symmetry to asymmetry. The resulting ferroelectric barrier layer has higher ferroelectricity. After the ferroelectric barrier layer is generated, the middle electrode is replaced with a second electrode. Since the specific performance of the second electrode is better than that of the middle electrode, it can be ensured that the obtained ferroelectric tunnel junction has both ferroelectricity and specific performance.

The electronic device provided by the embodiment of the present application includes the ferroelectric memory provided by the embodiment of the first aspect and the second aspect. Therefore, the electronic device provided by the embodiment of the present application and the ferroelectric memory of the above technical solution can solve the same technical problem. and achieve the same desired effect.

Description of the drawings

Figure 1 is a process structure diagram of a FeRAM ferroelectric capacitor in the prior art;

Figure 2 is a circuit diagram of an electronic device provided by an embodiment of the present application;

Figure 3 is a circuit diagram of a ferroelectric memory provided by an embodiment of the present application;

Figure 4 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment;

Figure 5-1 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment;

Figure 5-2 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment;

Figure 5-3 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment;

Figure 6-1 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment;

Figure 6-2 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment;

Figure 6-3 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment;

Figure 7-1 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment;

Figure 7-2 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment;

Figure 8 is a flow chart of a method for forming a ferroelectric memory provided by a feasible embodiment;

Figure 9 is a flow chart of a ferroelectric memory forming method provided by another feasible embodiment;

Figure 10 is a flow chart of a ferroelectric memory forming method provided by another feasible embodiment;

Figure 11 is a hysteresis curve of the resistance of the doped hafnium oxide-based ferroelectric tunnel junction changing with the applied pulse voltage when the pulse voltage pulse width of the ferroelectric tunnel junction provided by the embodiment of the present invention is td=600ps, 1ns, and 10ns;

Figure 12 is a diagram of two distinguishable resistance state transition repetition characteristics obtained by repeatedly applying different pulse voltages to the ferroelectric tunnel junction when the pulse voltage pulse width is td=10ns;

Figure 13 is a diagram showing the retention characteristics of the ferroelectric tunnel junction resistance state provided by a feasible embodiment;

Figure 14 shows the DC volt-ampere characteristics of ferroelectric tunnel junctions with and without silicon oxide.

Detailed ways

Before introducing the embodiments involved in this application, the technical terms involved in this application are first introduced, as follows:

A crystal unit cell (which may also be called a unit cell in the embodiments of this application) is a structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.

Relative permittivity (RP) is a physical parameter used to characterize the dielectric properties of dielectric materials. When an external electric field is applied to the dielectric material, it will generate induced charges and consume the electric field. The ratio of the original external electric field to the final electric field in the dielectric material is the relative dielectric constant.

The switching ratio is the ratio of the current flowing through the ferroelectric tunnel junction when the ferroelectric tunnel junction is in a low resistance state to the current flowing through the ferroelectric tunnel junction when the ferroelectric tunnel junction is in a low resistance state.

Leakage current (LC) is the current formed by the directional migration of electrons when an electric field is applied to the FTJ inside the FeRAM when the FeRAM is in the writing state.

Under certain external environments, such as high temperatures, oxygen in the crystal will break away from its original position, forming oxygen vacancies (OVS).

Band gap (BG) is the energy difference between two energy levels that electrons in a substance can jump from one energy level to a higher energy level when absorbing energy.

Grain boundary (GB) is the interface between hafnium oxide unit cells with the same structure but different orientations.

A capacitor is a structure composed of two conductors close to each other sandwiched by a layer of insulating material.

The integrated capacitance effect refers to the phenomenon that when an electric field is applied between two conductors of a capacitor, charges will accumulate on the two conductors, and charges will accumulate on the two conductors.

The embodiments of the present application will be introduced in detail below with reference to the accompanying drawings, see the following description.

Ferroelectric memory stores data based on the ferroelectric effect of ferroelectric materials. Ferroelectric memory is expected to become the main competitor to replace dynamic random access memory (DRAM) due to its ultra-high storage density, low power consumption and high speed. The memory unit in the ferroelectric memory includes a ferroelectric tunnel junction. The ferroelectric tunnel junction includes two electrodes, and a ferroelectric material, such as a ferroelectric film layer (also called a ferroelectric film layer in the embodiment of the present application), disposed between the two electrodes. It is a ferroelectric barrier layer). Due to the nonlinear characteristics of ferroelectric materials, the dielectric constant of ferroelectric materials can not only be adjusted, but also the difference before and after the polarization state of the ferroelectric film is flipped is very large, which makes Ferroelectric tunnel junctions are smaller than other capacitors. For example, they are much smaller than the capacitors used to store charge in DRAM.

In ferroelectric memory, the ferroelectric barrier layer can be formed using common ferroelectric materials. When an electric field is applied to the ferroelectric barrier layer of the memory cell, the central atom stops in a low energy state along the electric field. On the contrary, when the electric field reversal is applied to the ferroelectric barrier layer, the central atom stays in a low energy state along the direction of the electric field. The crystal moves and stops in another low energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, which form polarized charges under the action of an electric field. The polarization charge formed by the reversal of the ferroelectric domain under the electric field is high, and the polarization charge formed by the non-reversal of the ferroelectric domain under the electric field is low. The binary stable state of this ferroelectric material allows ferroelectricity to be used as memory.

An embodiment of the present application provides an electronic device including a ferroelectric memory. Figure 2 shows an electronic device 200 provided by an embodiment of the present application. The electronic device 200 can be a terminal device, such as a mobile phone, a tablet, a smart bracelet, or a personal computer (PC), server, workstation, etc. . The electronic device 200 includes a bus, and a system on chip (SOC) and a read-only memory (read-only memory, ROM) 220 connected to the bus. SOC can be used to process data, such as processing application data, processing image data, and caching temporary data. ROM 220 can be used to save non-volatile data, such as audio files, video files, etc. ROM 220 can be PROM (programmable read-only memory, programmable read-only memory), EPROM (erasable programmable read-only memory, erasable programmable read-only memory), flash memory (flash memory), etc.

In addition, the electronic device 200 may also include a communication chip 230 and a power management chip 240. The communication chip 230 can be used to process the protocol stack, or to amplify and filter analog radio frequency signals, or to implement the above functions at the same time. The power management chip 240 can be used to power other chips.

In one embodiment, the SOC may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a cache data Random access memory (RAM) 213.

The above-mentioned AP211, GPU212 and RAM213 can be integrated into one die, or integrated into multiple die, and packaged in a packaging structure, such as 2.5D (dimension) or 3D packaging. , or other advanced packaging technologies. In one implementation, the above-mentioned AP211 and GPU212 are integrated in one die, and the RAM 213 is integrated in another die. The two dies are packaged in a package structure to obtain a faster inter-die data transmission rate. and higher data transmission bandwidth.

FIG. 3 is a schematic structural diagram of a ferroelectric memory 300 provided by an embodiment of the present application. The ferroelectric memory 300 may be RAM 213 as shown in Figure 2, which belongs to FeRAM. In one implementation, the ferroelectric memory 300 may also be a RAM provided outside the SOC. This application does not limit the position of the ferroelectric memory 300 in the device and its positional relationship with the SOC.

Continuing with FIG. 3 , the ferroelectric memory 300 includes a memory array 310 , a decoder 320 , a driver 330 , a timing controller 340 , a buffer 350 and an input/output driver 360 . The storage array 310 includes a plurality of storage units 400 arranged in an array, where each storage unit 400 can be used to store 1 bit or multiple bits of data. The memory array 310 also includes signal lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL. One or more of the above-mentioned word lines WL and bit lines BL are used to select the memory cells 400 to be read and written in the memory array by receiving the control level output by the control circuit, so as to change the memory cells 400 in the memory array. The polarization direction of the ferroelectric tunnel junction enables data reading and writing operations.

In the structure of the ferroelectric memory 300 shown in Figure 3, the decoder 320 is used to decode according to the received address to determine the memory unit 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby achieving access to the designated storage unit 400. The buffer 350 is used to cache the read data. For example, first-in first-out (FIFO) may be used for caching. The timing controller 340 is used to control the timing of the buffer 350 and control the driver 330 to drive the signal lines in the memory array 310 . The input and output driver 360 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that the data signals can be transmitted over long distances.

The above-mentioned memory array 310, decoder 320, driver 330, timing controller 340, buffer 350 and input/output driver 360 can be integrated into one chip, or can be integrated into multiple chips respectively.

In the FeRAM memory unit 400 shown in FIGS. 2 and 3 above, the structure of the ferroelectric tunnel junction may be as shown in FIG. 4 , including not only the stacked first electrode 41 and the second electrode 42 , but also the structure formed on the first electrode. 41 and the second electrode 42 between the ferroelectric barrier layer 43 . In addition, it also includes at least one layer of insulating barrier interlayer 44 stacked between adjacent ferroelectric barrier layers 43 or between the ferroelectric barrier layer 43 and the first electrode 41 .

In the embodiment of the present application, the first electrode 41 is a device used to input or derive current. The material of the first electrode 41 may be metal. For example, you can choose tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), ruthenium (Ru), molybdenum (Mo), Iridium (Ir), nickel (Ni), platinum (Pt), ruthenium oxide (RuO), iridium oxide (IrO), indium tin oxide (ITO), etc. The material of the first electrode 41 may be non-metal. For example, heavily P-type doped or heavily N-type doped silicon can be selected.

In order to obtain a ferroelectric tunnel junction with strong ferroelectricity, as a feasible implementation method, the first electrode 41 can be a pinched electrode. In the embodiment of the present application, an electrode whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold is called a pinched electrode. The difference threshold can be set according to requirements. For example, the difference threshold can be ±1*10 ^-6 /℃.

Holding the electrode, the hafnium oxide will expand and contract due to temperature changes during the annealing and crystallization process. Tensile stress is generated during the expansion and contraction of the holding electrode. The tensile stress helps the unit cell of hafnium oxide in the ferroelectric barrier layer to convert from symmetry to asymmetry. Moreover, the smaller the absolute value of the difference between the thermal expansion coefficient of the holding electrode and the thermal expansion coefficient of hafnium oxide, the more tensile stress generated during the expansion and contraction of the holding electrode is more conducive to the formation of an asymmetric hafnium oxide unit cell. Using pinched electrodes can obtain more asymmetric hafnium oxide unit cells; the more asymmetric hafnium oxide unit cells, the stronger the ferroelectricity of the ferroelectric barrier layer. Therefore, the ferroelectricity of the ferroelectric barrier layer is higher, correspondingly The ferroelectric tunnel junction has higher ferroelectricity.

Furthermore, in order to obtain a ferroelectric tunnel junction with good electrical conductivity, good mechanical properties, and suitable for micro-nano processing, in some feasible implementation methods, the holding electrode can be a ferroelectric tunnel junction with good electrical conductivity, good mechanical properties, and suitable for micro-nano processing. Titanium nitride (TiN) electrode, tungsten (W) electrode, and ruthenium dioxide (RuO ₂ ) electrode.

In the embodiment of the present application, the second electrode 42 is a device used to input or derive current. The second electrode 42 may be made of the same material as the first electrode 41 , or may be made of different materials. In order to obtain a ferroelectric tunnel junction with strong ferroelectricity, as a feasible implementation method, the second electrode 42 can be a pinched electrode.

In the embodiment of the present application, the ferroelectric barrier layer 43 is made of hafnium oxide-based material and has ferroelectricity. Compared with other ferroelectric materials, the thickness of hafnium oxide-based ferroelectric tunnel junctions can be reduced to ten nanometers or even sub-ten nanometers. In this way, high-density integration and even three-dimensional integration can be achieved, which has greater advantages in building ultra-high-density memory chips. Big advantage. In addition, the preparation process of hafnium oxide-based ferroelectric tunnel junctions can be well compatible with silicon-based semiconductor processes. capacitive, so that the ferroelectric tunnel junction can be produced using mature manufacturing processes without increasing manufacturing costs. Wherein, the hafnium oxide-based material at least includes hafnium oxide.

The unit cell of hafnium oxide itself is a symmetric unit cell and does not have ferroelectricity. In order to obtain ferroelectric hafnium oxide, as a feasible implementation method, doping elements can be added to hafnium oxide.

In the embodiment of the present application, the doping element can change the hafnium oxide unit cell from a symmetric unit cell to an asymmetric hafnium oxide unit cell, thereby making the hafnium oxide have ferroelectricity. The doping elements may be, but are not limited to, zirconium (Zr), yttrium (Y), aluminum (Al), silicon (Si), gadolinium, strontium (Sr), lanthanum (La), nitrogen (N), iron (Fe), Lutetium (Lu), praseodymium (Pr), germanium (Ge), scandium (Se), cerium (Ce), neodymium (Nd), magnesium (Mg), barium (Ba), indium (In), gallium (Ga), At least one of calcium (Ca) and carbon (C).

It is worth noting that different doping elements have different doping ratios. The rules followed by these doping ratios are: at this doping ratio, hafnium oxide can form ferroelectric hafnium oxide through annealing and crystallization. , wherein the doping ratio can be the mass ratio of hafnium oxide and doping elements, and the annealing crystallization can be a process of exposing the material containing hafnium oxide to high temperature for a long time, and then cooling it to obtain ferroelectric hafnium oxide.

In order to obtain ferroelectric hafnium oxide, as a feasible implementation method, a pinched electrode can be used to contact the hafnium oxide-based material. During the annealing and crystallization process, the expansion and contraction of the holding electrode will generate tensile stress, which helps to form hafnium oxide with an asymmetric unit cell.

Hafnium oxide requires annealing and crystallization, and its unit cell is converted from symmetry to asymmetry. During the annealing and crystallization process, hafnium oxide will produce a large number of grain boundaries. Since the atoms at the grain boundaries are irregularly arranged and the structure at the grain boundaries is sparse, the electrons at the grain boundaries have higher energy, and the electrons can easily pass through the grain boundaries. migrate. Therefore, ferroelectric tunnel junctions containing hafnium oxide have larger leakage currents.

In order to obtain a ferroelectric tunnel junction with lower leakage current. In the embodiment of the present application, at least one insulating barrier interlayer is stacked between adjacent ferroelectric barrier layers 43 or between at least one of the first electrode 41 and the second electrode 42 and the ferroelectric barrier layer 43 44.

In the embodiment of the present application, the insulating barrier intercalation layer 44 has a layered structure with a low relative dielectric constant and can hinder electron migration. Since the insulating barrier intercalation layer 44 is interposed between adjacent ferroelectric barrier layers 43 or between at least one of the first electrode 41 and the second electrode 42 and the ferroelectric barrier layer 43, it is called an intercalation layer. .

In the memory unit of the ferroelectric memory provided by the present application, the ferroelectric tunnel junction used to store charges not only includes a first electrode 41, a second electrode 42, and an iron layer stacked between the first electrode 41 and the second electrode 42. The electric barrier layer 43 also includes an insulating barrier interlayer 44 stacked between at least one of the first electrode 41 and the second electrode 42 and the ferroelectric barrier layer 43, or stacked between adjacent ferroelectric barriers. An insulating barrier intercalates 44 between layers 43 . When the ferroelectric tunnel junction is in a high configuration, although there are still a large number of grain boundaries inside the ferroelectric barrier layer 43 , electrons can easily migrate inside the ferroelectric barrier layer 43 . However, when electrons migrate between adjacent ferroelectric barrier layers 43, the electrons need to pass through the insulating barrier intercalation layer 44. The insulating barrier intercalation layer 44 can break the grain boundary between the adjacent ferroelectric barrier layers 43. continuity, weakening the migration of electrons between adjacent ferroelectric barrier layers 43; similarly, electrons migrate between the ferroelectric barrier layer 43 and at least one of the first electrode 41 and the second electrode 42. When When electrons need to pass through the insulating barrier intercalation layer 44, the insulating barrier intercalation layer 44 can weaken the migration of electrons; the migration of electrons is weakened, and accordingly the leakage current generated due to electron migration is reduced. Therefore, the results obtained in the embodiment of the present application are Ferroelectric memory has low leakage current.

In order to further reduce the leakage current of the ferroelectric tunnel junction, as a feasible implementation method, multiple layers of insulating barrier intercalation layers 44 can be stacked. However, if the number of layers of the insulating barrier intercalation layer 44 is large, the insulating barrier intercalation layer 44 and The total thickness of the ferroelectric barrier layer 43 increases, correspondingly increasing the volume of the ferroelectric tunnel junction, which is not conducive to high-density integration of the ferroelectric tunnel junction. Therefore, in some feasible implementations, the number of layers of the insulating barrier intercalation layer 44 is less than or equal to three.

In order to obtain a ferroelectric tunnel junction with better electrical conductivity, as a feasible implementation method, the distance between the first electrode 41 and the second electrode 42 is less than or equal to 5 nm.

The smaller the distance between the first electrode 41 and the second electrode 42 is, the smaller the thickness of the insulating barrier intercalation layer 44 and the ferroelectric barrier layer 43 stacked between the first electrode 41 and the second electrode 42 is. Correspondingly, the smaller the resistance for electrons to pass through the insulating barrier intercalation layer 44 and the ferroelectric barrier layer 43, the better the conductivity of the ferroelectric tunnel junction. In this implementation, the distance between the first electrode 41 and the second electrode 42 is less than or equal to 5 nm, the resistance of electrons passing through the insulating barrier intercalation layer 44 and the ferroelectric barrier layer 43 is small, and the conductivity of the corresponding ferroelectric tunnel junction is relatively small. high.

Generally, the greater the relative dielectric constant of the insulating material in the capacitor, the greater the integrated capacitance effect, and the more electrons gather on the two conductors of the capacitor. Specifically applied to the ferroelectric tunnel junction provided in the embodiment of the present application, the ferroelectric tunnel junction is equivalent to a capacitor, the first electrode 41 and the second electrode are equivalent to two conductors, and the insulation barrier intercalation layer 44 and the ferroelectric barrier layer 43 are equivalent The insulating material in the capacitor. Since the relative dielectric constant of the insulating barrier intercalation layer 44 is low, the ferroelectric tunnel junction has a low integrated capacitance effect, and fewer electrons accumulate in the first electrode 41 and the second electrode 42 , so the ferroelectric tunnel junction The energy consumption is lower.

In the embodiment of the present application, the current input to the ferroelectric tunnel junction is called FTJ current. The FTJ current will be consumed in the process of flowing through the ferroelectric tunnel junction, and eventually part of the current can pass through the ferroelectric tunnel junction. Among them, the current consumed inside the ferroelectric tunnel junction can be called parasitic current. The current that ultimately passes through the ferroelectric tunnel junction is called the read current. Read current = FTJ current - parasitic current. One reason for the parasitic current is the integrated capacitance effect of the ferroelectric tunnel junction, and the greater the integrated capacitance effect, the greater the parasitic current.

In the ferroelectric tunnel junction provided by the embodiment of the present application, there is an insulating barrier intercalation layer 44 between at least one of the first electrode 41 and the second electrode 42 and the ferroelectric barrier layer 43, or an adjacent ferroelectric barrier. There are insulating barrier interlayers 44 between the layers 43. The relative dielectric constant of the insulating barrier intercalation layer 44 is low, and the corresponding ferroelectric tunnel junction has a low integrated capacitance effect, so the ferroelectric tunnel junction has a small parasitic current. In the case of obtaining the same read current, the FTJ current of the ferroelectric tunnel junction is smaller. Since the FTJ current is positively related to the number of dipole flips in the ferroelectric barrier layer 43, when the same read current is obtained, the ferroelectric tunnel junction provided by the embodiment of the present application has a smaller number of dipole flips.

In the embodiment of the present application, the electric field (which may also be called voltage in this embodiment) applied to the ferroelectric tunnel junction may be called an operating voltage. The operating voltage will cause consumption when acting on the ferroelectric tunnel junction, and eventually part of the electric field is used to trigger the flipping of the dipole in the ferroelectric barrier layer 43 . Among them, the electric field consumed inside the ferroelectric tunnel junction is called parasitic voltage, and the electric field acting on the ferroelectric barrier layer 43 to trigger the flipping of the dipole is called trigger voltage. Trigger voltage = operating voltage - parasitic voltage. One reason for the generation of parasitic voltage is the integrated capacitance effect of the ferroelectric tunnel junction, and the greater the integrated capacitance effect, the greater the parasitic voltage.

In the ferroelectric tunnel junction provided by the embodiment of the present application, there is an insulating barrier intercalation layer 44 between at least one of the first electrode 41 and the second electrode 42 and the ferroelectric barrier layer 43, or an adjacent ferroelectric barrier. There are insulating barrier interlayers 44 between the layers 43. The relative dielectric constant of the insulating barrier intercalation layer 44 is low, and the corresponding ferroelectric tunnel junction has a low integrated capacitance effect, so the ferroelectric tunnel junction has a small parasitic voltage. In the case of obtaining the same trigger voltage, the operating voltage of the ferroelectric tunnel junction is smaller.

Further, during the process of reading and writing data in the ferroelectric memory, by adjusting the operations applied to the ferroelectric tunnel junction The voltage is used to change the trigger voltage, and finally the trigger voltage can trigger the dipole flip of the ferroelectric barrier layer 43, thereby causing the potential barrier of the ferroelectric barrier layer 43 to switch between a high value and a low value. Since the ferroelectric tunnel junction provided by the embodiments of the present application has a smaller operating voltage under the same trigger voltage, the operating voltage can be adjusted in a shorter time under the same voltage adjustment amplitude. Therefore, ferroelectric memory has a high read and write rate.

Furthermore, during the annealing and crystallization process, oxygen vacancies will be formed in the ferroelectric barrier layer 43. The formation of oxygen vacancies reduces the stability of the ferroelectric barrier layer 43 to a certain extent, thereby affecting the stability of the ferroelectric tunnel junction. In the ferroelectric tunnel junction provided by the embodiment of the present application, there is an insulating barrier intercalation layer 44 between at least one of the first electrode 41 and the second electrode 42 and the ferroelectric barrier layer 43, or an adjacent ferroelectric barrier layer. There is an insulating barrier interlayer 44 between 43. The insulating barrier intercalation layer 44 can hinder the migration of oxygen in the ferroelectric barrier layer 43, reduce the number of oxygen vacancies in the ferroelectric barrier layer 43 to a certain extent, ensure the stability of the ferroelectric barrier layer 43, and thereby ensure the ferroelectric tunnel junction. The stability of the ferroelectric tunnel junction is correspondingly extended, making the ferroelectric tunnel junction more durable and reliable.

Normally, the wider the band gap of a substance, the more difficult it is for electrons of the substance to jump from one energy level to a higher energy level, and accordingly, the harder it is for the substance to be broken down.

In order to improve the penetration resistance of the ferroelectric tunnel junction, in some feasible implementations, the insulating barrier interlayer 44 may be aluminum oxide. Since alumina has a wide band gap, it is more difficult for electrons in alumina to transition from one energy level to a higher energy level, and the corresponding alumina is more difficult to breakdown, including the ferroelectric tunnel junction of the alumina. It is more difficult to penetrate. Furthermore, the aluminum element in alumina is a doping element, which can improve the ferroelectricity of the ferroelectric tunnel junction to a certain extent.

In order to improve the breakdown resistance of the ferroelectric tunnel junction, in some feasible implementations, the insulating barrier interlayer 44 may be silicon oxide. Since silicon oxide has a wide band gap, it is more difficult for electrons in silicon oxide to transition from one energy level to a higher energy level. The corresponding silicon oxide is more difficult to breakdown, including the ferroelectric tunnel junction of the silicon oxide. It is more difficult to penetrate. Furthermore, the silicon element in silicon oxide is a doping element, which can improve the ferroelectricity of the ferroelectric tunnel junction to a certain extent.

In the embodiment of the present application, the insulating barrier interlayer 44 may be stacked between adjacent ferroelectric barrier layers 43 , and may be stacked between at least one of the first electrode 41 and the second electrode 42 and the ferroelectric barrier layer 43 . The specific position of the insulation barrier intercalation layer 44 is determined by the properties of the first electrode 41 and the properties of the second electrode 42 . The position of the insulating barrier intercalation layer 44 is explained below according to the situation:

In the embodiment of the present application, an electrode whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is greater than a preset threshold can be called a non-hostage electrode.

In some feasible implementations, the first electrode 41 is a non-pinch electrode, the second electrode 42 is a non-pinch electrode, and the positions of the insulating barrier intercalation layer 44 and the ferroelectric barrier layer 43 are not specifically limited, that is, edge barriers. The intercalation layer 44 may be stacked between adjacent ferroelectric barrier layers 43 , and/or between the ferroelectric barrier layer 43 and the first electrode 41 , and/or between the ferroelectric barrier layer 43 and the second electrode 42 .

The position of the insulation barrier intercalation layer will be explained below with reference to the specific drawings;

Please continue to refer to Figure 4. The ferroelectric tunnel junction provided in Figure 4 includes: a first electrode 41, a second electrode 42, a ferroelectric barrier layer 43 stacked between the first electrode 41 and the second electrode 42, and a ferroelectric barrier layer 43 stacked between the second electrode 41 and the second electrode 42. 42 and an insulating barrier intercalation layer 44 between the ferroelectric barrier layer 43.

Figure 5-1 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment; in this embodiment, the first electrode 41 is a non-pinch electrode, and the second electrode 42 is a non-pinch electrode. The ferroelectric tunnel junction provided in Figure 5-1 includes: a first electrode 41, The second electrode 42, the ferroelectric barrier layers 43a and 43b stacked between the first electrode 41 and the second electrode 42, and the insulating barrier intercalation layer 44 stacked between the ferroelectric barrier layer 43a and the ferroelectric barrier layer 43b.

Figure 5-2 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment; in this embodiment, the first electrode 41 is a non-pinch electrode, and the second electrode 42 is a non-pinch electrode. The ferroelectric tunnel junction provided in Figure 5-2 includes: a first electrode 41, a second electrode 42, ferroelectric barrier layers 43a and 43b stacked between the first electrode 41 and the second electrode 42, and a ferroelectric barrier layer 43a stacked between the first electrode 41 and the second electrode 42. and the first electrode 41, and the insulating barrier interlayer 44b stacked between the ferroelectric barrier layer 43a and the ferroelectric barrier layer 43b.

Figure 5-3 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment; in this embodiment, the first electrode 41 is a non-pinch electrode, and the second electrode 42 is a non-pinch electrode. The ferroelectric tunnel junction provided in Figure 5-3 includes: a first electrode 41, a second electrode 42, a ferroelectric barrier layer 43 stacked between the first electrode 41 and the second electrode 42; an insulating barrier interlayer 44a between one electrode 41, and an insulating barrier interlayer 44b stacked between the ferroelectric barrier layer 43 and the second electrode 42.

It is worth noting that Figure 5-1, Figure 5-2, and Figure 5-3 are only exemplary introductions of several structures of ferroelectric tunnel junctions in which both the first electrode 41 and the second electrode are non-pinch electrodes. The above structures It does not constitute a limitation.

In some feasible implementations, if the first electrode 41 is a pinch electrode, in order to obtain a ferroelectric barrier layer with higher ferroelectricity, the ferroelectric barrier layer 43 can be in contact with the first electrode 41 .

The position of the insulating barrier intercalation layer 44 will be described below with reference to specific drawings;

Figure 6-1 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment; in this embodiment, the first electrode 41 is a pinched electrode, and the second electrode 42 is a non-pinched electrode. The ferroelectric tunnel junction provided in Figure 6-1 includes: a first electrode 41, a second electrode 42, a ferroelectric barrier layer 43 stacked between the first electrode 41 and the second electrode 42, the ferroelectric barrier layer 43 and the first electrode 41 contacts and stacks the insulating barrier intercalation layer 44 between the first electrode 41 and the ferroelectric barrier layer 43 .

Figure 6-2 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment; in this embodiment, the first electrode 41 is a pinched electrode, and the second electrode 42 is a non- pinched electrode. The ferroelectric tunnel junction provided in Figure 6-2 includes: a first electrode 41, a second electrode 42, ferroelectric barrier layers 43a and 43b stacked between the first electrode 41 and the second electrode 42, a ferroelectric barrier layer 43a and a third electrode. An electrode 41 contacts the insulating barrier intercalation layer 44 stacked between the ferroelectric barrier layer 43a and the ferroelectric barrier layer 43b.

Figure 6-3 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment; in this embodiment, the first electrode 41 is a pinched electrode, and the second electrode 42 is a non-pinched electrode. The ferroelectric tunnel junction provided in Figure 6-3 includes: a first electrode 41, a second electrode 42, ferroelectric barrier layers 43a and 43b stacked between the first electrode 41 and the second electrode 42, the ferroelectric barrier layer 43a and the An electrode 41 contacts; an insulating barrier intercalation layer 44a stacked between the ferroelectric barrier layer 43a and the ferroelectric barrier layer 43b, and an insulating barrier intercalation layer 44b stacked between the ferroelectric barrier layer 43b and the second electrode 42 .

It is worth noting that Figure 6-1, Figure 6-2, and Figure 6-3 are only exemplary introductions of several ferroelectric tunnel junction structures in which the first electrode is a pinched electrode and the second electrode 42 is a non-pinched electrode. The above structure does not constitute a limitation.

Since the tensile stress generated during the annealing and crystallization process of the holding electrode can act on the hafnium oxide in the ferroelectric barrier layer 43 in contact with it, the hafnium oxide unit cell changes from symmetry to asymmetry and becomes ferroelectric. In this embodiment, the ferroelectric barrier layer 43 is in contact with the clamping electrode. The tensile stress generated by the clamping electrode during the annealing and crystallization process can convert the symmetry of the hafnium oxide unit cell into asymmetry. Furthermore, more asymmetric hafnium oxide unit cells are obtained; the more asymmetric hafnium oxide unit cells, the stronger the ferroelectricity of the ferroelectric barrier layer 43. Therefore, the ferroelectricity of the ferroelectric barrier layer 43 is relatively high. The ferroelectric tunnel junction has higher ferroelectricity.

In order to further improve the ferroelectricity of the ferroelectric tunnel junction, as a feasible implementation method, the ferroelectric barrier layer 43 It includes a first ferroelectric barrier layer 43a and a second ferroelectric barrier layer 43a; there is an insulating barrier intercalation layer 44 between the first ferroelectric barrier layer 43a and the second ferroelectric barrier layer 43b. The first electrode 41 is a holding electrode, and the first ferroelectric barrier layer 43a is in contact with the first electrode 41; the thickness of the first ferroelectric barrier layer 43a is greater than the thickness of the second ferroelectric barrier layer 43b.

Figure 7-1 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment; in this embodiment, the first electrode 41 is a pinched electrode, and the second electrode 42 is a non- pinched electrode. The ferroelectric tunnel junction provided in Figure 7-1 includes: a first electrode 41, a second electrode 42, and a first ferroelectric barrier layer 43a and a second ferroelectric barrier layer 43b stacked between the first electrode 41 and the second electrode 42. , the first ferroelectric barrier layer 43a is in contact with the first electrode 41, the thickness of the first ferroelectric barrier layer 43a is greater than the thickness of the second ferroelectric barrier layer 43b, and the first ferroelectric barrier layer 43a and the second ferroelectric barrier are stacked An insulating barrier intercalates 44 between layers 43b.

Figure 7-2 is a schematic diagram of a ferroelectric tunnel junction provided by a feasible embodiment; in this embodiment, the first electrode 41 is a pinched electrode, and the second electrode 42 is a non- pinched electrode. The ferroelectric tunnel junction provided in Figure 7-2 includes: a first electrode 41, a second electrode 42, a first ferroelectric barrier layer 43a and a second ferroelectric barrier layer 43b stacked between the first electrode 41 and the second electrode 42. and 43c, the first ferroelectric barrier layer 43a is in contact with the first electrode 41, the thickness of the first ferroelectric barrier layer 43a is greater than the thickness of the second ferroelectric barrier layer 43b, the thickness of the first ferroelectric barrier layer 43a is greater than the thickness of the second ferroelectric barrier layer 43c. The thickness of the electric barrier layer 43c; the insulating barrier intercalation layer 44a stacked between the first ferroelectric barrier layer 43a and the second ferroelectric barrier layer 43b; the second ferroelectric barrier layer 43b and the second ferroelectric barrier layer stacked 43c between the insulating barrier intercalation 44b.

It is worth noting that Figure 7-1 and Figure 7-2 are only exemplary introductions of several ferroelectric tunnel junction structures in which the thickness of the first ferroelectric barrier layer is greater than the thickness of the second ferroelectric barrier layer. The above structures do not constitute a limitation. .

In this embodiment, the thickness of the first ferroelectric barrier layer 43a is greater than the thickness of the second ferroelectric barrier layer 43b, and the first ferroelectric barrier layer 43a contains more hafnium oxide than the second ferroelectric barrier layer 43b. Hafnium; the holding electrode is in contact with the first ferroelectric barrier layer 43a containing more hafnium oxide; during the annealing and crystallization process, the tensile stress generated by the holding electrode can act on more hafnium oxide, so that the unit cell of hafnium oxide changes from symmetry to The asymmetry is converted into asymmetry, so more asymmetric hafnium oxide unit cells can be obtained. The more asymmetric hafnium oxide unit cells, the stronger the ferroelectricity of the ferroelectric barrier layer. Therefore, the ferroelectricity of the ferroelectric barrier layer is higher, and the corresponding ferroelectric tunnel junction has higher ferroelectricity.

The second aspect of the embodiment of the present application provides a method for forming a ferroelectric memory. The forming method provided by the embodiment of the present application will be described below with reference to specific drawings. Figure 8 is a flow chart of a ferroelectric memory forming method provided by a feasible embodiment. The forming method includes S81 to S84:

S81 forms a first electrode on the substrate;

In the embodiment of the present application, the substrate is a structure used to support the ferroelectric tunnel junction, which may be but is not limited to a silicon wafer.

As a feasible implementation method, the substrate can be pre-treated. The pre-treatment process can be: using acetone, water, and alcohol to clean and process the polished silicon wafer to provide a clean and smooth surface.

In this embodiment of the present application, the material of the first electrode 41 may be metal. For example, you can choose tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), ruthenium (Ru), molybdenum (Mo), Iridium (Ir), nickel (Ni), platinum (Pt), ruthenium oxide (RuO), iridium oxide (IrO), indium tin oxide (ITO), etc. The material of the first electrode 41 may be non-metal. For example, heavily P-type doped or heavily N-type doped silicon can be selected.

In order to obtain a ferroelectric tunnel junction with strong ferroelectricity, as a feasible implementation method, the first electrode 41 can be formed of a host material whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold. In order to obtain a ferroelectric tunnel junction with good electrical conductivity, good mechanical properties, and suitable for micro-nano processing technology, in some feasible practices In the current method, the holding material can be at least one of titanium nitride (TiN), tungsten (W), and ruthenium dioxide (RuO2) that has good electrical conductivity, good mechanical properties, and is suitable for micro-nano processing technology.

There are many ways to form the first electrode 41 . For example: in some feasible implementation methods, physical vapor deposition (PVD) can be used; in some feasible implementation methods, chemical vapor deposition (CVD) can be used. In order to achieve a better combination between the first electrode 41 and the substrate, in some feasible implementations, magnetron sputtering may be used to form the first electrode 41 .

It is worth noting that the embodiment of the present application is only an exemplary introduction to several implementation methods for forming the first electrode 41. In actual applications, the implementation methods for forming the first electrode 41 may be but are not limited to the above methods. , the applicant does not make too many restrictions here.

S82 forms at least one layer of hafnium oxide-based material and at least one layer of insulating barrier intercalation layer on the side of the first electrode away from the substrate.

When the first electrode 41 is formed of a host material whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold, the hafnium oxide-based material is stacked on the first electrode 41 so that during the annealing and crystallization process, the first The tensile stress generated by an electrode can act on the hafnium oxide-based material, causing the hafnium oxide of the hafnium oxide-based material to form an asymmetric unit cell and become ferroelectric.

In the embodiment of the present application, the hafnium oxide-based material at least includes hafnium oxide.

In order to prepare a ferroelectric tunnel junction with higher ferroelectricity, in some feasible embodiments, the hafnium oxide-based material may include hafnium oxide and doping elements. For specific doping elements, please refer to the above-mentioned embodiments, and the applicant will not describe them in detail here.

Forming hafnium oxide-based materials can be achieved in a variety of ways. For example: in some feasible implementation methods, physical vapor deposition can be used to form hafnium oxide-based materials; in some feasible implementation methods, chemical vapor deposition can be used to form hafnium oxide-based materials. In order to control the thickness of the hafnium oxide-based material, in some feasible implementation methods, atomic layer deposition (ALD) can be used to form the hafnium oxide-based material.

It is worth noting that the embodiments of this application are only exemplary to introduce several formation methods of hafnium oxide-based materials. In the process of actual application, the formation method of the hafnium oxide-based material may be but not limited to the above-mentioned methods, and the applicant will not make too many limitations here.

There are many ways to form the insulating barrier intercalation layer 44 . For example: in some feasible implementations, physical vapor deposition may be used to form the insulating barrier interlayer 44; in some feasible implementations, chemical vapor deposition may be used to form the insulating barrier interlayer 44. In order to achieve a better combination between the insulating barrier interlayer 44 and the hafnium oxide-based material, in some feasible implementations, magnetron sputtering can be used to form the insulating barrier interlayer 44 .

It is worth noting that the embodiments of the present application are only exemplary to introduce several ways of forming the insulating barrier intercalation layer 44 . In the process of actual application, the formation method of the insulation barrier interlayer 44 may be but not limited to the above-mentioned methods, and the applicant will not make too many limitations here.

S83 anneals the first electrode, the hafnium oxide-based material and the insulating barrier intercalation layer, so that the hafnium oxide-based material is converted into a ferroelectric barrier layer.

The hafnium oxide-based material crystallizes through annealing and crystallization to form an asymmetric unit cell. The positive and negative charge centers in the asymmetric hafnium oxide unit cell do not overlap, generating an electric dipole to form spontaneous polarization. Under the action of an external electric field, the potential barrier of electrons in hafnium oxide changes between high and low values through polarization reversal. Switching between them shows ferroelectricity.

S84 forms the second electrode.

In the embodiment of the present application, the material of the second electrode 42 may be metal or non-metal. In order to obtain a ferroelectric tunnel junction with strong ferroelectricity, as a feasible implementation method, the second electrode 42 can be formed of a host material whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold. In the embodiment of the present application, the material of the second electrode 42 may be the same as the material of the first electrode 41 , or may be different from the material of the first electrode 41 , and the applicant will not make too many limitations here.

The formation method of the second electrode 42 may be, but is not limited to, PVD, CVD, magnetron sputtering, etc. In the embodiment of the present application, the second electrode 42 may be formed in the same manner as the first electrode 41 or may be formed in a different manner from the first electrode 41 , and the applicant will not make too many limitations here.

In the method for forming a ferroelectric memory given in the embodiment of the present application, not only the first electrode 41, the second electrode 42, and the ferroelectric barrier layer 43 stacked between the first electrode 41 and the second electrode 42 are produced, but also An insulating barrier intercalation layer 44 stacked between at least one of the first electrode 41 and the second electrode 42 and the ferroelectric barrier layer 43 is produced, or an insulating barrier interlayer 44 stacked between adjacent ferroelectric barrier layers 43 is produced. Barrier intercalation 44. Since the insulating barrier interlayer 44 with a lower dielectric constant is stacked, the prepared ferroelectric memory has lower leakage current, higher switching ratio, lower energy consumption, and a smaller number of dipoles. sub-flip, lower operating voltage, better stability, and longer service life.

Figure 9 is a flow chart of a ferroelectric memory forming method provided by another feasible embodiment. The forming method includes S91 to S92:

S91 forms a first electrode, at least one layer of hafnium oxide-based material, at least one layer of insulating barrier intercalation layer and a second electrode on the substrate;

Among them, the materials and formation methods of the first electrode 41, the hafnium oxide-based material, the insulation barrier interlayer 44 and the second electrode 42 can be referred to the above embodiments, and the applicant will not elaborate here.

S92 anneals the first electrode, the second electrode, the hafnium oxide-based material and the insulating barrier intercalation, and the hafnium oxide-based material is converted into a ferroelectric barrier layer. Wherein, the insulating barrier interlayer 44 can be stacked between adjacent ferroelectric barrier layers 43, can be stacked between the ferroelectric barrier layer 43 and the first electrode 41, and can be stacked between the ferroelectric barrier layer 43 and the second electrode. between 42.

In order to further improve the performance of the ferroelectric tunnel junction, as a feasible implementation method, embodiments of the present application also provide a method for forming a ferroelectric memory. For details, please refer to Figure 10. Figure 10 is a feasible embodiment. A method for forming a ferroelectric memory, the method comprising:

S101 forms a first electrode, at least one layer of hafnium oxide-based material, at least one layer of insulating barrier intercalation layer and an intermediate electrode on the substrate;

In this embodiment, the middle electrode is formed of a material whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold. The middle electrode is in contact with the hafnium oxide-based material. The intermediate electrode is produced during the annealing and crystallization process. Tensile stress can act on the hafnium oxide in the hafnium oxide-based material in contact with it, causing the hafnium oxide unit cell to convert from symmetry to asymmetry and become ferroelectric. Therefore, in this embodiment, the intermediate electrode is formed before the step of annealing and crystallization.

S102 anneals the first electrode, the middle electrode, the hafnium oxide-based material and the insulating barrier intercalation, and the hafnium oxide-based material is converted into a ferroelectric barrier layer.

The process of annealing and crystallization can be referred to the above embodiment.

S103 removes the middle electrode;

Removal of the middle electrode can be accomplished in several ways. In some feasible implementation methods, chemical etching can be used to remove the middle electrode. Chemical etching can be but is not limited to acid etching. In some feasible implementation methods, physical etching can be used to remove the middle electrode. Physical etching can be It is but is not limited to ion beam bombardment.

It is worth noting that the embodiments of this application are only exemplary to introduce several implementation methods of removing the middle electrode. In the process of actual application, the method of removing the middle electrode may be, but is not limited to, the above methods, and the applicant will not make too many limitations here.

S104 forms a second electrode, and the specific performance of the second electrode is better than that of the middle electrode.

In this embodiment, the specific performance may be, but is not limited to, one or more of hardness, electrical conductivity, and thermal conductivity. In the actual preparation process, the corresponding preparation material of the second electrode can be selected according to the requirements. For example, in some feasible embodiments, in order to prepare a ferroelectric tunnel junction with both high ferroelectricity and high conductivity, a material with high ferroelectricity and high conductivity can be used. The second electrode is prepared from Pt with higher conductivity.

The performance of the ferroelectric tunnel junction provided by the embodiment of the present application will be further described below with reference to specific drawings. The first electrode 41 of the ferroelectric tunnel junction provided by the embodiment of the present application is titanium nitride, and the ferroelectric raw material is zirconium doped oxide. Hafnium, the insulating barrier intercalation layer 44 is silicon oxide, and the first electrode 41 is a platinum electrode.

Figure 11 is a hysteresis curve of the resistance of the doped hafnium oxide-based ferroelectric tunnel junction changing with the applied pulse voltage when the pulse voltage pulse width is td=600ps, 1ns, and 10ns for the ferroelectric tunnel junction provided by the embodiment of the present invention; voltage The application amplitude is 0.2V. After each application of a single pulse voltage, switch to the resistance reading circuit and the reading voltage is 10mV. It can be seen that with the gradual increase of the forward pulse voltage, the ferroelectric tunnel junction The resistance shows a gradual increase and the switching process is relatively slow, which indicates that there are multiple resistance states between the low resistance state and the high resistance state of the ferroelectric tunnel junction, which has the potential for high-density storage.

Figure 12 is a repetitive characteristic diagram of two distinguishable resistance state transitions obtained by repeatedly applying different pulse voltages to the ferroelectric tunnel junction when the pulse voltage pulse width is td=10ns; the applied voltage pulse amplitudes are +4V and -3.5 V, the method of applying voltage is to apply a +4V amplitude, 10ns pulse width voltage pulse, switch the circuit to the resistance reading circuit, use the amplitude 10mV voltage to read the resistance, switch the circuit to the pulse writing circuit, apply -3.5V amplitude , a voltage pulse with a pulse width of 10ns, switches the circuit to the reading circuit, and uses a voltage with an amplitude of 10mV to read the resistor. This is a cycle, and then the above process is cycled to obtain the graph. It can be seen that the resistance state of the device is stable during reciprocating flipping, which proves the reliability of the ferroelectric tunnel junction. In addition, by measuring the current density when switching between different resistance states of the ferroelectric tunnel junction, the current density The maximum value is 2×10 ⁴ A/cm ² , which meets the current density and energy consumption requirements for practical application in large-scale integration.

Figure 13 is a retention characteristic diagram of the resistance state of the ferroelectric tunnel junction provided by a feasible embodiment; after a single write operation, two different resistances (high configuration and low resistance state) of the ferroelectric tunnel junction are respectively status was tested. The test process is: apply a large enough write electric pulse to the ferroelectric tunnel junction, switch the circuit to the resistance reading loop, use an amplitude of 10mV voltage to read the resistance, disconnect the overall circuit related to the device, and turn on the reading after 10 seconds. Circuit, use a voltage with an amplitude of 10mV to read the resistance, and cycle the above operation process. The resistance of the ferroelectric tunnel junction did not change significantly within 10,000 seconds, proving its non-volatile nature and ability to maintain its performance for a long time.

Figure 14 is a DC volt-ampere characteristic diagram of ferroelectric tunnel junctions with and without silicon oxide; silicon oxide is located between the zirconium-doped hafnium oxide ferroelectric barrier layer 43 and the second electrode (platinum electrode), with a thickness of 0.6 nm. The thickness of the zirconium-doped hafnium oxide layer is 2 nm. Due to the problem of a large number of grain boundaries formed by the annealing crystallization of zirconium-doped hafnium oxide, it can be seen that the leakage of the non-intercalated ferroelectric tunnel junction is very large. After the introduction of silicon oxide, the leakage current is significantly reduced, and the on-off ratio is also improved. An obvious improvement.

One or more ferroelectric tunnel junctions, steps, features and/or functions illustrated in the above embodiments may be rearranged and/or combined into a single component, step, feature or function, or may be implemented in several components, steps or functions. Functioning. Additional elements, components, steps, and/or functions may be added without departing from embodiments of the present application. In some implementations, the ferroelectric tunnel junctions and corresponding descriptions provided by the above embodiments may be used to fabricate, create, provide, and/or produce integrated devices. In some implementations, integrated devices may include die packages, packaging substrates, integrated circuits, wafers, semiconductor devices, and/or interposers.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior or advantageous over other aspects of the embodiments of the application.

It should also be noted that these embodiments may be described as processes depicted as flowcharts, flow diagrams, schematic diagrams, or block diagrams. Although a flowchart may describe operations as a sequential process, many of these operations can be performed in parallel or concurrently. Additionally, the order of these operations can be rearranged. A process terminates when its operation is complete.

Various aspects of the embodiments of the present application described herein may be implemented in different systems without departing from the embodiments of the present application. It should be noted that the above aspects of the embodiments of the present application are only examples and should not be construed as limiting the embodiments of the present application. The description of various aspects of the embodiments of the present application is intended to be illustrative and not to limit the scope of the appended claims. Thus, the teachings of the present invention are readily applicable to other types of devices, and many alternatives, modifications and variations will be apparent to those skilled in the art.

Claims

A ferroelectric memory, characterized by including:

substrate;

a plurality of memory cells formed on the substrate, each of the memory cells including a ferroelectric tunnel junction;

Wherein, the ferroelectric tunnel junction includes:

first electrode;

At least one ferroelectric barrier layer, the ferroelectric barrier layer comprising a hafnium oxide-based material having ferroelectricity;

a second electrode, the at least one ferroelectric barrier layer stacked between the first electrode and the second electrode;

At least one insulating barrier interlayer is provided between at least one of the first electrode and the second electrode and the ferroelectric barrier layer, or between the adjacent The insulating barrier interlayer is provided between the ferroelectric barrier layers.
The ferroelectric memory of claim 1, wherein at least one of the first electrode and the second electrode is a pinch electrode, the ferroelectric barrier layer is in contact with the pinch electrode, and the ferroelectric barrier layer is in contact with the pinch electrode. The absolute value of the difference between the thermal expansion coefficient of the holding electrode and the thermal expansion coefficient of hafnium oxide is less than the preset threshold.
The ferroelectric memory according to claim 1 or 2, characterized in that the hafnium oxide-based material includes hafnium oxide and doping elements, and the doping elements are such that the unit cell of the hafnium oxide is converted from symmetry to asymmetry. An element with ferroelectric properties.
The ferroelectric memory according to claim 3, wherein the doping elements include: zirconium, yttrium, aluminum, silicon, gadolinium, strontium, lanthanum, nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, At least one of neodymium, magnesium, barium, indium, gallium, calcium, and carbon.
The ferroelectric memory according to claim 2, characterized in that:

The ferroelectric barrier layer includes a first ferroelectric barrier layer and a second ferroelectric barrier layer, with the insulating barrier intercalation layer between the first ferroelectric barrier layer and the second ferroelectric barrier layer;

The first electrode is the holding electrode;

The first ferroelectric barrier layer is in contact with the first electrode, and the thickness of the first ferroelectric barrier layer is greater than the thickness of the second ferroelectric barrier layer along the stacking direction.
The ferroelectric memory according to any one of claims 1 to 5, wherein the distance between the first electrode and the second electrode along the stacking direction is less than or equal to 5 nm.
The ferroelectric memory according to any one of claims 1 to 6, wherein the insulating barrier interlayer includes at least one of silicon oxide and aluminum oxide.
The ferroelectric memory according to any one of claims 1 to 7, characterized in that the number of layers of the insulation barrier intercalation layer is less than or equal to 3.
A method of forming a ferroelectric memory, characterized by including:

forming a first electrode on the substrate;

Form at least one ferroelectric barrier layer and at least one insulating barrier intercalation layer on a side of the first electrode away from the substrate, where the ferroelectric barrier layer includes a hafnium oxide-based material with ferroelectricity;

forming a second electrode such that the first electrode, the second electrode, the ferroelectric barrier layer and the insulating barrier intercalation layer form a ferroelectric tunnel junction of the memory cell;

Wherein, the ferroelectric barrier layer is formed between the first electrode and the second electrode, and the first electrode and the insulating barrier intercalation layer is provided between at least one of the second electrodes and the ferroelectric barrier layer, or the insulating barrier intercalation layer is provided between adjacent ferroelectric barrier layers. .
The forming method according to claim 9, wherein forming at least one of the first electrode and the second electrode includes:

It is formed by using a material whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold, so that the formed electrode is a clamped electrode.
The formation method according to claim 10, wherein forming the ferroelectric barrier layer includes:

forming at least one layer of hafnium oxide-based material;

The hafnium oxide-based material is annealed and crystallized to form the ferroelectric barrier layer.
The forming method of claim 11, wherein the second electrode is formed after the step of forming at least one layer of hafnium oxide-based material, and the second electrode is formed by a thermal expansion coefficient and a thermal expansion coefficient of the hafnium oxide. Materials whose absolute value of the difference is smaller than the difference threshold are formed;

After the step of forming the second electrode, annealing and crystallizing the hafnium oxide-based material to form the ferroelectric barrier layer;

After the step of forming at least one layer of hafnium oxide-based material, and before annealing and crystallizing the hafnium oxide-based material, the second electrode is formed, and the second electrode is formed by a thermal expansion coefficient of the hafnium oxide thermal expansion coefficient. Materials whose absolute value of difference is less than the difference threshold are formed.
The formation method according to claim 11, wherein the second electrode is formed after the step of annealing and crystallizing the hafnium oxide-based material to form the ferroelectric barrier layer.
The formation method according to claim 11, characterized in that, after the step of forming at least one layer of hafnium oxide-based material, an intermediate electrode is formed, the intermediate electrode is in contact with the hafnium oxide-based material, and the intermediate electrode is made of The absolute value of the difference between the thermal expansion coefficient and the hafnium oxide thermal expansion coefficient is less than the difference threshold;

After the step of forming the intermediate electrode, annealing and crystallizing the hafnium oxide-based material to form the ferroelectric barrier layer;

Remove the middle electrode;

The second electrode is formed.
An electronic device, characterized by including:

processor; and

The ferroelectric memory according to any one of claims 1 to 8, and the ferroelectric memory produced by the method for forming a ferroelectric memory according to any one of claims 9 to 14;

Wherein, the processor and the ferroelectric memory are electrically connected.