WO2023220962A1

WO2023220962A1 - Ferroelectric field effect transistor, ferroelectric random-access memory, and manufacturing method

Info

Publication number: WO2023220962A1
Application number: PCT/CN2022/093530
Authority: WO
Inventors: 李秀妍; 钟舒曼; 刘川川; 马超; 秦青; 周雪; 焦慧芳
Original assignee: 华为技术有限公司
Priority date: 2022-05-18
Filing date: 2022-05-18
Publication date: 2023-11-23

Abstract

The present application provides a ferroelectric field effect transistor, a ferroelectric random-access memory, and a manufacturing method. The ferroelectric field effect transistor comprises a silicon-based substrate, a semiconductor layer, a ferroelectric layer, and a metal gate; the semiconductor layer is provided between the silicon-based substrate and the ferroelectric layer; the material of the silicon-based substrate is different from that of the semiconductor layer; and the semiconductor layer can moderate the difference in lattice parameters and thermal expansion coefficients of the silicon-based substrate and the ferroelectric layer, such that the ferroelectric field effect transistor can achieve higher retention performance.

Description

Ferroelectric field effect transistor, ferroelectric memory and manufacturing method

Technical field

This application relates to the field of semiconductors, specifically to a ferroelectric field effect transistor, a ferroelectric memory and a manufacturing method.

Background technique

Ferroelectric random access memory (FeRAM) using ferroelectric-gate field effect transistor (FeFET) has excellent erasing and writing capabilities and low operating voltage, and has attracted great attention in the field of non-volatile memory devices. received widespread attention. FeFET uses the flip of the ferroelectric polarization of the ferroelectric layer to control the switching of channel current. However, during the manufacturing process, a layer of oxide such as silicon dioxide is formed between the ferroelectric layer and the silicon-based substrate, resulting in poor long-term retention performance of FeFET.

Currently, in order to improve the retention performance of silicon-based FeFET, a metal electrode layer made of metal can be prepared between the ferroelectric layer and the substrate. However, the presence of the metal electrode layer will increase the difficulty of manufacturing the device and increase the risk of gate leakage.

Contents of the invention

This application provides a ferroelectric field effect transistor, a ferroelectric memory and a manufacturing method, which can achieve high retention performance.

In a first aspect, a ferroelectric field effect transistor is provided. The ferroelectric field effect transistor includes a silicon-based substrate, a semiconductor layer, a ferroelectric layer, and a metal gate electrode. The semiconductor layer is disposed on the silicon-based substrate and the metal gate electrode. Between the ferroelectric layer, the material of the silicon-based substrate and the semiconductor layer are different.

Based on this technical solution, by arranging a semiconductor layer between the silicon-based substrate and the ferroelectric layer, the differences in the lattice parameters and thermal expansion coefficients of the silicon-based substrate and the ferroelectric layer can be alleviated, the mutual diffusion of atoms can be reduced, and the ferroelectric field can be reduced. Effect transistors have longer retention capabilities for data, that is, they can achieve higher retention performance.

And compared with inserting a metal electrode layer between the silicon-based substrate and the ferroelectric layer, since the semiconductor material does not have as high conductivity as the metal conductor, it can reduce the risk of leakage when the operating voltage or current stress is applied to the metal gate electrode. . In addition, the preparation process of semiconductor materials is relatively simple, and the manufacturing difficulty of the ferroelectric field effect transistor proposed in this application is relatively low.

In conjunction with the first aspect, in some implementations of the first aspect, the semiconductor layer and the ferroelectric layer are in direct contact.

Based on this technical solution, the semiconductor layer and the ferroelectric layer are in direct contact, and the interface is clean, which reduces the adverse effects that easily appear on the interface, increases the life of the ferroelectric field effect transistor, and achieves higher durability.

Optionally, no oxidation interface is included between the semiconductor layer and the ferroelectric layer.

Optionally, the material of the semiconductor layer is a semiconductor material that is not easily oxidized or is easily degraded after oxidation.

Based on this technical solution, no oxide is included between the semiconductor layer and the ferroelectric layer, or only a trace amount of oxide is included, which reduces the various types of electrons generated in the oxidation interface due to electrons constantly passing through the oxidation interface during the erasing and writing process. The ferroelectric field effect transistor proposed in this application can achieve higher retention performance and durability.

Moreover, oxide (such as silicon dioxide) is usually a low dielectric constant material. The voltage drop easily generated on the low dielectric constant material will cause the ferroelectric field effect transistor to require a higher operating voltage. The ferroelectric field of this application Effect transistors can reduce operating voltage and reduce the risk of breakdown.

In conjunction with the first aspect, in some implementations of the first aspect, the material of the semiconductor layer includes germanium, gallium arsenide, potassium phosphide or gallium nitride.

Based on this technical solution, the semiconductor layer can be prepared using germanium, gallium arsenide, potassium phosphide or gallium nitride that is not easily oxidized or the oxides generated after oxidation are easily degraded, which can make the ferroelectric field effect transistor have higher performance.

In conjunction with the first aspect, in some implementations of the first aspect, the ferroelectric field effect transistor further includes a source electrode and a drain electrode, the semiconductor layer is further disposed between the silicon-based substrate and the source electrode, and the silicon-based substrate and between drain electrodes.

Based on this technical solution, the semiconductor layer can be integrally prepared on the silicon-based substrate so that the semiconductor layer is located between the silicon-based substrate and the ferroelectric layer, between the silicon-based substrate and the source electrode, and between the silicon-based substrate and the ferroelectric layer. and the drain electrode, which can alleviate certain process preparation processes.

In addition, the semiconductor layer is disposed between the silicon-based substrate and the source electrode, the silicon-based substrate and the drain electrode, and can also alleviate the differences in lattice parameters and thermal expansion coefficients between the silicon-based substrate and the electrode, playing a certain relaxing role. , improve the retention performance of ferroelectric field effect tubes.

In conjunction with the first aspect, in some implementations of the first aspect, the number of metal gate electrodes is multiple.

Based on this technical solution, the ferroelectric field effect transistor can also be a multi-gate ferroelectric field effect transistor, supporting a variety of application scenarios.

In a second aspect, a ferroelectric memory is provided. The ferroelectric memory includes: a memory array for storing data. The memory array includes a plurality of ferroelectric field effect transistors. The ferroelectric field effect transistors are any of the ferroelectric field effect transistors in the first aspect. The ferroelectric field effect transistor described in one item; a controller for writing data to the storage array and/or for reading data from the storage array.

Based on this technical solution, by setting up a semiconductor layer to block the silicon-based substrate and the ferroelectric layer, the differences in lattice parameters and thermal expansion coefficients of the silicon-based substrate and the ferroelectric layer can be alleviated, and the mutual diffusion of atoms can be reduced, thereby making the ferroelectric field effect The transistor has a long retention capacity for data and can achieve high retention performance.

In a third aspect, an electronic device is provided, including a circuit board and the ferroelectric memory described in the second aspect. The ferroelectric memory is disposed on the circuit board and is electrically connected to the circuit board.

In a fourth aspect, a preparation method is provided, which method includes: providing a silicon-based substrate; preparing a semiconductor layer on the silicon-based substrate by magnetron sputtering, where the material of the silicon-based substrate is different from the material of the semiconductor layer. ; Preparing a ferroelectric layer on the semiconductor layer by atomic layer deposition; preparing a metal gate electrode on the ferroelectric layer by magnetron sputtering.

In conjunction with the fourth aspect, in some implementations of the fourth aspect, the semiconductor layer and the ferroelectric layer are in direct contact.

Combined with the fourth aspect, in some implementations of the fourth aspect, the material of the semiconductor layer includes germanium, gallium arsenide, potassium phosphide or gallium nitride.

In conjunction with the fourth aspect, in some implementations of the fourth aspect, the method further includes: preparing a source electrode on the semiconductor layer by a complementary metal oxide semiconductor CMOS method; preparing a drain electrode on the semiconductor layer by a CMOS method.

In conjunction with the fourth aspect, in some implementations of the fourth aspect, preparing a metal gate electrode on the ferroelectric layer by magnetron sputtering includes: preparing a plurality of metal gate electrodes on the ferroelectric layer by magnetron sputtering. Metal gate electrode.

The technical effects that can be achieved by any possible implementation method in any one of the above-mentioned second to fourth aspects can be described with reference to the technical effects that can be achieved by any possible implementation method in any one of the above-mentioned first aspects. Duplication will not be discussed.

Description of the drawings

Figure 1 is a schematic structural diagram of a ferroelectric memory provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a storage array provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of the first ferroelectric field effect transistor;

Figure 4 is a schematic structural diagram of the second ferroelectric field effect transistor;

Figure 5 is a schematic structural diagram of a ferroelectric field effect transistor provided by an embodiment of the present application;

Figure 6 is a schematic structural diagram of a preparation process provided by the embodiment of the present application.

Detailed ways

The technical solutions in this application are described below in conjunction with the accompanying drawings.

In order to facilitate understanding of the embodiments of the present application, a ferroelectric memory to which the ferroelectric field effect transistor provided by the embodiment of the present application is applicable will be first described in detail with reference to FIG. 1 .

FIG. 1 is a schematic diagram of a ferroelectric memory 100 provided by an embodiment of the present application. Referring to Figure 1, the ferroelectric memory 100 includes a controller, such as the controller 110 shown in Figure 1; the ferroelectric memory 100 also includes a memory array, such as the memory array 120 shown in Figure 1. The controller 110 and the storage array 120 can communicate with each other. For example, the controller 110 can write data in the storage array 120, and/or the controller 110 can read data from the storage array 120.

The controller 110 may include a row decoder, an amplifier, a column decoder, and other control circuits, so that the controller 110 may control the read and write operations and other operations of the storage array 120 .

FIG. 2 is a schematic structural diagram of a storage array 120 provided by an embodiment of the present application. The memory array 120 may include at least one ferroelectric-gate field effect transistor (FeFET). For example, the memory array may include M×N FeFETs, and each FeFET may be used to store data. For example, FIG. 2 shows N bit line pairs (one bit line pair includes a bit line and a source line) and M word lines, where M and N are positive integers. Among them, N FeFETs in each row are connected to a word line, and M FeFETs in each column are connected in parallel between a pair of bit lines and source lines. The source of each FeFET is connected to the corresponding source line, the drain is connected to the corresponding bit line, and the gate is connected to the corresponding word line. For example, as shown in Figure 2, the FeFET between bit line 0, source line 0 and word line 0 is transistor A. When a voltage is applied to the word line, the FeFET is turned on and data can be written. When a small bias voltage is applied between the bit line and the source line, the FeFET can be read by reading the voltage between the source and drain. The current, or the resistance between the FeFET source and drain is detected to read the data.

It should be understood that FIG. 1 and FIG. 2 are only illustrative, and this application does not impose any special limitations on this. In order to facilitate a better understanding of the embodiments of the present application, two currently commonly used ferroelectric field effect transistors will be described below with reference to FIGS. 3 and 4 .

Figure 3 is a schematic structural diagram of the first ferroelectric field effect transistor. Referring to FIG. 3 , the ferroelectric field effect transistor 300 includes a silicon-based substrate 310 , a ferroelectric layer 320 , a gate electrode 330 , a source electrode 340 and a drain electrode 350 . The ferroelectric layer 320 is disposed on the silicon-based substrate 310 . During the preparation process, an oxide interface 360 will be formed between the silicon-based substrate 310 and the ferroelectric layer 320. The oxide interface 360 is usually a silicon dioxide SiO2 film that appears during the preparation process.

Figure 4 is a schematic structural diagram of the second ferroelectric field effect transistor. Referring to FIG. 4 , the ferroelectric field effect transistor 400 includes a silicon-based substrate 410 , a metal electrode layer 420 , a ferroelectric layer 430 , a gate electrode 440 , a source electrode 450 and a drain electrode 460 . The metal electrode layer 420 is disposed between the silicon-based substrate 410 and the ferroelectric layer 430 .

In the ferroelectric field effect transistor shown in Figure 3, due to the difference in lattice parameters and thermal expansion coefficients between the silicon-based substrate and the ferroelectric layer, atomic interdiffusion is caused, which is not conducive to the maintenance performance of the ferroelectric field effect transistor. In addition, due to the existence of the oxide interface, during the erasing and writing process, electrons continue to pass through the oxide interface, which easily causes various traps in the oxide interface that cause the voltage window to close, which is detrimental to the durability of the ferroelectric field effect transistor. and maintain performance. In the ferroelectric field effect transistor shown in Figure 4, due to the strong conductivity of the metal conductor, the risk of leakage is easily generated when operating voltage or current stress is applied to the metal gate electrode, and the insertion of metal materials also increases the difficulty of manufacturing the device. .

Therefore, this application proposes another ferroelectric field effect transistor that can achieve higher retention performance. This will be described below with reference to Figure 5 .

FIG. 5 is a schematic structural diagram of a ferroelectric field effect transistor provided by an embodiment of the present application.

Referring to Figure 5, the ferroelectric field effect transistor 500 of the present application includes a silicon-based substrate 510, a semiconductor layer 520, a ferroelectric layer 530 and a metal gate electrode 540. The semiconductor layer 520 is provided between the silicon-based substrate 510 and the ferroelectric layer 530. During the period, the material of the silicon-based substrate 510 and the semiconductor layer 520 are different.

In a possible implementation, the semiconductor layer 520 and the ferroelectric layer 530 are in direct contact.

The ferroelectric field effect transistor 500 may further include a source electrode 550 and a drain electrode 560. In a possible implementation, the source electrode 550 and the drain electrode 560 can be directly disposed on the silicon-based substrate 510. For example, see (a) of Figure 5, the semiconductor layer 520 can partially cover the silicon-based substrate. On top of 510, the ferroelectric layer 530 is provided on the semiconductor layer 520, and the source electrode 550 and the drain electrode 560 are respectively provided on both ends of the silicon-based substrate 510. In another possible implementation, the semiconductor layer 520 is also disposed between the silicon-based substrate 510 and the source electrode 550 , and between the silicon-based substrate 510 and the drain electrode 560 , for example, see (b) of FIG. 5 , the semiconductor layer 520 may completely cover the silicon-based substrate 510, the ferroelectric layer 530 is disposed on the semiconductor layer 520, and the source electrode 550 and the drain electrode 560 are respectively disposed on both ends of the semiconductor layer 520.

The metal gate electrode 540 is disposed on the ferroelectric layer 530 . In a possible implementation, the ferroelectric field effect transistor 500 may include a plurality of metal gate electrodes 540. For example, see (c) of FIG. 5, two mutually isolated ferroelectric layers 530 are provided on the semiconductor layer 520. Two mutually isolated metal gate electrodes 540 are respectively provided on the ferroelectric layer 530 . Optionally, an isolation layer 570 made of, for example, silicon-based material is filled between the two metal gate electrodes 540 for isolation.

It can be understood that the structural diagram shown in FIG. 5 is only an example of the ferroelectric field effect transistor proposed in this application. The ferroelectric field effect transistor provided in the embodiment of this application can be implemented in a variety of structures, which is not specifically limited by this application. In addition, the ferroelectric field effect transistor provided in the embodiment of the present application may also include other components. For example, the ferroelectric field effect transistor may also include sidewalls, etc. This application is not particularly limited in this regard.

It can be understood that the working principle of a ferroelectric field effect transistor is to use the flip of the ferroelectric polarization of the ferroelectric layer to control the switching of the channel current. For example, a voltage is applied to the metal gate electrode to polarize the ferroelectric layer. The lower surface of the ferroelectric layer can accumulate charges, causing electrons in the silicon-based substrate to migrate, and different resistances are generated according to different applied voltages. Different resistance states can represent different data, thereby realizing data storage. However, due to the differences in lattice parameters and thermal expansion coefficients between the ferroelectric layer and the silicon-based substrate, atoms diffuse into each other, so that the resistance state cannot be maintained for a long time, that is, the data retention ability is poor. The semiconductor layer in the ferroelectric field effect transistor proposed in this application can alleviate this difference, reduce atomic diffusion, and achieve higher retention performance. Each part of the ferroelectric field effect transistor proposed in this application will be described in detail below.

1. Silicon-based substrate

The shape of the silicon-based substrate may be plate-like, rectangular parallelepiped or cube. The silicon-based substrate may be made of silicon-based semiconductor materials such as silicon and silicon germanium.

Silicon-based semiconductor materials have good electron mobility. However, if the ferroelectric layer is directly prepared on the silicon-based semiconductor material, a layer of oxide silicon dioxide SiO ₂ film will be formed on the silicon-based semiconductor material, which will cause the data to be erased. During the writing process, electrons continue to pass through the oxidation interface, which easily generates various traps in the oxidation interface that cause the voltage window to close, affecting the retention performance of the ferroelectric field effect transistor.

2. Semiconductor layer

The semiconductor layer may be in the shape of a plate, a rectangular parallelepiped or a cube, and the thickness of the semiconductor layer is not particularly limited in this application.

Among them, not easily oxidized means that the material is not easy to synthesize oxides due to the preparation environment or use environment during the preparation process or use process. The oxides generated after oxidation are easily degraded means that even if the material is not easily oxidized during the preparation process or use process, The oxide is synthesized due to the preparation environment or use environment, but the oxide can degrade by itself or through simple operations.

It should be noted that when only a trace amount of oxide is contained between the semiconductor layer and the ferroelectric layer of the ferroelectric field effect transistor, the trace oxide will not have a major impact on the retention performance of the ferroelectric field effect transistor. The ferroelectric field effect transistor Transistors should also be considered within the scope of this application.

Optionally, the material of the semiconductor layer includes germanium Ge, gallium arsenide GaAs, gallium nitride GaN or gallium phosphide GaP.

Under normal circumstances, it has been verified that gallium nitride (GaN) can exist stably at high temperatures. The oxide impurities generated by germanium Ge, gallium arsenide (GaAs), and gallium phosphide (GaP) can be easily decomposed by heating. Therefore, germanium Ge, gallium arsenide (GaAs) are used. , gallium nitride GaN, and gallium phosphide GaP are used to prepare the semiconductor layer, which makes the oxidation interface less likely to appear between the semiconductor layer and the ferroelectric layer, which can improve the retention performance of the ferroelectric field effect transistor.

Optionally, no low dielectric constant material is included between the semiconductor layer and the ferroelectric layer (unless otherwise specified, high dielectric constant will be referred to as high K and low dielectric constant will be referred to as low K below). For example, the dielectric constant of silicon dioxide SiO ₂ is ε _{SiO 2} =3.9, which is a low-K material.

It should be understood that the working principle of a transistor is to utilize the flipping of the ferroelectric polarization of the ferroelectric layer to control the switching of the channel current. That is, the switching of controlling the channel current is realized through the voltage difference of the ferroelectric layer. For example, a voltage is applied to the gate so that the voltage difference of the ferroelectric layer reaches a predetermined threshold to achieve ferroelectric polarization. Therefore, if a low-K material is included between the semiconductor layer and the ferroelectric layer, there will be a large voltage drop on the low-K material. In order to make the voltage difference of the ferroelectric layer reach a predetermined threshold, a large voltage needs to be applied to the gate. voltage, thereby increasing the risk of device breakdown.

For example, silicon dioxide SiO ₂ has a dielectric constant ε _{SiO 2} =3.9. The material of the ferroelectric layer is hafnium zirconium oxide HfZrO ₂ (HZO) as an example. The dielectric constant of HZO is ε _HZO =28. When SiO ₂ is included between the silicon-based substrate and the ferroelectric layer, the voltage of the ferroelectric layer refers to formula (1):

Among them, V _HZO represents the voltage of the ferroelectric layer, C _SiO2 represents the capacitance of the semiconductor layer, C _HZO represents the capacitance of the ferroelectric layer, and V _total represents the operating voltage on the semiconductor layer and ferroelectric layer (that is, approximately equal to the voltage that needs to be applied to the gate). Voltage). In addition, C _SiO2 = ε _SiO2 ε ₀ S/d _SiO2 , ε ₀ is the dielectric constant of air, S is the surface area of the semiconductor layer (taking the surface areas of the ferroelectric layer and the semiconductor layer as equal), d _SiO2 is the thickness of the semiconductor layer (Take d _SiO2 =1nm as an example); C _HZO =ε _HZO ε ₀ S/d _HZO , d _HZO is the thickness of the semiconductor layer (take d _HZO =5 nm as an example). Substitute into the calculation to get V _HZO =0.41V _total .

When a semiconductor layer is disposed between the silicon-based substrate and the ferroelectric layer, the voltage of the ferroelectric layer can be approximately equal to the operating voltage V _HZO =V _total .

It can be seen that in order to make the voltage of the ferroelectric layer reach a predetermined threshold, compared to including SiO ₂ between the silicon-based substrate and the ferroelectric layer, a semiconductor layer is provided between the silicon-based substrate and the ferroelectric layer, which can significantly reduce the operating voltage V _total , which in turn reduces the risk of breakdown.

Therefore, in this application, by disposing a semiconductor layer between the ferroelectric layer and the silicon-based substrate, and no low dielectric constant material is included between the semiconductor layer and the ferroelectric layer, the operating voltage can be reduced and the risk of breakdown can be reduced.

3. Ferroelectric layer

This ferroelectric layer can also be called a dielectric layer. The ferroelectric layer is disposed on the semiconductor layer and can be in the shape of a plate, a cuboid or a cube. The thickness of the ferroelectric layer is not particularly limited in this application.

The material of the ferroelectric layer can be a ferroelectric material, such as HZO, HfO2 and other materials with a storage effect, or the material of the ferroelectric layer can also be an antiferroelectric material, such as zirconium oxide _ZrO2 and other materials with a storage effect. Among them, ferroelectric materials refer to materials that have spontaneous polarization within a certain temperature range, and the polarization direction can be reversed due to the reverse direction of the external electric field. Antiferroelectric materials refer to materials in which the dipoles on adjacent ion lines are arranged antiparallel within a certain temperature range, the spontaneous polarization intensity is zero macroscopically, and there is no hysteresis loop.

5. Electrode

The electrodes of ferroelectric field effect transistors include: metal gate electrode, source electrode and drain electrode. The location of the transistor electrodes is described in Figure 5. The electrode may be in the shape of a plate, a sheet or a film, and its shape may include but is not limited to polygonal or irregular geometric figures such as square or rectangle. The material of the source electrode and the drain electrode may be at least one of gold, titanium, nickel, platinum, chromium, aluminum, copper and tungsten. The material of the metal gate electrode may be titanium nitride TiN.

It should be understood that the ferroelectric field effect transistor proposed in this application can be a single-gate ferroelectric field effect transistor or a multi-gate ferroelectric field effect transistor. In the embodiment of this application, a semiconductor is disposed between the ferroelectric layer of the ferroelectric field effect transistor and the silicon-based substrate. layer to achieve higher retention performance.

The ferroelectric field effect transistor provided by the embodiment of the present application has been described above, and the manufacturing method of the ferroelectric field effect transistor is introduced below.

FIG. 6 is an explanatory diagram of a manufacturing method of a transistor provided by an embodiment of the present application. It should be understood that in order to illustrate the process effect, the illustrations are not drawn according to the actual device structure proportions. The specific manufacturing process steps are as follows:

Step 1: Referring to (a) of Figure 6, a silicon-based substrate is provided.

For example, silicon or silicon germanium is prepared as the silicon-based substrate.

Step 2: Referring to (b) of Figure 6, prepare a semiconductor layer on the silicon-based substrate.

For example, a semiconductor material such as Ge is epitaxially grown on a silicon-based substrate by magnetron sputtering or the like.

Optionally, the sample is polished by chemical mechanical polishing so that the semiconductor layer reaches a preset thickness. In addition, the areas of the source electrode and the drain electrode can be determined through photolithography processes such as glue leveling, pre-baking, front exposure, post-baking, post-exposure, and development, and the area of the ferroelectric layer can be determined through etching and other processes.

Step 3: Referring to (c) of Figure 6, prepare a ferroelectric layer on the semiconductor layer.

For example, the ferroelectric layer is formed through an atomic layer deposition (ALD) system.

For example, a HfO2-ZrO2 solid solution (HZO) ferroelectric film with a thickness of 10 nm can be used to obtain an HZO ferroelectric film with a ratio of hydrogen fluoride Hf and zirconium Zr of 1:1 through ALD. Under the conditions that the ALD reaction chamber temperature is 300°C, the tetrakis (methylethylamine) hafnium (TEMA-Hf) source temperature is 80°C, and the tetrakis (dimethylamino)zirconium (TEMA-Zr) source temperature is 90°C, alternate deposition Hafnium dioxide HfO2 and zirconium dioxide ZrO2 single atomic layer films can be deposited alternately 50 times to form a ferroelectric layer.

Step 4: Refer to (d) of Figure 6 to prepare a metal gate electrode, source electrode and drain electrode.

For example, a metal gate electrode is formed by magnetron sputtering deposition, and the source electrode and drain electrode are prepared by a standard complementary metal oxide semiconductor (CMOS) electrode preparation process.

For example, titanium nitride TiN can be selected as the material of the gate electrode, and the TiN electrode can be grown by magnetron sputtering. With a sputtering power of 150W and an Ar gas atmosphere of 0.5Pa, TiN was sputtered for 1200s to grow a 100nm gate electrode. Gold, titanium, nickel, platinum, chromium, aluminum, copper or tungsten are prepared into source and drain electrodes through standard CMOS electrode preparation processes.

Step 6: Crystallize the ferroelectric layer by annealing.

For example, you can pass nitrogen N ₂ into the annealing furnace, set the annealing temperature to room temperature and hold for 2 minutes, raise the temperature from room temperature to 400-700°C for 1 minute, maintain the temperature at 400-700°C for 30 seconds, and hold the temperature at 400-700°C for 30 seconds. The time for reducing 700°C to room temperature is 2 minutes, so that the ferroelectric layer exhibits ferroelectricity.

Therefore, the ferroelectric field effect transistor proposed in the embodiment of the present application can be obtained through the above method. A more detailed description of the ferroelectric field effect transistor including a silicon-based substrate, a semiconductor layer, a ferroelectric layer, a metal gate electrode, a source electrode and a drain electrode can be obtained directly by referring to the relevant description above, and will not be repeated here.

It should be understood that the above steps are only illustrative. For example, the process of preparing a ferroelectric field effect transistor may also include peeling off the sample, for example, using acetone to soak the sample, and also using ultrasonic cleaning as an auxiliary, followed by using anhydrous Clean with ethanol and deionized water, and then blow dry with a nitrogen gun.

Therefore, through the above preparation process, based on this technical solution, by setting up a semiconductor layer to block the silicon-based substrate and the ferroelectric layer, the differences in lattice parameters and thermal expansion coefficients of the silicon-based substrate and the ferroelectric layer can be alleviated, and the atomic energy density can be reduced. Mutual diffusion enables the ferroelectric field effect transistor to have a longer retention ability of data, that is, it can achieve higher retention performance. An embodiment of the present application also provides an electronic device, including a circuit board and the above-mentioned ferroelectric memory. The ferroelectric memory is disposed on the circuit board and is electrically connected to the circuit board.

It should be understood that in various embodiments of the present invention, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present invention. The implementation process constitutes any limitation.

In addition, the term "and/or" in this article is only an association relationship that describes related objects, indicating that there can be three relationships. For example, A and/or B can mean: A alone exists, and A and B exist simultaneously. There are three cases of B alone. In addition, the character "/" in this article generally indicates that the related objects are an "or" relationship.

It should be understood that in the embodiment of the present invention, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and/or other information.

It will also be understood that, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly supports an exception. It will also be understood that as used herein, "and/or" is meant to include any and all possible combinations of one or more of the associated listed items.

While preferred embodiments of the invention have now been described herein, it is to be understood that the terminology used is intended to be descriptive rather than restrictive in nature. It will be apparent to those skilled in the art that many modifications and variations of the invention are possible in light of the above teachings. Therefore, it is to be understood that within the scope of the appended claims, in which reference numerals are used for convenience only and are not in any way limiting, the invention may be practiced otherwise than as specifically described above.

Claims

A ferroelectric field effect transistor, characterized in that the ferroelectric field effect transistor includes a silicon-based substrate, a semiconductor layer, a ferroelectric layer and a metal gate electrode, and the semiconductor layer is provided on the silicon-based substrate and the iron gate electrode. Between the electrical layers, the material of the silicon-based substrate and the material of the semiconductor layer are different.
The ferroelectric field effect transistor of claim 1, wherein the semiconductor layer and the ferroelectric layer are in direct contact.
The ferroelectric field effect transistor according to claim 1 or 2, wherein the material of the semiconductor layer includes germanium, gallium arsenide, potassium phosphide or gallium nitride.
The ferroelectric field effect transistor according to any one of claims 1 to 3, wherein the ferroelectric field effect transistor further includes a source electrode and a drain electrode, and the semiconductor layer is further provided on the silicon-based substrate and between the source electrodes, and between the silicon-based substrate and the drain electrode.
The ferroelectric field effect transistor according to any one of claims 1 to 4, characterized in that there are multiple metal gate electrodes.
A ferroelectric memory, characterized in that the ferroelectric memory includes:

A storage array, used to store data, the storage array includes a plurality of ferroelectric field effect transistors, and the ferroelectric field effect transistors are the ferroelectric field effect transistors according to any one of claims 1 to 5;

A controller configured to write data to the storage array and/or to read data from the storage array.
An electronic device, characterized by comprising the ferroelectric memory as claimed in claim 6 and a circuit board, wherein the ferroelectric memory is disposed on the circuit board and is electrically connected to the circuit board.
A manufacturing method, characterized in that the method includes:

Provide silicon-based substrate;

Preparing a semiconductor layer on the silicon-based substrate by magnetron sputtering, where the material of the silicon-based substrate is different from the material of the semiconductor layer;

Preparing a ferroelectric layer on the semiconductor layer by atomic layer deposition;

A metal gate electrode is prepared on the ferroelectric layer by magnetron sputtering.
The method of claim 8, wherein the semiconductor layer and the ferroelectric layer are in direct contact.
The method of claim 8 or 9, wherein the semiconductor layer is made of germanium, gallium arsenide, potassium phosphide or gallium nitride.
The method according to any one of claims 8 to 10, characterized in that the method further includes:

Prepare a source electrode on the semiconductor layer by complementary metal oxide semiconductor CMOS;

A drain electrode is prepared on the semiconductor layer by CMOS.
The method according to any one of claims 8 to 11, wherein preparing a metal gate electrode on the ferroelectric layer by magnetron sputtering includes:

A plurality of metal gate electrodes are prepared on the ferroelectric layer by magnetron sputtering.