CN114141880A - FeFET based on antiferroelectric gate dielectric and oxide semiconductor channel and preparation method thereof - Google Patents
FeFET based on antiferroelectric gate dielectric and oxide semiconductor channel and preparation method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 46
- 239000003989 dielectric material Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000003860 storage Methods 0.000 claims abstract description 16
- 230000005684 electric field Effects 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 39
- 238000000231 atomic layer deposition Methods 0.000 claims description 35
- 238000005240 physical vapour deposition Methods 0.000 claims description 28
- 239000007772 electrode material Substances 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910052706 scandium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052582 BN Inorganic materials 0.000 claims description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 2
- 229910004166 TaN Inorganic materials 0.000 claims description 2
- 230000005620 antiferroelectricity Effects 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010445 mica Substances 0.000 claims description 2
- 229910052618 mica group Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 3
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 claims 1
- 230000015654 memory Effects 0.000 description 15
- 230000008569 process Effects 0.000 description 13
- 230000010287 polarization Effects 0.000 description 10
- 230000010354 integration Effects 0.000 description 9
- 230000006870 function Effects 0.000 description 8
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000028161 membrane depolarization Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ion Chemical class 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
The invention provides an antiferroelectric gate dielectric and oxide semiconductor channel-based FeFET and a preparation method thereof, belonging to the field of micro-nano electronics. The FeFET device comprises an insulating substrate, wherein a graphical back gate electrode layer is arranged on the insulating substrate, an antiferroelectric gate dielectric material layer is arranged on the back gate electrode layer, an oxide semiconductor material layer is arranged on the antiferroelectric gate dielectric layer and serves as a channel, source and drain contact electrodes are respectively arranged on the left side and the right side above the channel, the work function difference between the back gate electrode layer and the oxide semiconductor material layer is 1 eV-2 eV, a built-in electric field is provided for the antiferroelectric gate dielectric material layer, and the antiferroelectric gate dielectric material forms two different storage states. The invention replaces the traditional ferroelectric gate dielectric with the antiferroelectric gate dielectric and replaces the traditional silicon-based channel with the oxide semiconductor channel, thereby improving the durability of the memory device.
Description
Technical Field
The invention belongs to the technical field of micro-nano electronics, and particularly relates to a high-durability FeFET based on an antiferroelectric gate dielectric and an oxide semiconductor channel and a preparation method thereof.
Background
With the continuous development of integrated circuits, logic and memory devices are continuously developed as two basic routes, the size of devices is continuously reduced, the integration level is continuously improved, and the development is from planar integration to three-dimensional integration. In a traditional von Neumann architecture system, calculation and storage are separated, a bottleneck of a storage wall exists, and data transmission not only consumes a large amount of power consumption, but also severely limits the development of calculation power. In order to break the memory wall and meet the demand of the memory fusion trend, a series of novel memories with the potential of high speed, high density, low power consumption and the like are proposed, including a ferroelectric field effect transistor (FeFET), a Resistive Random Access Memory (RRAM), a phase change memory (PCRAM), a spin magnetic memory (STT-MRAM) and the like.
The hafnium oxide based ferroelectric field effect transistor (FeFET) having good compatibility with the CMOS process becomes a novel memory very promising in the post-molarity age due to the advantages of small area (only 1T), fast read/write speed, low power consumption, non-volatility, capability of hybrid integration with CMOS logic devices, and the like. The basic principle is that two polarization states of a ferroelectric material are controlled by using gate voltage, the different polarization states have different influences on the conductance of a transistor channel, and source-drain currents of the transistor are respectively in an off state and an on state, namely a storage state of 0 and a storage state of 1. The memory has non-volatility, and the source-drain current has almost no influence on the grid when being read out, namely the memory has the characteristic of read-write separation. The present hafnium oxide based fefets face a major challenge in terms of durability, for two reasons: in the aspect of ferroelectric materials, the coercive electric field of the hafnium oxide-based ferroelectric material is larger, so that the operating voltage of the device is larger, more charge injection is introduced by large voltage, and new defects are easily generated; in terms of device structure, the normally existing ferroelectric-semiconductor interface intermediate layer bears a higher electric field, so that breakdown is easily caused, and tunneling current causes newly added defects, so that a memory window is gradually closed in a cyclic process. The durability of the FeFET at the present stage is usually 105On the other hand, this is far from sufficient for the application requirements of nonvolatile storage. Therefore, how to realize a high-durability FeFET becomes an urgent problem to be solved.
Disclosure of Invention
The invention aims to provide a FeFET and a preparation method thereof, wherein the durability of the FeFET is obviously improved, and the structure is simple in preparation process, compatible with a CMOS (complementary metal oxide semiconductor) back-end process and capable of realizing large-scale integration.
The technical scheme of the invention is as follows:
a FeFET device is characterized by comprising an insulating substrate, wherein a graphical back gate electrode layer is arranged on the insulating substrate, an antiferroelectric gate dielectric material layer is arranged on the back gate electrode layer, an oxide semiconductor material layer is arranged on the antiferroelectric gate dielectric layer and serves as a channel, source and drain contact electrodes are respectively arranged on the left side and the right side above the oxide semiconductor channel, the difference of work functions of the back gate electrode layer and the oxide semiconductor material layer is 1 eV-2 eV, a built-in electric field is provided for the antiferroelectric gate dielectric material layer, and the antiferroelectric gate dielectric material forms two different storage states.
The insulating substrate can be selected from silicon dioxide, silicon wafer covered by boron nitride, mica, or any other insulating substrate material with an insulating layer on the surface and good mechanical and thermal stability.
The antiferroelectric gate dielectric material layer needs to meet two conditions, and on one hand, the antiferroelectric gate dielectric material layer needs to be used as a gate dielectric insulator, so that the electric leakage is small, and the breakdown resistance is strong; on the other hand, it is required to have antiferroelectric property, that is, the PV curve has a hysteresis in the first and third quadrants, and the available hafnium oxide based ferroelectric/antiferroelectric material compatible with CMOS process includes: ZrO (ZrO)2、Zr:HfO2、Al:HfO2、Si:HfO2And the like.
The two sides of the antiferroelectric gate dielectric material layer play a ferroelectric-like storage effect, and the important point is that only one of the first quadrant or the third quadrant in the PV curve is utilized, so that the operating voltage can be halved, the injection of electric charges is reduced, and the endurance characteristic of the device is greatly improved. And the oxide semiconductor channel and the anti-ferroelectric gate dielectric material layer are both made of oxide materials, so that an interface layer can be eliminated, a large number of defects caused by interface layer breakdown are avoided, and the durability is further improved. The back gate electrode material layer and the oxide semiconductor material layer can be selected from the following materials according to the requirements (the difference of work functions of the two materials is 1 eV-2 eV): back gate electrode material layer: pt, Se, Mg, Sc, TiN, W, etc.; oxide semiconductorMaterial layer: IGZO, IWO, ITO, ZnO2And the like.
The source and drain contact electrodes need to form ohmic contact with an oxide semiconductor channel, so that the contact resistivity of the source and drain electrodes is reduced, and the available materials comprise: al, Ti, Sc, Cr, Pt, Pd, Au, etc.
The thickness of the insulating substrate is larger than 50nm, the thickness of a back gate electrode material layer on the insulating substrate is 10 nm-20 nm, the thickness of an antiferroelectric gate dielectric material layer is 5 nm-15 nm, the thickness of an oxide semiconductor material layer on the antiferroelectric gate dielectric is 5 nm-20 nm, and the thickness of source and drain contact electrodes on the left side and the right side above a channel is about 50 nm.
The preparation method of the FeFET comprises the following steps:
(1) photoetching and exposing a back gate electrode pattern on an insulating substrate, preparing a back gate electrode material by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method, and stripping;
(2) depositing an antiferroelectric gate dielectric material (not activated) on the whole sheet obtained in the step (1) by an Atomic Layer Deposition (ALD) method;
(3) depositing a stress layer on the whole wafer obtained in the step (2) by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method, rapidly annealing the stress layer, activating the antiferroelectricity of the antiferroelectric gate dielectric, and removing the stress layer by a wet etching or dry etching method;
(4) photoetching and exposing a channel region pattern on the activated antiferroelectric gate dielectric material, preparing an oxide semiconductor material by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method, and stripping;
(5) and photoetching the left side and the right side above the oxide semiconductor channel to expose a source-drain electrode contact area, preparing a metallic material by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method, and stripping.
In the above preparation method, the stress layer selected in step (3) needs to provide sufficient stress to the antiferroelectric gate dielectric layer to activate antiferroelectric property during annealing, and the selectable stress materials include: TiN, TaN, Pt, W, Ru, etc.; the temperature and time of the annealing process are based onThe ferroelectric gate dielectric material, the back electrode material and the stress layer material are flexibly adjusted according to different ranges, wherein the general ranges are as follows: the annealing temperature is 350-650 ℃, and the annealing time is 30-120 s; the stress layer material can be removed by wet etching (including hydrochloric acid or ammonia water) or dry etching (including SF)6、Cl2Etching by argon ion, etc.).
Furthermore, the preparation method is compatible with a CMOS back-end process, the insulating substrate can be replaced by a passivation layer which is flattened by Chemical Mechanical Polishing (CMP) in the CMOS process, the steps are completed in the back-end process, and then the operations of covering the passivation layer, punching a through hole, interconnecting and the like can be continued, so that the high-durability FeFET memory based on the antiferroelectric gate dielectric and the oxide semiconductor channel can be mixed and integrated with a CMOS logic circuit.
The invention has the following technical effects:
the invention replaces the ferroelectric gate medium with the antiferroelectric material (the residual polarization of the antiferroelectric material is 0, but the polarization charge-voltage curve still has hysteresis in the first and third quadrants), and forms a built-in electric field between the metallic electrode material with proper work function and the channel, so that the polarization charge-voltage curve (namely PV curve) of the antiferroelectric material is translated, and thus, when the gate voltage is 0, the residual polarization is not 0, and two different storage states are formed. Experiments prove that the device has good durability; meanwhile, the oxide semiconductor channel is adopted to replace the traditional silicon-based channel, an interface layer is eliminated, the working voltage of the device can be reduced due to the partial pressure of the non-interface layer, and the non-interface layer can reduce the depolarization field, so that the retention characteristic of the device is improved. Therefore, the storage performance of the FeFET can be comprehensively optimized by combining the antiferroelectric gate dielectric and the oxide semiconductor channel.
The invention has the following specific advantages:
a conventional FeFET memory utilizes the ferroelectric material for storage in both up and down polarization states, i.e., two intersections of the PV curve of the ferroelectric material with the Y-axis (positive and negative remanent polarizations) at a gate voltage of 0. The residual polarization of the antiferroelectric material is 0, but a metastable state exists at about 0V, so that the PV curve has a hysteresis at the first quadrant and the third quadrant, and if only one of the antiferroelectric material can be used, the required voltage can be directly halved. In order to ensure the non-volatility of the memory, a built-in electric field can be formed by utilizing the work function difference between the gate electrode material and the oxide semiconductor channel material, so that the PV curve of the antiferroelectric material is translated leftwards or rightwards, and thus when the voltage is 0, two polarization states are provided, and the effect of non-volatile storage is achieved. Through the analysis, the biggest advantages of replacing ferroelectrics by antiferroelectrics are that the operation voltage is reduced, and the charge injection and defect generation caused by large voltage are reduced, so that the endurance characteristic of the FeFET memory is greatly improved, and the method has important significance for the practical application of the FeFET memory. In addition, in the traditional silicon-based FeFET, an interface layer of 0.5 nm-2 nm, namely a silicon oxide layer, is usually arranged between the ferroelectric material and the channel. On one hand, the interface layer can divide voltage in the writing process, so that the device has higher operating voltage and is difficult to match with a logic circuit; on the other hand, the existence of the interface layer can increase the depolarization field (compared with the interface layer), so that the holding characteristic of the device is deteriorated; meanwhile, in the third aspect, since the interfacial layer is usually thin, breakdown is easy, and a large number of defects are introduced during breakdown, which affects the endurance characteristics of the device. In combination with the oxide semiconductor channel of the invention to replace the traditional silicon-based channel, as the antiferroelectric gate dielectric material and the oxide semiconductor channel are both oxides, and an interface without an interface layer can be formed between the antiferroelectric gate dielectric material and the oxide semiconductor channel, three problems caused by the interface layer are avoided, so that the antiferroelectric combined oxide semiconductor channel can comprehensively optimize the storage characteristics of the FeFET from the aspects of operating voltage, retention characteristics, durability characteristics and the like.
And secondly, the invention is compatible with the CMOS back-end process and has the capability of large-scale back-end integration.
The growth temperature of the device can be controlled below 450 ℃, and the thermal budget requirement of back-end integration is easily met under the cooperative optimization of annealing temperature. Therefore, the structure can be compatibly realized on the passivation layer of the CMOS logic chip, and the structure is interconnected with the CMOS logic device through the through hole to realize the storage and calculation integration of the rear end. The device is simple in process preparation method, compatible in CMOS rear-end process and easy to realize large-scale integration, and further storage density and memory calculation efficiency are effectively improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a high endurance FeFET based on an antiferroelectric gate dielectric and an oxide semiconductor channel prepared according to an embodiment of the present invention.
In the figure:
1-insulating substrate 2-Back Gate electrode layer
3-antiferroelectric gate dielectric material layer (after activation) 4-oxide semiconductor channel
5-source terminal contact electrode 6-drain terminal contact electrode
Fig. 2 is a schematic diagram of steps of a high endurance FeFET based on an antiferroelectric gate dielectric and an oxide semiconductor channel prepared by an embodiment of the present invention, wherein:
(a) is a sectional view of a patterned back gate electrode material layer obtained by photoetching and stripping a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method on an insulating substrate;
(b) is a cross section after an initial non-activated antiferroelectric material layer is obtained by an Atomic Layer Deposition (ALD) method on the basis of (a);
(c) based on (b), obtaining a cross-sectional view of the stress layer material which provides enough stress activated ferroelectric/antiferroelectric by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method;
(d) is a cross section after rapid thermal annealing (activating ferroelectric/antiferroelectric properties) on the basis of (c);
(e) based on (d), removing the material of the stress layer on the uppermost layer by a wet etching or dry etching method to obtain a cross-sectional view;
(f) is a cross-sectional view obtained after photoetching and stripping a patterned oxide semiconductor channel obtained by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method on the basis of (e);
(g) and (f) forming a source-drain contact electrode by photoetching and stripping the patterned metallic material obtained by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method on the basis of the (f).
In the figure:
1-insulating substrate 2-Back Gate electrode layer
3*Anti-ferroelectric gate dielectric material (before activation) 7-stress layer material
3-antiferroelectric gate dielectric material (after activation) 4-oxide semiconductor channel
5-source terminal contact electrode 6-drain terminal contact electrode
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings.
As shown in fig. 1, the high endurance FeFET based on the antiferroelectric gate dielectric and the oxide semiconductor channel of the present invention comprises an insulating substrate 1, a back gate electrode layer 2, an activated antiferroelectric gate dielectric material layer 3, an oxide semiconductor channel 4, a source terminal electrode 5 and a drain terminal electrode 6. The patterned gate electrode layer 2 is located above the insulating substrate 1, the activated antiferroelectric gate dielectric material layer 3 is located above the insulating substrate 1 and the gate electrode layer 2, the patterned oxide semiconductor channel 4 is located above the activated antiferroelectric gate dielectric material layer 3, and the source contact electrode 5 and the drain contact electrode 6 are respectively located on source and drain regions on the left side and the right side of the patterned oxide semiconductor channel 4.
The preparation method comprises the following process steps as shown in figure 2:
1) photoetching and exposing a gate electrode pattern on an insulating substrate, depositing a gate electrode material on the whole substrate by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method, and stripping with acetone, wherein the difference between the metal work function of the gate electrode and the work function of the oxide semiconductor is about 1 eV-2 eV (for example, for an IGZO film, the work function is about 4.5eV, Pt with the metal work function of 5.6 can be selected), so as to provide a sufficient built-in electric field, and the thickness of the built-in electric field is 10 nm-20 nm, as shown in FIG. 2 (a);
2) depositing an antiferroelectric gate dielectric material (not activated) on a full wafer by Atomic Layer Deposition (ALD), optionally ZrO2、Hf0.3Zr0.7O2And the like, the thickness of which is 5nm to 15nm, as shown in FIG. 2 (b);
3) depositing a stress layer material on the whole wafer by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method, wherein the stress layer material provides enough stress in a subsequent annealing process so as to activate ferroelectric/antiferroelectric property, and the stress layer material can be selected from metallic materials such as TiN, W, Ru and the like, and the thickness of the stress layer material is 10 nm-20 nm, as shown in FIG. 2 (c);
4) performing rapid thermal annealing on the whole wafer to activate the antiferroelectric of the gate dielectric to make the gate dielectric become the activated antiferroelectric gate dielectric, wherein the annealing temperature is 350-650 ℃, the annealing time is 30-120 s, and the steps 2), 3) and 4) can be flexibly selected according to different conditions to ensure the antiferroelectric activation, as shown in fig. 2 (d);
5) the stress layer material on the uppermost layer is removed by wet etching or dry etching, for example, liquid No. 1 (NH) may be used for TiN metallic material4OH:H2O2:H2O1: 1:5), as shown in fig. 2 (e);
6) exposing the channel region pattern by photoetching, depositing oxide semiconductor channel material by Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) on the whole wafer, and stripping with acetone, wherein the oxide semiconductor channel material can be IGZO, IWO, ITO, ZnO2And the like, the thickness of which is 5nm to 20nm, as shown in FIG. 2 (f);
7) and photoetching electrode contact region patterns exposing a source electrode and a drain electrode, depositing a source electrode material and a drain electrode material (which can be consistent or inconsistent) on the whole wafer by a Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) method, and stripping by using acetone, wherein the contact electrode material can be Al (50nm), Ti/Au (5nm/50nm) and the like, as shown in figure 2(g), and then the high-durability FeFET based on the antiferroelectric gate dielectric and the oxide semiconductor channel can be prepared.
Finally, it is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.
Claims (10)
1. A FeFET device is characterized by comprising an insulating substrate, wherein a graphical back gate electrode layer is arranged on the insulating substrate, an antiferroelectric gate dielectric material layer is arranged on the back gate electrode layer, an oxide semiconductor material layer is arranged on the antiferroelectric gate dielectric material layer and serves as a channel, source and drain contact electrodes are respectively arranged on the left side and the right side above the oxide semiconductor channel, the work function difference between the back gate electrode layer and the oxide semiconductor material layer is 1 eV-2 eV, a built-in electric field is provided for the antiferroelectric gate dielectric material layer, and the antiferroelectric gate dielectric material forms two different storage states.
2. An FeFET device as claimed in claim 1 wherein the insulating substrate is selected from silicon dioxide, boron nitride coated silicon wafers or mica, the insulating substrate having a thickness greater than 50 nm.
3. The FeFET device of claim 1, wherein the layer of antiferroelectric gate dielectric material is ZrO2、Zr:HfO2、Al:HfO2Or Si: HfO2The thickness range of the antiferroelectric gate dielectric material layer is 5 nm-15 nm.
4. The FeFET device of claim 1, wherein the back gate electrode layer is selected from Pt, Se, Mg, Sc, TiN, or W, and wherein the back gate electrode layer has a thickness in the range of 10nm to 20 nm.
5. The FeFET device of claim 1, wherein the layer of oxide semiconductor material is selected from IGZO, IWO, ITO or ZnO2The thickness of the oxide semiconductor material layer is 5 nm-20 nm.
6. The FeFET device of claim 1 wherein the source and drain contact electrodes are selected from Al, Ti, Sc, Cr, Pt, Pd or Au and have a thickness of about 50 nm.
7. The method of fabricating an FeFET according to claim 1, comprising the steps of:
1) photoetching and exposing a back gate electrode pattern on an insulating substrate, preparing a back gate electrode material by a physical vapor deposition or atomic layer deposition method, and stripping to form a back gate electrode layer;
2) depositing an antiferroelectric gate dielectric material by an atomic layer deposition method to form an antiferroelectric gate dielectric layer;
3) depositing a stress layer by a physical vapor deposition or atomic layer deposition method and rapidly annealing the stress layer by heat, activating the antiferroelectricity of the antiferroelectric gate dielectric layer, and then removing the stress layer by a wet etching or dry etching method;
4) photoetching and exposing a channel region pattern on the activated antiferroelectric gate dielectric material layer, preparing an oxide semiconductor material by a physical vapor deposition or atomic layer deposition method, and stripping to form an oxide semiconductor channel;
5) and photoetching the left side and the right side above the oxide semiconductor channel to expose contact areas of the source electrode and the drain electrode, preparing a metallic material by a physical vapor deposition or atomic layer deposition method, and stripping to form source and drain contact electrodes.
8. The method for fabricating an FeFET device as recited in claim 7, wherein the stress layer in step 3) is made of TiN, TaN, Pt, W or Ru.
9. The method for manufacturing a FeFET device according to claim 7, wherein the annealing in step 3) is performed at a temperature of 350 ℃ to 650 ℃ for a time of 30s to 120 s.
10. The method for manufacturing an FeFET device according to claim 7, wherein the step 3) of removing the stress layer material is performed by wet etching or dry etching.
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