TWI836349B - Thin-film storage transistor with ferroelectric storage layer - Google Patents

Abstract

By harnessing the ferroelectric phases in the charge storage material of thin-film storage transistors of a 3-dimensional array of NOR memory strings, the storage transistors are adapted to operate as ferroelectric field-effect transistors (“FeFETs”), thereby providing a very high-speed, high-density memory array.

Description

Thin film storage transistor with ferroelectric storage layer

The present invention relates to a thin film storage transistor that can be programmed into a three-dimensional memory array. In particular, the present invention relates to thin film transistors that may include a ferroelectric storage layer.

This application is a continuation-in-part of U.S. Patent Application No. 17/155,673 filed on January 22, 2021, entitled “Cold Electronic Erase in Thin Film Storage Transistors” and claims and relates to: (i) U.S. Provisional Patent Application No. 62/964,472 filed on January 22, 2020 (Provisional Application I), entitled “Cold Electronic Erase in Thin Film Storage Transistors” and (ii) U.S. Provisional Patent Application No. 62/992,754 filed on March 20, 2020 (Provisional Application II), entitled “Cold Electronic Erase in Thin Film Storage Transistors”.

This application also claims and relates to U.S. provisional patent application No. 63/054,743 filed on July 21, 2020 (Provisional Application III), entitled "Method for making a three-dimensional memory structure of an NOR memory group"; U.S. provisional patent application No. 63/054,750 filed on July 21, 2020 (Provisional Application IV), entitled "Three-dimensional memory structure of an NOR memory group A U.S. provisional patent application filed on January 20, 2021 (Provisional Application V), application number 64/139,435, entitled "Vertical NOR Gate Thin Film Transistor Group and Its Fabrication" and a U.S. provisional patent application filed on February 22, 2021 (Provisional Application VI), application number 63/152.266, entitled "Thin Film Storage Transistor with Ferroelectric Storage Layer".

This application is also related to the official U.S. patent application (related application) filed on June 5, 2020, with application number 16/894,596, titled "Capacitively coupled non-volatile thin film transistor group in three-dimensional array", which It is a continuation of the U.S. patent application filed on August 21, 2018, with application number 16/107,118, titled "Capacitively coupled non-volatile thin film transistor assembly in three-dimensional array", which was filed in August 2016 The division of the U.S. patent application filed on the 26th, with application number 15/248,420, titled "Capacitively coupled non-volatile thin film transistor assembly in three-dimensional array", claims and concerns: (i) In September 2015 The U.S. provisional patent application filed on the 30th, with application number 62/235,322, is titled "Multiple gate flip-flop or gate flash thin film transistor groups in stacked horizontal active strings with vertical control gates"; (ii) in 2015 A U.S. provisional patent application filed on November 25, 2016, with application number 62/260,137, titled "Three-dimensional vertical inverse OR gate flash thin film transistor assembly"; (iii) a U.S. patent application filed on July 26, 2016 Formal patent application, application number 15/220,375, titled "Multi-gate inverter or gate flash thin film transistor array in stacked horizontal active string with vertical control gate" and (vi) on July 15, 2016 The U.S. provisional patent application filed, application number 62/363,189, is titled "Capacitively coupled non-volatile thin film transistor assembly."

The full disclosure of the aforementioned related applications, parent applications, and provisional applications I, II, III, IV, and V is hereby provided for reference.

According to one embodiment of the present invention, a storage transistor has a tunneling dielectric layer and a charge trapping layer between a channel region and a gate, wherein the charge trapping layer has a conduction band offset relative to an n-type silicon conduction band that is smaller than the low point of the tunneling barrier in the tunneling dielectric layer when a write voltage is applied, so that electrons directly tunnel into the charge trapping layer. The conduction band offset of the charge trapping layer is selected to have a value between -1.0 eV and 2.3 eV. In some embodiments, the charge capture layer may include one or more of: yttrium oxide (HfO ₂ ), yttrium oxide (Y ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), zirconium oxide (ZrSiO ₄ ), laminar oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), chalcanthite oxide (CeO ₂ ), titanium oxide (TiO ₂ ), strontium titanium oxide (SrTiO ₃ ), other semiconductors, and metal nanodots (e.g., silicon, ruthenium, platinum, and cobalt nanodots).

According to an embodiment of the present invention, the storage transistor may further include an energy barrier layer between the tunneling dielectric layer and the charge trapping layer. The energy barrier layer has a conduction band compensation difference that is smaller than the conduction band compensation difference of the charge trapping layer. . The energy barrier layer may also include a material with a conduction band compensation difference between 1.0eV and 2.3eV, preferably between -1.0eV and 1.5eV, such as one or more: hafnium oxide (HfO ₂ ), Yttrium oxide (Y ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), zirconium oxide (ZrSiO ₄ ), tantalum oxide (Ta ₂ O ₅ ), cerium oxide (CeO ₂ ), oxide Titanium (TiO ₂ ), strontium titanium oxide (SrTiO ₃ ), other semiconductor and metal nanodots (such as silicon, ruthenium, platinum and cobalt nanodots).

In one embodiment, when a voltage substantially less than the write voltage is applied across the channel region and the gate, the electrons pass through an energy barrier that is wider than the thickness of the tunneling dielectric layer and pass through the Fowler-Nordham (Fowler-Nordheim) mechanism tunnels into the charge trapping layer.

In one embodiment, the tunnel dielectric layer may be as thin as 5-40 angstroms (Å) and may be formed of silicon oxide (e.g., SiO ₂ ) or silicon nitride. The silicon oxide tunnel dielectric layer may be formed using a typical oxidation technique (e.g., a high temperature oxidation), chemical synthesis (e.g., atomic layer deposition), or any suitable combination of these techniques. An active oxygen (O ₂ ) process may include ozone for precise control of thickness and improved oxide quality (e.g., reduced leakage due to defect sites). The silicon nitride tunnel dielectric layer may be formed using a typical nitridation technique, direct synthesis, chemical synthesis (e.g., by atomic layer deposition), or any suitable combination of these techniques. A plasma process may be used to precisely control thickness and improve dielectric quality (e.g., reduced leakage due to defect sites).

The tunnel dielectric layer may additionally include a thin aluminum oxide (Al ₂ O ₃ ) layer (eg, 10 Angstroms or less). The aluminum oxide layer in the tunnel dielectric layer can be synthesized in the amorphous phase to reduce leakage due to defective sites.

Further, according to an embodiment of the present invention, a memory group in a three-dimensional array of memory groups is formed on a plane of a semiconductor substrate, including: (a) a first and a second semiconductor layer of a first conductivity type; (b) a third semiconductor layer having a second conductivity type different from the first conductivity type to contact the first semiconductor layer and the second semiconductor layer; (c) a plurality of conductors; and (d) a ferroelectric storage layer located between the conductors and the third semiconductor layer, wherein (i) the first, second and third semiconductor layers, the ferroelectric storage layer and the ferroelectric storage layer are connected to each other. The storage layer and the conductors form a plurality of ferroelectric field effect transistors (FeFETs) for the memory set; (ii) the first and second semiconductor layers provide a common bit line and a common source line for the ferroelectric field effect transistors, respectively; (iii) the third semiconductor layer provides a channel region for each ferroelectric field effect transistor in the memory set; (iv) the ferroelectric storage layer provides a polarization layer for each ferroelectric field effect transistor; and (v) each conductor provides a gate electrode for one of the ferroelectric field effect transistors in the memory set. The memory set can be organized into a horizontal NOR memory set. The memory group may be a memory group of a portion of a three-dimensional array, wherein the thin film ferroelectric field effect transistors (FeFETs) of the memory group are arranged along a direction substantially parallel to the plane to form a NOR group. In another embodiment, the ferroelectric field effect transistors (FeFETs) of the memory group are arranged along a direction substantially perpendicular to the plane to form a vertical NOR thin film ferroelectric field effect transistor (FeFETs) group.

In one embodiment, the ferroelectric storage layer may simultaneously include an interface dielectric layer and a ferroelectric material layer, wherein the interface dielectric layer has a dielectric coefficient in the range of 3.9 to greater than 2500.0, or any greater than 3.9 value. The interface dielectric layer may include one or more silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ), or silicon oxide (SiO ₂ ), providing a refractive index between 1.5 and 2.0. The thickness of the interface dielectric layer can be between 0.0 nm and 2.0 nm. The interface dielectric layer may include silicon oxide (SiO ₂ ) and zirconium oxide (ZrO ₂ ). In another embodiment, the interfacial dielectric layer may comprise a native oxide that is inherently formed when a layer of ferroelectric material is deposited directly on the third semiconductor layer. Alternatively, the interfacial dielectric layer may be formed by chemically cleaning the surface of the third semiconductor layer, followed by, for example, pulsed ozone or by thermal annealing in a hydrogen or deuterium environment or any other technique known to those of ordinary skill in the art. A primitive oxide formed by densification. This treatment reduces electron leakage through the interface dielectric layer and may also reduce surface states at the interface between the third semiconductor layer and the ferroelectric storage layer.

In one embodiment, the ferroelectric material layer may include zirconium-doped zirconium oxide (HfO ₂ :Zr or HZO), aluminum-doped zirconium oxide (HfO ₂ :Al), silicon-doped zirconium oxide (HfO ₂ :Si), or yttrium-doped zirconium oxide (HfO ₂ :La), or any combination thereof. The term HZO may include zirconium oxide (HfZrO), zirconium oxynitride (HfZrON), zirconium aluminum oxide (HfZrAlO), any combination thereof, or any other zirconium oxide containing zirconium dopants.

Memory banks containing three-dimensional arrays of ferroelectric field effect transistors can be organized such that the ferroelectric material layer of each ferroelectric field effect transistor (FeFET) is consistent with the ferroelectric fields in other memory banks. Separation of ferroelectric material layers in FeFETs.

In one embodiment, the ferroelectric storage layer of the ferroelectric field effect transistor can be deposited on the third semiconductor layer using atomic layer deposition (ALD) technology at a temperature between 200°C and 330°C, preferably between 270°C and 330°C. The ferroelectric storage layer undergoes a post-deposition annealing step at a temperature between 400°C and 1000°C.

In one embodiment, the conductor in the memory group can be formed of tungsten (W), molybdenum (Mo), aluminum (Al), ruthenium (Ru), tantalum (Ta), titanium (Ti), titanium nitride (TiN) or any combination thereof or alloys thereof.

The thin film ferroelectric field effect transistor of the present invention may have a conducting state critical voltage greater than 0.0 volt, and a wide window period (e.g., 0.5 volts to 2.5 volts) between its conducting state critical voltage and its non-conducting state critical voltage.

According to another embodiment of the present invention, a thin film ferroelectric field effect transistor (FeFET) may include a channel region formed of an oxide semiconductor material, and a metal source region or a metal bit line. The ferroelectric material of the channel region with a thickness between 7.0 nm and 14.0 nm may include indium zinc oxide (InZnO or IZO), which has an electron mobility greater than or equal to 10.0 ^cm2 /V when the thickness of the channel region is greater than 7.0 nm. The metal source region or the metal bit line may include molybdenum.

The present invention can be better understood through the following detailed description in conjunction with the accompanying drawings.

101, 102: Line

110: Channel area

111: Tunneling dielectric sublayer

112: Charge trapping sub-layer

113: Barrier dielectric sublayer

114: Gate electrode

120:Material

203: Isolation dielectric layer (insulating dielectric layer

204-1~204-4: Memory group

204a, 204e: Conductor layer

204b: First transistor material layer (N ⁺ doped amorphous silicon or polycrystalline silicon layer)

204d: second transistor material layer (N ⁺ doped amorphous silicon or polycrystalline silicon layer)

204c:Oxide layer

250: Channel region (third transistor material layer)

251: Charge storage layer

251-1~251-4: Composite layer

252: Gate electrode or local word line

254-1~254-4: NOR memory group

270: Channel material (third transistor material layer)

271: Ferroelectric storage layer

272: Gate electrode or local word line (conductive material)

301, 302, 514, 1001, 1002, 1201: arrow

401: Write status critical voltage

402: Erase state critical voltage

501: Channel area

502: Tunneling dielectric layer

503: Charge capture layer

511: conduction band boundary

512:Boundary of the price band

515:Electron Energy

516:Electric hole energy

601: Base

602: Tunneling dielectric layer

603: Barrier dielectric layer for low conductivity band steps

604: Charge trapping layer

605: blocking dielectric layer

606: Gate electrode

607: Alumina (Al2O3) layer

608: Silicon dioxide (SiO2) layer

610: blocking dielectric layer

615: Electron energy shift

1202: Obstacle height

1300:NOR memory group

1301-1, 1301-2: stacking

1302:Silicon substrate

1303: Storage transistor

1350: Three-dimensional array

1351-1, 1351-2: Active stacking

1353: Ferroelectric Field Effect Transistor (FeFET)

1401, 1402, 1403, 1404: Waveform

1500: Intermediate memory structure

1501-1, 1501-2: Active stacking

1502: Groove

1504: Dielectric materials

1505: Well (elliptical well)

1510:X-Y cross section

1600: Intermediate memory structure

1601-1, 1601-2: Active stacking

1602: Groove

1604: Oxide

1605: Well

1700: Intermediate memory structure

1701-1, 1701-2: Active stacking

1702: Groove

1704:Oxide

1705:well

1707: Amorphous silicon lining

a, b, b’, c, d, A, B: parameters

A-A’: line

_Id : sink current

V _g : Gate voltage

X, Y, Z: direction

Figure 1 is a typical energy band diagram of a storage transistor, which includes a dielectric material between a channel region and a gate electrode and various sublayers for storing charges.

Figure 2 shows the typical direct tunneling current density (gate current) for various silicon dioxide thicknesses under different bias conditions.

Figure 3(a) and Figure 3(b) respectively depict electrons tunneling directly into and out of the charge trapping sublayer 112 during write and erase operations.

Figure 4 is an evolution diagram of the write window over ¹⁰⁹ write and erase cycles in a storage transistor depicting the write state threshold voltage (Vth) 401 and the erase state threshold voltage (Vth) 402.

FIG5 is an energy band diagram of an exemplary storage transistor, which has a channel region 501, a tunnel dielectric layer 502, and a charge trapping layer 503.

Figures 6(a), 6(b) and 6(c) respectively illustrate (i) the lowest energy levels of the conduction bands of the substrate 501, tunnel dielectric layer 502 and charge trapping layer 503 of a storage transistor; (ii) the lowest energy levels of the conduction bands of the layers before the storage transistor when no voltage is applied; and (iii) the electron energy shift 515 between the substrate 501 and the charge trapping layer 503 when an erase voltage is applied.

Figures 7(a), 7(b) and 7(c) respectively illustrate (i) the relative conduction band offsets of a substrate 601, a tunneling dielectric layer 602, a low conduction band step (LCBO) barrier dielectric 603 and a charge trapping layer 604 in a storage transistor; (ii) the energy band diagram of the aforementioned layers of the storage transistor without applying a voltage; and (iii) the electron energy offset 615 between the substrate 601 and the charge trapping layer 604 when an erase voltage is applied.

Figures 8(a), 8(b) and 8(c) depict the conduction band step parameters of the dielectric layers 602-604 in Figures 7(a)-7(c).

Figure 9(a) schematically illustrates direct tunneling in the storage transistor of Figure 7(a), and Figure 9(b) and Figure 9(c) illustrate MFN tunneling in the storage transistor of Figures 7(b) to 7(c) respectively. tunnel.

10(a) and 10(b) are energy band diagrams of the structure during write and erase operations based on a one volt voltage drop across the tunnel dielectric layer 602 (ie, during a write operation: b=1 eV , and during an erase operation: b'=1 eV ).

Figures 11(a), 11(b), 11(c) and 11(d) are various simulation results of the storage transistor in the present invention.

Figure 12(a) is an energy band diagram of the conduction band of a gate stack in a storage transistor during an erase operation.

FIG. 12(b) is a band diagram of the conduction band of a gate stack in a storage transistor during an erase operation, wherein the storage transistor has an additional aluminum oxide layer 607 in the blocking dielectric layer 610 according to an embodiment of the present invention.

FIG. 13(a) is a cross-sectional view of a three-dimensional array 1300 of NOR memory cells formed by thin film storage transistors described herein according to an embodiment of the present invention.

Figure 13(b) shows active stacks 1351-1 and 1351-2 of NOR memory groups in a three-dimensional array 1350 according to an embodiment of the present invention, and each NOR memory group includes a plurality of FeFETs as storage transistors.

Figure 14(a) shows the hysteresis of drain current versus gate voltage in a typical FeFET.

FIG. 14(b) shows the ideal hysteresis of the drain current (I _d ) against an applied gate voltage (V _g ) in a thin film FeFET in an inverter-gate memory array according to an embodiment of the present invention.

Figures 15(a), 15(b), 15(c) and 15(d) illustrate a first process for forming a three-dimensional memory array of thin-film FeFET transistors organized as a NOR memory group according to an embodiment of the present invention.

Figures 16(a), 16(b), 16(c) and 16(d) illustrate a second process for forming a three-dimensional memory array of thin-film FeFET transistors organized as a NOR memory group according to an embodiment of the present invention.

Figures 17(a), 17(b), 17(c), 17(d), 17(e), 17(f) and 17(g) illustrate a third process for forming a three-dimensional memory array of thin-film FeFET transistors organized as a NOR memory group according to an embodiment of the present invention.

To facilitate cross-referencing between the drawings, identical components are assigned the same symbol designations.

The aforementioned related application discloses a three-dimensional array of NOR memory banks, each of which is formed of a thin film storage transistor. Provisional Application III further discloses, for example, different methods of fabricating such three-dimensional array NOR memory banks. These three-dimensional arrays may be formed, for example, on a planar surface of a semiconductor substrate. In this detailed description, a Cartesian coordinate system is used to make the spatial relationships between the features shown in the figures clearer. In the coordinate system, the Z direction corresponds to a direction substantially perpendicular to the planar surface, and the directions corresponding to the X direction and the Y direction are orthogonal to each other and to the Z direction. The storage transistors of such NOR memory banks can be written to and erased in 100 nanoseconds (ns) or less, making them suitable for a variety of applications typical of volatile memory devices, such as dynamic Random Access Memory (DRAM) device. These thin film storage transistors of the related application have the advantage of retention times of several minutes compared to typical conventional DRAM devices of only a few milliseconds. Therefore, these thin film storage transistors can also be used as quasi-volatile storage transistors. In many applications, such quasi-volatile storage transistors should ideally have high endurance (e.g., in the range of 10 ¹¹ cycles) and preferably be usable at voltages of about 8-9 volts or less to be written or erased.

Fast write and fast erase operations require relatively high currents through the gate stack of the storage transistor. Figure 1 is an energy band diagram of a portion of a storage transistor, which includes multiple sub-layers of dielectric material and charge storage between a channel region and a gate electrode. As shown in Figure 1, various materials 120 between the channel region 110 and the gate electrode 114 allow data to be stored in the storage transistor. These materials include tunneling dielectric sublayer 111, charge trapping sublayer 112 (eg, silicon nitride), and blocking dielectric sublayer 113 (eg, silicon oxide). The charge trapping sublayer 112 and the blocking dielectric sublayer 113 may each be, for example, 4 nm thick. In Figure 1, line 101 depicts the lowest energy state in the conduction bands of various materials, and line 102 depicts the highest energy state in the valence bands of various materials. In such a system, to change the threshold voltage of the storage transistor by 1 volt in 100 nanoseconds, a write current density of approximately 5.0 amperes per square centimeter (5.0amps/cm ² ) is required. Using silicon dioxide as the tunneling dielectric sublayer 111, high current density can be achieved through a direct tunneling mechanism at a moderate electric field in the range of 10.0MV/cm.

Figure 2 shows the typical direct tunneling current density (gate current) for various SiO2 thicknesses under different bias conditions. As shown in Figure 2, even when the voltage across the SiO2 layer is less than 1.5 volts, a desired high current density (e.g., 5.0 amps/ ^cm2 ) can be achieved when the SiO2 thickness is less than 1.5 nm.

3(a) and 3(b) depict electrons tunneling directly into and out of the charge trapping sublayer 112 during write and erase operations, respectively. As shown in FIG. 3(a) , applying a write voltage through the gate electrode 114 and the channel region 110 reduces the tunneling dielectric sublayer 111 , the charge trapping sublayer 112 and the blocking dielectric sublayer relative to the channel region 110 113 conductor band. In particular, the lowest energy level in the conduction band of the charge trapping sublayer 112 is slightly lower than the lowest energy level in the conduction band of the channel region 110 , so that the energy level at the lowest energy level in the conduction band of the channel region 110 is The electrons tunnel directly into the charge trapping sublayer 112, as indicated by arrow 301 in Figure 3(a).

Likewise, as shown in FIG. 3(b) , applying an erase voltage through the gate electrode 114 and the channel region 110 increases the tunneling dielectric sublayer 111 , the charge trapping sublayer 112 and the blocking dielectric relative to the channel region 110 . The lowest energy level in the conduction band of sub-layer 113. The electric field imparts energy to the electrons at the allowed energy level of the charge trapping point in the charge trapping sublayer 112 to tunnel directly into the channel region 110, as shown by arrow 302 in FIG. 3(b).

As shown in Figures 3(a) and 3(b), fast writing and erasing can be achieved through the direct electron tunneling mechanism. In contrast, erasing through holes is a slow mechanism. In a floating-substrate quasi-volatile storage cell (such as the thin film storage transistor disclosed in the related application), for example, the holes in the channel region 110 are insufficient to provide a suitable hole current into the charge trapping sublayer 112; the same erasing mechanism of this storage transistor pulls electrons out of the charge trapping sublayer 112.

In a memory transistor, the voltage difference between the critical voltage of the memory transistor in the erased state and the programmed state is called the "programming window". The programming window shrinks or closes with the number of cycles in which the memory transistor is written and erased. This reduction in the programming window is due to, for example, interface state formation resulting in interface degradation between the channel region 110 and the tunnel dielectric 111. The reduction in the programming window may also be caused by charge trapping at other material interfaces, such as between the charge trapping sublayer 112 and the blocking dielectric sublayer 113. The endurance of a storage transistor refers to the number of write-erase cycles before the storage transistor cannot maintain an acceptable write window period. As shown in FIG3(a), the electrons that tunnel directly from the channel region 110 to the charge trapping sublayer 112 have low energy to enter the charge trapping sublayer 112, so they only lose a small portion of the energy in the lowest allowed energy state in the charge trapping sublayer 112. (That is, in the presence of the write voltage, the lowest energy levels in the conduction bands of the channel region 110 and the charge trapping sublayer 112 are very close.) These energy losses do not cause any significant damage to the charge trapping sublayer 112. In contrast, as depicted in FIG3(b), during an erase operation, the energy loss through electrons entering the channel region 110 is significantly larger. The huge energy loss will generate high energy holes (energetic holes) "hot holes" in the channel region 110, which are driven by the electric field of the erase voltage towards the gate electrode 114. Such hot holes cause interface traps at the interface between the channel region 110 and the tunnel dielectric sublayer 111. These interface traps are detrimental to the durability of the storage transistor and may in fact be the main cause of closing the write window. Those skilled in the art will also know that the hot hole phenomenon, known as the "anode hot hole injection mechanism", provides a dielectric breakdown model.

Figure 4 depicts the evolution of the write window in a storage transistor over ¹⁰⁹ write and erase cycles, which illustrates the write state threshold voltage 401 and the erase state threshold voltage 402.

The present invention improves the endurance of a storage transistor to over 10 ¹¹ write-erase cycles by utilizing a device structure that ensures that electrons tunnel out of a charge trapping layer into the channel region of the storage transistor (e.g., during an erase operation) at a desired low energy range (referred to as "cold electrons") so that the final holes generated are also low energy, thereby reducing damage to the write window. The device structure provides a direct tunneling write current density in excess of 1.0 amps/cm ² (e.g., 5.0 amps/cm ² ). The present invention is particularly advantageous for use in forming a storage layer of a thin film storage transistor in a three-dimensional memory structure, such as a quasi-volatile storage transistor in a three-dimensional array of NOR gate memory strings as disclosed in the aforementioned related applications.

One embodiment of the present invention is depicted by the model of FIG. 5 , which shows a conduction band boundary 511 and a valence band boundary 512 of an exemplary storage transistor, which has a channel region 501, a tunneling dielectric layer 502, and a charge trapping layer 503. As shown in FIG. 5 , arrow 514 indicates that electrons directly tunnel from the charge trapping layer 503 to the channel region 501. The energy difference (conduction band offset) between the lowest energy level in the conduction band of the charge trapping layer 503 and the lowest energy level in the conduction band of the channel region 501, as indicated by symbol 515, is the energy loss expected for electron tunneling.

The present invention obtains the conduction band compensation difference required in these layers relative to the semiconductor substrate (i.e., the channel region) of the storage transistor by carefully selecting a combination of a tunneling dielectric material and a charge trapping dielectric material. FIG6(a) shows the lowest energy level of the conduction band of the substrate 501, the tunneling dielectric layer 502, and the charge trapping layer 503 in the storage transistor. FIG6(b) shows the lowest energy level of the conduction band of the aforementioned layers in the storage transistor when no voltage is applied. FIG6(c) shows the electron energy offset 515 between the substrate 501 and the charge trapping layer 503 when an erase voltage is applied. The electron energy offset 515 depends on the conduction band compensation difference between the substrate 501 and each of the tunneling dielectric layer 502 and the charge trapping layer 503, and on the voltage applied during the erase operation. As shown in FIG6(c), for the tunneling dielectric layer 502, using different charge trapping materials as the charge trapping layer 503 has different conduction band compensation differences relative to the substrate layer 501, resulting in greater or less energy loss of the tunneling electrons reaching the substrate 501. Similarly, for the charge trapping layer 503, using different tunneling dielectric materials as the tunneling dielectric layer 502 has different conduction band compensation differences relative to the substrate layer 501, also resulting in greater or less energy loss of the tunneling electrons reaching the substrate 501.

Tunnel dielectric layer 502 can be as thin as 5-40 Angstroms (Å), and can be formed of silicon oxide (eg, SiO ₂ ), silicon nitride (SiN), or silicon oxynitride (SiON). The silicon oxide tunneling dielectric layer may be formed using conventional oxidation techniques (eg, a high temperature oxidation), chemical synthesis (eg, atomic layer deposition (ALD)), or any appropriate combination of the foregoing techniques. An active oxygen (O ₂ ) process may include an ozone step (eg using pulsed ozone) for precise thickness control and improved oxide quality (eg reducing leakage due to defective sites). The ozone step enhances solidification of the oxide in a conformal manner, which is particularly advantageous for three-dimensional transistor structures. An annealing step (eg, a hydrogen (H ₂ ) anneal, an ammonia (NH ₃ ) anneal, or a rapid thermal anneal) may also strengthen the tunnel dielectric layer 502. The silicon nitride tunneling dielectric layer may be formed using conventional nitridation, direct synthesis, chemical synthesis (eg, atomic layer deposition (ALD)), or a suitable combination of any of the foregoing techniques. Plasma processes can be used to precisely control thickness and improve dielectric quality (such as reducing leakage due to defective bits).

The tunnel dielectric layer 502 may also include an additional thin aluminum oxide (Al ₂ O ₃ ) layer (eg, 10 Å or thinner). The additional aluminum oxide layer in the tunnel dielectric layer may be synthesized in an amorphous phase to reduce leakage caused by defects.

The following materials may be used to provide the tunneling dielectric layer 502 and the charge trapping layer 503:

Using a lower conduction band offset in the charge trapping layer can effectively increase the tunneling barrier in the tunneling dielectric layer, thereby improving data retention.

Alternatively, a low conduction band compensation barrier material may be introduced into the storage transistor between the tunneling dielectric layer and the charge trapping layer. Figure 7(a)-Figure 7(c) are representative band diagrams of this structure. Figure 7(a) shows the relative conduction band compensation difference in the substrate 601 of the storage transistor, the tunnel dielectric layer 602, the low conduction band compensation difference barrier dielectric 603 and the charge trapping layer 604. Figure 7(b) is an energy band diagram of the aforementioned layer in the storage transistor when no voltage is applied. Figure 7(c) shows the electron energy shift 615 between the substrate 601 and the charge trapping layer 604 when an erasure voltage is applied. The electron energy shift 615 depends on the conduction band compensation difference between each of the substrate 601 and the tunneling dielectric layer 602, the low conduction band compensation difference barrier dielectric 603, and the charge trapping layer 604, and depends on the erase operation applied voltage. As shown in Figures 7(a) to 7(c), the conductive compensation difference of the low conduction band compensation difference (LCBO) barrier dielectric 603 is preferably smaller than that of the tunnel dielectric layer 602 and the substrate 601. charge trapping layer 604 Poor conductor band compensation. The materials of the tunneling dielectric layer 602, the barrier dielectric 603 with low conduction band compensation difference and the charge trapping layer 604 are carefully selected to achieve direct tunneling of cold electrons, regardless of writing or erasing operations, so as to store electricity. The crystals are highly durable.

Figures 8(a)-8(c) depict the conduction band compensation difference parameters of the dielectric layers 602-604 in Figures 7(a)-7(c). As shown in Figure 8(a), (i) parameter B represents the conduction compensation difference of the tunnel dielectric layer 602 relative to the substrate 601, (ii) parameter a represents the conduction band compensation difference of the LCBO barrier layer 603 relative to the tunneling dielectric layer 602. The conduction band compensation difference of the dielectric layer 602, (iii) parameter d represents the conduction compensation difference of the LCBO barrier layer 603 relative to the substrate 601, and (iv) parameter c represents the conduction compensation difference of the charge trapping layer 604 relative to the substrate 601. According to an embodiment of the present invention, the conductive compensation difference of the LCBO barrier layer 603 should be no greater than the conductive compensation difference of the charge trapping layer 604 (that is, d ≦ c ), so that a large amount of direct tunneling writing current density exceeds 1.0amps /cm ² (eg 5.0amps/cm ² ).

Figure 8(b) shows that the energy level at the bottom of the conduction band of the tunneling dielectric layer 602 is tilted due to the write voltage. Through the thickness of the tunnel dielectric layer 602, the sloping reduces the energy level of the tunnel dielectric layer 602 by a parameter b . In order to implement write operations through direct tunneling, parameter b should be greater than or equal to the value of parameter c (that is, b ≧ c ). The value of parameter b (in electron volts eV) is the product of the voltage drop across the tunnel dielectric layer 602 and the charge q (ie, 1.6×10 ⁻¹⁹ coulombs).

When the voltage drop of the tunnel dielectric layer 602 is smaller than the conductivity compensation difference of the charge trapping layer 604 (i.e., b < c ), the tunnel barrier becomes wider because at least a portion of the LCBO barrier layer 603 remains a tunnel barrier. In that case, direct tunneling can be replaced by a modified Fowler-Nordheim (MFN) mechanism to provide a much smaller current (e.g., less than 0.1 amps/ ^cm2 ) than direct tunneling.

In the storage transistor of Figures 7(a) to 7(c), Figure 9(a) shows direct tunneling under the application of a write voltage, Figure 9(b) and Figure 9(c) respectively show a MFN tunneling at low voltage (intermediate voltage) and one lower voltage. It can be understood that during operation of storage transistors, MFN tunneling may occur in the presence of low voltage disturbances. in the area. However, for a storage transistor having the structure depicted in Figures 7(a) to 7(c), such MFN tunneling current can be very low in the applied voltage range. The materials and thicknesses of the charge trapping layer 604 and the barrier layer 603 are selected so that the read disturb voltages, programming inhibit voltages, or erase inhibit voltages fall into a low voltage. or within the intermediate voltage range to limit tunneling to the MFN mechanism.

Thus, the storage transistor of the present invention has an important advantage: it has a high current due to direct tunneling at a write voltage, and only a low MFN tunneling current at a low voltage. This characteristic reduces interference under read, write inhibit or erase inhibit operations, and improves data retention and durability, especially the quasi-volatile storage transistor of the present invention that uses direct tunneling for fast write and erase operations. In this regard, since the holes generated in the channel region are low energy, the LCBO barrier layer 603 improves durability by allowing cold electron erase operations, reducing device degradation.

Since read disturb, write inhibit disturb or erase inhibit disturb all occur at a low voltage, the LCBO barrier layer 603 also improves data retention and durability and reduces read disturb, write inhibit disturb or erase inhibit disturb by limiting the tunneling to MFN tunneling at a low voltage. For example, write inhibit disturb or erase inhibit disturb occurs at a half-select voltage or a voltage lower than that used for write and erase operations respectively. All advantages are realized when the storage transistor is biased at a low voltage, while maintaining the high efficiency advantage of direct tunneling at a storage transistor biased at a higher read, write or erase voltage.

FIG8(c) shows the energy level of the bottom slope of the conduction band of the lower tunnel dielectric layer 602 during an erase operation. The slope (the slope) raises the energy level of the tunnel dielectric layer 602 by the parameter b ' through the thickness of the tunnel dielectric layer 602. During the erase operation, the electrons tunnel directly from the charge trapping layer 604 to the substrate 601 and lose energy represented by the parameter A , where the parameter A is related by A = b' + c . It is noted that the conduction band compensation difference of the charge trapping layer 604 should be larger than the amount of the energy level of the charge trapping point and the difference between the conduction band of the energy level so that the electrons at the charge trapping point are included in the direct tunneling current.

According to one embodiment of the present invention, the substrate 601 can be implemented by a P-doped silicon, the tunnel dielectric layer 602 can be implemented by a 1 nm thick silicon dioxide layer (SiO ₂ , B = 3.15 eV ), the low conductivity compensation barrier layer 603 can be implemented by a 2 nm thick titanium dioxide layer (Ti ₂ O ₅ , d = 0.3 eV ), the charge trapping layer 604 can be implemented by a 4 nm thick silicon-rich silicon nitride (i.e. SiN:Si, c = 1.35 eV ), and another 4 nm thick silicon dioxide layer can serve as a blocking dielectric layer. Unlike silicon nitride (stoichiometrically, Si ₃ N ₄ ), silicon-rich silicon nitride contains silicon as a dopant, which reduces the bandgap from 4.6 eV for silicon nitride to about 3.6 eV for silicon-rich silicon nitride. In addition, the refractive index of silicon nitride is 2.0, while the refractive index of silicon-rich silicon nitride ranges from 2.1-2.3. The gate electrode 606 can be implemented by a highly doped P-type polysilicon. Figures 10(a) and 10(b) are energy band diagrams of the structure during write and erase operations based on a one volt voltage drop across the tunnel dielectric layer 602 (i.e., b = 1 eV during a write operation, and b' = 1 eV during an erase operation). As shown by arrow 1001 in Figure 10(b), during an erase operation, an electron loses about 1.4 electron volts of energy by tunneling directly to the substrate 601. Dispersion in the LCBO barrier layer 603, as indicated by arrow 1002, can further reduce these energy losses.

According to another embodiment of the present invention, the substrate 601 can be implemented by P-doped silicon, the tunnel dielectric layer 602 can be implemented by a 1 nm thick silicon dioxide layer ( B = 3.15 eV ), the low conductivity compensation barrier layer 603 can be a 2 nm thick caesium dioxide layer (CeO ₂ , d = 0.6 eV ), the charge trapping layer 604 can be a 4 nm thick silicon-rich silicon nitride (Si ₃ N ₄ : Si, c = 1.35 eV ), and another 5 nm thick silicon dioxide layer can be used as a blocking dielectric layer 605. The gate electrode 606 can be implemented by a highly doped P-type polysilicon.

Figures 11(a) to 11(d) show various simulation results of the storage transistor in the present invention.

Figure 11(a) is a simulation of a storage transistor with a 0.8 nm thick silicon dioxide tunneling dielectric layer, a 2.0 nm thick zirconium dioxide LCBO barrier layer, and a 5.0 nm thick silicon-rich silicon nitride trapping layer. Figure 11(a) shows that at a write voltage of about 3.1 volts, a direct tunneling current density of more than 1.0 amps/cm ² can be achieved.

Figure 11(b) is a simulation of a storage transistor with a 1.0 nm thick silicon dioxide tunneling dielectric layer, a 2.0 nm thick LCBO barrier layer of n-O2, and a 4.0 nm thick silicon-rich silicon nitride trapping layer. Figure 11(b) shows that at a write voltage of about 1.6 volts, a direct tunneling current density of more than 1.0 amps/ ^cm2 can be achieved.

Figure 11(c) is a simulation of a storage transistor with a 1.0 nm thick silicon dioxide tunneling dielectric layer, a 2.0 nm thick LCBO barrier layer of tantalum pentoxide, and a 4.0 nm thick silicon-rich silicon nitride trapping layer. Figure 11(c) shows that at a write voltage of about 1.8 volts, a direct tunneling current density of more than 1.0 amps/ ^cm2 can be achieved.

Figure 11(d) is a simulation diagram of a storage transistor with a 1.0 nm thick silicon nitride tunneling dielectric layer, a 2.0 nm thick ceria LCBO barrier layer, and a 4.0 nm thick LCBO barrier layer. A capture layer of silicon-rich silicon nitride. Figure 11(d) shows that at a write voltage of approximately 2.1 volts, a direct tunneling current density exceeding 1.0amps/cm ² can be achieved.

Figure 12(a) depicts a "reverse injection electrons" phenomenon that may occur during an erase operation. Back-injected electrons may adversely affect durability. Figure 12(a) is an energy band diagram of the conduction band of the gate stack in a storage transistor during an erase operation. As shown in FIG. 12(a) , the gate stack includes a substrate 601, a tunnel dielectric 602, an LCBO barrier dielectric 603, a charge trapping layer 604, a blocking dielectric layer 605, and a gate electrode 606. (Blocking dielectric layer 605 may be, for example, silicon dioxide (SiO ₂ )). During an erase operation, the relatively high electric field across the blocking dielectric layer 605 may cause high-energy electrons, as indicated by arrow 1201 in Figure 12(a) , to tunnel from the gate electrode to the charge trapping layer 604, or even enter Tunnel dielectric layer 602. These back-injected electrons can damage these layers, adversely affecting the durability of the storage transistor.

According to one embodiment of the present invention, by including a material layer with a high dielectric constant (high-k material), such as aluminum oxide in a blocking dielectric layer (blocking dielectric layer 605 in Figure 10(a)) (Al ₂ O ₃ ), can significantly reduce or essentially eliminate reverse injection of electrons. In this embodiment, the gate electrode may use a high work function metal (for example, higher than 3.8 eV, preferably not less than 4.0 eV). The t _H of high-k materials provides an equivalent oxide thickness t _EOT as:

Among them, κ _ox and κ _H are the relative dielectric constants of silicon dioxide and high-k materials respectively. Therefore, a high-k material can provide the same required transistor characteristics (e.g. gate capacitance) at a thickness t _H without causing the incompatibility of its silicon dioxide counterpart at a much thinner equivalent thickness t _EOT Undesired leakage.

12(b) is an energy band diagram of the conduction band of the gate stack in a storage transistor having an additional aluminum oxide layer 607 in the blocking dielectric layer 610 according to an embodiment of the present invention during an erase operation. In FIG. 12(b) , the blocking dielectric layer 610 includes an aluminum oxide layer 607 and a silicon dioxide layer 608. In a practical aspect, the equivalent oxide thickness of blocking dielectric layer 610 is substantially the same as blocking dielectric layer 605 in FIG. 12(a). However, since the relative dielectric constant of alumina is 9.0 and that of silicon dioxide is 3.9, the actual combined physical thickness of alumina 607 and silicon dioxide 608 in Figure 12(b) is greater than that in Figure 12(a) ) the thickness of the barrier dielectric layer 605. Since the relative dielectric constant of the high-k dielectric layer 607 is greater than the relative dielectric constant of the silicon dioxide layer 608, the electric field in the high-k dielectric layer 607 is lower than the electric field in the silicon dioxide layer 608. The larger combined physical thickness of blocking dielectric layer 610 in Figure 12(b) (providing a wider tunneling barrier between gate electrode 606 and charge trapping layer 604), and the combination of gate electrode 606 and high-k A lower electric field at the interface between materials 607 reduces or eliminates reverse electron injection, thereby achieving improved durability. In conjunction with the high-k electrical layer 607 (such as aluminum oxide), a high work function metal is preferably used as the gate electrode. High work function metal at gate electrode-alumina interface A high barrier is generated (as indicated by barrier height 1202 in Figure 12(b)), which significantly reduces the erasure operation of reverse electron injection. Suitable high work function metals include: tungsten (w), tantalum nitride (TaN) and tantalum silicon nitride (TaSiN).

FIG. 13(a) is a cross-sectional view of a NOR memory group of a three-dimensional array 1300 formed of the aforementioned thin film storage transistors according to an embodiment of the present invention. As shown in FIG. 13(a) , stacks 1301-1 and 1301-2 of NOR memory groups are formed on a plane of a silicon substrate 1302. Stacks 1301-1 and 1301-2 represent a row of any suitable number (e.g., 2, 4, 6, 8, 16...) of active stacks, each row along the X direction and separated by isolation dielectric layer 203 ( For example, silicon oxycarbide (SiOC)) are separated from each other. Each active stack may contain any suitable number (e.g., 2, 4, 6, 8, 16...) of active multi-layers, and each active multi-layer may provide any suitable number (e.g., 8, 16...) ..., 2048, 4096...) storage transistors - forming one or more inverse-OR gate (NOR) memory banks - separated from each other along the Y direction. For example, stack 1301-1 in Figure 13(a) includes NOR memory banks 204-1 to 204-4. The inset of Figure 13(a) presents a cross-sectional view of storage transistor 1303 in a NOR memory bank of active stack 1301-2.

As shown in FIG. 13( a ), the storage transistor 1303 includes (i) a conductive layer 204a (e.g., a titanium nitride-lined tungsten layer), (ii) a first transistor material layer 204b such as an N ⁺ doped amorphous silicon or polycrystalline silicon layer (e.g., phosphorus or arsenic doped amorphous silicon or polycrystalline silicon), (iii) an oxide layer 204c, (iv) a second transistor material layer 204d such as N ⁺ doped amorphous silicon or polycrystalline silicon layer (e.g., phosphorus or arsenic doped amorphous silicon or polycrystalline silicon), (v) a conductor layer 204e (e.g., a titanium nitride lined tungsten layer), a third transistor material layer such as a channel region 250, the channel region 250 includes any channel region formed by any appropriate semiconductor material described above, a charge storage layer 251 (e.g., a composite layer that may include any tunneling layer, any charge trapping layer and any blocking layer described above), and a gate electrode or local word line 252 (e.g., any gate electrode described above). N ⁺ doped amorphous silicon or polysilicon layers 204b and 204d extend along the Y direction to form common source regions and common drain regions (“common bit lines”) for all storage transistors of the NOR gate memory group, respectively. Conductive layers 204a and 204e contact the common source regions and common bit lines, respectively, and are provided to reduce resistivity.

The three-dimensional array 1300 of NOR gate memory banks can be formed using any process or any combination of the aforementioned provisional application III or provisional application IV (e.g., in combination with the process discussed in FIGS. 2a-2j of provisional application III).

The inventors understand that the material used for the charge trapping layer of the above-described thin film storage transistor (eg, charge trapping layer 503 in FIG. 5), such as hafnium oxide, can have a ferroelectric polarization phase as is known in the art. The present inventors have realized that by utilizing these ferroelectric phases for data storage, thin film storage transistors in three-dimensional memory arrays of NOR memory banks can be easily adapted as ferroelectric field effect transistors ("FeFETs"). ”) operation, thereby providing high endurance, long data retention and relatively low voltage operation for erase (at 7.0 volts) and write (at -7.0 volts). High-speed random access (i.e., low read latency) can be achieved through thin-film ferroelectric field-effect transistors (FeFETs). The ferroelectric polarization phase characteristics of ferroelectric field-effect transistors are similar to those of the aforementioned thin-film horizontal (or vertical) NOR memories. The combination of three-dimensional organizations enables the additional benefits of high-density, low-cost memory arrays.

FIG. 13( b ) schematically shows active stacks 1351-1 and 1351-2 of NOR memory groups in a three-dimensional array 1350 according to an embodiment of the present invention, and each NOR memory group includes a plurality of FeFETs as storage transistors. In the three-dimensional array 1350 , each active stack (e.g., stack 1351-1) includes a plurality of NOR memory groups (e.g., NOR memory groups 254-1 to 254-4) formed by a plurality of FeFETs. The inset of FIG. 13( b ) shows a cross-sectional view of FeFET 1353 in an active stack 1351-2 of a NOR memory group.

FIG13( b) illustrates a representative FeFET 1353 in a NOR memory group in a three-dimensional array 1350. The representative FeFET 1353 includes (i) a conductor layer 204a (e.g., a titanium nitride-lined tungsten layer), (ii) a first transistor material layer 204b such as an N ⁺ doped amorphous silicon or polycrystalline silicon layer, (iii) an oxide layer 204c, (iv) a second transistor material layer 204d such as an N ⁺ doped amorphous silicon or polycrystalline silicon layer and (v) a conductor layer 204e (e.g., a titanium nitride-lined tungsten layer), which play similar roles to those layers assigned the same reference numerals as those in FIG13( a) and can provide substantially the same method. However, instead of the charge storage layer 251 of the storage transistor 1303, the FeFET 1353 has a ferroelectric storage layer 271, which may include a ferroelectric material and an interfacial dielectric layer. The FeFET 1353 has a third transistor material layer such as a channel material 270 and a gate electrode or local word line 272, the channel material 270 may be formed of the same or different material as the channel region 250, and the gate electrode or local word line 272 may be formed of the material of the gate electrode or local word line 252. As in the storage transistor of a NOR memory set of FIG13(a), the N ⁺ doped amorphous silicon or polysilicon layers 204b and 204d extend in length along the Y direction to form the common source region and the common drain region (“common bit line”) of all FeFETs of the NOR memory set of FIG13(b), respectively. Similarly, the conductive layers 204a and 204e in FIG13(b) are in contact with the common source region and the common bit line, respectively, and are provided to reduce the resistivity.

As described in detail herein, the semiconductor substrate in all embodiments of the present invention generally includes control, sensing and drive circuits to support the memory operation of the storage transistors or FeFETs in the three-dimensional array of NOR memory groups above it.

In some embodiments, to reduce interference between adjacent FeFETs, the ferroelectric storage layer 271 of FeFET 1353 in Figure 13(b) is preferably separated from the ferroelectric storage layers in the active stack of other active composite layers. , the charge storage layer 251 different from the storage transistor 1303 in FIG. 13(a) may be continuous with the charge storage layer in the active stack of other active composite layers.

According to one embodiment of the present invention, the channel region (channel material 270) of the FeFET 1353 can be formed in a three-dimensional memory array and can include p-doped polysilicon (e.g., 7.0-14.0 nm thick), and the gate electrode 272 can be formed of tungsten (W), molybdenum (Mo), aluminum (Al), ruthenium (Ru), tantalum (Ta), titanium (Ti), or any combination or alloy of these metals. The ferroelectric storage layer 271 may include an interfacial dielectric layer (e.g., silicon oxynitride (SiON), silicon _nitride ( _Si3N4 ), or silicon oxide ( _SiO2 ), 0.0 to 2.0 nm thick, with a refractive index between 1.5 and 2.0), and a ferroelectric material layer (e.g., zirconium-doped ferroxene oxide ( _HfO2 :Zr or HZO), aluminum-doped ferroxene oxide ( _HfO2 :Al), silicon-doped ferroxene oxide ( _HfO2 :Si), or titanium-doped ferroxene oxide ( _HfO2 :La)). The ferroelectric material layer may be, for example, 3.0 to 8.0 nm thick. The term HZO may include HfZrO, HfZrON, HfZrAlO, or any other HfZr oxide containing zirconium dopants. Based on the crystalline phase requirements of the ferroelectric material, the HZO ferroelectric material layer may be formed by deposition at a temperature between 200° C. and 330° C. (e.g., about 300° C.) using an atomic layer deposition (ALD) technique, followed by a post-deposition annealing step at a temperature between 400° C. and 1000° C.

Since tunneling of electrons or holes into the ferroelectric material layer may have an adverse effect on the polarization of the ferroelectric material layer, the interfacial dielectric layer isolates the ferroelectric material layer from the electrons or holes tunneling from the channel region during conduction. The interfacial dielectric layer can be formed of a material with a higher interface constant than silicon oxide (a "high-k" material, preferably with a dielectric constant greater than 3.9) to reduce the electric field during write or erase operations and reduce tunneling from the channel region. To obtain a 0.0 nm thick interfacial dielectric layer, the ferroelectric material layer can be deposited directly on the channel region (e.g., polysilicon) by atomic layer deposition (ALD) technology. A self-limiting thickness (e.g., 1.0-10.0 angstroms) of native oxide will be inherently formed at the interface of the channel region and the ferroelectric material layer. This approach is particularly advantageous when the channel region is formed after a high temperature step, so that contamination from dopant diffusion is less of a concern. In some embodiments, a bandgap-engineered tunneling layer (e.g., a multilayer of silicon oxide (SiO ₂ ) and zirconium oxide (ZrO ₂ )) can be used as an interfacial dielectric layer to help reduce tunneling into the ferroelectric material layer. The high-k dielectric properties of zirconium oxide reduce the electric field in the interfacial dielectric layer.

Ferroelectric field effect transistors can be polarized into a conducting or "erasing" state or a non-conducting or "writing" state. In a FeFET, its critical voltage in the erase state is lower than its critical voltage in the conduction band state. Figure 14(a) shows the hysteresis of the drain current (I _d ) versus an applied gate voltage (V _g ) in a typical FeFET. (A typical FeFET is formed on the plane of a single-crystal semiconductor substrate, rather than forming a thin-film field effect transistor.) In Figure 14(a), when the gate voltage changes from less than -1.0 volts Increasing to greater than 1.0 volts, waveform 1401 depicts the current drained by the FeFET in its erase state, and as the gate voltage decreases from greater than 1.0 volts to less than -1.0 volts, waveform 1402 depicts the current drained by the FeFET in its write state. As shown in Figure 14(a), a typical FeFET has a negative threshold voltage (V _t ).

However, in some applications it is desirable for FeFETs (such as thin film FeFETs in an inverter or gate memory bank) to have a positive threshold voltage (V _t ), such as around 0.5 volts, to prevent undesirable behavior when subjected to disturbing conditions. leakage current (e.g., selecting an adjacent FeFET in a NOR memory bank during a read operation, rather than the FeFET itself).

FIG14( b ) shows the ideal hysteresis of drain current (I _d ) versus applied gate voltage (V _g ) in a thin film FeFET in an NOR gate memory array according to an embodiment of the present invention. In FIG14( b ), waveform 1403 depicts the drain current of the FeFET in its erase state when the gate voltage increases from less than -1.0 volt to greater than 1.0 volt, and waveform 1404 depicts the drain current of the FeFET in its write state when the gate voltage decreases from greater than 1.0 volt to less than -1.0 volt. As shown in FIG14( b ), the FeFET has a positive critical voltage (V _t ) of about 0.5 V, and a critical voltage difference (“window”) between the erase state and the write state of 1.0 V to 2.5 V. For a p-polysilicon channel region (e.g., boron doped), the critical voltage can be achieved by (i) increasing the boron dopant concentration in the channel region, (ii) providing a gate electrode formed of a conductive material with a high work function (e.g., tungsten (W), molybdenum (Mo), aluminum (Al), ruthenium (Ru), tantalum (Ta), or titanium (Ti)), (iii) appropriate biasing in the common source region (see below), or (iv) a combination of (i), (ii), and (iii).

Table 1 summarizes exemplary bias voltages (V, volts) for a three-dimensional array of NOR memory cells during erase, write, and read operations on (i) the gate or word line, common source line, and common bit line of a selected FeFET and (ii) the non-selected word lines and bit lines of the three-dimensional memory array:

When the body region of a FeFET in a NOR memory set is floated, its write speed may be slower than its erase speed. Under such conditions, the gate-induced drain leakage (GIDL) effect can be beneficial to improve the write speed. During write, the GIDL effect can be activated by generating a voltage difference of 0.5 volts to 2.0 volts between the common bit line and the common source line, for example, by first pre-charging the common source line to a predetermined source line voltage at any time through the common bit line, and then setting the common bit line to its target voltage, as described in the related application.

During a read operation, when the thin film FeFET has a negative threshold voltage in the erase state, its common source line can be biased to a voltage higher than this threshold voltage to prevent unselected FeFETs in the NOR memory bank. conduction. It is important that during a read operation, the voltage between the gate or word line and the common bit line or common source line in the selected FeFET is maintained at a voltage that is less than a voltage that may change the polarization of the selected FeFET to avoid Read interference phenomenon.

Three-dimensional memory arrays of thin film FeFET transistors organized into NOR memory groups may be formed by adapting any suitable process or processes disclosed in Provisional Applications III and IV.

Figures 15(a)-15(d) depict a first process for forming a three-dimensional memory array of thin film FeFET transistors organized as NOR memory groups according to an embodiment of the present invention. After active stacks 1501-1 and 1501-2 are formed and deposited into the recesses of composite layers 251-1 to 251-4 and etched back to a channel material (e.g., p ^- doped amorphous silicon or polysilicon), Figure 15(a) illustrates the intermediate memory structure 1500 in cross-section in the top surface (e.g., XY plane) and XZ plane. In Figure 15(a), adjacent active stacks are separated by trenches 1502 and extend along the Y direction. The intermediate memory structure 1500 can be implemented using, for example, the process steps of FIGS. 2a to 2h of the provisional application III. In FIG. 15(a), the channel region (channel material 270) in the composite layer 251-4 is separated from the similar channel region in the composite layer 251-3 by the composite layer being sunken into the adjacent insulating dielectric layer 203 (e.g., SiOC). Therefore, the trench 1502 is filled with a dielectric material 1504 (e.g., silicon oxide), and the excess dielectric material is removed from the top of the intermediate memory structure 1500 by, for example, chemical mechanical polishing (CMP), resulting in the intermediate structure 1500 shown in FIG. 15(b).

A well 1505 (eg, an elliptical well) is then formed in the dielectric material 1504 filling the trench 1502 using a process as described in Provisional Application IV in connection with FIG. 2j. The resulting intermediate structure 1500 is shown in Figure 15(c). Wells 1505 expose the sidewalls of insulating dielectric layer 203 and channel material 270, respectively.

Next, self-assembled monolayers (SAMs; eg, substances with active hydroxyl (-OH) bonds) are provided to passivate the sidewalls of the insulating dielectric layer 203 . Ferroelectric storage layer 271 may then be selectively deposited on the exposed surface of channel material 270 . (The process of self-assembling a single layer prevents the ferroelectric storage layer 271 from being deposited on the sidewalls of the insulating dielectric layer 203.) The resulting intermediate structure 1500 is shown in 15(d). The ferroelectric storage layer 271 can be selectively deposited to form an interface dielectric layer and a ferroelectric material layer by using ALD technology in an ozone environment.

The interface dielectric layer may comprise a raw oxide layer formed from the surface of chemically cleaned channel material 270, followed by densification, such as by pulsed ozone or by thermal annealing in a hydrogen or deuterium environment, or any other known to those of ordinary skill in the art. Technology. Such treatment reduces electron leakage through the interface dielectric layer, reduces the surface state at the interface between the third semiconductor layer and the ferroelectric storage layer, or both. The ferroelectric material layer may be deposited using, for example, repeated cycles of hafnium oxide deposition and zirconium oxide deposition (for example, the ratio of HfO ₂ :ZrO ₂ is 4:1). For thicker ferroelectric material layers (e.g., greater than 40 nm), additional SAM processing between deposition cycles is preferable. Figure 15(d) includes an additional XY cross-sectional view 1510 of the memory structure 1500 along line AA' through the oxide layer 204c of the XY cross-sectional view. The three-dimensional array can then be completed using, for example, the process steps described in conjunction with Figures 21 to 2t of Provisional Application IV.

Figures 16(a)-16(d) depict a second process for forming a three-dimensional memory array whose thin film FeFET transistor structure is a NOR memory group according to an embodiment of the present invention. Active stacks 1601-1 and 1601-2 are formed and deposited into the recesses of composite layers 251-1 through 251-4 and etched back to a channel material (eg, p ^- doped amorphous silicon or polycrystalline silicon) to expose the insulating dielectric After the sidewalls of layer 203, Figure 16(a) illustrates an XZ plane cross-section of the intermediate memory structure 1600. As shown in Figure 15(a), adjacent active stacks in Figure 16(a) are separated by trenches (eg, trench 1602) and extend along the Y direction. The intermediate memory structure 1600 may be implemented using, for example, the process steps of Figures 2a to 2h of Provisional Application III.

However, the grooves of the composite layers 251-1 to 251-4 in FIG. 16(a) are deeper than the intermediate memory structure 1500 of FIG. 15(a). For example, for a target channel region (channel material 270) thickness of 10.0 nm, the grooves of the composite layers 251-1 to 251-4 are made 20.0 nm thick, resulting in the channel material 270 being 20.0 nm thick in the process step of FIG. 16(a). Further etching back to the channel region (channel material 270), such as by a wet etch, reduces the thickness of the channel region (channel material 270), such as to 10.0 nm, thereby producing grooves of approximately 10.0 nm deep between adjacent insulating dielectric layers 203. The intermediate memory structure 1600 is obtained as shown in Figure 16(b).

Next, the ferroelectric storage layer 271 can be formed by ALD deposition, and the interface dielectric layer and the ferroelectric material layer are formed on the channel material 270 in a 10 nm deep groove between the adjacent insulating dielectric layer 203. The ferroelectric material layer can be formed by, for example, repeated cycles of ferroelectric oxide deposition and zirconia deposition (for example, the ratio of HfO ₂ :ZrO ₂ is 4:1). The intermediate memory structure 1600 shown in FIG. 16( c ) is obtained. As shown in FIG. 16( c ), the composite ferroelectric storage layer 271 is separated from each other by the insulating dielectric layer 203 because of the grooves.

The three-dimensional array of NOR memory banks can be accomplished using, for example, the process steps described in connection with Figures 2j to 2t of Provisional Application IV. Figure 16(d) presents an X-Z cross-sectional view of a completed three-dimensional array of NOR memory banks, illustrating (i) conductive material 272 (eg, gate) in well 1605 and (ii) with adjacent gates and each other. Electrically isolated oxide 1604.

17(a)-17(g) depict a third process for forming a three-dimensional memory array whose thin film FeFET transistor structure is a NOR memory group according to an embodiment of the present invention. After forming active stacks 1701-1 and 1701-2 and depositing into the recesses of composite layers 251-1 through 251-4 and etching back a channel material (eg, p ^- doped amorphous silicon or polycrystalline silicon; eg, 20.0 nm thick ) to expose the sidewalls of the insulating dielectric layer 203, FIG. 17(a) illustrates the XZ plane cross-section of the intermediate memory structure 1700. As shown in Figure 16(a), adjacent active stacks in Figure 17(a) are separated by trenches (eg, trench 1702) and extend along the Y direction. Further etching back to the channel region (channel material 270 , for example by a wet etch) reduces the thickness of the channel region (channel material 270 ), for example to 10.0 nm, thereby creating proximity between adjacent insulating dielectric layers 203 10.0 nm deep grooves. The intermediate memory structure 1700 shown in Figure 17(b) is obtained. The intermediate memory structures 1700 of Figures 17(a) and 17(b) may be formed using substantially the same process steps discussed above for forming the intermediate memory structures 1600 of Figures 16(a) and 16(b) respectively. .

Then, the ferroelectric storage layer 271 can be deposited on the intermediate memory structure 1700 using the aforementioned ALD technology, for example, in combination with the previous FIG. 16( c ), followed by conformal deposition of the amorphous silicon liner 1707 , to obtain the intermediate memory structure 1700 as shown in FIG. 17( c ). The anisotropic dry etching step then removes a portion of the amorphous silicon liner 1707 to expose a portion of the ferroelectric storage layer 271 on the sidewalls of the insulating dielectric layer 203 in the trench 1702, while allowing the remaining amorphous silicon liner 1707 to protect a portion of the ferroelectric storage layer 271 in the grooves of the composite layers 251-1 to 251-4. The anisotropic dry etching also sputters the amorphous silicon liner 1707 and the ferroelectric storage layer 271 from the top of the intermediate memory structure 1700. The intermediate memory structure 1700 is obtained as shown in Figure 17(d).

Next, wet etching for removing the ferroelectric material layer (e.g., zirconium doped oxide HZO) removes the ferroelectric storage layer 271 from the sidewalls of the insulating dielectric layer 203. The intermediate memory structure 1700 shown in FIG. 17(e) is obtained. The remaining amorphous silicon liner 1707 can then be removed by wet etching. The intermediate memory structure 1700 shown in FIG. 17(f) is obtained.

Then, the three-dimensional array NOR memory set can be completed using, for example, the process steps described in conjunction with Figures 2j to 2t of Provisional Application IV. Figure 17(g) shows an X-Z cross-sectional view of a completed three-dimensional array NOR memory set, illustrating (i) conductive material 272 (e.g., gate) in well 1705 and (ii) oxide 1704 electrically isolated from adjacent gates.

According to another embodiment of the present invention, the channel region (channel material 270) of the FeFET 1353 can be formed of an oxidized semiconductor material (e.g., indium zinc oxide (InZnO or IZO)) with a thickness of 8.0 to 15.0 nm. The IZO channel region has the advantage of high mobility, which can improve switching performance without worrying about electron or hole tunneling. For example, compared to the electron mobility of aluminum zirconium oxide (AZO) of equivalent thickness of 5.6 cm ² /V, the electron mobility of a 10.0 nm thick IZO film is 40.6 cm ² /V. In addition, the common source region and the common bit line can be formed of a metal (e.g., Mo). The ferroelectric storage layer of the FeFET 1353 can be provided by any of the ferroelectric storage layers described above (e.g., a SiON interface dielectric layer and a HZO ferroelectric material layer). Since this FeFET does not have a p/n junction, any leakage current from the FeFET in the written state is relatively small. Therefore, such a FeFET is particularly advantageous for high temperature applications. Such a FeFET can also be constructed with a relatively short channel length because no margin is required to allow dopants to diffuse from the heavily doped semiconductor common bit lines and common source lines during any annealing steps affecting the channel region. Metal common bit and common source lines also reduce the thickness of the active composite layer (e.g., 40.0 nm common bit or common source line, 40.0 nm channel region and 30.0 nm SiOC interface dielectric layer, totaling a relatively thin 150.0 nm). Common source and drain regions can also be constructed using a sacrificial material that is replaced in a post-metal-replacement step.

The FeFETs of the three-dimensional "horizontal" NOR memory set disclosed herein have significant advantages because they are ferroelectric when constructing the three-dimensional memory structures disclosed herein (e.g., memory structures 1300, 1500, 1600, or 1700). A storage layer (eg, ferroelectric storage layer 271 in Figures 15(d), 16(d), or 17(j)) provides a relatively large surface area and, due to the advantage of its vertical orientation relative to the substrate, is only in A very small footprint is required on a semiconductor substrate. This larger surface area provides a tight distribution of voltage during erase and write states, which is difficult to achieve in highly-scaled planar FeFETs.

The FeFETs disclosed herein are demonstrated by tuning storage transistors in three-dimensional "horizontal" NOR memory strings, as disclosed in Provisional Applications III-IV. However, FeFETs can also be formed by tailoring storage transistors in three-dimensional "vertical" NOR memory strings, as disclosed in Provisional Application V, by substantially applying the principles and methods disclosed herein.

The above detailed description provides a description of a specific implementation of the present invention, but the present invention is not limited thereto. Many variations and modifications may be made within the scope of the present invention. For example, although the above detailed description illustrates that the present invention uses a thin film field effect transistor having a PN junction between semiconductor layers (e.g., polysilicon layers), the present invention may also be applied to junction-less transistors. In some embodiments, such a junction-less transistor may include a thin film junction-less transistor having a conductive oxide channel region. In some embodiments, suitable conductive metal oxides include gallium oxide, zinc oxide, indium oxide (e.g., indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO)) and any suitable conductive metal oxide whose charge carrier mobility is modulated or modulated using appropriate preparation or including appropriate dopants. For example, in one embodiment, a junction-less transistor of a low-resistance conductive material (e.g., tungsten (W), tungsten, cobalt, molybdenum lined with titanium nitride (TiN)) provides source and drain regions, and a conductive metal oxide (e.g., IGZO) provides a channel region, replacing a polysilicon thin film field effect transistor having N ⁺ polysilicon source and drain regions and a P ^- polysilicon channel region.

The following claims describe the invention.

203: Isolation dielectric layer (insulating dielectric layer)

204a, 204e: Conductor layer

204b: first transistor material layer (N ⁺ doped amorphous silicon or polycrystalline silicon layer)

204d: second transistor material layer (N ⁺ doped amorphous silicon or polycrystalline silicon layer)

204c: Oxide layer

250: Channel region (third transistor material layer)

254-1~254-4: NOR memory group

270: Channel material (third transistor material layer)

271: Ferroelectric storage layer

272: Gate electrode or local word line (conductive material)

1350: Three-dimensional array

1351-1, 1351-2: Active stacking

1353: Ferroelectric field effect transistor (FeFET)

Claims (32)

A memory group in a three-dimensional array formed on a plane of a semiconductor substrate. The memory group includes: a first, a second and a third transistor material layer. The third transistor material layer is formed to contacting the first layer of transistor material and the second layer of transistor material; a plurality of conductors; and a ferroelectric storage layer located between the conductors and the third layer of transistor material, wherein (i) the 1. The second and third transistor material layers, the ferroelectric storage layer and the conductors form a plurality of ferroelectric field effect transistors (FeFETs) for the memory group; (ii) the first The first and second transistor material layers respectively provide a common bit line and a common source line for the ferroelectric field effect transistors; (iii) the third transistor material layer provides a channel region for the memory group each of the ferroelectric field effect transistors; (iv) the ferroelectric storage layer provides a polarization layer to each of the ferroelectric field effect transistors; and (v) each of the conductors provides a gate electrode to One of the ferroelectric field effect transistors in the memory set; wherein at least a portion of the ferroelectric storage layer is deposited on an insulating dielectric layer using a selective atomic layer deposition technique. The memory set of claim 1, wherein the first and second transistor material layers each include a semiconductor layer of a first conductivity type, and the third transistor material layer includes a semiconductor layer different from the first conductivity type. A semiconductor layer of a second conductivity type. The memory set of claim 1, wherein the first and second transistor material layers each include a conductor layer, and the third transistor material layer includes a conductive metal oxide. A memory device as claimed in claim 3, wherein the conductive layer comprises one or more of titanium nitride-lined tungsten, tungsten, cobalt and molybdenum. A memory set as claimed in claim 3, wherein the conductive metal oxide comprises one or more of: gallium oxide, zinc oxide and indium oxide. The memory set of claim 5, wherein the indium oxide includes one or more of: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) and any material capable of modulating electrical current by including one or more impurities. Charge carrier mobility in conductive metal oxides. For example, the memory group of claim 1, wherein the ferroelectric field effect transistors (FeFETs) of the memory group form a NOR memory group. The memory set of claim 1, wherein the ferroelectric storage layer includes an interface dielectric layer and a ferroelectric material layer. A memory device as claimed in claim 8, wherein the interface dielectric layer comprises a metal having a dielectric constant greater than 3.9. The memory set of claim 8, wherein the interface dielectric layer includes one or more zirconium oxide (ZrO ₂ ), silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ) or silicon oxide (SiO ₂ ) . The memory set of claim 8, wherein the interface dielectric layer has a refractive index between 1.5 and 2.0. As in the memory set of claim 8, the thickness of the interface dielectric layer is between 0.0 and 2.0 nanometers. The memory set of claim 8, wherein the interface dielectric layer includes a primary oxide that is inherently formed when the layer of ferroelectric material is deposited directly on the layer of third transistor material. The memory set of claim 8, wherein the interface dielectric layer includes silicon oxide (SiO ₂ ) and a high- k dielectric material. The memory device of claim 14, wherein the high- k dielectric material comprises zirconium oxide (ZrO ₂ ). The memory set of claim 8, wherein the ferroelectric material layer comprises zirconium-doped bismuth oxide (HfO ₂ :Zr or HZO), aluminum-doped bismuth oxide (HfO ₂ :Al), silicon-doped bismuth oxide (HfO ₂ :Si), or onium-doped bismuth oxide (HfO ₂ :La), or any combination thereof. A memory set as claimed in claim 16, wherein the zirconium-doped zirconium oxide (HZO) comprises zirconium oxide (HfZrO), zirconium oxynitride (HfZrON), zirconium aluminum oxide (HfZrAlO), any combination thereof, or any other zirconium oxide containing zirconium impurities. A memory group as claimed in claim 8, wherein the three-dimensional array of memory groups is configured so that the ferroelectric material layer of each ferroelectric field effect transistor (FeFET) is separated from the ferroelectric material layers of the ferroelectric field effect transistors (FeFETs) in other memory groups. The memory set of claim 1, wherein the ferroelectric storage layer is deposited on the third transistor material layer using atomic layer deposition (ALD) technology at a temperature between 200°C and 330°C. A memory array as claimed in claim 19, wherein the temperature is between 270°C and 330°C. A memory device as claimed in claim 19, wherein the ferroelectric storage layer undergoes a post-deposition annealing step at a temperature between 400°C and 1000°C. A memory set as claimed in claim 1, wherein each of the conductors comprises tungsten (W), molybdenum (Mo), aluminum (Al), ruthenium (Ru), tantalum (Ta), titanium (Ti) or any combination thereof or alloy thereof. For example, in the memory set of claim 1, a conducting state critical voltage of each ferroelectric field effect transistor (FeFET) is greater than 0.0 volts. A memory device as claimed in claim 23, wherein the third transistor material layer is boron-doped. A memory set as claimed in claim 1, wherein each of the ferroelectric field effect transistors (FeFET) has a window period of 1.0 volts to 2.0 volts between the critical voltage of its conducting state and the critical voltage of its non-conducting state. The memory set of claim 1, wherein the third transistor material layer is floating during a write operation, wherein the write operation is performed with a bias voltage to provide a gate induced drain leakage (GIDL) effect. The memory group of claim 1, wherein the memory groups in the three-dimensional array are separated from each other by the insulating dielectric layer. A memory device as claimed in claim 1, wherein the selective atomic layer deposition technique involves self-assembled monolayers (SAMs) acting on the insulating dielectric layer. The memory set of claim 28, wherein the self-assembled monolayers (SAMs) comprise substances with hydroxyl termini. The memory set of claim 1, wherein the ferroelectric field effect transistors (FeFETs) of the memory set are arranged along a direction substantially parallel to the plane. The memory set of claim 1, wherein the ferroelectric field effect transistors (FeFETs) of the memory set are arranged along a direction substantially perpendicular to the plane. The memory set of claim 1, wherein a surface area of the channel region of each ferroelectric field effect transistor (FeFET) is larger than that of the ferroelectric field effect transistor (FeFET) on the plane of the semiconductor substrate. ) area.