TW202240869A - Thin-film storage transistor with ferroelectric storage layer - Google Patents

Abstract

By harnessing the ferroelectric phases in the charge storage material of thin-film storage transistors of a 3-dimensional array of NOR memory strings, the storage transistors are adapted to operate as ferroelectric field-effect transistors (“FeFETs”), thereby providing a very high-speed, high-density memory array.

Description

Thin film storage transistor with ferroelectric storage layer

The invention relates to a thin film storage transistor that can be programmed as a three-dimensional memory array. In particular, the invention relates to thin film transistors which may include a ferroelectric storage layer.

According to an embodiment of the present invention, a storage transistor has a tunneling dielectric layer and a charge trapping layer between a channel region and a gate, wherein the charge trapping layer has a conduction band offset- --Compared to an n-type silicon conduction band---When a write voltage is applied, the low point of the tunneling energy barrier in the tunneling dielectric layer is lower, allowing electrons to tunnel directly into the charge trapping layer. The conduction band compensation difference of the charge trapping layer is selected to have a value between -1.0 eV and 2.3 eV. In some embodiments, the charge trapping layer may include one or more of: hafnium oxide (HfO ₂ ), yttrium oxide (Y ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), oxide Zirconium (ZrSiO ₄ ), Lanthanum Oxide (La ₂ O ₃ ), Tantalum Oxide (Ta ₂ O ₅ ), Cerium Oxide (CeO ₂ ), Titanium Oxide (TiO ₂ ), Strontium Titanium Oxide (SrTiO ₃ ), Other Semiconductors and Metals Nanodots (e.g. silicon, ruthenium, platinum and cobalt nanodots).

According to an embodiment of the present invention, the storage transistor may further include an energy barrier layer between the tunneling dielectric layer and the charge trapping layer, and the energy barrier layer has a conduction band compensation difference which is smaller than that of the charge trapping layer. . The barrier layer may also comprise a material having a conduction band compensation difference between 1.0 eV and 2.3 eV, preferably between -1.0 eV and 1.5 eV, such as one or more of: hafnium oxide (HfO ₂ ), Yttrium oxide (Y ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), zirconia (ZrO ₂ ), zirconia (ZrSiO ₄ ), tantalum oxide (Ta ₂ O ₅ ), cerium oxide (CeO ₂ ), oxide Titanium (TiO ₂ ), strontium titanium oxide (SrTiO ₃ ), other semiconductor and metal nanodots (such as silicon, ruthenium, platinum and cobalt nanodots).

In one embodiment, when a voltage substantially less than the write voltage is applied across the channel region and the gate, electrons pass through an energy barrier wider than the thickness of the tunneling dielectric layer, by Fowler-Nordheim (Fowler-Nordheim) mechanism tunneling into the charge trapping layer.

In one embodiment, the tunneling dielectric layer may be as thin as 5-40 angstroms (Å), and may be formed of silicon oxide (eg, SiO ₂ ) or silicon nitride. The silicon oxide tunneling dielectric layer can be formed using typical oxidation techniques (such as a high temperature oxidation), chemical synthesis (such as atomic layer deposition), or any suitable combination of these techniques. An active oxygen (O ₂ ) process can include ozone for precise thickness control and improved oxide quality (eg, reducing leakage due to defect sites). The silicon nitride tunneling dielectric layer can be formed using typical nitridation techniques, direct synthesis, chemical synthesis (eg, by atomic layer deposition), or any suitable combination of these techniques. Plasma processing can be used to precisely control thickness and improve dielectric quality (eg, reduce leakage due to defective bits).

The tunneling dielectric layer may additionally include a thin aluminum oxide (Al ₂ O ₃ ) layer (eg, 10 Angstroms or less). The aluminum oxide layer in the tunneling dielectric layer can be synthesized in the amorphous phase to reduce leakage due to defect sites.

Further, according to an embodiment of the present invention, a memory group in a memory group of a three-dimensional array is formed on a plane of a semiconductor substrate, including: (a) a first and a first conductive type Two semiconductor layers; (b) a third semiconductor layer having a second conductivity type different from the first conductivity type to contact the first semiconductor layer and the second semiconductor layer; (c) a plurality of conductors; and (d ) a ferroelectric storage layer is located between the conductors and the third semiconductor layer, wherein (i) the first, second and third semiconductor layers, the ferroelectric storage layer and the conductors are formed for the memory group A plurality of ferroelectric field effect transistors (FeFET); (ii) the first and second semiconductor layers respectively provide a common bit line and a common source line to these ferroelectric field effect transistors; (iii) the second The three semiconductor layers provide a channel region to each of the ferroelectric field effect transistors in the memory pack; (iv) the ferroelectric storage layer provides a polarization layer to each of the ferroelectric field effect transistors; and (v) Each conductor provides a gate electrode to one of the ferroelectric field effect transistors in the memory bank. The memory banks can be organized into horizontal Negative OR (NOR) memory banks. The memory bank may be part of a three-dimensional array of memory banks in which the memory bank's thin-film ferroelectric field-effect transistors (FeFETs) are aligned along a direction substantially parallel to the plane of the inverted OR gate (NOR )Group. In another embodiment, the ferroelectric field effect transistors (FeFETs) of the memory group are aligned along a direction substantially perpendicular to the plane to form a vertical negative OR (NOR) thin film ferroelectric field effect Transistor (FeFETs) groups.

In one embodiment, the ferroelectric storage layer may include an interfacial dielectric layer and a ferroelectric material layer, wherein the interfacial dielectric layer has a dielectric coefficient in the range of 3.9 to greater than 2500.0, or any value greater than 3.9 value. The interfacial dielectric layer may comprise one or more of silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ) or silicon oxide (SiO ₂ ), providing a refractive index between 1.5 and 2.0. The thickness of the interfacial dielectric layer can be between 0.0 nm and 2.0 nm. The interfacial dielectric layer may include silicon oxide (SiO ₂ ) and zirconium oxide (ZrO ₂ ). In another embodiment, the interfacial dielectric layer may include a native oxide that is inherently formed when the ferroelectric material layer is deposited directly on the third semiconductor layer. Alternatively, the interfacial dielectric layer may be formed by chemically cleaning the surface of the third semiconductor layer, followed by, for example, pulsed ozone or by thermal annealing in a hydrogen or deuterium environment or any other technique known to those of ordinary skill in the art. A primary oxide formed by densification. This treatment reduces electron leakage through the interfacial dielectric layer and also reduces surface states at the interface between the third semiconductor layer and the ferroelectric storage layer.

In one embodiment, the ferroelectric material layer may include a zirconium-doped hafnium oxide (HfO ₂ :Zr or HZO), an aluminum-doped hafnium oxide (HfO ₂ :Al), a silicon-doped hafnium oxide (HfO ₂ :Si) or a lanthanum-doped hafnium oxide (HfO ₂ :La ), or any combination thereof. The term HZO may include hafnium zirconium oxide (HfZrO), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), any combination thereof, or any other hafnium oxide containing zirconium impurities.

Memory banks comprising three-dimensional arrays of ferroelectric field effect transistors can be organized such that the ferroelectric material layer of each ferroelectric field effect transistor (FeFET) is compatible with the ferroelectric fields in other memory banks. Separation of ferroelectric material layers in FeFETs.

In one embodiment, the ferroelectric storage layer of the ferroelectric field effect transistor may be deposited on the third semiconductor layer using atomic layer deposition (ALD) at a temperature between 200°C and 330°C, which The temperature is preferably between 270 °C and 330 °C. The ferroelectric storage layer is subjected to a post-deposition annealing step at a temperature between 400°C and 1000°C.

In one embodiment, the conductors in the memory group can be made of tungsten (W), molybdenum (Mo), aluminum (Al), ruthenium (Ru), tantalum (Ta), titanium (Ti), titanium nitride (TiN ) or any combination or alloy thereof.

The thin film ferroelectric field effect transistor of the present invention can have a conducting state voltage greater than 0.0 volts, and a wide window between its conducting state threshold voltage and its non-conducting state threshold voltage period (eg, 0.5 volts to 2.5 volts).

According to another embodiment of the present invention, a thin film ferroelectric field effect transistor (FeFET) may include a channel region formed of an oxide semiconductor material, and a metal source region or a metal bit line. The ferroelectric material of the channel layer between a thickness of 7.0 nm and 14.0 nm may include indium zinc oxide (InZnO or IZO), which has a thickness greater than or equal to 10.0 cm ² /V when the thickness of the channel region is greater than 7.0 nm. An electron mobility of . Metal source regions or metal bitlines may include molybdenum.

The present invention can be better understood through the following detailed description in conjunction with the accompanying drawings.

The aforementioned related application discloses a three-dimensional array of Negative OR (NOR) memory groups, each of which is formed by a thin film storage transistor. Provisional Application III further discloses, for example, different methods of fabricating such three-dimensional arrays of Negative OR (NOR) memory banks. These three-dimensional arrays can be formed, for example, on a planar surface of a semiconductor substrate. In this detailed description, a Cartesian coordinate system is employed to clarify the spatial relationship between the features shown in the drawings. In the coordinate system, the Z direction corresponds to a direction substantially perpendicular to the planar surface, and the directions corresponding to the X direction and the Y direction are orthogonal to each other and to the Z direction. The storage transistors of such a NOR memory group can be written and erased in 100 nanoseconds (ns) or less, making it suitable for many applications of typical volatile memory devices, such as dynamic random access memory (DRAM) device. The thin film storage transistors of the related application also have the advantage of a retention time of several minutes compared to a typical conventional DRAM device of only a few milliseconds. Therefore, these thin film storage transistors can also be used as quasi-volatile storage transistors. In many applications, such quasi-volatile storage transistors should preferably have high durability (e.g., in the range of 10 ¹¹ cycles) and preferably be usable at voltages of about 8-9 volts or less to be written or erased.

Fast write and fast erase operations require relatively high current through the gate stack of the storage transistor. 1 is an energy band diagram of a portion of a storage transistor including a channel region and a gate electrode between dielectric materials and various sublayers for storing charge. As shown in FIG. 1, various materials 120 between the channel region 110 and the gate electrode 114 allow data to be stored in the storage transistor. These materials include a tunneling dielectric sublayer 111 , a charge trapping sublayer 112 (such as silicon nitride), and a blocking dielectric sublayer 113 (such as silicon oxide). The charge trapping sublayer 112 and the blocking dielectric sublayer 113 can be, for example, 4 nm thick respectively. In FIG. 1 , line 101 depicts the lowest energy states in the conduction bands of various materials, and line 102 depicts the highest energy states in the valence bands of various materials. In such a system, to change the threshold voltage of the storage transistor by 1 volt in 100 nanoseconds, a write current density of approximately 5.0 amperes per square centimeter (5.0 amps/cm ² ) is required. Using silicon dioxide as the tunneling dielectric sublayer 111, high current densities can be achieved at a moderate electric field in the range of 10.0 MV/cm through a direct tunneling mechanism.

Figure 2 shows typical direct tunneling current densities (gate currents) for various SiO2 thicknesses under different bias conditions. As shown in FIG. 2, even though the voltage across the silicon dioxide layer is lower than 1.5 volts, the desired high current density (eg, 5.0 amps/cm ² ) can be achieved when the silicon dioxide thickness is less than 1.5 nm.

FIG. 3( a ) and FIG. 3( b ) depict electrons tunneling directly into and out of the charge-trapping sublayer 112 during write and erase operations, respectively. As shown in FIG. 3(a), the applied write voltage through the gate electrode 114 and the channel region 110 reduces the tunneling dielectric sublayer 111, the charge trapping sublayer 112 and the blocking dielectric sublayer relative to the channel region 110. 113 conduction band. In particular, the lowest energy level in the conduction band of the charge trapping sublayer 112 is slightly lower than the lowest energy level in the conduction band of the channel region 110, so that bits having energy at the lowest energy level in the conduction band of the channel region 110 The electrons directly tunnel into the charge trapping sublayer 112, as shown by arrow 301 in FIG. 3(a).

Similarly, as shown in FIG. 3(b), the application of the erase voltage through the gate electrode 114 and the channel region 110 improves the tunneling dielectric sublayer 111, the charge trapping sublayer 112 and the blocking dielectric layer relative to the channel region 110. The lowest energy level in the conduction band of the sublayer 113 . The electric field imparts energy to electrons at the allowable energy levels of the charge trapping sites in the charge trapping sublayer 112 to tunnel directly into the channel region 110, as indicated by arrow 302 in FIG. 3(b).

Fast writing and erasing can be achieved by direct electron tunneling mechanism as depicted in Figure 3(a) and Figure 3(b). In contrast, erasing through holes is a slow mechanism. In a floating-substrate quasi-volatile storage unit (such as the thin-film storage transistor disclosed in the related application), for example, the holes in the channel region 110 are not enough to provide a suitable hole current into the charge Trapping sublayer 112; the same erasing mechanism of the storage transistor pulls electrons out of the charge trapping sublayer 112.

In a storage transistor, the voltage difference between the threshold voltages of the storage transistor in an erased state and a programmed state is called a "programming window". The write window shrinks or closes with the number of cycles that the storage transistor is written and erased. This shrinking of the write window is due to the degradation of the interface between the channel region 110 and the tunneling dielectric 111 due to, for example, the formation of an interface state. The shrinking of the write window may also be caused by charge trapping at other material interfaces such as between the charge trapping sublayer 112 and the blocking dielectric sublayer 113 . The endurance of a storage transistor refers to the number of write-erase cycles before the storage transistor fails to maintain an acceptable write window. As shown in FIG. 3(a), the electrons that tunnel directly from the channel region 110 to the charge trapping sublayer 112 have low energy to enter the charge trapping sublayer 112, so they only lose a small portion of the electrons that are lowest in the charge trapping sublayer 112. The energy in the energy state is allowed. (That is, the lowest energy levels in the conduction bands of channel region 110 and charge-trapping sublayer 112 are very close in the presence of a write voltage.) These energy losses do not cause any appreciable effect on charge-trapping sublayer 112. harm. In contrast, as depicted in FIG. 3( b ), during an erase operation, the energy loss through electrons entering the channel region 110 is significantly greater. The huge energy loss will generate energetic holes (hot holes) in the channel region 110, which are driven towards the gate electrode 114 by the electric field of the erase voltage. Such hot holes cause interface traps at the interface between the channel region 110 and the tunneling dielectric sublayer 111 . These interface traps are detrimental to the durability of storage transistors and may in fact be the main cause of closing the write window. Those skilled in the art will also know that the hot hole phenomenon known as the "anode hot hole injection mechanism" provides a dielectric breakdown model.

FIG. 4 depicts the evolution of the write window over 10 ⁹ write and erase cycles in a storage transistor, which illustrates the write state threshold voltage 401 and the erase state threshold voltage 402 .

The present invention improves the endurance of storage transistors to exceed 10 ¹¹ write-erase cycles by utilizing a device structure that ensures electron tunneling in a desired low energy range (called "cold electrons") Exiting a charge-trapping layer into the channel region of the storage transistor (eg during an erase operation), the final hole generation is also low energy, thus reducing damage to the write window. The device structure provides a direct tunneling write current density substantially in excess of 1.0 amps/cm ² (eg, 5.0 amps/cm ² ). The present invention is particularly beneficial to use the storage layer of thin-film storage transistors formed in three-dimensional memory structures, such as the quasi-volatile storage transistors disclosed in the NOR memory strings of three-dimensional arrays disclosed in the aforementioned related applications.

An embodiment of the present invention is depicted by the model of FIG. 5, which shows a conduction band boundary 511 and a valence band boundary 512 of an exemplary storage transistor having a channel region 501, a tunneling dielectric layer 502, and a charge trapping layer. 503. As shown in FIG. 5 , an arrow 514 indicates that electrons directly tunnel from the charge trapping layer 503 to the channel region 501 . The energy difference (conduction band offset) between the lowest energy level in the conduction band of the charge trapping layer 503 and the lowest energy level in the conduction band of the channel region 501, as indicated by symbol 515, is an electron tunneling expected energy loss.

The present invention carefully selects a combination of a tunneling dielectric material and a charge trapping dielectric material to obtain the required conduction band compensation difference in these layers relative to the semiconductor substrate (that is, the channel region) of the storage transistor. FIG. 6( a ) is the lowest energy level of the conduction bands of the substrate 501 , the tunneling dielectric layer 502 and the charge trapping layer 503 in the storage transistor. Fig. 6(b) is the lowest energy level of the conduction band of the aforementioned layers in the storage transistor without applying a voltage. FIG. 6( c ) shows the electron energy offset 515 between the substrate 501 and the charge trapping layer 503 when an erase voltage is applied. The electron energy shift 515 depends on the difference in conduction band compensation between the substrate 501 and each of the tunneling dielectric layer 502 and the charge trapping layer 503 , and on the applied voltage for the erase operation. As shown in Figure 6(c), for the tunneling dielectric layer 502, using different charge trapping materials as the charge trapping layer 503 has a different conduction band compensation difference relative to the substrate layer 501, resulting in the tunneling dielectric layer 501 reaching the substrate 501. Tunneling electrons lose more or less energy. Similarly, for the charge trapping layer 503, using different tunneling dielectric materials as the tunneling dielectric layer 502 has a different conduction band compensation difference relative to the substrate layer 501, which also causes the tunneling electrons reaching the substrate 501 greater or less energy loss.

The tunnel dielectric layer 502 can be as thin as 5-40 angstroms (Å), and can be formed of silicon oxide (eg, SiO ₂ ), silicon nitride (SiN), or silicon oxynitride (SiON). The silicon oxide tunneling dielectric layer can be formed using conventional oxidation techniques (such as a high temperature oxidation), chemical synthesis (such as atomic layer deposition ALD), or any suitable combination of the foregoing techniques. An active oxygen (O ₂ ) process may include an ozone step (eg, using pulsed ozone) for precise thickness control and improved oxide quality (eg, reduced leakage due to defect sites). The ozone step enhances the curing of the oxide in a conformal manner, which is particularly beneficial for three-dimensional transistor structures. An annealing step (eg, a hydrogen (H ₂ ) anneal, an ammonia (NH ₃ ) anneal, or a rapid thermal anneal) can also strengthen the tunneling dielectric layer 502 . The silicon nitride tunneling dielectric layer can be formed using conventional nitridation, direct synthesis, chemical synthesis (eg, ALD), or any suitable combination of the foregoing techniques. Plasma processing can be used to precisely control thickness and improve dielectric quality (eg, reduce leakage due to defective bits).

The tunneling dielectric layer 502 may also include an additional thin aluminum oxide (Al ₂ O ₃ ) layer (eg, 10 Å or less). An additional aluminum oxide layer in the tunneling dielectric layer can be synthesized in an amorphous phase to reduce leakage due to defect sites.

The following materials can be used to provide the tunneling dielectric layer 502 and the charge trapping layer 503: Material Conduction Band Offset Silicon oxide (SiO ₂ ) 3.15 eV Hafnium oxide (HfO ₂ ) 1.5 eV Silicon Nitride (Silicon Nitride, Si ₃ N ₄ ) 2.4 eV Yttrium oxide (Yttrium oxide, Y ₂ O ₃ ) 2.3eV Zirconium dioxide (Zirconium oxide, ZrO ₂ ) 1.4 eV Zirconium silicon oxide (ZrSiO ₄ ) 1.5 eV Lanthanum oxide (Lanthanum oxide, La ₂ O ₃ ) 2.3eV Silicon oxinitrides (SiN:H) 1.3-2.4eV Tantalum pentoxide (Tantalum oxide, Ta ₂ O ₅ ) 0.3eV Cerium oxide (CeO ₂ ) 0.6 eV Titanium oxide (TiO ₂ ) 0.0 eV Strontium titanium oxide (SrTiO ₃ ) 0.0 eV Silicon-rich silicon nitride (SiN:Si) 1.35 eV Silicon nano dots 0.0 eV Ruthenium Nanodots -0.7eV Cobalt Nanodots -1.0 eV

Using a lower conduction band compensation difference in the charge trapping layer can effectively increase the tunneling barrier in the tunneling dielectric layer, thereby improving data retention.

Alternatively, a low conduction band compensating barrier material can be introduced into the storage transistor between the tunneling dielectric layer and the charge trapping layer. Figure 7(a)-Figure 7(c) are representative energy band diagrams for this structure. FIG. 7( a ) shows the relative conduction band compensation difference of the substrate 601 of the storage transistor, the tunneling dielectric layer 602 , the barrier dielectric 603 with low conduction band compensation difference, and the charge trapping layer 604 . Fig. 7(b) is an energy band diagram of the aforementioned layers in the storage transistor without applying a voltage. FIG. 7( c ) shows the electron energy shift 615 between the substrate 601 and the charge trapping layer 604 when an erase voltage is applied. The electron energy shift 615 depends on the conduction band compensation difference between the substrate 601 and the tunneling dielectric layer 602, the low conduction band compensation difference barrier dielectric 603, and the charge trapping layer 604, and depends on the erase operation the applied voltage. As shown in Figure 7(a)-Figure 7(c), a conduction compensation difference of the barrier dielectric 603 of the low conduction band compensation difference (LCBO) is preferably smaller than the tunneling dielectric layer 602 and the opposite substrate 601. The conduction band of the charge trapping layer 604 compensates for the difference. The materials of the tunneling dielectric layer 602, the barrier dielectric 603 with low conduction band compensation difference, and the charge trapping layer 604 are carefully selected. Whether it is writing or erasing, cold electrons can directly tunnel to make the stored electricity Crystals are highly durable.

8(a)-8(c) depict the conduction band compensation difference parameters of the dielectric layers 602-604 in FIGS. 7(a)-7(c). As shown in Figure 8(a), (i) parameter B represents the conduction compensation difference of the tunneling dielectric layer 602 relative to the substrate 601, (ii) parameter a represents the conduction band compensation difference of the LCBO barrier layer 603 relative to the tunneling The conduction band compensation difference of the dielectric layer 602, (iii) parameter d represents the conduction compensation difference of the LCBO barrier layer 603 relative to the substrate 601, and (iv) parameter c represents the conduction compensation difference of the charge trapping layer 604 relative to the substrate 601. According to an embodiment of the present invention, the conduction compensation difference of the LCBO barrier layer 603 should not be larger than the conduction compensation difference of the charge trapping layer 604 (that is, d ≦ c ), so that a large amount of direct tunneling write current density exceeds 1.0 amps /cm ² (eg, 5.0 amps/cm ² ).

FIG. 8( b ) shows that the energy level is tilted at the bottom of the conduction band of the tunneling dielectric layer 602 due to the write voltage. Through the thickness of the tunneling dielectric layer 602, the sloping lowers the energy level of the tunneling dielectric layer 602 by a parameter b . In order to implement write operations through direct tunneling, parameter b should be greater than or equal to the value of parameter c (that is, b ≧ c ). The value of the parameter b (in electron volts eV) is the product of the voltage drop across the tunneling dielectric layer 602 and the charge q (ie, 1.6×10 ⁻¹⁹ coulombs).

)，由於至少一部分的LCBO阻障層603保持一穿隧阻障，穿隧阻障會變寬。在那種情況下，直接穿隧可被改進的福勒-諾德漢(modified Fowler-Nordheim，MFN)機制取代，以提供一相對直接穿隧小得多的電流(例如小於0.1 amps/cm ²)。 When the voltage drop of the tunneling dielectric layer 602 is smaller than the conduction compensation difference of the charge trapping layer 604 (that is,

), since at least a portion of the LCBO barrier layer 603 maintains a tunnel barrier, the tunnel barrier becomes wider. In that case, direct tunneling can be replaced by a modified Fowler-Nordheim (MFN) mechanism to provide a much lower current than direct tunneling (eg, less than 0.1 amps/cm ² ).

In the storage transistor of Figure 7(a)-Figure 7(c), Figure 9(a) is a direct tunneling under the application of a write voltage, and Figure 9(b) and Figure 9(c) are a MFN tunneling at low voltage (intermediate voltage) and a lower voltage. It can be appreciated that MFN tunneling may occur in regions of low voltage disturbance during operation of the storage transistor. However, for storage transistors having the structures depicted in FIGS. 7( a )- 7 ( c ), such MFN tunneling current can be very low in the applied voltage range. The material and thickness of the charge trapping layer 604 and the barrier layer 603 are selected so that the read disturb voltages, programming inhibit voltages or erase inhibit voltages fall into a low voltage or in the range of intermediate voltages to limit tunneling to the MFN mechanism.

Thus, the storage transistor in the present invention has an important advantage: high current due to direct tunneling at write voltage, and low MFN tunneling current at a low voltage. This characteristic reduces disturbance under read, write inhibit, or erase inhibit operations, and improves data retention and durability, especially the quasi-volatile nature of the present invention utilizing direct tunneling for fast write and erase operations. permanent storage transistors. In this regard, since the holes generated in the channel region are of low energy, the LCBO barrier layer 603 improves durability by allowing cold electron erase operations, reducing device degradation.

The LCBO barrier layer 603 also improves data retention and durability by limiting tunneling to MFN tunneling at a low voltage since read disturb, write inhibit disturb, or erase inhibit disturb all occur at a low voltage And read disturb, write inhibit disturb or erase inhibit disturb is reduced. For example, write-inhibit or erase-inhibit occurs at a half-select voltage or a voltage lower than that used for write and erase operations, respectively. All of the advantages are realized when the storage transistor is biased at low voltages, while maintaining the advantages of high efficiency of direct tunneling when the storage transistor is biased at higher read, write or erase voltages.

。注意得是，電荷捕捉層604之導帶補償差應該比電荷捕捉點之能階的量和該能階之導帶之差還要大，以令位在電荷捕捉點的電子包含在直接穿隧電流中。 FIG. 8( c ) shows a sloped energy level at the bottom of the conduction band of the lower tunneling dielectric layer 602 during an erase operation. Through the thickness of the tunneling dielectric layer 602, the sloping increases the energy level of the tunneling dielectric layer 602 by a parameter b' . During the erasing operation, electrons tunneling directly from the charge trapping layer 604 to the substrate 601 lose energy represented by a parameter A , where the relationship between the parameter A is

. It should be noted that the conduction band compensation difference of the charge trapping layer 604 should be larger than the difference between the energy level of the charge trapping point and the conduction band of the energy level, so that the electrons at the charge trapping point are included in the direct tunneling current.

)實現，低導電補償差之阻障層603可由2奈米厚的二氧化鈦層(Ti ₂O ₅，

)實現，電荷捕捉層604可由4奈米厚的富矽之氮化矽(也就是SiN:Si，

)實現，以及另一4奈米厚的二氧化矽層可作為阻擋介電層。不同於氮化矽(化學計量地，Si ₃N ₄)，富矽之氮化矽包含矽作為摻雜，減少了由氮化矽4.6

至富矽之氮化矽約3.6

之能隙。此外，氮化矽之折射率為2.0，而富矽之氮化矽之折射率的範圍為2.1-2.3。閘電極606可由一高摻雜P型多晶矽來實現。圖10(a)及10(b)為基於橫跨穿隧介電層602的一伏特壓降下寫入及抹除操作期間結構之能帶圖(也就是一寫入操作期間下

，以及一抹除操作期間下

)。如圖10(b)中箭頭1001所示，在抹除操作期間，一電子通過直接穿隧到達基板601損失了大約1.4電子伏特的能量。在LCBO阻障層603中分散，如箭頭1002所指，可更加減少這些能量損失。 According to an embodiment of the present invention, the substrate 601 can be realized by a P-doped silicon, and the tunneling dielectric layer 602 can be made of a silicon dioxide layer (SiO ₂ ,

), the barrier layer 603 for low conductivity compensation can be made of a 2 nm thick titanium dioxide layer (Ti ₂ O ₅ ,

), the charge trapping layer 604 can be made of silicon-rich silicon nitride (that is, SiN:Si,

) to achieve, and another 4 nm thick silicon dioxide layer can be used as a blocking dielectric layer. Unlike silicon nitride (stoichiometrically, Si ₃ N ₄ ), silicon-rich silicon nitride contains silicon as a dopant, reducing the

To silicon-rich silicon nitride about 3.6

The energy gap. In addition, the refractive index of silicon nitride is 2.0, and the refractive index of silicon-rich silicon nitride is in the range of 2.1-2.3. The gate electrode 606 can be realized by a highly doped P-type polysilicon. 10(a) and 10(b) are energy band diagrams of the structures during write and erase operations based on a voltage drop across the tunneling dielectric layer 602 (that is, during a write operation).

, and during an erase operation under

). As shown by arrow 1001 in FIG. 10( b ), during the erase operation, an electron loses about 1.4 eV of energy by direct tunneling to the substrate 601 . Dispersion in the LCBO barrier layer 603, as indicated by arrow 1002, can further reduce these energy losses.

)實現，低導電補償差之阻障層603可由2奈米厚的二氧化鈰層(CeO ₂，

)，電荷捕捉層604可由4奈米厚的富矽之氮化矽(Si ₃N ₄:Si，

)，以及另一5奈米厚的二氧化矽層可作為阻擋介電層605。閘電極606可由一高摻雜P型多晶矽來實現。 According to another embodiment of the present invention, the substrate 601 can be realized by P-doped silicon, and the tunneling dielectric layer 602 can be made of a 1-nm thick silicon dioxide layer (

), the barrier layer 603 for low conductivity compensation can be made of a 2 nm thick ceria layer (CeO ₂ ,

), the charge trapping layer 604 can be made of silicon-rich silicon nitride (Si ₃ N ₄ : Si,

), and another 5 nm thick silicon dioxide layer can be used as the blocking dielectric layer 605 . The gate electrode 606 can be realized by a highly doped P-type polysilicon.

Fig. 11(a)-Fig. 11(d) are various simulation results of the storage transistor in the present invention.

Figure 11(a) is a simulation diagram of a storage transistor with a tunneling dielectric layer of 0.8 nm thick silicon dioxide, a 2.0 nm thick LCBO barrier layer of zirconia and a 5.0 nm thick Capture layer of silicon-rich silicon nitride. Figure 11(a) shows that at a writing voltage of about 3.1 volts, a direct tunneling current density exceeding 1.0 amps/cm ² can be achieved.

Figure 11(b) is a simulation diagram of a storage transistor with a tunneling dielectric layer of 1.0 nm thick silicon dioxide, a 2.0 nm thick LCBO barrier layer of ceria and a 4.0 nm thick Capture layer of silicon-rich silicon nitride. Figure 11(b) shows that at a writing voltage of about 1.6 volts, a direct tunneling current density exceeding 1.0 amps/cm ² can be achieved.

Figure 11(c) is a simulation diagram of a storage transistor with a tunneling dielectric layer of 1.0 nm thick silicon dioxide, a 2.0 nm thick LCBO barrier layer of tantalum pentoxide and a 4.0 nm thick The trapping layer of silicon-rich silicon nitride. Figure 11(c) shows that at a writing voltage of about 1.8 volts, a direct tunneling current density exceeding 1.0 amps/cm ² can be achieved.

Figure 11(d) is a simulation diagram of a storage transistor with a tunneling dielectric layer of 1.0 nm thick silicon nitride, a 2.0 nm thick LCBO barrier layer of ceria and a 4.0 nm thick Capture layer of silicon-rich silicon nitride. Figure 11(d) shows that at a writing voltage of about 2.1 volts, a direct tunneling current density exceeding 1.0 amps/cm ² can be achieved.

Figure 12(a) depicts a "reverse injection electrons" phenomenon that may occur during an erase operation. Reversely injected electrons may adversely affect durability. Figure 12(a) is a band diagram of the conduction band of a gate stack in a storage transistor during an erase operation. As shown in FIG. 12( a ), the gate stack includes a substrate 601 , a tunneling dielectric 602 , an LCBO barrier dielectric 603 , a charge trapping layer 604 , a blocking dielectric layer 605 and a gate electrode 606 . (The blocking dielectric layer 605 may be, for example, silicon dioxide (SiO ₂ )). During an erase operation, the relatively high electric field across the blocking dielectric layer 605 may cause high energy electrons, as indicated by arrow 1201 in FIG. 12(a), to tunnel from the gate electrode to the charge trapping layer 604, or even enter tunneling dielectric layer 602 . These back-injected electrons may damage these layers, adversely affecting the durability of the storage transistor.

提供一等效氧化物厚度

為： According to one embodiment of the present invention, by including a material layer with a high dielectric constant (high-k material), such as aluminum oxide in a blocking dielectric layer (such as the blocking dielectric layer 605 in FIG. 10(a)), (Al ₂ O ₃ ), can significantly reduce or substantially eliminate back-injected electrons. In this embodiment, a metal with a high work function (for example higher than 3.8 eV, preferably not less than 4.0 eV) can be used for the gate electrode. of high-k materials

Provides an equivalent oxide thickness

for:

及

分別為二氧化矽及高k材料的相對介電常數。因此，高k材料可以在一厚度

下，提供相同需求的電晶體特性(例如閘極電容)，而不會在相當薄的等效厚度

下，引起其二氧化矽層對應物之不期望的洩漏。 in,

and

are the relative permittivity of silicon dioxide and high-k materials, respectively. Therefore, high-k materials can be made in a thickness

, providing the same required transistor characteristics (e.g. gate capacitance) without at a considerably thinner equivalent thickness

, causing undesired leakage of its silicon dioxide layer counterpart.

12( b ) is an energy band diagram of the conduction band of the gate stack in a storage transistor with an additional aluminum oxide layer 607 in the blocking dielectric layer 610 according to an embodiment of the present invention during an erase operation. In FIG. 12( b ), the blocking dielectric layer 610 includes an aluminum oxide layer 607 and a silicon dioxide layer 608 . In an actual aspect, the equivalent oxide thickness of the blocking dielectric layer 610 is substantially the same as that of the blocking dielectric layer 605 in FIG. 12( a ). However, since the relative permittivity of alumina is 9.0 and that of silicon dioxide is 3.9, the actual combined physical thickness of alumina 607 and silicon dioxide 608 in Figure 12(b) is greater than that of Figure 12(a ) is the thickness of the blocking dielectric layer 605. Since the relative permittivity of the high-k dielectric layer 607 is greater than that of the silicon dioxide layer 608 , the electric field in the high-k dielectric layer 607 is lower than the electric field in the silicon dioxide layer 608 . The larger combined physical thickness of the blocking dielectric layer 610 in Figure 12(b) (providing a wider tunneling barrier between the gate electrode 606 and the charge trapping layer 604), and the gap between the gate electrode 606 and the high-k A lower electric field at the interface between materials 607 reduces or eliminates reverse electron injection, resulting in an improved durability. In conjunction with the high-k electrical layer 607 (for example, aluminum oxide), a high work function metal is preferably used as the gate electrode. The high work function metal creates a high barrier (as indicated by the barrier height 1202 in FIG. 12( b )) at the gate electrode-alumina interface, which significantly reduces the erasing operation of reverse electron injection. Suitable high work function metals include: tungsten (w), tantalum nitride (TaN) and tantalum silicon nitride (TaSiN).

FIG. 13( a ) is a cross-sectional view of a three-dimensional array 1300 of a Negative OR gate (NOR) memory group formed by the aforementioned thin film storage transistors according to an embodiment of the present invention. As shown in FIG. 13( a ), stacks 1301 - 1 and 1301 - 2 of Negative OR (NOR) memory groups are formed on a plane of a silicon substrate 1302 . Stacks 1301-1 and 1301-2 represent any suitable number (e.g., 2, 4, 6, 8, 16...) of actively stacked rows, each along the X direction and separated by a dielectric layer 203 (e.g., carbon Silicon Oxide (SiOC)) are separated from each other. Each active stack may comprise any suitable number (e.g. 2, 4, 6, 8, 16...) of active multi-layers (active multi-layer), and each active multi-layer provides any suitable number (e.g. 8, 16..., 2048, 4096…) of storage transistors – forming one or more NOR memory banks – separated from each other along the Y direction. For example, stack 1301-1 in FIG. 13(a) includes Negative OR (NOR) memory banks 204-1 to 204-4. The inset of FIG. 13(a) presents a cross-sectional view of storage transistor 1303 in a NOR memory group of active stack 1301-2.

As shown in Figure 13(a), the storage transistor 1303 includes (i) a conductor layer 204a (such as a titanium nitride-lined tungsten layer), (ii) an N ⁺ doped amorphous silicon or polysilicon layer 204b (such as phosphorus or arsenic doped amorphous silicon or polysilicon), (iii) oxide layer 204c, (iv) N ⁺ doped amorphous silicon or polysilicon layer 204d (for example phosphorus or arsenic doped amorphous silicon or polysilicon), (v) Conductor layer 204e (such as a titanium nitride-lined tungsten layer), channel layer 250 (such as any channel region formed by any suitable semiconductor material described above), charge storage layer 251 (such as a composite layer may include the above-described any tunneling layer, any charge trapping layer, and any blocking layer), and the gate electrode or local word line 252 (such as any gate electrode described above). The N ⁺ doped amorphous silicon or polysilicon layers 204b and 204d extend along the Y direction to respectively form a common source region and a common drain region (“common bit line”) of all storage transistors of the NOR memory group. Conductor layers 204a and 204e respectively contact the common source region and the common bit line and are provided to reduce resistivity.

The three-dimensional array 1300 of NOR banks can be formed using any or any combination of the aforementioned processes in Provisional Application III or Provisional Application IV (eg, processes discussed in connection with FIGS. 2a-2j in Provisional Application III).

The present inventors understand that the material used for the charge trapping layer of the thin film storage transistor described above (eg, charge trapping layer 503 in FIG. 5 ), such as hafnium oxide, may have a ferroelectric polarization phase as known in the art. The present inventors have realized that by utilizing these ferroelectric phases for data storage, thin-film storage transistors in three-dimensional memory arrays of NOR memory groups can be easily adapted as ferroelectric field-effect transistors ("FeFETs"). ”) operation, thereby providing high endurance, long data retention, and relatively low voltage operation for erasing (at 7.0 volts) and writing (at -7.0 volts). High-speed random access (i.e., low read delay) can be achieved by thin-film ferroelectric field-effect transistors (FeFETs), whose ferroelectric polarization phase characteristics are similar to those of the aforementioned thin-film horizontal (or vertical) NOR memory The combination of the 3-dimensional organization of the groups achieves the added benefit of high-density, low-cost memory arrays.

FIG. 13( b ) shows active stacks 1351 - 1 and 1351 - 2 of NOR memory groups in a three-dimensional array 1350 according to an embodiment of the present invention, and each NOR memory group includes many FeFETs as storage transistors. In three-dimensional array 1350, each active stack (eg, stack 1351-1) contains a number of NOR memory groups (eg, NOR memory groups 254-1 to 254-4) formed from a plurality of FeFETs. The inset of Figure 13(b) presents a cross-sectional view of FeFET 1353 in active stack 1351-2 of a NOR memory group.

FIG. 13( b ) illustrates representative FeFETs 1353 in a NOR memory group in a three-dimensional array 1350 . A representative FeFET 1353 includes (i) a conductor layer 204a (such as a titanium nitride-lined tungsten layer), (ii) an N ⁺ doped amorphous silicon or polysilicon layer 204b, (iii) an oxide layer 204c, (iv) a N ⁺ doped amorphous silicon or polysilicon layer 204d and (v) conductor layer 204e (eg a titanium nitride lined tungsten layer), similar to those layers assigned the same reference numerals in FIG. 13(a) function, and can provide essentially the same method. However, FeFET 1353 has ferroelectric storage layer 271 , which may include a ferroelectric material and an interfacial dielectric layer, instead of charge storage layer 251 of storage transistor 1303 . FeFET 1353 has channel region 270 and gate electrode or local wordline 272, which may be formed of the same or different materials as channel region 250 and gate electrode or local wordline 252, respectively. As in the storage transistor of a NOR memory group in Figure 13(a), the N ⁺ doped amorphous silicon or polysilicon layers 204b and 204d extend along the Y direction to form the NOR gates of Figure 13(b) respectively The common source and common drain regions ("common bit line") of all FeFETs of the memory bank. Likewise, conductor layers 204a and 204e in FIG. 13(b) are respectively in contact with the common source region and the common bit line and provided to reduce resistivity.

As described in detail herein, the semiconductor substrate in all embodiments of the present invention generally includes control, sensing, and drive circuitry to support memory operation of storage transistors or FeFETs in a three-dimensional array of NOR memory banks above it.

In some embodiments, to reduce interference between adjacent FeFETs, the ferroelectric storage layer 271 of FeFET 1353 in FIG. 13(b) is preferably separated from the ferroelectric storage layer in the active stack of other active recombination layers 13(a), the charge storage layer 251, which is different from the storage transistor 1303 in FIG. 13(a), may be continuous with the charge storage layer in the active stack of other active recombination layers.

According to an embodiment of the present invention, the channel region 270 of the FeFET 1353 may be formed in a three-dimensional memory array, may include p-doped polysilicon (eg, 7.0-14.0 nm thick), and the gate electrode 272 may be made of tungsten (W ), molybdenum (Mo), aluminum (Al), ruthenium (Ru), tantalum (Ta), titanium (Ti), or any combination or alloy of these metals. The ferroelectric storage layer 271 may include an interfacial dielectric layer (such as silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ) or silicon oxide (SiO ₂ ) with a thickness of 0.0 to 2.0 nm and a thickness of 1.5 to 2.0), and a ferroelectric material layer (such as zirconium-doped hafnium oxide (HfO ₂ :Zr or HZO), aluminum-doped hafnium oxide (HfO ₂ :Al), silicon-doped hafnium oxide (HfO ₂ :Si) or lanthanum-doped hafnium oxide (HfO ₂ :La )). The layer of ferroelectric material can be, for example, 3.0 to 8.0 nm thick. The term HZO may include hafnium zirconium oxide (HfZrO), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), or any other hafnium oxide containing zirconium impurities. Based on the crystalline phase requirements required for the ferroelectric material, the HZO ferroelectric material layer can be deposited at a temperature between 200 °C and 330 °C (eg around 300 °C) using atomic layer deposition (ALD) techniques formed with a post-deposition annealing step at a temperature between 400°C and 1000°C.

Since the tunneling of electrons or holes into the ferroelectric material layer may have adverse effects on the polarization of the ferroelectric material layer, the interfacial dielectric layer separates the ferroelectric material layer from the electrons or holes tunneled from the channel region during conduction. hole isolation. The interfacial dielectric layer can be formed of a material with a higher interfacial constant than silicon oxide ("high-k" material, preferably with a dielectric constant greater than 3.9) to reduce the electric field during write or erase operations and reduce the tunneling. To obtain a 0.0 nm thick interfacial dielectric layer, a layer of ferroelectric material can be deposited directly on the channel region (eg, polysilicon) by atomic layer deposition (ALD). A native oxide of a self-limiting thickness (eg, 1.0-10.0 Angstroms) will inherently form at the interface of the channel region and the ferroelectric material layer. This approach is particularly beneficial when the channel region is formed after a high temperature step, so that contamination by dopant diffusion is less of a concern. In some embodiments, bandgap-engineered tunneling layers (such as silicon oxide (SiO ₂ ) and zirconia (ZrO ₂ ) multilayers) can be used as interfacial dielectric layers, which are beneficial to reduce tunneling into ferroelectric material layer. The high-k dielectric properties of zirconia reduce the electric field in the interfacial dielectric layer.

Ferroelectric field effect transistors can be polarized into a conductive or "erase" state or a non-conductive or "write" state. In a FeFET, its threshold voltage in the erased state is lower than that in the conduction band state. Fig. 14(a) presents the hysteresis of drain current (I _d ) versus an applied gate voltage (V _g ) in a typical FeFET. (A typical FeFET is formed on the plane of a single crystal semiconductor substrate, rather than forming a thin-film field effect transistor.) In Figure 14(a), when the gate voltage is lower than -1.0 volts Increasing to greater than 1.0 volts, waveform 1401 depicts the current drawn by the FeFET in its erased state, and waveform 1402 depicts the current drawn by the FeFET in its written state as the gate voltage decreases from greater than 1.0 volts to less than -1.0 volts. As shown in FIG. 14( a ), a typical FeFET has a negative threshold voltage (negative threshold voltage, V _t ).

In some applications, however, it is desirable for FeFETs (such as thin-film FeFETs in an inverting-OR memory stack) to have a positive threshold voltage (V _t ), such as about 0.5 volts, to prevent undesirable leakage current (for example, selecting an adjacent FeFET in a NOR memory bank in a read operation, rather than the FeFET itself).

FIG. 14( b ) shows the ideal hysteresis of the drain current (I _d ) corresponding to an applied gate voltage (V _g ) in a thin film FeFET in an NOR memory array according to an embodiment of the present invention. In Figure 14(b), waveform 1403 depicts the FeFET sink current in its erased state when the gate voltage increases from less than -1.0 volts to greater than 1.0 volts, and when the gate voltage decreases from greater than 1.0 volts to less than -1.0 volts , waveform 1404 depicts the FeFET sink current in its written state. As shown in Figure 14(b), the FeFET has a positive threshold voltage (V _t ) of about 0.5 volts, and a threshold voltage difference ("window period window") between the erased and written states of 1.0 volts to 2.5 volts between. For a p-polysilicon channel region (e.g. boron doped), the threshold voltage can be achieved by (i) increasing the concentration of boron dopant in the channel region, (ii) providing a high work function conductive material such as tungsten (W ), molybdenum (Mo), aluminum (Al), ruthenium (Ru), tantalum (Ta) or titanium (Ti)), (iii) proper biasing in the common source region (see below) , or (iv) a combination of (i), (ii) and (iii).

Table 1 summarizes the common bit lines at (i) the gate or word line, common source line and a selected FeFET and (ii) the non-selected word lines of the 3D memory array Exemplary bias voltage (V, volts) during erase, write and read operations of (non-selected word lines) and bit lines, three-dimensional array of NOR memory: operate selected non-selected Gate/Word Line source drain character line source/bit line Erase 2.0 to 6.0V (eg 4.0V) 0V 0V eg, 1.0V 1.0 to 3.0V (eg 2.0V) Write (Program) 0V 3.0 to 6.0V (eg 4.0 V) 3.0 to 6.0V (eg 4.0 V) 1.0 to 3.0V (eg 1.0V) e.g. 2.0V read 1.0 to 3.0V 0.0V 0.05 to 1.0V 0.0V 0.0 to 1.0V Table 1

When the body region of an FeFET is floating in a NOR memory group, its writing speed may be slower than its erasing speed. Under such conditions, the Gate Induced Drain Leakage (GIDL) effect can be beneficial to improve the write speed. During writing, the GIDL effect can be initiated by creating a voltage difference between the common bit line and the common source line of 0.5 volts to 2.0 volts, for example, first switching the common bit line through the common bit line as described in the related application. The source line is pre-charged to a predetermined source line voltage at any time, and then the common bit line is set to its target voltage.

During a read operation, when thin-film FeFETs have a negative threshold voltage in the erased state, their common source line can be biased to a voltage higher than such threshold voltage to prevent conduction. It is important that during a read operation the voltage between the gate or word line and the common bit or common source line in the selected FeFET is maintained at a voltage less than that which would change the polarization of the selected FeFET to avoid The phenomenon of read interference.

The thin-film FeFET transistors of the three-dimensional memory array organized into NOR memory groups can be formed by adapting any suitable process or processes disclosed in Provisional Applications III and IV.

15(a)-15(d) depict a first process for forming a three-dimensional memory array of thin-film FeFET transistors organized as NOR memory groups according to an embodiment of the present invention. 15 ⁽ a) illustrates the intermediate memory structure 1500 in the top surface (eg.. XY plane) and in cross-section in the XZ plane. In FIG. 15( a ), adjacent active stacks are separated by trenches 1502 and extend along the Y direction. The intermediate memory structure 1500 can be implemented using, for example, the process steps of FIGS. 2a to 2h in Provisional Application III. In FIG. 15(a), channel region 270 in composite layer 251-4 is separated from a similar channel region in composite layer 251-3 due to the composite layer sinking into the adjacent insulating dielectric layer 203 (eg, SiOC). Thus, the trenches 1502 are filled with a dielectric material 1504 (such as silicon oxide), and excess dielectric material is removed from the top of the intermediate memory structure 1500 by, for example, chemical mechanical polishing (CMP), resulting in the result shown in FIG. 15(b). The intermediate structure 1500 is shown.

A well 1505 (eg, an elliptical well) is then formed in the dielectric material 1504 filling the trench 1502 using a process as described in provisional application IV in connection with FIG. 2j. The resulting intermediate structure 1500 is shown in Figure 15(c). The well 1505 exposes the sidewalls of the insulating dielectric layer 203 and the channel material 270, respectively.

Next, self-assembled monolayers (SAMs; eg, substances having active hydroxyl (-OH) bonds) are provided to passivate the sidewalls of the insulating dielectric layer 203 . Then, a ferroelectric storage layer 271 may be selectively deposited on the exposed surface of the channel material 270 . (Processing by the self-assembled monolayer prevents deposition of the ferroelectric storage layer 271 on the sidewalls of the insulating dielectric layer 203.) The resulting intermediate structure 1500 is shown in FIG. 15(d). The ferroelectric storage layer 271 can be selectively deposited by using ALD technology in an ozone environment to form an interfacial dielectric layer and a ferroelectric material layer.

The interfacial dielectric layer may comprise a native oxide layer formed by chemically cleaning the surface of the channel material 270, followed by densification, such as by pulsed ozone or by thermal annealing in a hydrogen or deuterium environment, or any other method known to those of ordinary skill in the art. technology. Such treatment reduces electron leakage through the interfacial dielectric layer, or reduces the surface state at the interface between the third semiconductor layer and the ferroelectric storage layer, or both. The ferroelectric material layer may be deposited using, for example, repeated cycles of hafnium oxide deposition and zirconium oxide deposition (eg HfO ₂ :ZrO ₂ ratio 4:1). For thicker ferroelectric material layers (eg, greater than 40 nm), additional SAM treatments between deposition cycles are preferred. FIG. 15( d ) includes an additional XY cross-sectional view 1510 of memory structure 1500 along line AA' through oxide layer 204c of the XY cross-sectional view. A three-dimensional array can then be completed using, for example, the process steps described in connection with Figures 21 to 2t of Provisional Application IV.

16(a)-16(d) depict a second process for forming a three-dimensional memory array of thin-film FeFET transistors organized as NOR memory groups according to an embodiment of the present invention. In the recesses where the active stacks 1601-1 and 1601-2 are formed and deposited into the composite layers 251-1 to 251-4 and etched back a channel material (such as p ^- doped amorphous silicon or polysilicon) to expose the insulating dielectric After the sidewalls of layer 203, FIG. 16(a) illustrates the intermediate memory structure 1600 in XZ plane cross-section. As shown in FIG. 15( a ), adjacent active stacks in FIG. 16( a ) are separated by trenches (such as trenches 1602 ) and extend along the Y direction. The intermediate memory structure 1600 can be implemented using, for example, the process steps of FIGS. 2a to 2h in Provisional Application III.

However, compared to the intermediate memory structure 1500 of FIG. 15( a ), the grooves of the composite layers 251 - 1 to 251 - 4 in FIG. 16( a ) are deeper. For example, for the target channel region 270 to be 10.0 nm thick, let the grooves of the composite layers 251-1 to 251-4 be 20.0 nm thick, so that the channel material 270 in the process step of FIG. 16(a) is 20.0 nm thick. Etching further back into the channel region 270 (e.g., by a wet etch) reduces the thickness of the channel region 270, for example, to 10.0 nm, thereby creating a groove approximately 10.0 nm deep between adjacent insulating dielectric layers 203 . The intermediate memory structure 1600 shown in FIG. 16(b) is obtained.

Next, the ferroelectric storage layer 271 can be formed by ALD deposition. The interfacial dielectric layer and the ferroelectric material layer are in the 10 nm deep groove between the adjacent insulating dielectric layers 203 on the channel material 270 . A layer of ferroelectric material may be used, for example, with repeated cycles of hafnium oxide deposition and zirconium oxide deposition (eg HfO ₂ :ZrO ₂ ratio 4:1). The intermediate memory structure 1600 shown in FIG. 16(c) is obtained. As shown in FIG. 16( c ), the ferroelectric storage layer 271 of the composite layer is separated from each other by the insulating dielectric layer 203 because of the grooves.

A three-dimensional array of NOR memory groups can be accomplished using, for example, the process steps described in connection with FIGS. 2j to 2t of Provisional Application IV. Figure 16(d) presents an X-Z cross-sectional view of a completed three-dimensional array of NOR memory groups, illustrating (i) the conductive material 272 (e.g., gate) in the well 1605 and (ii) the relationship between adjacent gates The oxide 1604 is electrically isolated.

17(a)-17(g) depict a third process for forming a three-dimensional memory array of thin-film FeFET transistors organized as NOR memory groups according to an embodiment of the present invention. In the recesses where active stacks 1701-1 and 1701-2 are formed and deposited into composite layers 251-1 to 251-4 and etched back a channel material (eg, p ^- doped amorphous silicon or polysilicon; eg, 20.0 nm thick ) to expose the sidewalls of the insulating dielectric layer 203 , FIG. 17( a ) illustrates the intermediate memory structure 1700 in cross-section on the XZ plane. As shown in FIG. 16( a ), adjacent active stacks in FIG. 17( a ) are separated by a trench (eg, trench 1702 ) and extend along the Y direction. Etching further back into the channel region 270 (e.g., by a wet etch) reduces the thickness of the channel region 270, for example, to 10.0 nm, thereby creating a groove approximately 10.0 nm deep between adjacent insulating dielectric layers 203 . The intermediate memory structure 1700 shown in Fig. 17(b) is obtained. The intermediate memory structure 1700 of Figures 17(a) and 17(b) can be formed using substantially the same process steps as previously discussed for forming the intermediate memory structure 1600 of Figures 16(a) and 16(b), respectively. .

Then, the ferroelectric storage layer 271 can be deposited and formed on the intermediate memory structure 1700 using the aforementioned ALD technique, for example, referring to the previous FIG. Conformal deposition. The intermediate memory structure 1700 shown in FIG. 17(c) is obtained. The anisotropic dry etching step then removes a portion of the amorphous silicon liner 1707 to expose a portion of the ferroelectric storage layer 271 on the sidewalls of the insulating dielectric layer 203 in the trench 1702 while allowing the remaining amorphous silicon The silicon lining 1707 protects part of the ferroelectric storage layer 271 in the grooves of the composite layers 251-1 to 251-4. The anisotropic dry etch also sputters away the amorphous silicon liner 1707 and the ferroelectric storage layer 271 from the top of the intermediate memory structure 1700 . The intermediate memory structure 1700 shown in Fig. 17(d) is obtained.

Next, a wet etch to remove the ferroelectric material layer (eg, zirconium-doped HZO) removes the ferroelectric storage layer 271 from the sidewalls of the insulating dielectric layer 203 . The intermediate memory structure 1700 shown in Fig. 17(e) is obtained. The remaining amorphous silicon liner 1707 can then be removed by wet etching. The intermediate memory structure 1700 shown in FIG. 17(f) is obtained.

Then, a three-dimensional array of NOR memory groups can be completed using, for example, the process steps described in connection with FIGS. 2j to 2t of Provisional Application IV. Figure 17(g) presents an X-Z cross-sectional view of a completed three-dimensional array of NOR memory groups, illustrating (i) the conductive material 272 (eg, gate) in the well 1705 and (ii) the relationship between adjacent gates The oxide 1704 is electrically isolated.

According to another embodiment of the present invention, the channel region 270 of the FeFET 1353 may be formed with 8.0 to 15.0 thick oxide semiconductor material such as indium zinc oxide (InZnO or IZO). The IZO channel region has the advantage of high mobility, which improves switching performance without worrying about electron or hole tunneling. For example, compared to 5.6 cm ² /V for aluminum zirconium oxide (AZO) with a comparable thickness, the electron mobility of a 10.0 nm thick IZO film is 40.6 cm ² /V. In addition, the common source region and the common bit line can be formed of metal (such as molybdenum Mo). The ferroelectric storage layer of FeFET 1353 can be provided by any of the ferroelectric storage layers described above, such as a SiON interfacial dielectric layer and a HZO ferroelectric material layer. Since this FeFET does not have a p/n junction, any leakage current from the FeFET in the written state is relatively small. Therefore, such FeFETs are particularly beneficial for high temperature applications. Such FeFETs can also be constructed with a relatively short channel length, since no margin is required to allow dopant diffusion from heavily doped semiconductor common-bit and common-source lines during any annealing steps affecting the channel region. Metal common-site lines and common-source lines also reduce the thickness of the active recombination layer (for example, 40.0nm common-site line or common-source line, 40.0nm channel region and 30.0nm SiOC interface dielectric layer, total for a relatively thin 150.0 nm). The common source and drain regions can also be constructed using a sacrificial material that is replaced in a later metal-replacement step.

The FeFETs of the three-dimensional "horizontal" NOR memory groups disclosed herein have significant advantages in that they are ferroelectric when constructing the three-dimensional memory structures disclosed herein (e.g., memory structures 1300, 1500, 1600, or 1700) The storage layer (such as the ferroelectric storage layer 271 in Figure 15(d), 16(d) or 17(j)) provides a relatively large surface area, and due to its vertical orientation with respect to the substrate, only in the A very small footprint is required on the semiconductor substrate. This large surface area provides a tight distribution of voltages in the erased and written states, which is difficult to achieve in highly-scaled planar FeFETs.

The FeFETs disclosed herein are illustrated by aligning storage transistors in three-dimensional "horizontal" NOR memory strings, as disclosed in provisional applications III-IV. However, FeFETs can also be formed by substantially applying the principles and methods disclosed herein by tuning the storage transistors in three-dimensional "vertical" NOR memory strings, as disclosed in Provisional Application V.

The above detailed description provides a depiction of specific embodiments of the invention but the invention is not limited thereto. Many variations and modifications are possible within the scope of the invention. For example, although the foregoing detailed description shows that the present invention uses thin film field effect transistors with PN junctions between semiconductor layers (such as polysilicon layers), the present invention is also applicable to junction-less transistors. In some embodiments, such a junctionless transistor may comprise a thin film junctionless transistor with a conductive oxide channel region. In some embodiments, suitable conductive metal oxides include gallium oxide, zinc oxide, indium oxide (e.g., indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO)) and Any suitable conductive metal oxide that modulates or modulates the mobility of its charge carriers. For example, in one embodiment, a junctionless transistor of low resistance conductive material (eg, titanium nitride (TiN) lined with tungsten (W), tungsten, cobalt, molybdenum) provides the source and drain region, and a conductive metal oxide (such as IGZO) provides the channel region, replacing the polysilicon thin film field effect transistor with N ⁺ polysilicon source and drain regions and P ^- polysilicon channel region.

The following claims set forth the invention.

101, 102: line 110: channel region 111: tunneling dielectric sublayer 112: charge trapping sublayer 113: blocking dielectric sublayer 114: gate electrode 120: material 203: isolation dielectric layer (insulating dielectric layer 204- 1~204-4: memory group 204a, 204e: conductor layer 204b, 204d: N ⁺ doped amorphous silicon or polysilicon layer 204c: oxide layer 250: channel layer 251: charge storage layer 251-1~251-4: Composite layer 252: gate electrode or local word line 254-1~254-4: NOR memory group 270: channel area (channel material) 271: ferroelectric storage layer 272: gate electrode or local word line (conductive material ) 301, 302, 514, 1001, 1002, 1201: Arrow 401: Writing state critical voltage 402: Erasing state critical voltage 501: Channel region 502: Tunneling dielectric layer 503: Charge trapping layer 511: Conduction band boundary 512 : valence band boundary 515: electron energy 516: hole energy 601: substrate 602: tunneling dielectric layer 603: barrier dielectric layer with low conduction band step 604: charge trapping layer 605: blocking dielectric layer 606: gate electrode 607: aluminum oxide (Al2O3) layer 608: silicon dioxide (SiO2) layer 610: blocking dielectric layer 615: electron energy offset 1202: barrier height 1300: NOR memory group 1301-1, 1301-2: stacking 1302 : Silicon substrate 1303: Storage transistor 1350: Three-dimensional array 1351-1, 1351-2: Active stacking 1353: Ferroelectric field effect transistor (FeFET) 1401, 1402, 1403, 1404: Waveform 1500: Intermediate memory structure 1501 -1, 1501-2: Active stacking 1502: Trench 1504: Dielectric material 1505: Well (oval well) 1510: XY cross section 1600: Intermediate memory structure 1601-1, 1601-2: Active stacking 1602: Groove Groove 1604: oxide 1605: well 1700: intermediate memory structure 1701-1, 1701-2: active stack 1702: trench 1704: oxide 1705: well 1707: amorphous silicon lining a, b, b', c , d, A, B: parameters A-A': line I _d drain current V _g gate voltage X, Y, Z: direction

FIG. 1 is an energy band diagram of a typical storage transistor, which includes a channel region and a dielectric material between gate electrodes and various sublayers for storing charge.

Figure 2 shows typical direct tunneling current densities (gate currents) for various SiO2 thicknesses under different bias conditions.

FIG. 3( a ) and FIG. 3( b ) depict electrons tunneling directly into and out of the charge-trapping sublayer 112 during write and erase operations, respectively.

FIG. 4 is an evolution diagram of write and erase cycles with a write window period exceeding 10 ⁹ times in a storage transistor, which depicts write state threshold voltage (Vth) 401 and erase state threshold voltage (Vth) 402.

FIG. 5 is an energy band diagram of an exemplary storage transistor, which has a channel region 501 , a tunneling dielectric layer 502 and a charge trapping layer 503 .

Fig. 6 (a), Fig. 6 (b) and Fig. 6 (c) respectively show (i) the lowest energy level ( lowest energy levels of the conduction bands); (ii) when no voltage is applied, the lowest energy level of the conduction band of the aforementioned layer of the storage transistor; and (iii) when an erasing voltage is applied, the substrate 501 and the charge trapping layer Electron energy offset 515 between 503 .

Fig. 7(a), Fig. 7(b) and Fig. 7(c) respectively show (i) the barrier dielectric in the substrate 601 of a storage transistor, the tunnel dielectric layer 602, and the low conduction band step (LCBO). 603 and the charge trapping layer 604 relative conduction band offsets (relative conduction band offsets); (ii) without applying a voltage, the energy band diagram of the aforementioned layers of the storage transistor; and (iii) when an erase voltage is applied , the electron energy shift 615 between the substrate 601 and the charge trapping layer 604 .

FIG. 8(a), FIG. 8(b) and FIG. 8(c) depict the conduction band step parameters of the dielectric layers 602-604 in FIG. 7(a)-FIG. 7(c).

Figure 9(a) schematic diagram 7(a) direct tunneling in the storage transistor, and Figure 9(b) and Figure 9(c) respectively schematic diagram 7(b)-Figure 7(c) MFN tunneling in the storage transistor tunnel.

10(a) and FIG. 10(b) are energy band diagrams of the structures during write and erase operations based on a voltage drop across the tunneling dielectric layer 602 (that is, during a write operation: b =1 eV , and during an erase operation: b'=1 eV ).

Fig. 11(a), Fig. 11(b), Fig. 11(c) and Fig. 11(d) are various simulation results of the storage transistor in the present invention.

Figure 12(a) is a band diagram of the conduction band of a gate stack in a storage transistor during an erase operation.

Figure 12(b) is an energy band diagram of the conduction band of the gate stack in a storage transistor with an additional aluminum oxide layer 607 in the blocking dielectric layer 610 according to an embodiment of the present invention during an erase operation .

FIG. 13( a ) is a cross-sectional view of a three-dimensional array 1300 of a Negative OR (NOR) memory group formed by the thin film storage transistors described herein according to an embodiment of the present invention.

FIG. 13( b ) shows active stacks 1351 - 1 and 1351 - 2 of NOR memory groups in a three-dimensional array 1350 according to an embodiment of the present invention, and each NOR memory group includes many FeFETs as storage transistors.

Figure 14(a) presents the hysteresis of sink current versus gate voltage in a typical FeFET.

FIG. 14( b ) shows the ideal hysteresis of the drain current (I _d ) corresponding to an applied gate voltage (V _g ) in a thin film FeFET in an NOR memory array according to an embodiment of the present invention.

Fig. 15(a), Fig. 15(b), Fig. 15(c) and Fig. 15(d) depict according to an embodiment of the present invention, the thin film FeFET transistor structure forming a three-dimensional memory array is a first NOR memory group One process.

Fig. 16(a), Fig. 16(b), Fig. 16(c) and Fig. 16(d) depict a first embodiment of a NOR memory group in which the thin film FeFET transistors forming a three-dimensional memory array are organized according to an embodiment of the present invention Second process.

Figure 17(a), Figure 17(b), Figure 17(c), Figure 17(d), Figure 17(e), Figure 17(f) and Figure 17(g) depict according to an embodiment of the present invention, forming The thin film FeFET transistor structure of the three-dimensional memory array is a third process of the NOR memory group.

In order to facilitate cross-referencing between the figures, the same elements are assigned the same reference numerals.

203: isolation dielectric layer (insulation dielectric layer

204a, 204e: conductor layer

204b, 204d: N ⁺ doped amorphous silicon or polysilicon layer

204c: oxide layer

250: channel layer

254-1~254-4: NOR memory group

270: Channel area (channel material)

271: Ferroelectric storage layer

272: Gate electrode or local word line (conductive material)

1350: Three-dimensional array

1351-1, 1351-2: active stacking

1353: Ferroelectric Field Effect Transistor (FeFET)

Claims (42)

A memory group in a three-dimensional array formed on a plane of a semiconductor substrate, the memory group comprising: a first, a second and a third layer of transistor material, the third layer of transistor material formed to contact the first layer of transistor material and the second layer of transistor material; a plurality of conductors; and a ferroelectric storage layer located between the conductors and the third transistor material layer, wherein (i) the first, the second and the third transistor material layers, the ferroelectric storage layer and the These conductors form a plurality of ferroelectric field effect transistors (FeFETs) for the memory set; (ii) the first and second transistor material layers respectively provide a common bit line and a common source line to the ferroelectric field effect transistor; (iii) the third transistor material layer provides a channel area to each of the ferroelectric field effect transistors in the memory group; (iv) the ferroelectric storage layer provides a a polarization layer for each of the ferroelectric field effect transistors; and (v) each of the conductors provides a gate electrode to one of the ferroelectric field effect transistors in the memory bank. A memory group as claimed in item 1 of the scope of the patent application, wherein each of the first and second transistor material layers includes a semiconductor layer of a first conductivity type, and the third transistor material layer includes a semiconductor layer different from the A semiconductor layer of the first conductivity type and a second conductivity type. A memory group according to claim 1, wherein the first and second transistor material layers each include a metal layer, and the third transistor material layer includes a conductive metal oxide. A memory set according to claim 3, wherein the metal layer comprises one or more of titanium nitride-lined tungsten, tungsten, cobalt and molybdenum. A memory group as claimed in item 3 of the patent application, wherein the conductive metal oxide comprises one or more of: gallium oxide, zinc oxide and indium oxide. A memory group as claimed in claim 5, wherein the indium oxide comprises one or more of: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) and any Conductive metal oxides to modulate charge carrier mobility. A memory group as claimed in item 1 of the scope of the patent application, wherein the ferroelectric field effect transistors (FeFETs) of the memory group form a Negative OR gate (NOR) memory group. A memory group according to item 1 of the scope of the patent application, wherein the ferroelectric storage layer includes an interfacial dielectric layer and a ferroelectric material layer. A memory group according to claim 8, wherein the interfacial dielectric layer comprises a metal with a dielectric coefficient greater than 3.9. A memory assembly as claimed in claim 8, wherein the interfacial dielectric layer comprises one or more of zirconia (ZrO ₂ ), silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ) or silicon oxide (SiO ₂ ). A memory group according to claim 8, wherein the interfacial dielectric layer has a refractive index between 1.5 and 2.0. A memory group as claimed in claim 8, wherein the interface dielectric layer has a thickness between 0.0 and 2.0 nanometers. A memory device according to claim 8, wherein the interfacial dielectric layer includes a native oxide inherently formed when the ferroelectric material layer is directly deposited on the third semiconductor layer. A memory group according to claim 8, wherein the interfacial dielectric layer includes silicon oxide (SiO ₂ ) and a high- k dielectric material. A memory device according to claim 14, wherein the high- k dielectric material comprises zirconia (ZrO ₂ ). A memory group according to item 8 of the scope of the patent application, wherein the ferroelectric material layer comprises a zirconium-doped hafnium oxide (HfO ₂ :Zr or HZO), an aluminum-doped hafnium oxide (HfO ₂ :Al), a Silicon-doped hafnium oxide (HfO ₂ :Si) or lanthanum-doped hafnium oxide (HfO ₂ :La ), or any combination thereof. A memory group according to item 16 of the scope of the patent application, wherein the zirconium-doped hafnium oxide (HZO) includes hafnium zirconium oxide (HfZrO), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), Any combination thereof, or any other hafnium oxide containing zirconium impurities. A memory group as in item 8 of the scope of the patent application, wherein the memory group of the three-dimensional array is composed such that the ferroelectric material layer of each of the ferroelectric field effect transistors (FeFET) and other memory groups The ferroelectric material layers of the ferroelectric field effect transistors (FeFETs) are separated. A memory set according to claim 1, wherein the ferroelectric storage layer is deposited on the third semiconductor layer at a temperature between 200°C and 330°C using atomic layer deposition (ALD). A memory group as claimed in claim 19, wherein the temperature is between 270°C and 330°C. A memory set according to claim 19, wherein the ferroelectric storage layer undergoes a post-deposition annealing step at a temperature between 400°C and 1000°C. A memory group as claimed in item 1 of the scope of the patent application, wherein each of the conductors comprises tungsten (W), molybdenum (Mo), aluminum (Al), ruthenium (Ru), tantalum (Ta), titanium (Ti) or Any combination or alloy thereof. A memory group as claimed in claim 1, wherein each of the ferroelectric field effect transistors (FeFET) has a conducting state threshold (conducting state) voltage greater than 0.0 volts. A memory set according to claim 23, wherein the third transistor material layer is boron doped. A memory group as claimed in claim 1, wherein each of the ferroelectric field-effect transistors (FeFET) has a voltage between its critical voltage in its conduction state and its critical voltage in its non-conduction state with a voltage of 1.0 volts to 2.0 volt window. A memory group as claimed in claim 1, wherein the third transistor material layer is floating during a write operation, wherein the write operation is performed together with a bias voltage to provide a gate induced drain leakage ( GIDL) effect. A memory group according to item 1 of the patent scope, wherein the memory groups in the three-dimensional array are separated from each other by an insulating dielectric layer. A memory group as claimed in claim 27, wherein at least a part of the ferroelectric storage layer is deposited on the insulating dielectric layer using a selective atomic layer deposition technique, the selective atomic layer deposition technique involves Self-assembled monolayers (SAMs) act on this insulating dielectric layer. A memory set according to claim 27, wherein the self-assembled monolayers (SAMs) comprise substances with hydroxyl ends. A memory group as claimed in claim 1, wherein the ferroelectric field effect transistors (FeFETs) of the memory group are arranged along a direction substantially parallel to the plane. A memory group according to claim 1, wherein the ferroelectric field effect transistors (FeFETs) of the memory group are arranged along a direction substantially perpendicular to the plane. A memory group as claimed in claim 1, wherein a surface area of the channel region of each of the ferroelectric field effect transistors (FeFET) is larger than the ferroelectric field effect on the plane of the semiconductor substrate The footprint of a transistor (FeFET). A thin film ferroelectric field effect transistor (FeFET) in a three-dimensional memory array includes a channel region formed of an oxide semiconductor material, and a metal source region or a metal bit line. A thin-film ferroelectric field-effect transistor according to claim 33 of the patent application, wherein the oxide semiconductor material includes indium zinc oxide (InZnO or IZO). A thin film ferroelectric field effect transistor according to claim 33, wherein the channel region is 8.0 to 12.0 nanometers thick. A thin film ferroelectric field effect transistor according to claim 33 of the patent application, wherein when the thickness of the channel region is greater than 6.0 nm, the electron mobility of the channel region is greater than or equal to 12.0 cm ² /V. A thin film ferroelectric field effect transistor according to claim 33, wherein the metal source region or the metal bit line contains molybdenum. A thin-film ferroelectric field-effect transistor according to item 33 of the scope of the patent application, wherein the thin-film ferroelectric field-effect transistor is one of a plurality of thin-film ferroelectric field-effect transistors on a memory group. A thin-film ferroelectric field-effect transistor as claimed in claim 38 of the patent application, wherein the memory group constitutes a Negative OR (NOR) memory group of the plurality of thin-film ferroelectric field-effect transistors (FeFETs). A thin-film ferroelectric field-effect transistor according to item 38 of the scope of the patent application, wherein the memory group is one of a plurality of memory groups formed above a plane of a semiconductor substrate. A thin film ferroelectric field effect transistor according to claim 40 of the patent application, wherein the plurality of thin film ferroelectric field effect transistors of each memory group are arranged along a direction substantially parallel to the plane. A thin-film ferroelectric field-effect transistor according to claim 40 of the patent application, wherein the plurality of thin-film ferroelectric field-effect transistors of each memory group are arranged along a direction substantially perpendicular to the plane.

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