CN109817706A - ZrO2Based antiferroelectric negative capacitance field effect transistor - Google Patents
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Abstract
The invention discloses a kind of ZrO2Based antiferroelectric negative capacitance field effect transistor mainly solves the problems, such as that existing negative capacitance field effect transistor generates timing disorder to application circuit due to hysteresis characteristic.It includes substrate (1), gate dielectric layer (2), gate electrode (3) from bottom to top；Substrate (1) both sides are equipped with source electrode (4) and drain electrode (5)；The first insulating gap wall (6) are equipped between gate electrode (3) and source electrode (4)；The second insulating gap wall (7) are equipped between gate electrode (3) and drain electrode (5), it is characterised in that: gate dielectric layer (2) uses ZrO2Based antiferroelectric material effectively inhibits hysteresis characteristic to form good interface with substrate.The present invention significantly reduces subthreshold swing, reduces operating voltage, effectively inhibition hysteresis characteristic, and process complexity is low, and interfacial characteristics are preferable, and performance is stablized, and can be used for IC design.
Description
Technical field
The invention belongs to microelectronics technology, in particular to a kind of ZrO2Based antiferroelectric negative capacitance field effect transistor,
It can be used for IC design.
Technical background
With the further development of Moore's Law, characteristic size constantly reduces, and integrated level and performance are continuously improved, and thus produces
Raw power problems become to get worse.For conventional CMOS device, hindering the key factor of its lower power consumption is device subthreshold
The value amplitude of oscillation is limited by thermodynamics, and there are theoretical limits, i.e., subthreshold swing minimum value is 60mV/dec, also referred to as glass at room temperature
The graceful limitation of Wurz.Negative capacitance transistor is to break through Boltzmann limitation, is hopeful very much to continue the device that performance of integrated circuits is promoted
Part structure.
This device architecture of existing negative capacitance field-effect-transistor-based is to do gate medium with ferroelectric material, and ferroelectric material can draw
Enter capacitor CFE.The C born in deviceFEWith channel MOS capacitor CMOSSeries connection, at room temperature subthreshold swing reach 60mV/dec with
Under, Boltzmann limitation can be broken through, to reduce transistor operating voltage VDDPossibility is provided with size is further decreased.But iron
The sequence problem that the hysteresis characteristic of electric material generate transistor application can into logic circuit, it is disorderly when logic circuit being caused to work
Disorderly, to make the switch state of transistor reach desirable level, it is necessary to avoid the generation of hysteresis characteristic, it is therefore desirable to can effectively inhibit
The method of hysteresis characteristic, including the different ferroelectric materials of research and device architecture.ZrO2Based antiferroelectric material is as a kind of new material
Material is applied to negative capacitance field effect transistor, will have very big prospect.
Summary of the invention
It is an object of the invention in view of the above shortcomings of the prior art, provide a kind of ZrO2Based antiferroelectric negative capacitance field effect
Transistor is answered, to reduce subthreshold swing, reduces operating voltage, effectively inhibition hysteresis characteristic.
To achieve the above object, the present invention provides the following two kinds technical solution:
Technical solution 1, a kind of ZrO2Based antiferroelectric negative capacitance field effect transistor includes substrate, gate medium from bottom to top
Layer, gate electrode；Substrate both sides are equipped with source electrode and drain electrode；The first insulating gap wall is equipped between gate electrode and source electrode；Grid
The second clearance for insulation layer is equipped between electrode and drain electrode, it is characterised in that: gate dielectric layer uses ZrO2Based antiferroelectric material, can
To form good interface with substrate, effectively inhibit hysteresis characteristic.
Further, the substrate uses silicon Si, germanium Ge, SiGe SiGe, in silicon-on-insulator SOI, germanium on insulator GOI
Any one.
Further, the antiferroelectric gate dielectric layer uses non-impurity-doped ZrO2Material, the ZrO containing doping2It is any one in material
Kind.
Further, the ZrO containing doping2Material, dopant include carbon C, silicon Si, magnesium Mg, aluminium Al, yttrium Y, nitrogen N, germanium
At least one of Ge, tin Sn, strontium Sr, lead Pb, calcium Ca, barium Ba, titanium Ti, gadolinium Gd and lanthanum La element.
Further, the gate electrode uses tungsten, Titanium, metallic copper, metallic aluminium, metal platinum, metal iridium, metal
In ruthenium, tungsten nitride, titanium nitride, tantalum nitride, yttrium oxide, ruthenium-oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide
Any one.
Technical solution 2, a kind of ZrO2Based antiferroelectric negative capacitance field effect transistor includes substrate, gate medium from bottom to top
Layer, gate electrode；Substrate both sides are equipped with source electrode and drain electrode；The first insulating gap wall is equipped between gate electrode and source electrode；Grid
The second clearance for insulation layer is equipped between electrode and drain electrode, it is characterised in that: gate dielectric layer uses ZrO2Based antiferroelectric material；Lining
It is equipped with a bed boundary insulating layer between bottom and gate dielectric layer, for improving interfacial characteristics, reduces gate leak current.
Further, the interface layer insulating is using in silica material, oxidation germanium material, aluminium oxide and silicon oxynitride
It is at least one.
Compared with prior art, the present invention due to using ZrO2Based antiferroelectric material, can be with lining as gate dielectric layer
Bottom forms good interface, effectively inhibition hysteresis characteristic；Reduce preparation process complexity.Simultaneously because in substrate and gate medium
It is equipped with a bed boundary insulating layer between layer, improves interfacial characteristics, reduces gate leak current.
Detailed description of the invention
Fig. 1 is the first example of the invention without boundary layer ZrO2Illustrate in the section of based antiferroelectric negative capacitance field effect transistor
Figure；
Fig. 2 is the production process schematic diagram of the first example of the invention；
Fig. 3 is the second example interfacial TCO layer ZrO of the present invention2Illustrate in the section of based antiferroelectric negative capacitance field effect transistor
Figure；
Fig. 4 is the production process schematic diagram of the second example of the invention.
Specific embodiment
First embodiment
Referring to Fig.1, this example includes between substrate 1, gate dielectric layer 2, gate electrode 3, source electrode 4, the insulation of drain electrode 5, first
Gap wall 6 and the second insulating gap wall 7.Substrate 1, gate dielectric layer 2 and gate electrode 3 are arranged from bottom to top；Source electrode 4 and drain electrode 5
The both sides of substrate 1 are set；First insulating gap wall 6 is arranged between gate electrode 3 and source electrode 4, for electric isolation grid electricity
Pole 3 and source electrode 4；Second clearance for insulation layer 7 is arranged between gate electrode 3 and drain electrode 5, is used for 3 He of electric isolation gate electrode
Drain electrode 5.Wherein substrate 1, using germanium wafer；Gate dielectric layer 2, using zirconia material or the zirconia material of doping；Grid electricity
Pole 3, using tantalum nitride；Source electrode 4, using NiGe；Drain electrode 5, using NiGe；First insulating gap wall 6, using SiN；Second
Insulating gap wall 7 uses SiN.
The ZrO containing doping2Material, dopant include carbon C, silicon Si, magnesium Mg, aluminium Al, yttrium Y, nitrogen N, germanium Ge, tin
At least one of Sn, strontium Sr, lead Pb, calcium Ca, barium Ba, titanium Ti, gadolinium Gd and lanthanum La element.
Referring to Fig. 2, the making step of the first example is as follows；
Step 1, substrate is selected.
This example selects N-shaped germanium wafer Ge as substrate 1, and the upper surface of the substrate is (100) crystal face.
Step 2, antiferroelectric ZrO is deposited2Film, as shown in Fig. 2 (a).
The antiferroelectric ZrO of 5nm is deposited on substrate 1 with plasma enhanced atomic layer deposition PEALD equipment2It is situated between as grid
Matter layer 2, the process conditions of deposition are as follows: use four dimethylamino zirconiums as presoma zirconium source, water is presoma oxygen source, depositing temperature
It is 250 degree.
Step 3, using Radiofrequency muti-hook probe equipment in antiferroelectric ZrO2100nm tantalum nitride is deposited on gate medium 2
TaN, as grid metal, as shown in Fig. 2 (b).
Step 4, gate electrode figure and ion implanting are defined, as shown in Fig. 2 (c).
Lithographic definition gate electrode figure is first carried out on the surface TaN, then etching forms gate electrode 3 and source and drain areas, then
Carry out BF2 +Ion implanting, Implantation Energy 30Kev, implantation dosage are 1 × 1015cm-2。
Step 5, the body structure surface shown in Fig. 2 (c) deposits layer of sin film, forms the first clearance for insulation by etching
Wall 6 and the second insulating gap wall 7, as shown in Fig. 2 (d).
Step 6, the body structure surface shown in Fig. 2 (d) carries out photoetching, defines the region for needing deposited metal nickel, deposits
The Ni of 20nm thickness, is put into acetone soln and carries out lift-off processing, source electrode 4 and drain electrode 5 is formed, as shown in Fig. 2 (e).
Step 7, the device entirely made is annealed under the conditions of 500 degree of 30s activation.
Second embodiment
Referring to Fig. 3, this example includes substrate 1, interfacial insulator layer 8, gate dielectric layer 2, gate electrode 3, source electrode 4, drain electrode
5, the first insulating gap wall 6 and the second insulating gap wall 7.Substrate 1, interfacial insulator layer 8, gate dielectric layer 2 and gate electrode 3 from lower and
Upper setting；The both sides of substrate 1 are arranged in source electrode 4 and drain electrode 5；First insulating gap wall 6 is arranged in gate electrode 3 and source electrode
Between 4, it to be used for electric isolation gate electrode 3 and source electrode 4；Second clearance for insulation layer 7 is arranged between gate electrode 3 and drain electrode 5,
For electric isolation gate electrode 3 and drain electrode 5.Wherein substrate 1, using germanium on insulator piece；Interfacial insulator layer 8, using but not
It is limited to alumina material；Gate dielectric layer 2, using zirconia material or containing the zirconia material of doping；Gate electrode 3, using but
It is not limited to tantalum nitride；Source electrode 4 uses NiGe；Drain electrode 5 uses NiGe；First insulating gap wall 6 uses SiN；Second insulation
Clearance wall 7 uses SiN.
The ZrO containing doping2Material, dopant include carbon C, silicon Si, magnesium Mg, aluminium Al, yttrium Y, nitrogen N, germanium Ge, tin
At least one of Sn, strontium Sr, lead Pb, calcium Ca, barium Ba, titanium Ti, gadolinium Gd and lanthanum La element.
Referring to Fig. 4, the making step of the second example is as follows；
Step 1, substrate is selected.
This example selects N-shaped germanium on insulator piece GeOI as substrate 1, and the upper surface of the substrate is (100) crystal face.
Step 2, deposited oxide aluminium film, as shown in Fig. 4 (a).
Plasma enhanced atomic layer deposition PEALD equipment is used to deposit 0.7nm aluminium oxide on substrate 1 exhausted as interface
Edge layer 8, the process conditions of deposition are as follows: use trimethyl aluminium as presoma silicon source, water is presoma oxygen source, and depositing temperature is
300 degree.
Step 3, the ZrO of deposition doping yttrium2Film, as shown in Fig. 4 (b).
The ZrO of 5nm doping yttrium is deposited on aluminum oxide film with plasma enhanced atomic layer deposition PEALD equipment2
As gate dielectric layer 2, the process conditions of deposition are as follows: use four dimethylamino zirconiums as presoma zirconium source, three (2,2,6,6- tetramethyls
Base -3,5- heptadione) for yttrium as yttrium source, water is presoma oxygen source, depositing temperature is 250 degree.
Step 4, using Radiofrequency muti-hook probe equipment in antiferroelectric ZrO2100nm tantalum nitride is deposited on gate medium 2
TaN, as grid metal, as shown in Fig. 4 (c).
Step 5, gate electrode figure and ion implanting are defined, as shown in Fig. 4 (d).
Lithographic definition gate electrode figure is first carried out on the surface TaN, then etching forms gate electrode 3 and source and drain areas, then
Carry out BF2 +Ion implanting, Implantation Energy 30Kev, implantation dosage are 1 × 1015cm-2。
Step 6, the body structure surface shown in Fig. 4 (d) deposits layer of sin film, forms the first clearance for insulation by etching
Wall 6 and the second insulating gap wall 7, as shown in Fig. 4 (e).
Step 7, the body structure surface shown in Fig. 4 (f) carries out photoetching, defines the region for needing deposited metal nickel (Ni),
The Ni for depositing 20nm thickness, is put into acetone soln and carries out lift-off processing, source electrode 4 and drain electrode 5 is formed, as shown in Fig. 2 (e).
Step 8, the device entirely made is annealed under the conditions of 500 degree of 30s activation.
Above description is only two specific examples of the invention, does not constitute any limitation of the invention, it is clear that for
It, all may be without departing substantially from the principle of the invention, structure after having understood the content of present invention and principle for one of skill in the art
In the case where, carry out various modifications and change in form and details, but these modifications and variations based on inventive concept
Still within the scope of the claims of the present invention.
Claims (7)
1. a kind of ZrO2Based antiferroelectric negative capacitance field effect transistor includes substrate (1), gate dielectric layer (2), grid electricity from bottom to top
Pole (3)；Substrate (1) both sides are equipped with source electrode (4) and drain electrode (5)；First is equipped between gate electrode (3) and source electrode (4) absolutely
Edge clearance wall (6)；The second insulating gap wall (7) are equipped between gate electrode (3) and drain electrode (5), it is characterised in that: gate dielectric layer
(2) ZrO is used2Based antiferroelectric material can form good interface with substrate, effectively inhibition hysteresis characteristic.
2. ZrO according to claim 12Based antiferroelectric negative capacitance field effect transistor, which is characterized in that substrate (1) uses
Any one in silicon Si, germanium Ge, SiGe SiGe, silicon-on-insulator SOI, germanium on insulator GOI.
3. ZrO according to claim 12Based antiferroelectric negative capacitance field effect transistor, which is characterized in that antiferroelectric grid are situated between
Matter layer (2) uses non-impurity-doped ZrO2Material and ZrO containing doping2Material any one.
4. ZrO according to claim 32Based antiferroelectric negative capacitance field effect transistor, it is characterised in that the ZrO containing doping2
Material, dopant include carbon C, silicon Si, magnesium Mg, aluminium Al, yttrium Y, nitrogen N, germanium Ge, tin Sn, strontium Sr, lead Pb, calcium Ca, barium Ba, titanium
At least one of Ti, gadolinium Gd and lanthanum La element.
5. ZrO according to claim 12Based antiferroelectric negative capacitance field effect transistor, it is characterised in that gate electrode (3) is adopted
With tungsten, Titanium, metallic copper, metallic aluminium, metal platinum, metal iridium, metal Ru, tungsten nitride, titanium nitride, tantalum nitride, oxidation
Any one in iridium, ruthenium-oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide.
6. a kind of ZrO2Based antiferroelectric negative capacitance field effect transistor includes substrate (1), gate dielectric layer (2), grid electricity from bottom to top
Pole (3)；Substrate (1) both sides are equipped with source electrode (4) and drain electrode (5)；First is equipped between gate electrode (3) and source electrode (4) absolutely
Edge clearance wall (6)；The second insulating gap wall (7) are equipped between gate electrode (3) and drain electrode (5), it is characterised in that: gate dielectric layer
(2) ZrO is used2Based antiferroelectric material can form good interface with substrate, effectively inhibition hysteresis characteristic；Substrate (1) and grid
It is equipped with a bed boundary insulating layer (8) between dielectric layer (2), for improving interfacial characteristics, reduces gate leak current.
7. ZrO according to claim 62Based antiferroelectric negative capacitance field effect transistor, wherein interface layer insulating (8) is adopted
With at least one of silica material, oxidation germanium material, aluminium oxide and silicon oxynitride.
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Cited By (4)
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| CN111598229A (en) * | 2020-05-11 | 2020-08-28 | 中国科学院微电子研究所 | Neuron circuit, integrated circuit based on neural network and electronic equipment |
| CN112768527A (en) * | 2021-01-04 | 2021-05-07 | 西安电子科技大学 | Based on amorphous ZrOxNegative capacitance transistor of |
| CN114141880A (en) * | 2021-11-02 | 2022-03-04 | 北京大学 | FeFET based on antiferroelectric gate dielectric and oxide semiconductor channel and preparation method thereof |
| CN118213409A (en) * | 2024-05-22 | 2024-06-18 | 华中科技大学 | Ferroelectric negative capacitance transistor and preparation method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111598229A (en) * | 2020-05-11 | 2020-08-28 | 中国科学院微电子研究所 | Neuron circuit, integrated circuit based on neural network and electronic equipment |
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| CN114141880A (en) * | 2021-11-02 | 2022-03-04 | 北京大学 | FeFET based on antiferroelectric gate dielectric and oxide semiconductor channel and preparation method thereof |
| CN114141880B (en) * | 2021-11-02 | 2024-04-19 | 北京大学 | FeFET based on antiferroelectric gate dielectric and oxide semiconductor channel and preparation method thereof |
| CN118213409A (en) * | 2024-05-22 | 2024-06-18 | 华中科技大学 | Ferroelectric negative capacitance transistor and preparation method thereof |
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