KR20190001455A - Ferroelectric Memory Device - Google Patents

Ferroelectric Memory Device Download PDF

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KR20190001455A
KR20190001455A KR1020170081465A KR20170081465A KR20190001455A KR 20190001455 A KR20190001455 A KR 20190001455A KR 1020170081465 A KR1020170081465 A KR 1020170081465A KR 20170081465 A KR20170081465 A KR 20170081465A KR 20190001455 A KR20190001455 A KR 20190001455A
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dielectric layer
ferroelectric
memory device
oxide
interfacial
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KR1020170081465A
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Korean (ko)
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유향근
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에스케이하이닉스 주식회사
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Publication of KR20190001455A publication Critical patent/KR20190001455A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/516Insulating materials associated therewith with at least one ferroelectric layer
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
    • H01L21/28291
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11585Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40111Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225Auxiliary circuits
    • G11C11/2275Writing or programming circuits or methods

Abstract

In one embodiment, a ferroelectric memory device includes: a substrate having a source electrode and a drain electrode; a first interfacial dielectric layer disposed on the substrate and having anti-ferroelectric properties; a gate dielectric layer disposed on the first interfacial dielectric layer and having ferroelectricity; and a gate electrode layer disposed on the gate dielectric layer. The first interfacial dielectric layer suppresses the generation of a depolarizing electric field inside the ferroelectric gate dielectric layer. It is possible to perform the switching operation of polarization orientation reliably.

Description

[0001] Ferroelectric Memory Device [0002]

This disclosure relates to a generally ferroelectric memory device.

Generally, a ferroelectric substance means a substance having a spontaneous electric polarization in a state in which no external electric field is applied. Specifically, the ferroelectric material can maintain either of two residual polarization states. The remanent polarization state can be controllable by application of an external electric field.

Recently, studies have been made to apply the ferroelectric substance to a nonvolatile memory device by using the property that the remanent polarization state is changed by application of an external electric field. That is, the residual polarization state of the ferroelectric substance in the memory cell after the external electric field is removed can be applied to non-volatile storage of digital information of "0" or "1".

One embodiment of the present disclosure provides a ferroelectric memory device having a ferroelectric gate dielectric layer that reliably performs the switching operation of the polarization orientation and a method of manufacturing the same.

A ferroelectric memory device in accordance with an aspect of the disclosure is disclosed. The ferroelectric memory device comprising a substrate having a source electrode and a drain electrode, a first interfacial dielectric layer disposed on the substrate and having anti-ferroelectric properties, a gate dielectric layer disposed on the first interfacial dielectric layer and having ferroelectricity, And a gate electrode layer disposed on the gate electrode layer. The first interfacial dielectric layer suppresses the generation of a depolarizing electric field inside the ferroelectric gate dielectric layer.

A ferroelectric memory device according to another aspect of the disclosure is disclosed. The ferroelectric memory device includes a semiconductor substrate, a first interfacial dielectric layer disposed on the semiconductor substrate, an interfacial dielectric layer disposed on the first interfacial dielectric layer and having antiferroelectric properties, a ferroelectric gate dielectric layer disposed on the interfacial dielectric layer, And a gate electrode layer disposed on the gate dielectric layer. The interfacial dielectric layer has a dielectric constant higher than that of the first interface insulating layer, and the interfacial dielectric layer has a crystal lattice constant difference of 3% or less with respect to the anisotropic dielectric layer.

A ferroelectric memory device according to another aspect of the disclosure is disclosed. The ferroelectric memory device includes a silicon substrate having a source electrode and a drain electrode, a first interface insulating layer including silicon oxide disposed on the silicon substrate, an interfacial insulating layer disposed on the first interface insulating layer, A second interfacial dielectric layer disposed on the interfacial dielectric layer and comprising a ferroelectric hafnium oxide layer, a hafnium oxide layer disposed on the second interfacial dielectric layer and including a dielectric or antiferroelectric zirconium oxide, A third interface insulating layer containing an oxide, and a gate electrode layer disposed on the third interface insulating layer. The interfacial dielectric layer includes at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

According to an embodiment of the present disclosure described above, a ferroelectric memory device includes an interfacial dielectric layer having anti-ferroelectricity between a substrate and a ferroelectric gate dielectric layer. The interfacial dielectric layer can offset the depolarization field created in the ferroelectric material layer near the interface when the ferroelectric material layer interfaces with a heterogeneous material layer. When the voltage is applied between the substrate and the gate electrode layer, the anti-ferroelectric interfacial dielectric layer has a high dielectric constant, thereby reducing the magnitude of the voltage to be distributed to the interfacial dielectric layer in the lamination structure of the interfacial dielectric layer and the ferroelectric gate dielectric layer . As the voltage to be distributed to the interfacial dielectric layer decreases, the interfacial dielectric layer is tunneled to inhibit conduction of electrons or holes between the substrate and the gate electrode. Accordingly, the leakage current due to the electrons or holes can be reduced.

1 is a cross-sectional view schematically illustrating a ferroelectric memory device according to one embodiment of the present disclosure;
FIG. 2A is a polarization hysteresis curve of a ferroelectric material according to one embodiment of the present disclosure, and FIG. 2B is a polarization hysteresis curve of an antiferroelectric material according to an embodiment of the present disclosure.
FIG. 3A is a cross-sectional view schematically illustrating an energy band diagram of a ferroelectric memory device according to one comparative example of the present disclosure; FIG.
3B is a cross-sectional view schematically illustrating an energy band diagram of a ferroelectric memory device according to one embodiment of the present disclosure;
4 is a cross-sectional view schematically illustrating a ferroelectric memory device according to another embodiment of the present disclosure;
5 is a cross-sectional view schematically illustrating a ferroelectric memory device according to another embodiment of the present disclosure;
6 is a cross-sectional view schematically illustrating a ferroelectric memory device according to another embodiment of the present disclosure;

Embodiments of the present application will now be described in more detail with reference to the accompanying drawings. In the drawings, the widths, thicknesses and the like of the components are slightly enlarged in order to clearly illustrate the components of the respective devices. It is to be understood that when an element is described as being located on another element, it is meant that the element is directly on top of the other element or that additional elements can be interposed between the elements . Like numbers refer to like elements throughout the several views.

It is also to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise, and the terms "comprise" Or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. Further, in carrying out the method or the manufacturing method, the respective steps of the method may take place differently from the stated order unless clearly specified in the context. That is, each process may occur in the same order as described, may be performed substantially concurrently, or may be performed in the opposite order.

1 is a cross-sectional view schematically illustrating a ferroelectric memory device according to one embodiment of the present disclosure; FIG. 2A is a polarization hysteresis curve of a ferroelectric material according to one embodiment of the present disclosure, and FIG. 2B is a polarization hysteresis curve of an antiferroelectric material according to an embodiment of the present disclosure.

Referring to FIG. 1, a ferroelectric memory device 1 includes a substrate 101 having a source electrode 102 and a drain electrode 103. The ferroelectric memory device 1 also includes an interfacial dielectric layer 110 disposed on the substrate 101, a ferroelectric gate dielectric layer 120, and a gate electrode layer 130.

In the ferroelectric memory device 1 of this embodiment, depending on the polarity or magnitude of the voltage applied to the gate electrode layer 130, a residual polarization having different orientations in the ferroelectric gate dielectric layer 120 may be formed. The remanent polarization can induce a carrier having charge, such as electrons or holes, in the channel region 104 of the substrate 101. The channel region 104 is a region of the substrate 101 located under the ferroelectric gate dielectric layer 120 and is a region where the conductive carrier is conductive when the operating voltage is applied between the source electrode 102 and the drain electrode 103. [ Which is a path through which a channel is formed.

At this time, depending on the orientation of the remnant polarization, the density of the carriers introduced into the channel region 104 of the substrate 101 may vary. Further, depending on the density of the carrier to be induced, the thickness t of the channel region 104 having electrical conductivity can be determined. As an example, when the residual polarization in the ferroelectric gate dielectric layer 120 has a first orientation that can induce electrons into the channel region 104, the thickness t of the channel region 104 is reduced by the induced electrons, Can be increased. Thus, the channel resistance of the electron carrier moving between the source electrode 102 and the drain electrode 130 via the channel region 104 can be reduced. As another example, when the remanent polarization in the ferroelectric gate dielectric layer 120 has a second orientation that can evoke electrons in the channel region 104, the thickness of the channel region 104 is reduced by decreasing the electron density . As a result, the channel resistance of the electron carrier, which moves between the source electrode 102 and the drain electrode 130 via the channel region 104, may increase. As a result, by controlling the orientation of the remanent polarization of the ferroelectric gate dielectric layer 120, different signal information can be stored non-volatilely.

Referring to FIG. 1, the substrate 101 may include, by way of example, a semiconductor material. The substrate 101 may be, for example, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. The substrate 101 may be doped n-type or p-type to have conductivity.

The source electrode 102 and the drain electrode 103 may be disposed at both ends of the gate electrode 130. [ In one embodiment, the source electrode 101 and the drain electrode 103 may be regions doped with a dopant in the semiconductor substrate 101. The source electrode 101 and the drain electrode 103 may be a doped region doped in a type opposite to the doping type of the semiconductor substrate 101. [ As an example, when the substrate 101 is doped with p-type, the source electrode 102 and the drain electrode 103 may be doped n-type to have a predetermined conductivity. The source electrode 101 and the drain electrode 103 may be a conductive pattern layer disposed inside the substrate 101 or on the substrate 101. [ The conductive pattern layer may include, by way of example, a metal, a conductive metal nitride, a conductive silicide, and a doped semiconductor.

The interfacial dielectric layer 110 and the ferroelectric gate dielectric layer 120 may be sequentially arranged on the substrate 101. The interfacial dielectric layer 110 and the ferroelectric gate dielectric layer 120 may be crystalline and the difference in crystal lattice constant between the interfacial dielectric layer 110 and the ferroelectric gate dielectric layer 120 may be less than 3%.

The interfacial dielectric layer 110 may comprise an antiferroelectric material. The interfacial dielectric layer 110 may comprise, by way of example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. The interfacial dielectric layer 110 may have a cubic or tetragonal crystal structure as an example. The interfacial dielectric layer 110 may, for example, have a thickness of 2 nm to 5 nm.

The ferroelectric gate dielectric layer 120 may comprise a ferroelectric material. As an example, the ferroelectric material may be a metal oxide. As an example, the ferroelectric gate dielectric layer 120 may comprise hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. The ferroelectric gate dielectric layer 120 may have an orthorhombic crystal structure as an example. The ferroelectric gate dielectric layer 120 may have a thickness of, for example, 5 nm to 10 nm.

In one embodiment, the ferroelectric gate dielectric layer 120 may comprise a dopant. The dopant may be, for example, carbon, silicon, magnesium, yttrium, nitrogen, germanium, tin, ), Lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), lanthanum (La) or a combination of two or more thereof.

The gate electrode layer 130 may comprise, by way of example, a metal, a conductive metal nitride, a conductive metal oxide, or a conductive metal silicide. As an example, the gate electrode layer 130 may include at least one of tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten nitride, , Tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, or a combination of two or more thereof.

In one embodiment, the substrate 101 is a silicon substrate and the ferroelectric gate dielectric layer 120 is a ferroelectric hafnium oxide layer, the antiferroelectric interfacial dielectric layer 110 may comprise hafnium oxide, zirconium oxide, hafnium zirconium oxide, Combinations thereof. In a specific example, the anti-ferroelectric interfacial dielectric layer 110 may be a zirconium oxide layer.

On the other hand, when the ferroelectric gate dielectric layer 120 and the different material layers form an interface, a depolarization electric field may be formed from the interface to the inside of the ferroelectric gate dielectric layer 120. The depolarization electric field can reduce the ferroelectricity of the ferroelectric gate dielectric layer 120 by lowering the degree of alignment of the polarization orientation of the ferroelectric gate dielectric layer 120.

Although not necessarily explained by one theory, according to one of the various theories of depolarizing electric field formation, continuity of chemical bonding between interfacial materials in the ferroelectric gate dielectric layer 120 can be broken at the interface. Then, when the ferroelectric gate dielectric layer 120 and the heterogeneous material layers are bonded to each other at the interface, stress due to lattice strain from the interface to the ferroelectric gate dielectric layer 120 due to the difference in lattice constant of each other Can occur. Due to the gradient of the stress, a depolarizing electric field can be generated within the ferroelectric gate dielectric layer 120.

According to another example of various theories of depolarizing field formation, when the ferroelectric gate dielectric layer 120 comprises a metal oxide, the integrity of the chemical bond of the metal oxide in the region near the interface may be compromised. Accordingly, an oxygen vacancy having a positive charge in the metal oxide near the interface can be generated. The oxygen vacancies generate a concentration gradient of the positive charge from the near-interface region to the interior region, and the concentration gradient can form a depolarization field within the ferroelectric gate dielectric layer 120.

According to the various theories described above, the depolarization electric field formed in the ferroelectric gate dielectric layer 120 may degrade the degree of alignment of the polarization orientation of the ferroelectric gate dielectric layer 120. Thus, the reliability of the signal information stored in the ferroelectric gate dielectric layer 120 can be lowered.

According to one embodiment of the present disclosure, the interfacial dielectric layer 110 having anti-ferroelectricity disposed between the substrate 101 and the ferroelectric gate dielectric layer 120 can suppress formation of the depolarization electric field. The interfacial dielectric layer 110 and the ferroelectric gate dielectric layer may each comprise a metal oxide and the difference in crystal lattice constant between the interfacial dielectric layer 110 and the ferroelectric gate dielectric layer 120 may be less than 3%. Accordingly, generation of strains due to a difference in crystal lattice constant or generation of oxygen vacancies due to disconnection of chemical bonds can be suppressed between the interfacial dielectric layer 110 and the ferroelectric gate dielectric layer 120. As a result, the formation of a depolarizing electric field in the ferroelectric gate dielectric layer 120 can be suppressed. In this case, the ferroelectric gate dielectric layer 120 may have a thickness of 5 to 10 nm, and the interfacial dielectric layer 110 may have a thickness of 2 to 5 nm.

2A and 2B show the polarization hysteresis curves of the ferroelectric material and the antiferroelectric material applied to the ferroelectric gate dielectric layer 120 and the interfacial dielectric layer 110, respectively. Referring to FIG. 2A, the ferroelectric material may have a varying polarization value along the path of 1 to 4 on the polarization hysteresis curve when an electric field is applied to the ferroelectric material from the outside. The ferroelectric material may have first and second coercive fields (Ec 1 , Ec 2 ) and first and second remanent polarization (Pr 1 , Pr 2 ) on the polarization hysteresis curve of FIG. Also, referring to FIG. 2B, the anti-ferroelectric material may be an antiferroelectric substance. When an electric field is externally applied to the antiferroelectric material, it may have a varying polarization value along the path of 1 to 4 on the polarization hysteresis curve. The antiferroelectric material may have first and second coercive fields (Ec 3 , Ec 4 ) on the polarization hysteresis curve of FIG. 2b. At this time, when an external electric field having an absolute value equal to or greater than the absolute value of the first and second coercive force fields (Ec 3 Ec 4 ) is applied to the anti-ferroelectric material, the anti-ferroelectric material has a ferroelectric characteristic, , The anti-ferroelectric material may not have ferroelectric properties.

If during a write operation of the ferroelectric memory device (1), an electric field having a first or claim 2 coercive force absolute value or more (Ec3, Ec 4) of the surface dielectric layer 110, which is shown in Figure 2b is applied from the outside, the antiferroelectric The ferroelectric polarization orientation formed in the interfacial dielectric layer 110 can lead to improved alignment of the polarization orientation of the ferroelectric gate dielectric layer 120. Thus, after the external field is removed, the degree of alignment alignment of the remanent polarization located in the ferroelectric gate dielectric layer 120 can be improved. After the external electric field is removed, the ferroelectric polarization orientation formed on the interfacial dielectric layer 110 may disappear.

FIG. 3A is a cross-sectional view schematically illustrating an energy band diagram of a ferroelectric memory device according to one comparative example of the present disclosure; FIG. 3B is a cross-sectional view schematically illustrating an energy band diagram of a ferroelectric memory device according to one embodiment of the present disclosure; The interfacial dielectric layer 105 of the ferroelectric memory device of FIG. 3a includes conventional silicon oxide, or silicon nitride, and the interfacial dielectric layer 110 of the ferroelectric memory device 12 of FIG. 3b may comprise an antiferroelectric material. In this embodiment, the interfacial dielectric layer 110 may comprise hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof as an anti-ferroelectric material. Accordingly, the dielectric constant of the interfacial dielectric layer 110 of this embodiment may be greater than the dielectric constant of the interfacial dielectric layer 105 of the comparative example.

1, the interfacial dielectric layer 110 and the ferroelectric gate dielectric layer 120 may be electrically in-line between the substrate 101 and the gate electrode layer 130. In this case, Thus, when an external voltage V tot is applied, the amount of charge to be filled in the interfacial dielectric layer 110 and the ferroelectric gate dielectric layer 120, respectively, may be the same. The product (C 110 V 110 ) of the capacitance C 110 of the interfacial dielectric layer 110 and the voltage V 110 distributed to the interfacial dielectric layer 110 is less than the capacitance C 120 of the ferroelectric gate dielectric layer 120 , (C 120 V 120 ) divided by the voltage V 120 applied to the ferroelectric gate dielectric layer 120.

Accordingly, as the ratio of increase of the capacitance (C 120) of the ferroelectric gate dielectric layer 120 to the capacitance (C 110) of the surface dielectric layer 110, and the voltage (V 110) to be distributed to the interface between the dielectric layer 110 may increase have. 1, the capacitances C 120 and C 110 of ferroelectric gate dielectric layer 120 and interfacial dielectric layer 110 are proportional to the dielectric constants of ferroelectric gate dielectric layer 120 and interfacial dielectric layer 110, respectively . Therefore, as the ratio of the dielectric constant of the ferroelectric gate dielectric layer 120 to the dielectric constant of the interfacial dielectric layer 110 increases, the voltage V 110 distributed to the interfacial dielectric layer 110 may increase.

In the comparative example shown in FIG. 3A, bending of an energy band occurs due to a voltage V 105 distributed to the interfacial dielectric layer 105, and the first barrier A barrier having energy E a can be generated. 3B, a barrier having a second barrier energy E b at both ends of the interface insulating layer 110 is generated by the voltage V 110 distributed to the interface insulating layer 110 . 3B and the embodiment of FIG. 3B, the dielectric constant of the interfacial dielectric layer 105 of FIG. 3A is less than the dielectric constant of the interfacial dielectric layer 110 of FIG. 3B, 105 are relatively larger than the voltage applied to the interfacial dielectric layer 110. Thus, the first barrier energy E a may be greater than the second barrier energy E b . 3A, the substantial path through which electrons or holes pass through the interfacial dielectric layer 105 is reduced by the bending phenomenon due to the first barrier energy Ea, so that the probability of tunneling electrons or holes becomes relatively high. As an example, since the degree of bending caused by the first barrier energy Ea in Fig. 3A is larger than the degree of bending caused by the first barrier energy Eb in Fig. 3B, The possibility of FN tunneling can be relatively increased. The tunneling electrons or holes may cause a leakage current. On the other hand, in the case of the embodiment of FIG. 3B, leakage current due to electrons or holes passing through the interfacial dielectric layer 110 can be relatively suppressed.

3B, the dielectric constant of the interfacial dielectric layer 110 may be greater than the dielectric constant of the interfacial dielectric layer 105 of one comparative example. Therefore, when the capacitance of the interfacial dielectric layers 105 and 110 is designed to a predetermined target value, the thickness t 110 of the interfacial dielectric layer 110 of one embodiment is set to be equal to the thickness t 105 of the interfacial dielectric layer 105 of the comparative example. Can be made larger. Accordingly, the interfacial dielectric layer 110 of one embodiment having a relatively large thickness can relatively effectively suppress the leakage current due to the tunneling.

4 is a cross-sectional view schematically illustrating a ferroelectric memory device according to another embodiment of the present disclosure; 4, a ferroelectric memory device 2 includes a ferroelectric memory device 1 (not shown), described above with respect to FIG. 1, except that it further includes an insulating layer 115 between the substrate 101 and the interfacial dielectric layer 110. [ ) And its configuration are substantially the same. In this embodiment, the interfacial structure under the ferroelectric gate dielectric layer 120 may have a stacked structure of an insulating layer 115 and an anti-ferroelectric interfacial dielectric layer 110.

The insulating layer 115 is disposed on the substrate 101. The first interface insulating layer 115 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a combination of two or more thereof. In one embodiment, when the substrate 101 is a silicon substrate, the insulating layer 115 may be a silicon oxide layer. The insulating layer 115 may have a thickness of more than 0 and 1 nm or less. The insulating layer 115 can additionally suppress conduction of electrons or holes from the substrate 101 to the gate electrode layer 130. [ An antiferroelectric interfacial dielectric layer 110, a ferroelectric gate dielectric layer 120, and a gate electrode layer 130 may be sequentially disposed on the insulating layer 115.

5 is a cross-sectional view schematically illustrating a ferroelectric memory device according to another embodiment of the present disclosure; Referring to FIG. 5, ferroelectric memory device 3 additionally includes an interfacial dielectric layer 122 between ferroelectric gate dielectric layer 120 and gate electrode layer 130, as compared to ferroelectric memory device 1 of FIG. The ferroelectric memory device 3 thus includes a first interfacial dielectric layer 110 disposed between the substrate 104 and the ferroelectric gate dielectric layer 120 and a second interfacial dielectric layer 110 disposed between the ferroelectric gate dielectric layer 120 and the gate electrode layer 130 And a second interfacial dielectric layer 122.

The second interfacial dielectric layer 122 may have a paraelectric or antiferroelectric property. The second interfacial dielectric layer 122 may have a higher bandgap energy than the ferroelectric gate dielectric layer 120. Thus, the interface energy barrier between the second interface dielectric layer 122 and the gate electrode layer 130 can be increased. As a result, the leakage current between the ferroelectric gate dielectric layer 120 and the gate electrode layer 130 can be reduced.

The second interfacial dielectric layer 122 may comprise a metal oxide. In one embodiment, the metal oxide is selected from the group consisting of silicon oxide, magnesium oxide, calcium oxide, strontium oxide, barium oxide, aluminum oxide, gallium oxide, yttrium oxide, scandium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, , Gadolinium oxide, zirconium silicon oxide, hafnium silicon oxide, titanium silicon oxide, or a combination of two or more thereof. The second interfacial dielectric layer 122 may, for example, have a thickness of greater than 0 and less than or equal to 1 nm. In this case, the gate electrode layer 130 may be formed of any one of tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten nitride, Tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, or a combination of two or more thereof.

The ferroelectric memory device 3 can be provided with the second interface dielectric layer 122 for further suppressing the leakage current generated between the ferroelectric gate dielectric layer 120 and the gate electrode layer 130 in this embodiment.

In some other embodiments, an insulating layer may be additionally disposed between the substrate 101 and the first interfacial dielectric layer 110, although not shown. The insulating layer may have substantially the same configuration as the insulating layer 115 described above with reference to FIG.

6 is a cross-sectional view schematically illustrating a ferroelectric memory device according to another embodiment of the present disclosure; 6, the ferroelectric memory device 4 includes a third interfacial dielectric layer 124 (not shown) between the second interfacial dielectric layer 122 and the ferroelectric gate dielectric layer 120, as compared to the ferroelectric memory device 3 of FIG. ). That is, the ferroelectric memory device 4 may include the first to third interfacial dielectric layers 110, 122, and 124.

The third interfacial dielectric layer 124 may have either paraelectric or antiferroelectric properties. The third interfacial dielectric layer 124 may comprise, by way of example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. The third interfacial dielectric layer 124 may have a crystal lattice constant difference of less than 3% with the ferroelectric gate dielectric layer 120. The third interface insulating layer 124 may have a thickness of more than 0 and 1 nm or less, for example.

The second interfacial dielectric layer 122 serves to reduce the leakage current between the ferroelectric gate dielectric layer 120 and the gate electrode layer 130 and the third interfacial dielectric layer 124 serves to reduce leakage current between the ferroelectric gate dielectric layer 120 And the second interfacial dielectric layer 122. In this case, the first interfacial dielectric layer 122 and the second interfacial dielectric layer 122 are formed of the same material.

In one embodiment, when the ferroelectric gate dielectric layer 120 is a ferroelectric hafnium oxide layer, the third interfacial dielectric layer 124 may comprise zirconium oxide. The second interfacial dielectric layer 122 includes aluminum oxide and the gate electrode layer 130 is formed of tungsten W, titanium Ti, copper Cu, aluminum Al, platinum Pt, iridium Ir ), Ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide or combinations of two or more thereof. The third interface dielectric layer 124 comprising zirconium oxide may function as a buffer layer to mitigate the difference in lattice constant between the ferroelectric hafnium oxide layer and the second interface dielectric layer 122 comprising aluminum oxide.

In some other embodiments, an insulating layer may be additionally disposed between the substrate 101 and the first interfacial dielectric layer 110, although not shown. The insulating layer may have substantially the same configuration as the insulating layer 115 described above with reference to FIG.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It can be understood that

1 2 3 4: ferroelectric memory device,
101: substrate, 102: source electrode, 103: drain electrode,
104: channel region, 105, 110: interfacial dielectric layer,
115: insulating layer, 120: ferroelectric gate dielectric layer,
122: second interfacial dielectric layer, 124: third interfacial dielectric layer,
130: gate electrode layer.

Claims (20)

  1. A substrate having a source electrode and a drain electrode;
    An anti-ferroelectric first interface dielectric layer disposed on the substrate;
    A ferroelectric gate dielectric layer disposed on the interfacial dielectric layer; And
    And a gate electrode layer disposed on the ferroelectric gate dielectric layer,
    The first interfacial dielectric layer suppresses the generation of a depolarizing electric field inside the ferroelectric gate dielectric layer
    Ferroelectric memory device.
  2. The method according to claim 1,
    Wherein the antiferroelectric first interfacial dielectric layer and the ferroelectric gate dielectric layer have a crystal lattice constant difference of less than 3%
    Ferroelectric memory device.
  3. The method according to claim 1,
    Wherein the antiferroelectric first interfacial dielectric layer comprises at least one of hafnium oxide, zirconium oxide, hafnium zirconium oxide,
    Ferroelectric memory device.
  4. The method according to claim 1,
    Wherein the ferroelectric gate dielectric layer comprises at least one of hafnium oxide, zirconium oxide, hafnium zirconium oxide,
    Ferroelectric memory device.
  5. The method according to claim 1,
    The ferroelectric gate dielectric layer may include at least one of carbon, silicon, magnesium, aluminum, yttrium, nitrogen, germanium, tin, strontium, And at least one dopant selected from the group consisting of lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd) and lanthanum
    Ferroelectric memory device.
  6. The method according to claim 1,
    Further comprising an insulating layer disposed between the substrate and the anti-ferroelectric first interface dielectric layer,
    Wherein the insulating layer comprises at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide
    Ferroelectric memory device.
  7. The method according to claim 1,
    The gate electrode layer
    Tantalum nitride, tantalum nitride, iridium oxide, ruthenium oxide, tantalum oxide, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir) At least one of tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.
    Ferroelectric memory device.
  8. The method according to claim 1,
    Further comprising a second interfacial dielectric layer disposed between the ferroelectric gate dielectric layer and the gate electrode layer, the second interfacial dielectric layer comprising a metal oxide of phase dielectric or antiferroelectric
    Ferroelectric memory device.
  9. 9. The method of claim 8,
    Wherein the second interface dielectric layer has a higher bandgap energy than the ferroelectric gate dielectric layer.
  10. 9. The method of claim 8,
    And a third interfacial dielectric layer disposed between the ferroelectric gate dielectric layer and the second interfacial dielectric layer,
    Wherein the third interface insulating layer has a crystal lattice constant difference with the ferroelectric gate dielectric layer of 3% or less
    Ferroelectric memory device.
  11. A semiconductor substrate;
    An insulating layer disposed on the semiconductor substrate;
    An anti-ferroelectric first interfacial dielectric layer disposed on the insulating layer;
    A ferroelectric gate dielectric layer disposed on the anti-ferroelectric first interfacial dielectric layer; And
    And a gate electrode layer disposed on the ferroelectric gate dielectric layer,
    Wherein the anti-ferroelectric first interfacial dielectric layer has a higher dielectric constant than the insulating layer,
    Wherein the antiferroelectric first interfacial dielectric layer has a crystal lattice constant difference of less than 3% with the ferroelectric gate dielectric layer
    Ferroelectric memory device.
  12. 12. The method of claim 11,
    Wherein the insulating layer comprises at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide
    Ferroelectric memory device.
  13. 12. The method of claim 11,
    Wherein the antiferroelectric first interfacial dielectric layer comprises at least one of hafnium oxide, zirconium oxide, hafnium zirconium oxide,
    Ferroelectric memory device.
  14. 12. The method of claim 11,
    Wherein the ferroelectric gate dielectric layer comprises at least one of hafnium oxide, zirconium oxide, hafnium zirconium oxide,
    Ferroelectric memory device.
  15. 12. The method of claim 11,
    And a second and a third interfacial dielectric layer having a dielectric or antiferroelectricity disposed between the ferroelectric gate dielectric layer and the gate electrode layer
    Ferroelectric memory device.
  16. 16. The method of claim 15,
    Wherein the second interface dielectric layer has a bandgap energy greater than that of the ferroelectric gate dielectric layer
    Ferroelectric memory device.
  17. 17. The method of claim 16,
    Wherein the third interfacial dielectric layer is disposed between the ferroelectric gate dielectric layer and the second interfacial dielectric layer,
    Wherein the third interface dielectric layer has a crystal lattice constant difference with the ferroelectric gate dielectric layer of less than 3%
    Ferroelectric memory device.
  18. 12. The method of claim 11,
    The gate electrode layer
    Tantalum nitride, tantalum nitride, iridium oxide, ruthenium oxide, tantalum oxide, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir) At least one of tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.
    Ferroelectric memory device.
  19. 12. The method of claim 11,
    A channel region formed in the semiconductor substrate region under the insulating layer; And
    And a source electrode and a drain electrode formed at both ends of the channel region
    Ferroelectric memory device.
  20. 20. The method of claim 19,
    The source electrode and the drain electrode
    When the semiconductor substrate is doped, a doped region, which is opposite to the doping type of the substrate,
    Ferroelectric memory device.
KR1020170081465A 2017-06-27 2017-06-27 Ferroelectric Memory Device KR20190001455A (en)

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US6602720B2 (en) 2001-03-28 2003-08-05 Sharp Laboratories Of America, Inc. Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same
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US7973348B1 (en) * 2004-08-06 2011-07-05 Dalton David I Single transistor charge transfer random access memory
US7378286B2 (en) * 2004-08-20 2008-05-27 Sharp Laboratories Of America, Inc. Semiconductive metal oxide thin film ferroelectric memory transistor
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