CN116209259A - Memory cell array structure and preparation method - Google Patents

Memory cell array structure and preparation method Download PDF

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Publication number
CN116209259A
CN116209259A CN202211358553.5A CN202211358553A CN116209259A CN 116209259 A CN116209259 A CN 116209259A CN 202211358553 A CN202211358553 A CN 202211358553A CN 116209259 A CN116209259 A CN 116209259A
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electrode
capacitor
memory cell
layer
cell array
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CN116209259B (en
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戴瑾
梁静
余泳
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B12/00—Superconductive or hyperconductive conductors, cables, or transmission lines
    • H01B12/02—Superconductive or hyperconductive conductors, cables, or transmission lines characterised by their form
    • H01B12/10—Multi-filaments embedded in normal conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/10—DRAM devices comprising bipolar components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The present disclosure provides a memory cell array structure and a method of manufacturing the same, the memory cell array structure including an insulating substrate, a three-dimensional memory cell array formed on a surface of the insulating substrate, the three-dimensional memory cell array including a plurality of layers of memory cells, and a plurality of memory cells, a plurality of bit lines, and a plurality of word lines located at each layer; wherein each memory cell comprises a transistor and a capacitor comprising a first electrode, a second electrode, and a capacitor dielectric layer; the transistor is electrically connected with the capacitor; each bit line extends along a first direction, the first direction being parallel to the insulating substrate surface; memory cells located on the same layer and symmetrically distributed on both sides of the same bit line share the same bit line; the capacitors of the memory cells between adjacent bit lines of different layers in the vertical direction share the same second electrode; each word line extends along a second direction, the second direction being perpendicular to the insulating substrate surface; memory cells of different layers in the vertical direction share the same word line.

Description

Memory cell array structure and preparation method
Technical Field
The present disclosure relates to the field of semiconductor materials, and more particularly, to a memory cell array structure and a method for manufacturing the same.
Background
Currently, the manufacture of dynamic random access memory (Dynamic Random Access memory, DRAM) generally adopts a two-dimensional structure, and reduces the size of bit lines, word lines, transistors, etc., to increase the number of one transistor-capacitor (1Transistor and 1Capacitor,1T1C) elements to meet the requirements of next-generation memories.
Disclosure of Invention
The present disclosure provides a memory cell array and a method of manufacturing the same. Compared with the traditional process, the memory cell array can be directly stacked and etched for multiple layers at one time, so that the process flow of array stacking is optimized, and the manufacturing cost is reduced.
The present disclosure provides a memory cell array structure,
the semiconductor device comprises an insulating substrate, a three-dimensional memory cell array formed on the surface of the insulating substrate, wherein the three-dimensional memory cell array comprises a plurality of layers of memory cells, a plurality of bit lines and a plurality of word lines, wherein the memory cells are positioned on each layer;
wherein each memory cell comprises a transistor and a capacitor comprising a first electrode, a second electrode, and a capacitor dielectric layer; the transistor is electrically connected with the capacitor; each bit line extends along a first direction, the first direction being parallel to the insulating substrate surface; memory cells located on the same layer and symmetrically distributed on both sides of the same bit line share the same bit line; the capacitors of the memory cells between adjacent bit lines of different layers in the vertical direction share the same second electrode;
each word line extends along a second direction, the second direction being perpendicular to the insulating substrate surface; memory cells of different layers in the vertical direction share the same word line.
In an exemplary embodiment, the transistor includes:
a ring channel;
a ring-shaped gate oxide layer;
a gate;
a first pole;
a second pole;
the storage units in different layers are provided with through holes perpendicular to the substrate, and the through holes penetrate through the storage units;
the annular channels are arranged on the periphery of the inner side of the through hole; the annular gate oxide layer is arranged around the inner side of the annular channel; the grid electrode is arranged on the inner side of the annular grid oxide layer;
the grid electrode is connected with the corresponding word line;
the first pole is in contact with a first side of the ring channel; the first electrode is used for being connected with a corresponding bit line;
the second pole being in contact with a second side of the ring channel opposite the first side; the second pole is used for being connected with the capacitor.
In an exemplary embodiment, the capacitor includes:
a first electrode of the capacitor contacts a second side of the ring channel;
the capacitor dielectric layer is located on the first electrode of the capacitor;
the second electrode surrounds the capacitor dielectric layer.
In an exemplary embodiment, the first electrode of the capacitor and the bit line have the same thickness.
In an exemplary embodiment, the material of the ring channel is an oxide semiconductor material.
In an exemplary embodiment, the oxide semiconductor material includes at least one of indium oxide, tin oxide, indium zinc-based oxide, tin zinc-based oxide, aluminum zinc-based oxide, indium gallium zinc-based oxide, indium aluminum zinc-based oxide, indium tin zinc-based oxide, tin gallium zinc-based oxide, aluminum gallium zinc-based oxide, tin aluminum zinc-based oxide.
In one exemplary embodiment, the memory cell array structure further includes a predetermined number of word line control transistors; each word line control transistor is connected to each word line, respectively, and is configured to switch-control the connected word line.
The present disclosure provides a method for manufacturing a memory cell array structure, including:
providing an insulating substrate;
forming a first stacked body with alternating dielectric layers and conductive material layers on the insulating substrate;
forming a through hole array in the first stacking body according to preset positions of the through holes;
forming a ring channel, a ring gate oxide layer and a word line inside each through hole of the through hole array;
forming a plurality of capacitors and a plurality of bit lines;
the two sides of one bit line are symmetrically distributed with a plurality of capacitors and a plurality of through holes, and each capacitor comprises a first electrode, a second electrode and a capacitor dielectric layer; the capacitors of the memory cells between adjacent bit lines of different layers in the vertical direction share the same second electrode; each layer of the layer line extends along a first direction, and the first direction is parallel to the surface of the insulating substrate; the word line extends along a second direction, which is perpendicular to the insulating substrate surface.
In one exemplary embodiment, forming a ring channel, a ring gate oxide, and a word line inside each via of the array of vias includes:
forming a ring channel by depositing a semiconductive material channel material on the periphery of the inner side of each through hole through an atomic layer;
forming an annular gate oxide layer by depositing high-K dielectric on the periphery of the inner side of the formed annular channel through an atomic layer;
and filling conductive materials on the inner side of the annular gate oxide layer to form word lines.
In one exemplary embodiment, forming a plurality of capacitors and a plurality of bit lines includes:
forming a first groove by etching all the conductive material layers and the dielectric layers between every two adjacent groups of through holes and at a preset distance from each group of through holes; wherein each group of through holes comprises two adjacent rows of through holes; selectively etching all the dielectric layers and removing all the ring channels positioned on the dielectric layers;
etching each conductive material layer according to a preset pattern for each set of through holes to form a first electrode of each capacitor and a bit line; the number of first electrodes of the formed capacitor is the same as the number of the group of through holes; the number of the bit lines is the same as the number of the conductive material layers occupied by the group of through holes;
refilling the second stack with a dielectric material; the second stacking body is formed by etching each conductive material layer according to a preset pattern;
forming a second groove by etching a portion between each adjacent two sets of through holes of the second stack;
filling a dielectric material between the second trench and the first electrode of the capacitor to form a dielectric layer of the capacitor;
and filling a conductor in the second groove to form a second electrode shared by a plurality of capacitors.
In one exemplary embodiment, removing all of the ring channels located in the dielectric layer includes:
the ring channel in the dielectric layer is selectively etched away.
In one exemplary embodiment, removing all of the ring channels located in the dielectric layer includes:
the addition of chemicals deactivates the channel material of the ring channel located in the dielectric layer.
In an exemplary embodiment, the method of manufacturing further includes forming a plurality of word line control transistors; each word line control transistor is connected to a corresponding one of the word lines.
Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. Other advantages of the present disclosure may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.
FIG. 1A is a horizontal cross-sectional view of a single layer of a memory cell array according to an embodiment of the present disclosure;
FIG. 1B is a vertical cross-sectional view of a memory cell array according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of a method for fabricating a memory cell array structure according to an embodiment of the disclosure;
FIG. 3 is a vertical cross-sectional view of a stack of memory cell array structures according to an embodiment of the present disclosure;
FIG. 4A is a top view of a via of a memory cell array structure according to an embodiment of the present disclosure;
FIG. 4B is a vertical cross-sectional view of a via of a memory cell array structure according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a method of fabricating a via-in-structure according to an embodiment of the present disclosure;
FIG. 6A is a horizontal cross-sectional view of a via-in-structure according to an embodiment of the present disclosure;
FIG. 6B is a vertical cross-sectional view of a via-in-structure according to an embodiment of the disclosure;
fig. 7A is a horizontal cross-sectional view of an embodiment of the present disclosure after forming an in-via transistor;
fig. 7B is a vertical cross-sectional view of an embodiment of the present disclosure after forming an in-via transistor;
FIG. 8A is a horizontal cross-sectional view of an etched first capacitive slot according to an embodiment of the present disclosure;
FIG. 8B is a vertical cross-sectional view of an etched first capacitive slot according to an embodiment of the present disclosure;
FIG. 9A is a horizontal cross-sectional view of a dielectric layer etched away and a ring channel at the dielectric layer in accordance with an embodiment of the present disclosure;
FIG. 9B is a vertical cross-section of the ring channel etched away from the dielectric layer and where the dielectric layer is in accordance with an embodiment of the present disclosure;
FIG. 10 is a horizontal cross-sectional view of an etched first electrode and bit line according to an embodiment of the present disclosure;
FIG. 11A is a horizontal cross-sectional view of an embodiment of the present disclosure after a first capacitor trench has been etched and then refilled with dielectric;
fig. 11B is a vertical cross-sectional view of an embodiment of the present disclosure after the first capacitor trench has been etched and then refilled with dielectric.
Detailed Description
In this disclosure, to distinguish between two electrodes of a transistor except a gate electrode, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source or a drain, the second electrode may be a drain or a source, and in addition, the gate electrode of the transistor is referred to as a control electrode. In the case of using transistors having opposite polarities, or in the case of a change in current direction during circuit operation, the functions of the "source" and the "drain" may be exchanged with each other. Thus, in this disclosure, "source" and "drain" may be interchanged.
Embodiments of the present disclosure provide a memory cell array structure
The semiconductor device comprises an insulating substrate, a three-dimensional memory cell array formed on the surface of the insulating substrate, wherein the three-dimensional memory cell array comprises a plurality of layers of memory cells, a plurality of bit lines and a plurality of word lines, wherein the memory cells are positioned on each layer;
wherein each memory cell comprises a transistor and a capacitor comprising a first electrode, a second electrode, and a capacitor dielectric layer; the transistor is electrically connected with the capacitor; each bit line extends along a first direction, the first direction being parallel to the insulating substrate surface; memory cells located on the same layer and symmetrically distributed on both sides of the same bit line share the same bit line; the capacitors of the memory cells between adjacent bit lines of different layers in the vertical direction share the same second electrode;
each word line extends along a second direction, the second direction being perpendicular to the insulating substrate surface; memory cells of different layers in the vertical direction share the same word line.
In this way, the memory cell array structure may include a multi-layer memory structure, in each layer of memory structure, memory cells symmetrically distributed on two sides of the same bit line share the same bit line, memory cells of different layers overlapping in a projection manner in a vertical direction share the same word line, and memory cells between adjacent bit lines overlapping in a projection manner in different layers in a vertical direction share a second electrode of a capacitor, so that a 3D stack is formed among the word line, the bit line and the memory cells, and a semiconductive material structure having a 3D structure is obtained.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
Fig. 1A shows a plan view illustration of a single layer of a memory cell array (the illustration of fig. 1A applies to all but fig. 2 and 5). Although a single layer is shown for simplicity, the memory cell array may include one or more layers stacked in a vertical direction. For example, the memory cell array may include three or more layers. The number of layers of the memory cell array may be limited only by the capabilities of the available lithography, etching and deposition tools. In the drawings of the embodiments of the present disclosure, the memory cell array structure is exemplarily illustrated with 3 layers, each layer having 2 bit lines, but in practical applications, more or fewer layers may be formed, each layer having a memory cell array structure with more or fewer bit lines.
The memory cell array structure includes:
a substrate (not shown);
at least one layer of memory structure is formed over the substrate. Each layer of memory structure includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cell structures. Each memory cell structure may include a ring channel, a ring gate oxide, a capacitor first electrode, a capacitor dielectric layer, and a capacitor second electrode. The bit line also acts as the source or drain (i.e., first pole) of the transistor in the corresponding memory cell, the word line also acts as the gate of the transistor in the corresponding memory cell, and the capacitor first electrode also acts as the source or drain (i.e., second pole) of the transistor in the corresponding memory cell.
The bit lines extend in a first direction, which is parallel to the substrate direction. Memory cell structures in a layer symmetrically distributed with the same bit line share the same bit line. Memory cell structures corresponding to the same bit line are arranged in the extending direction of the bit line. The memory cell structures corresponding to the same bit line are not limited to 6. The number of bit lines in the same layer may be 1 or more, and is not limited to the 2 shown.
The word lines extend in a second direction, which is perpendicular to the substrate direction. Memory cells with overlapping vertical projection positions share the same word line. The word lines extend through the entire memory structure.
Each memory cell structure includes a transistor and a capacitor. The transistor includes a ring channel, a ring gate oxide, a word line that serves as a gate of the transistor, a bit line that serves as a source or drain of the transistor, and a capacitor first electrode that serves as a source or drain of the transistor. One side of the ring channel is in contact with the capacitor first electrode, forming a source or drain of the transistor, and electrically connecting the formed source or drain of the transistor with the capacitor. The other side of the ring channel corresponding to the side contacts the bit line to form a source or drain of the transistor and electrically connects the source or drain of the transistor to the bit line. The inner periphery of the annular gate oxide layer is in contact with the word line, which serves as the gate of the transistor.
The capacitor may include a capacitor first electrode, a capacitor dielectric layer, and a capacitor second electrode. The dielectric layer of the capacitor may be formed of a dielectric disposed on the surface of the first electrode of the capacitor. The capacitor second electrode may be composed of a conductive material. The shape of the capacitor dielectric around the first electrode of the capacitor in the drawing is not limited to U-shape, but may be other shapes that can constitute the capacitor, and is not limited herein. The plurality of capacitors share the second electrode.
In the exemplary embodiments of the present disclosure, the substrate is an insulating substrate, and any suitable oxide or nitride may be selected. The isolation medium of the memory cell array structure can be a low-K dielectric material, such as silicon oxide, silicon nitride, etc. The ring gate oxide and capacitor dielectric layers may use high K dielectric materials, which may include, but are not limited to, silicon oxide, aluminum oxide, hafnium oxide, and the like. The annular gate oxide layer may comprise multiple annular gate oxide layers of a variety of different materials. The capacitor dielectric layer may use any suitable high-K dielectric material, which may include, for example, but is not limited to, silicon oxide, aluminum oxide, hafnium oxide, and the like. The word lines and bit lines may be formed of any suitable conductive material, such as a conductive material (e.g., copper, cobalt, tungsten, titanium, aluminum, ruthenium, etc.). The ring channel may be formed of the following materials: amorphous, polycrystalline, or crystalline group iii-v materials; amorphous, polycrystalline or crystalline silicon; amorphous, polycrystalline or crystalline germanium; amorphous, polycrystalline, or crystalline silicon germanium; amorphous, polycrystalline, or crystalline gallium arsenide; amorphous, polycrystalline or crystalline indium antimonide; amorphous, polycrystalline or crystalline indium gallium arsenide; amorphous, polycrystalline or crystalline Indium Gallium Oxide (IGO); or amorphous, polycrystalline or crystalline Indium Gallium Zinc Oxide (IGZO), etc. Illustratively, the oxide semiconductor may include at least one of indium or zinc. The oxide semiconductor may also contain aluminum, gallium, yttrium, tin, or the like, for example. The oxide semiconductor may also contain one or more of boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like, for example. Illustratively, the oxide semiconductor contains indium, an element M, and zinc, and the element M may be aluminum, gallium, yttrium, tin, or the like, or may be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like, or may be a combination of a plurality of the above elements. For example, an oxide semiconductor including indium, gallium, and zinc may be referred to as Indium Gallium Zinc Oxide (IGZO). Illustratively, if the material of the semiconductor layer of one transistor is IGZO.
For example, the oxide semiconductor material includes at least one of indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, tin aluminum zinc oxide.
In an exemplary embodiment of the present disclosure, the first electrode of the capacitor and the bit line have the same thickness.
In an exemplary embodiment of the present disclosure, to reduce transistor leakage with overlapping vertical projections, the wordline periphery between layers in the second direction is free of ring channels.
In the exemplary embodiment of the present disclosure, the cross-sectional shape of the ring channel may be a zigzag shape, or may be other shapes, which is not limited herein.
In an exemplary embodiment of the present disclosure, each memory cell is isolated with a low K dielectric material between each memory cell. For example, isolation is required between multiple memory cells sharing the same bit line; isolation is also required between memory cells that do not share the same bit line; memory cells of the same word line between different layers also need to be isolated (typically with high K dielectric material and low K dielectric material). Isolation is required between the exposed word lines.
As seen from fig. 1A and 1B, the 48 memory cell structures of the embodiments of the present disclosure use only 8 bit lines and 12 word lines, and the number of the bit lines and the word lines is much smaller than that of the memory cells, so that the memory cell array structure is simple and compact, not only improves the memory density, but also is convenient to manufacture.
In one exemplary embodiment, the memory cell array structure further includes a predetermined number of word line control transistors; each word line control transistor is connected to each word line, respectively, and is configured to switch-control the connected word line. The switching control of the whole word line is realized through the word line control transistor (namely the switching transistor on the top layer), so that the design of the peripheral circuit in the vertical direction of the array is facilitated, and the circuit area is effectively reduced. The word line control transistor is perpendicular to the substrate and is connected with the word line up and down, and the peripheral circuit can realize the switching control of the word line through the word line control transistor. During read-write operation, the word line control transistor opens the corresponding word line and simultaneously opens the bit line.
The embodiment of the disclosure also provides a preparation method of the memory cell array structure, as shown in fig. 2, including the following steps S11-S14:
s11, providing an insulating substrate; forming a first stacked body with alternating dielectric layers and conductive material layers on the insulating substrate;
s12, forming a through hole array in the first stacking body according to preset positions of the through holes;
s13, forming a ring channel, a ring gate oxide layer and a word line on the inner side of each through hole of the through hole array;
s14, forming a plurality of capacitors and a plurality of bit lines;
the two sides of one bit line are symmetrically distributed with a plurality of capacitors and a plurality of through holes, and each capacitor comprises a first electrode, a second electrode and a capacitor dielectric layer; the capacitors of the memory cells between adjacent bit lines of different layers in the vertical direction share the same second electrode; each layer of the layer line extends along a first direction, and the first direction is parallel to the surface of the insulating substrate; the word line extends along a second direction, which is perpendicular to the insulating substrate surface.
The number of capacitors symmetrically distributed on both sides of one bit line may be the same as the number of via holes sharing the bit line; in step S11, as shown in fig. 3, a dielectric layer is provided on the insulating substrate (not shown), and a conductive material layer is provided on the dielectric layer. The dielectric layers and the conductive material layers are alternately stacked to form a stacked body. The dielectric material of the dielectric layer may be a low-K dielectric material, such as silicon oxide, silicon nitride, or the like. The material of the conductive material layer may be any suitable conductive material including, but not limited to, copper, cobalt, tungsten, titanium, aluminum, ruthenium, and the like.
It should be noted that fig. 3 is only an example, and that the specific number of stacked layers is limited only by the capabilities of the available lithography, etching and deposition tools.
In step S12, an array of through holes penetrating the stack may be formed in the stack at preset through hole positions. As shown in fig. 4A, 4B, a total of 12 through holes of 3 rows and 4 columns are provided in the drawing, which is merely an example, and the number and arrangement layout of the through holes are actually set as needed. The through holes penetrate through all dielectric layers and conductive material layers and are perpendicular to the substrate. The through holes in the figures are square, and in other exemplary embodiments of the present disclosure, other shapes, such as rectangular or circular, etc., may be used, without limitation.
In exemplary embodiments of the present disclosure, the via holes may be formed by photolithography and etching.
In step S13, a ring channel, a ring gate oxide layer, and a word line are formed inside each via of the via array, including the following steps S131-S133 (as shown in fig. 5):
s131, forming a ring channel by depositing a semiconductive material channel material on the periphery of the inner side of each through hole through an atomic layer;
s132, forming an annular gate oxide layer on the periphery of the inner side of the formed annular channel through atomic layer deposition of a high-K dielectric;
s133, filling conductive materials on the inner side of the annular gate oxide layer to form word lines.
In step S131, for each via hole, a ring channel may be formed by atomic layer deposition of a semiconductive material channel material. The semiconductive material channel materials herein may include, but are not limited to, amorphous, polycrystalline, or crystalline group iii-v materials; amorphous, polycrystalline or crystalline silicon; amorphous, polycrystalline or crystalline germanium; amorphous, polycrystalline, or crystalline silicon germanium; amorphous, polycrystalline, or crystalline gallium arsenide; amorphous, polycrystalline or crystalline indium antimonide; amorphous, polycrystalline or crystalline indium gallium arsenide; amorphous, polycrystalline or crystalline Indium Gallium Oxide (IGO); or amorphous, polycrystalline or crystalline Indium Gallium Zinc Oxide (IGZO), etc. The cross-sectional shape of the ring channel as in fig. 6A, 6B may be a zigzag shape, but may be any other suitable shape.
In step S132, a ring-shaped gate oxide layer is formed around the inner side of the formed ring channel by atomic layer deposition of a high K dielectric, such as the ring-shaped gate oxide layer shown in fig. 6A and 6B. The material of the annular gate oxide layer may be a high-K dielectric material, and may include, but is not limited to, silicon oxide, aluminum oxide, hafnium oxide, and the like, for example. The annular gate oxide layer is in contact with the annular channel, and the cross section of the annular gate oxide layer can be in a shape like a Chinese character 'hui', but can be in other suitable shapes.
In step S133, the word lines are filled with a conductive material within the annular gate oxide layer, and the material of the word lines may be any suitable conductive material, such as a conductive material (e.g., copper, cobalt, tungsten, titanium, aluminum, ruthenium, etc.). The word lines extend through the stack dielectric layers and the conductive material layers, and the vertically-projected overlapping memory cells share one word line, as shown in fig. 6A and 6B, and the cross-sectional shape of the word lines may be square, or may be other suitable shapes, such as circular, in other exemplary embodiments of the present disclosure.
Taking the structures shown in fig. 4A and 4B as an example, a cross-sectional view after forming a ring channel, a ring gate oxide and a word line by a via is shown in fig. 7A and a vertical cross-sectional view is shown in fig. 7B.
In step S14, forming a plurality of capacitors and a plurality of bit lines, comprising:
forming a first groove by etching all the conductive material layers and the dielectric layers between every two adjacent groups of through holes and at a preset distance from each group of through holes; wherein each group of through holes comprises two adjacent rows of through holes; selectively etching all the dielectric layers and removing all the ring channels positioned on the dielectric layers;
etching each conductive material layer according to a preset pattern for each set of through holes to form a first electrode of each capacitor and a bit line; the number of first electrodes of the formed capacitor is the same as the number of the group of through holes; the number of the bit lines is the same as the number of the conductive material layers occupied by the group of through holes;
refilling the second stack with a dielectric material; the second stacking body is formed by etching each conductive material layer according to a preset pattern;
forming a second groove by etching a portion between each adjacent two sets of through holes of the second stack;
filling a dielectric material between the second trench and the first electrode of the capacitor to form a dielectric layer of the capacitor;
and filling a conductor in the second groove to form a second electrode shared by a plurality of capacitors.
Fig. 8A and 8B show the first grooves (the white portions in the drawing, i.e., the first grooves) formed.
Fig. 9A and 9B show the structure after etching away all of the dielectric layer and removing all of the ring channels located in the dielectric layer. Fig. 10 shows a cross section of the etched first electrode of each capacitor, and the bit line.
When the number of through holes per column is 3, the preset pattern may be a "rich" character pattern as shown in fig. 10. When the number of the through holes in each row is not 3, the preset pattern is a similar 'Feng' pattern, and the number of the transverse one in the similar 'Feng' pattern is the same as the number of the through holes in each row. In other exemplary embodiments of the present disclosure, the shape of the "a" and "a" of the above-mentioned chevron pattern may be a "cross" shape or a cross-fold shape. The first electrode of the capacitor is etched and the bit line is also present between the two columns of vias, for example, the bit line may be formed by two vertical-type intermediate conductive material regions that are non-word-type.
The first electrode of each capacitor is in contact with a corresponding ring channel;
fig. 11A and 11B illustrate a second stack formed after refilling with dielectric material.
Fig. 1A and 1B illustrate a capacitor dielectric layer formed by filling a high K dielectric in a trench after etching a second capacitor trench, and a capacitor second electrode formed by filling a conductor outside the trench.
The first electrode of the capacitor is substantially part of the conductive material layer, and the material of the first electrode of the capacitor is the same as that of the conductive material layer. As shown in fig. 1A, 1B, the capacitor dielectric layer surrounds the capacitor first electrode in a U-shape, and the capacitor second electrode surrounds the capacitor dielectric layer. When the preset pattern changes, the shape of the capacitor dielectric layer surrounding the first electrode of the capacitor also changes.
In exemplary embodiments of the present disclosure, the high-K dielectric material of the capacitor dielectric layer may include, but is not limited to, silicon oxide, aluminum oxide, hafnium oxide, and the like. The material of the second electrode of the capacitor may be a conductive material, such as copper, cobalt, tungsten, titanium, aluminum, ruthenium, etc.
In an exemplary embodiment of the present disclosure, to reduce leakage of transistors adjacent to the upper and lower layers, the ring channel in the dielectric layer is typically removed. Fig. 9B shows the case of removing the ring channel in the dielectric layer.
In an exemplary embodiment of the present disclosure, removing all of the ring channels located in the dielectric layer may include:
the ring channel in the dielectric layer is etched away.
In an exemplary embodiment of the present disclosure, removing all of the ring channels located in the dielectric layer includes:
the addition of chemicals deactivates the channel material of the ring channel located in the dielectric layer.
In an exemplary embodiment, the method of manufacturing further includes, in an exemplary embodiment, forming a plurality of word line control transistors; each word line control transistor is connected to a corresponding one of the word lines.
Depositing metal on the word line on the upper surface of the memory cell array structure formed in the step S14 and selectively etching the metal to serve as a bottom electrode of the word line control transistor; depositing a low-K dielectric material at the bottom electrode of the word line control transistor; depositing metal on the low-K dielectric material, and etching a through hole of the bottom electrode at the lower part; depositing IGZO in the through hole through ALD atomic layer to form a channel, and then depositing a high-K dielectric material to form a gate oxide layer; and then filling metal in the through holes. Thereby completing the fabrication of the word line control transistor.
The memory cell array structure provided by the embodiment of the disclosure can optimize the process flow of array stacking and reduce the manufacturing cost.
The present disclosure describes several embodiments, but the description is illustrative and not limiting, and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
Any features shown and/or discussed in this disclosure may be implemented alone or in any suitable combination.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (13)

1. A memory cell array structure is characterized in that,
the semiconductor device comprises an insulating substrate, a three-dimensional memory cell array formed on the surface of the insulating substrate, wherein the three-dimensional memory cell array comprises a plurality of layers of memory cells, a plurality of bit lines and a plurality of word lines, wherein the memory cells are positioned on each layer;
wherein each memory cell comprises a transistor and a capacitor comprising a first electrode, a second electrode, and a capacitor dielectric layer; the transistor is electrically connected with the capacitor; each bit line extends along a first direction, the first direction being parallel to the insulating substrate surface; memory cells located on the same layer and symmetrically distributed on both sides of the same bit line share the same bit line; the capacitors of the memory cells between adjacent bit lines of different layers in the vertical direction share the same second electrode;
each word line extends along a second direction, the second direction being perpendicular to the insulating substrate surface; memory cells of different layers in the vertical direction share the same word line.
2. The memory cell array structure of claim 1, wherein,
the transistor includes:
a ring channel;
a ring-shaped gate oxide layer;
a gate;
a first pole;
a second pole;
the storage units in different layers are provided with through holes perpendicular to the substrate, and the through holes penetrate through the storage units;
the annular channels are arranged on the periphery of the inner side of the through hole; the annular gate oxide layer is arranged around the inner side of the annular channel; the grid electrode is arranged on the inner side of the annular grid oxide layer;
the grid electrode is connected with the corresponding word line;
the first pole is in contact with a first side of the ring channel; the first electrode is used for being connected with a corresponding bit line;
the second pole being in contact with a second side of the ring channel opposite the first side; the second pole is used for being connected with the capacitor.
3. The memory cell array structure of claim 2, wherein,
a first electrode of the capacitor contacts a second side of the ring channel;
the capacitor dielectric layer is located on the first electrode of the capacitor;
the second electrode surrounds the capacitor dielectric layer.
4. The memory cell array structure of claim 3, wherein,
the first electrode of the capacitor and the bit line have the same thickness.
5. The memory cell array structure of claim 2, wherein,
the material of the ring channel is an oxide semiconductor material.
6. The memory cell array structure of claim 5, wherein,
the oxide semiconductor material comprises at least one of indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide and tin aluminum zinc oxide.
7. The memory cell array structure of claim 1, wherein,
the memory cell array structure further includes a predetermined number of word line control transistors; each word line control transistor is connected to each word line, respectively, and is configured to switch-control the connected word line.
8. A method for manufacturing a memory cell array structure, applied to the memory cell array structure of any one of claims 1 to 7, characterized in that,
providing an insulating substrate;
forming a first stacked body with alternating dielectric layers and conductive material layers on the insulating substrate;
forming a through hole array in the first stacking body according to preset positions of the through holes;
forming a ring channel, a ring gate oxide layer and a word line inside each through hole of the through hole array;
forming a plurality of capacitors and a plurality of bit lines;
the two sides of one bit line are symmetrically distributed with a plurality of capacitors and a plurality of through holes, and each capacitor comprises a first electrode, a second electrode and a capacitor dielectric layer; the capacitors of the memory cells between adjacent bit lines of different layers in the vertical direction share the same second electrode; each layer of the layer line extends along a first direction, and the first direction is parallel to the surface of the insulating substrate; the word line extends along a second direction, which is perpendicular to the insulating substrate surface.
9. The method of claim 8, wherein,
forming a ring channel, a ring gate oxide layer and a word line inside each via of the via array, comprising:
forming a ring channel by depositing a semiconductive material channel material on the periphery of the inner side of each through hole through an atomic layer;
forming an annular gate oxide layer by depositing high-K dielectric on the periphery of the inner side of the formed annular channel through an atomic layer;
and filling conductive materials on the inner side of the annular gate oxide layer to form word lines.
10. The method of claim 9, wherein,
forming a plurality of capacitors and a plurality of bit lines, comprising:
forming a first groove by etching all the conductive material layers and the dielectric layers between every two adjacent groups of through holes and at a preset distance from each group of through holes; wherein each group of through holes comprises two adjacent rows of through holes; selectively etching all the dielectric layers and removing all the ring channels positioned on the dielectric layers;
etching each conductive material layer according to a preset pattern for each set of through holes to form a first electrode of each capacitor and a bit line; the number of first electrodes of the formed capacitor is the same as the number of the group of through holes; the number of the bit lines is the same as the number of the conductive material layers occupied by the group of through holes;
refilling the second stack with a dielectric material; the second stacking body is formed by etching each conductive material layer according to a preset pattern;
forming a second groove by etching a portion between each adjacent two sets of through holes of the second stack;
filling a dielectric material between the second trench and the first electrode of the capacitor to form a dielectric layer of the capacitor;
and filling a conductor in the second groove to form a second electrode shared by a plurality of capacitors.
11. The method of manufacturing of claim 10, wherein removing all of the ring channels located in the dielectric layer comprises:
the ring channel in the dielectric layer is selectively etched away.
12. The method of manufacturing of claim 10, wherein removing all of the ring channels located in the dielectric layer comprises:
the addition of chemicals deactivates the channel material of the ring channel located in the dielectric layer.
13. The method of manufacturing as set forth in claim 8, further comprising:
forming a plurality of word line control transistors; each word line control transistor is connected to a corresponding one of the word lines.
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