CN116209246B

CN116209246B - Semiconductor device, method of manufacturing the same, and electronic apparatus

Info

Publication number: CN116209246B
Application number: CN202210802655.5A
Authority: CN
Inventors: 王祥升; 戴瑾; 王桂磊; 赵超
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2022-07-07
Filing date: 2022-07-07
Publication date: 2024-03-15
Anticipated expiration: 2042-07-07
Also published as: CN116209246A

Abstract

A semiconductor device includes a substrate, a peripheral circuit region and a memory region which are sequentially stacked on one side of the substrate, a circuit of the peripheral circuit region being electrically connected to a circuit of the memory region; the storage area includes: a plurality of memory cell columns, each of which is formed of a plurality of memory cells stacked in a first direction, the memory cells including transistors and capacitors, the structures of the transistors and the capacitors being the same as the definitions of the specification; a plurality of bit lines, source regions of transistors of the plurality of memory cells being connected to a common bit line; a plurality of word lines; the peripheral circuit region includes a first gate transistor electrically connected to the bit line and a second gate transistor electrically connected to the word line. According to the semiconductor device, the plurality of memory cells are stacked, and the peripheral circuit and the memory cells are stacked to form a three-dimensional stacked structure, so that the memory density of the semiconductor memory can be effectively improved.

Description

Semiconductor device, method of manufacturing the same, and electronic apparatus

Technical Field

The present invention relates to the field of semiconductor devices, and more particularly, to a semiconductor device, a method of manufacturing the same, and an electronic apparatus.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a common system memory that stores data in memory cells having capacitors and array transistors. The capacitor may be set to a charged state or a discharged state, taking both states to represent "0" and "1". The DRAM further includes peripheral transistors to form peripheral circuits. Peripheral circuits and array transistors handle data input/output (I/O) and memory cell operations (e.g., write or read).

As DRAM technology moves toward higher density and higher capacity, the miniaturization of semiconductor structures encounters bottlenecks, which make it difficult to further miniaturize. And the number of capacitors increases and the size decreases, resulting in longer process time and more complex process flows for manufacturing the capacitors.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the application.

The embodiment of the application provides a semiconductor device, a manufacturing method thereof and electronic equipment, wherein a plurality of memory cells are stacked, a peripheral circuit and the memory cells are stacked to form a three-dimensional stacked structure, more memory cells can be arranged on a limited substrate area, and the memory density of a semiconductor memory is improved.

The embodiment of the application provides a semiconductor device, which comprises: the substrate, peripheral circuit area and storage area that the cascade is set up in one side of the said substrate sequentially, the circuit of the said peripheral circuit area is connected with circuit of the said storage area electrically; the storage area includes:

a plurality of memory cell columns extending in a first direction, each of the memory cell columns being formed by stacking a plurality of memory cells disposed on one side of the substrate in the first direction, the plurality of memory cell columns being arranged in a second direction and a third direction to form an array;

each memory cell includes a transistor and a capacitor, the transistor including a semiconductor layer and a gate electrode, the semiconductor layer extending in a second direction and including a source region, a channel region, and a drain region in this order; the grid surrounds the periphery of the channel region, and a grid insulating layer is arranged between the grid and the channel region;

the capacitor comprises a first electrode plate, a second electrode plate and a dielectric layer arranged between the first electrode plate and the second electrode plate, wherein the first electrode plate, the dielectric layer and the second electrode plate sequentially encircle the periphery of one end, far away from the channel region, of the drain region;

A plurality of bit lines extending in the first direction, source regions of transistors of a plurality of memory cells of two adjacent memory cell columns in the second direction being connected to one common bit line;

a plurality of word lines extending in a third direction, wherein the memory area is provided with one memory cell column in the third direction, each of the word lines being formed of gates of transistors of one memory cell of the one memory cell column arranged in the third direction; alternatively, the memory area is provided with a plurality of memory cell columns in a third direction, and each of the word lines is formed by connecting together gates of transistors of a plurality of memory cells arranged in the third direction;

the peripheral circuit region comprises a peripheral circuit, the peripheral circuit comprises a first gating transistor group and a second gating transistor group, the first gating transistor group comprises at least one first gating transistor, each first gating transistor is electrically connected with one bit line, the second gating transistor group comprises at least one second gating transistor, and each second gating transistor is electrically connected with one word line.

In the embodiment of the present application, lengths of the plurality of word lines arranged along the first direction may be different, and the plurality of word lines arranged along the first direction and located at different layers may be formed in a stepped shape.

In the embodiment of the present application, the material of the semiconductor layer may be a metal oxide semiconductor material, and the material of the word line may be a metal oxide conductor material.

In this embodiment of the present application, the first electrode plate may be an inner electrode plate, the second electrode plate may be an outer electrode plate, and the drain region is connected to the inner electrode plate.

In an embodiment of the present application, the memory cell column may further include an interlayer isolation layer disposed between gates of transistors of two adjacent memory cells in the memory cell column, and isolating the gates of the transistors of the two adjacent memory cells.

In an embodiment of the present application, the semiconductor device may further include one or more memory cell isolation pillars extending along the first direction, and one of the memory cell isolation pillars may be disposed every two memory cell columns spaced apart in the second direction.

In an embodiment of the present application, the semiconductor device may further include an internal support layer, which may be disposed between two semiconductor layers adjacent in the first direction, configured to provide support to the semiconductor layers.

In the embodiment of the application, the peripheral circuit region may further include a metal contact layer and a metal interconnection layer; the peripheral circuit is arranged on one side of the substrate, the metal contact layer is arranged on one side of the peripheral circuit far away from the substrate, a metal contact column is arranged in the metal contact layer, the metal interconnection layer is arranged on one side of the metal contact layer far away from the substrate, and a metal wire is arranged in the metal interconnection layer; the memory cell columns are arranged on one side of the metal interconnection layer away from the substrate; the metal wire comprises a first metal wire and a second metal wire, the metal contact column comprises a first metal contact column and a second metal contact column, one end of the first metal wire is electrically connected with the bit line of the storage area, the other end of the first metal wire is electrically connected with the first gating transistor through the first metal contact column, one end of the second metal wire is electrically connected with the word line of the storage area, and the other end of the second metal wire is electrically connected with the second gating transistor through the second metal contact column.

The embodiment of the application also provides a manufacturing method of the semiconductor device, which comprises the following steps:

a peripheral circuit is arranged on one side of the substrate to form a peripheral circuit area;

a plurality of composite layers consisting of a sacrificial layer and a channel layer are stacked along a first direction on one side of the peripheral circuit, which is far away from the substrate, in an staggered sequence of the sacrificial layer and the channel layer;

defining a storage unit area in a plurality of composite layers, etching a bit line groove along a first direction, and filling isolation materials in the bit line groove;

removing the sacrificial layer, and forming a plurality of semiconductor layers which are arrayed along the first direction and the third direction and extend along the second direction by the residual channel layers, wherein the semiconductor layers sequentially comprise a source region, a channel region and a drain region;

a grid insulating layer and a grid electrode which encircle the channel region are sequentially arranged around the channel region of the semiconductor layer, and the semiconductor layer and the grid electrode form a transistor; and one of the semiconductor layers arranged in the third direction, the gate electrode on the one semiconductor layer being made to be a word line; alternatively, the semiconductor layers arranged in the third direction are plural, and the gates on the plural semiconductor layers arranged in the third direction are connected together in the third direction to form the word line;

A first electrode plate, a dielectric layer and a second electrode plate which surround one end of the drain region are sequentially arranged around one end of the drain region of the semiconductor layer, which is far away from the channel region, and the first electrode plate, the dielectric layer and the second electrode plate form a capacitor;

removing isolation materials in the bit line grooves, filling bit line materials in the bit line grooves to form bit lines extending along a first direction, and connecting the bit lines with the source electrode areas of the semiconductor layers contacted with the bit lines so that the source electrode areas of the semiconductor layers share one bit line to obtain a storage area;

the circuitry of the memory region and the circuitry of the peripheral circuit region are electrically connected.

The embodiment of the application also provides electronic equipment comprising the semiconductor device.

The semiconductor device of the embodiment of the application increases the storage density of the semiconductor device by adopting the lateral transistor semiconductor layer (i.e., the transistor semiconductor layer extending in the second direction) and the lateral capacitor (i.e., the capacitor is disposed between the semiconductor layers of the transistor instead of being disposed on the left and right sides of the transistor), so that the transistor and the capacitor can form a three-dimensional stacked structure, and the memory cells formed by the transistor and the capacitor can be stacked together; in addition, the peripheral circuit is arranged below the memory cell columns by adopting the CuA (CMOS under Array) structure, and the sources of the transistors of the memory cells of the two adjacent memory cell columns share one bit line, so that the size of the semiconductor device can be reduced, the storage density of the semiconductor device can be further increased, the manufacturing cost of a unit Gb is reduced, and a new technology development direction is provided for the bottleneck of the semiconductor device (such as a DRAM). In addition, the arrangement of the gating transistors may be directed to select a particular bit line and word line to read from or write to a particular transistor.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.

Fig. 1 is a schematic perspective view of a semiconductor device according to an exemplary embodiment of the present application;

fig. 2 is a schematic view showing a perspective structure of a semiconductor device according to an exemplary embodiment of the present application at another angle;

fig. 3A is a schematic view of a front view cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application;

fig. 3B is a schematic top view of a semiconductor device according to an exemplary embodiment of the present application;

fig. 4A is a schematic view of a front sectional structure of a memory region of a semiconductor device according to an exemplary embodiment of the present application;

fig. 4B is a schematic top view of a memory region of the semiconductor device according to an exemplary embodiment of the present application;

fig. 5A is a schematic view showing a front sectional structure of a memory region of a semiconductor device according to another exemplary embodiment of the present application;

Fig. 5B is a schematic top view of a memory region of a semiconductor device according to another exemplary embodiment of the present application;

fig. 6A is a schematic view showing a front view in cross-sectional structure of a peripheral circuit region of a semiconductor device according to an exemplary embodiment of the present application;

fig. 6B is a schematic top view of a peripheral circuit region of a semiconductor device according to an exemplary embodiment of the present application;

fig. 7 is a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present application;

fig. 8-1A is a schematic view showing a cross-sectional front view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

fig. 8-1B are schematic top view structures of intermediate products obtained in an intermediate step of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present application;

fig. 8-2A is a schematic view showing a cross-sectional front view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

fig. 8-2B are schematic top view structures of intermediate products obtained in intermediate steps of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present application;

fig. 8 to 3A are schematic front view cross-sectional structures of intermediate products obtained in intermediate steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

Fig. 8-3B are schematic top view structures of intermediate products obtained in intermediate steps of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present application;

fig. 8 to 4A are schematic front view cross-sectional structures of intermediate products obtained in intermediate steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

fig. 8-4B are schematic top view structures of intermediate products obtained in intermediate steps of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present application;

fig. 8 to 5A are schematic front view cross-sectional structures of intermediate products obtained in intermediate steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

fig. 8 to 5B are schematic top view structures of intermediate products obtained in intermediate steps of the method for manufacturing a semiconductor device according to the exemplary embodiment of the present application.

The meaning of the reference symbols in the drawings is:

a-a peripheral circuit region; b-storage area; 100-a substrate; 200-columns of memory cells; 300-bit line; 300' -slot; 400-word lines; 500-peripheral circuits; 501-a first gating transistor; 5011—a first source; 5012—a first drain; 5013—a first channel; 5014—a first gate; 502-a second gating transistor; 5021-a second source; 5022-a second drain; 5023-second channel; 5024-second gate; 503-a first type well; 504-a second type well; 600-metal contact layer; 601-first metal contact pillars; 602-second metal contact pillars; 700-metal interconnect layer; 701-a first metal line; 702-a second metal line; 800-a sacrificial layer; 1-a memory cell; 1' -memory cell region; a 10-transistor; 11-a semiconductor layer; 11' -channel layer; 111-source regions; 112-a channel region; 113-drain region; 12-grid; 20-a capacitor; 21-a first electrode plate; 22-a second electrode plate; 23-a dielectric layer; 2-an interlayer isolation layer; 3-memory cell isolation columns; 3' -memory cell isolation trenches; 4-an inner support layer; 4' -internal support slots; 5-isolating material.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.

In the description of the present application, ordinal numbers such as "first", "second", etc., are provided to avoid intermixing of constituent elements, and are not intended to be limiting in terms of number.

The embodiment of the application provides a semiconductor device. Fig. 1 is a schematic perspective view of a semiconductor device according to an exemplary embodiment of the present application; fig. 2 is a schematic view showing a perspective structure of a semiconductor device according to an exemplary embodiment of the present application at another angle; fig. 3A is a schematic view of a front view cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application; fig. 3B is a schematic top view of a semiconductor device according to an exemplary embodiment of the present application. As shown in fig. 1 to 3B, the semiconductor device may include: a substrate 100, a peripheral circuit region a and a memory region B, which are sequentially stacked on one side of the substrate 100, and the circuit of the peripheral circuit region a and the circuit of the memory region B are electrically connected.

Fig. 4A is a schematic view of a front sectional structure of a memory region of a semiconductor device according to an exemplary embodiment of the present application; fig. 4B is a schematic top view of a memory region of the semiconductor device according to an exemplary embodiment of the present application. As shown in fig. 3A to 4B, the memory area B includes: a plurality of memory cell columns 200 extending in a first direction, a plurality of Bit lines 300 (BL) extending in the first direction, and a plurality of Word lines 400 (WL) extending in a third direction;

each memory cell column 200 is formed by stacking a plurality of memory cells 1 arranged on one side of the substrate 100 in a first direction, and one or more memory cells belonging to the same layer are used as a group, the memory cells of the group are stacked in a direction perpendicular to the substrate, and the memory cell groups of different stacks constitute a column extending in the direction perpendicular to the substrate.

The plurality of groups form an array, that is, the memory cell groups of each layer form an array, or the plurality of columns formed by the plurality of stacked memory cell groups form an array. It can also be expressed as: the plurality of memory cell columns 200 are arranged in the second direction and the third direction to form an array; each memory cell 1 includes a transistor 10 and a capacitor 20, the transistor 10 includes a semiconductor layer 11 and a gate electrode 12, the semiconductor layer 11 extends in the second direction and includes a source region 111, a channel region 112 and a drain region 113 in this order, the gate electrode 12 surrounds the channel region 112, and a gate insulating layer (not shown) is provided between the gate electrode 12 and the channel region 112; the capacitor 20 includes a first electrode plate 21, a second electrode plate 22, and a dielectric layer 23 disposed between the first electrode plate 21 and the second electrode plate 22, wherein the first electrode plate 21, the dielectric layer 23, and the second electrode plate 22 sequentially surround the drain region 113 at one end far from the channel region 112;

The source regions 111 of the transistors 10 of the plurality of memory cells 1 of the two memory cell columns 200 adjacent in the second direction are each connected to one common bit line 300;

the memory area B may be provided with one or more memory cell columns 200 in the third direction; when the memory area B is provided with one memory cell column 200 in the third direction, each word line 400 is formed by the gate 12 of the transistor 10 of one memory cell 1 of one memory cell column 200 arranged in the third direction; alternatively, when the memory area B is provided with a plurality of memory cell columns 200 in the third direction, each word line 400 is formed by connecting together the gates 12 of the transistors 10 of the plurality of memory cells 1 arranged in the third direction.

As shown in fig. 1 to 3B, the peripheral circuit region a includes a peripheral circuit 500 disposed on the substrate 100, the peripheral circuit including a first gate transistor group including at least one first gate transistor 501, each of the first gate transistors 501 being electrically connected to one of the bit lines 300, and a second gate transistor group including at least one second gate transistor 502, each of the second gate transistors being electrically connected to one of the word lines 400.

In the description of the present application, the "first direction" is defined as a direction perpendicular to the plane in which the substrate is located, i.e., a direction in which the height of the semiconductor device is located; "second direction" is defined as the direction perpendicular to the "first direction" and in which the width of the substrate is located; the "third direction" is defined as the direction perpendicular to the "first direction" and in which the length of the substrate is located. The "first direction", "second direction" and "third direction" may be as shown in fig. 3A.

In the embodiment of the present application, one memory cell column may be formed of 2 to 100 memory cells stacked in the first direction, for example, may be formed of 2, 3 (as shown in fig. 3A and 4A), 4, 5, 10, 13, 15, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100 memory cells.

In the embodiment of the present application, the memory B may be provided with 2 to 1000 memory cell columns in the second direction, for example, 2, 4 (as shown in fig. 3A and 4A), 6, 8, 10, 12, 14, 16, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000 memory cell columns may be provided; the memory B may be provided with 1 to 100 memory cell columns in the third direction, for example, 1, 2, 3 (as shown in fig. 3A and 4A), 4, 5, 12, 14, 16, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100 memory cell columns may be provided.

In the embodiments of the present application, the substrate may be a semiconductor substrate, for example, may be a monocrystalline Silicon substrate, and may also be a semiconductor-On-insulator (Semiconductor On Insulator, SOI) substrate, for example, a Silicon-On-sapphire (Silicon On Sapphire, SOS) substrate, a Silicon-On-Glass (SOG) substrate, an epitaxial layer of Silicon On a base semiconductor basis, or other semiconductor or optoelectronic material, for example, silicon-germanium (Si) _1-x Ge _x Where x may be, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). The substrate may or may not be dopedDoped.

In the embodiment of the application, the material of the bit line may be selected from any one or more of other metal materials with similar properties, such as tungsten, molybdenum, cobalt, and the like.

In the embodiment of the present application, lengths of the plurality of word lines arranged along the first direction may be different, so that the plurality of word lines arranged along the first direction at different layers may be formed in a stepped shape.

In the embodiment of the present application, the material of the semiconductor layer may be a metal oxide semiconductor material, for example, the material of the semiconductor layer may be selected from indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), zinc stannate (ZTO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide (ZnO _x ) Indium tungsten oxide (InWO), indium zinc tin oxide (Indium Zinc Tin Oxide, IZTO), indium oxide (InO) _x For example, in ₂ O ₃ ) Tin oxide (SnO) _x For example, snO ₂ ) Titanium oxide (TiO) _x ) Zinc oxynitride (Zn) _x O _y N _z ) Magnesium zinc oxide (Mg) _x Zn _y O _z ) Zirconium indium zinc oxide (Zr) _x In _y Zn _z O _a ) Hafnium indium zinc oxide (Hf) _x In _y Zn _z O _a ) Aluminum tin indium zinc oxide (Al _x Sn _y In _z Zn _a O _d ) Indium zinc silicon oxide (Si _x In _y Zn _z O _a ) Aluminum zinc tin oxide (Al _x Zn _y Sn _z O _a ) Gallium zinc tin oxide (Ga _x Zn _y Sn _z O _a ) Zirconium zinc tin oxide (Zr) _x Zn _y Sn _z O _a ) And indium gallium silicon oxide (InGaSiO) _x ) Any one or more of the following. For another example, the material of the semiconductor layer may be IGZO. A plurality of memory cells stacked in the first direction are more easily formed using IGZO as a material of the semiconductor layer than single crystal silicon.

In this embodiment of the present application, the material of the word line may be a material compatible with the semiconductor layer, for example, the material of the semiconductor layer may be a metal oxide semiconductor material, the material of the word line may be a metal oxide conductor material, and both the metal oxide semiconductor material and the metal oxide conductor material belong to a metal oxide material, which may be better compatible with each other. For another example, the material of the word line may be Indium Tin Oxide (ITO) or the like. The ITO material has a small resistance.

In this embodiment of the present application, the height of the semiconductor layer along the first direction may be set according to actual electrical requirements, for example, may be 10nm to 50nm.

In this embodiment of the present application, the first electrode plate may be an inner electrode plate, and the second electrode plate may be an outer electrode plate. As shown in fig. 3A and 4A, the drain region 113 may be connected to the first electrode plate 21 (i.e., the inner electrode plate). The second electrode plates 22 of the plurality of capacitors 20 arranged in the third direction may be connected together, but the first electrode plates 21 thereof are separated.

In the embodiment of the present application, as shown in fig. 3A and 4A, one transistor 10 may correspond to one capacitor 20, that is, the memory cell 1 may have a 1T1C structure.

In embodiments of the present application, two capacitors adjacent in the first direction may share one external electrode plate.

In the embodiment of the present application, the materials of the first electrode plate and the second electrode plate may be each independently selected from any one or more of titanium nitride (for example, tiN), aluminum-titanium based alloy (for example, tiAl), tantalum nitride (for example, taN), and other metal materials having similar properties. The thickness of the first electrode plate may be 5nm to 15nm, and the thickness of the second electrode plate may be 5nm to 15nm.

In an embodiment of the present application, the material of the dielectric layer may be a high dielectric constant (K) material, for example, may be selected from hafnium oxide (e.g., hfO ₂ ) Aluminum oxide (e.g. Al ₂ O ₃ ) Zirconium oxide (e.g., zrO) and strontium titanate (e.g., srTiO ₃ STO). The thickness of the dielectric layer may be 5nm to 15nm.

In the embodiment of the present application, as shown in fig. 3A and 4A, the memory cell column 200 may further include an interlayer isolation layer 2, where the interlayer isolation layer 2 is disposed between the gates 12 of the transistors 10 of two adjacent memory cells 1 in the memory cell column 200, and isolates the gates 12 of the transistors 10 of two adjacent memory cells 1.

In the embodiment of the present application, the material of the interlayer isolation layer may be silicon oxide, for example, may be SiO ₂ 。

In an embodiment of the present application, as shown in fig. 3A and 4A, the semiconductor device may further include one or more memory cell isolation pillars 3 extending in the first direction. For example, one memory cell isolation column 3 may be provided every two memory cell columns 200 in the second direction.

In an embodiment of the present application, the material of the memory cell isolation pillar may be silicon oxide, for example, may be any one or more selected from Spin-On Deposition (SOD) silicon oxide films, high density plasma (High Density Plasma, HDP) silicon oxide films, and high aspect ratio process (High Aspect Ratio Process, HARP) silicon oxide films.

In embodiments of the present application, the material of the gate insulating layer may be selected from silicon oxide (e.g., siO ₂ ) Hafnium oxide (e.g., hfO) ₂ ) Zirconium oxide (e.g., zrO) and aluminum oxide (e.g., al) ₂ O ₃ ) Any one or more of the following.

In this embodiment of the present application, the thickness of the gate insulating layer may be set according to practical electrical requirements, for example, may be 2nm-5nm.

In the embodiment of the application, the material of the gate electrode may be selected from any one or more of Indium Tin Oxide (ITO) or other low-temperature semiconductor materials.

In the embodiment of the present application, as shown in fig. 3A and 4A, the semiconductor device may further include an internal support layer 4, where the internal support layer 4 is disposed between two semiconductor layers 11 adjacent in the first direction and configured to provide support to the semiconductor layers 11.

In the embodiment of the present application, the internal support layer 4 may be located at both sides of the bit line 300 as shown in fig. 3A and 4A, or may be located at both sides of the bit line 300 and both sides of the memory cell isolation pillar 3 as shown in fig. 3A and 4A. When the internal support layers 4 are provided on both sides of the bit line 300 and both sides of the memory cell isolation pillar 3, a more firm support can be provided to the semiconductor layer 11.

In the embodiment of the present application, the material of the inner support layer may be a thin film material with a supporting effect, for example, may be silicon nitride (for example, siN).

Fig. 5A is a schematic view showing a front sectional structure of a memory region of a semiconductor device according to another exemplary embodiment of the present application; fig. 5B is a schematic top view of a memory region of a semiconductor device according to another exemplary embodiment of the present application. As shown in fig. 5A and 5B, in an exemplary embodiment of the present application, an empty space among the semiconductor layer, the bit line, and the word line may be filled with an isolation material 5.

In the embodiment of the application, the isolation material may be selected from any one or more of a SOD silicon oxide film, a HDP silicon oxide film and a HARP silicon oxide film.

In an embodiment of the present application, the first gate transistor and the second gate transistor may be CMOS transistors.

Fig. 6A is a schematic view showing a front view in cross-sectional structure of a peripheral circuit region of a semiconductor device according to an exemplary embodiment of the present application; fig. 6B is a schematic top view of a peripheral circuit region of the semiconductor device according to an exemplary embodiment of the present application. In the embodiment of the present application, as shown in fig. 3A, 3B, 6A, and 6B, the peripheral circuit region a may include a peripheral circuit 500, a metal contact layer 600, and a metal interconnection layer 700; the peripheral circuit 500 may be disposed on one side of the substrate 100, and include a first gate transistor group including at least one first gate transistor 501, each first gate transistor 501 being electrically connected to one bit line 300, and a second gate transistor group including at least one second gate transistor 502, each second gate transistor 502 being electrically connected to one word line 400; the metal contact layer 600 is disposed on a side of the peripheral circuit 500 away from the substrate 100, the metal interconnection layer 700 is disposed on a side of the metal contact layer 600 away from the substrate 100, the metal contact layer 600 may include a metal contact stud and an insulating medium, the metal contact stud may include a first metal contact stud 601 and a second metal contact stud 602, the metal interconnection layer 700 may include a metal line and an insulating medium, and the metal line may include a first metal line 701 and a second metal line 702; one end of the first metal line 701 is electrically connected to the bit line 300 of the memory region B, the other end of the first metal line 701 is electrically connected to the first gate transistor 501 through the first metal contact post 601, one end of the second metal line 702 is electrically connected to the word line 400 of the memory region B, and the other end of the second metal line 702 is electrically connected to the second gate transistor 502 through the second metal contact post 602.

In the embodiment of the present application, as shown in fig. 6A and 6B, the first gate transistor 501 and the second gate transistor 502 may be disposed in parallel on the same plane.

In the embodiment of the application, the material of the metal wire can be selected from any one or more of copper and aluminum, and for example, the material can be copper; the material of the metal contact stud may be selected from any one or more of tungsten and molybdenum, for example, may be tungsten.

In this embodiment of the present application, the first gating transistors are electrically connected to the bit lines in a one-to-one correspondence, and the second gating transistors are electrically connected to the word lines in a one-to-one correspondence.

In this embodiment, as shown in fig. 6A and 6B, the first gate transistor 501 and the second gate transistor 502 are disposed side by side on one side of the substrate 100, and a first type well 503 may be further disposed between the first gate transistor 501 and the substrate 100, and a second type well 504 may be further disposed between the second gate transistor 502 and the substrate 100; the first gate transistor 501 may include a first source electrode 5011, a first drain electrode 5012, a first channel 5013 disposed between the first source electrode 5011 and the first drain electrode 5012, and a first gate electrode 5014 disposed on one side of the first channel 5013, wherein the first source electrode 5011 and the first drain electrode 5012 are the same material and may be both N-type semiconductor materials or P-type semiconductor materials, the first channel 5013 and the first well 503 are the same material and may be both P-type semiconductor materials or N-type semiconductor materials, but the first source electrode 5011 and the first drain electrode 5012 are different from the first channel 5013 and the first well 503; a first gate insulating layer (or gate oxide layer, not shown) may be further disposed between the first channel 5013 and the first gate 5014; the second gate transistor 502 includes a second source electrode 5021, a second drain electrode 5022, a second channel 5023 disposed between the second source electrode 5021 and the second drain electrode 5022, and a second gate electrode 5024 disposed at one side of the second channel 5023, wherein the second source electrode 5021 and the second drain electrode 5022 are made of the same material and may be made of P-type semiconductor material or N-type semiconductor material, the second channel 5023 and the second well 504 are made of the same material and may be made of N-type semiconductor material or P-type semiconductor material, but the second source electrode 5021 and the second drain electrode 5022 are made of different materials from the second channel 5023 and the second well 504; a second gate insulating layer (or gate oxide layer, not shown) may be further disposed between the second channel 5023 and the second gate 5024.

In an embodiment of the present application, the peripheral circuit region may further include a third transistor, and the third transistor may be disposed on the same plane as the first and second gate transistors.

In an embodiment of the present application, the semiconductor device may be a Dynamic Random Access Memory (DRAM).

The embodiment of the application also provides a manufacturing method of the semiconductor device. The semiconductor device provided by the embodiments of the present application as described above can be obtained by the manufacturing method.

Fig. 7 is a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present application. As shown in fig. 7, the manufacturing method may include:

s10: a peripheral circuit is arranged on one side of the substrate to form a peripheral circuit area;

s20: a plurality of composite layers consisting of a sacrificial layer and a channel layer are stacked along a first direction on one side of the peripheral circuit, which is far away from the substrate, in an staggered sequence of the sacrificial layer and the channel layer;

s30: defining a storage unit area in a plurality of composite layers, etching a bit line groove along a first direction, and filling isolation materials in the bit line groove;

s40: removing the sacrificial layer, and forming a plurality of semiconductor layers which are arrayed along the first direction and the third direction and extend along the second direction by the residual channel layers, wherein the semiconductor layers sequentially comprise a source region, a channel region and a drain region;

S50: a grid insulating layer and a grid electrode which encircle the channel region are sequentially arranged around the channel region of the semiconductor layer, and the semiconductor layer and the grid electrode form a transistor; and one of the semiconductor layers arranged in the third direction, the gate electrode on the one semiconductor layer being made to be a word line; alternatively, the semiconductor layers arranged in the third direction are plural, and the gates on the plural semiconductor layers arranged in the third direction are connected together in the third direction to form the word line;

s60: a first electrode plate, a dielectric layer and a second electrode plate which surround one end of the drain region are sequentially arranged around one end of the drain region of the semiconductor layer, which is far away from the channel region, and the first electrode plate, the dielectric layer and the second electrode plate form a capacitor;

s70: removing isolation materials in the bit line grooves, filling bit line materials in the bit line grooves to form bit lines extending along a first direction, and connecting the bit lines with the source electrode areas of the semiconductor layers contacted with the bit lines so that the source electrode areas of the semiconductor layers share one bit line to obtain a storage area;

s80: the circuitry of the memory region and the circuitry of the peripheral circuit region are electrically connected.

In the embodiment of the present application, step S30 may include:

s31: defining a storage unit area in a plurality of composite layers, and etching a storage unit isolation groove and a bit line groove at intervals along a first direction;

s32: performing side etching on the part, corresponding to the sacrificial layer, of the bit line groove along the second direction to obtain an inner supporting groove, and filling an inner supporting layer in the inner supporting groove;

optionally, S33: performing side etching on the part, corresponding to the sacrificial layer, of the storage unit isolation groove along the second direction to obtain an inner support groove, and filling an inner support layer in the inner support groove;

s34: and filling storage unit isolation columns in the storage unit isolation grooves and filling isolation materials in the bit line grooves.

For example, in the exemplary embodiments of the present application,

i) Step S30 may include:

S34: filling storage unit isolation columns in the storage unit isolation grooves and filling isolation materials in the bit line grooves;

alternatively, ii) step S30 may include:

s33: performing side etching on the part, corresponding to the sacrificial layer, of the storage unit isolation groove along the second direction to obtain an inner support groove, and filling an inner support layer in the inner support groove;

In the embodiment of the present application, step S50 may include:

s51: a grid insulating layer and a grid electrode which encircle the channel region are sequentially arranged around the channel region of the semiconductor layer, and the semiconductor layer and the grid electrode form a transistor; and one of the semiconductor layers arranged in the third direction, the gate electrode on the one semiconductor layer being made to be a word line; alternatively, the semiconductor layers arranged in the third direction are plural, and the gates on the plural semiconductor layers arranged in the third direction are connected together in the third direction to form the word line;

Optionally, S52: setting a plurality of word lines arranged along a first direction to be different in length, so that the plurality of word lines arranged along the first direction and located at different layers are in a ladder shape;

optionally, S53: an interlayer isolation layer is provided between two semiconductor layers adjacent in the first direction, thereby isolating the gates on the two semiconductor layers adjacent in the first direction.

For example, in an exemplary embodiment of the present application, i) step S50 may include:

alternatively, ii) step S50 may include:

S52: setting a plurality of word lines arranged along a first direction to be different in length, so that the plurality of word lines arranged along the first direction and located at different layers are in a ladder shape;

alternatively, iii) step S50 may include:

s53: an interlayer isolation layer is provided between two semiconductor layers adjacent in the first direction, thereby isolating the gates on the two semiconductor layers adjacent in the first direction;

alternatively, iii) step S50 may include:

s53: an interlayer isolation layer is provided between two semiconductor layers adjacent in the first direction, thereby isolating the gates on the two semiconductor layers adjacent in the first direction.

In the embodiment of the present application, step S70 may include:

s71: removing isolation materials in the bit line grooves, filling bit line materials in the bit line grooves to form bit lines extending along a first direction, and connecting the bit lines with the source electrode regions of the semiconductor layers contacted with the bit lines so that the source electrode regions of the semiconductor layers share one bit line;

s72: and filling isolation materials in the blank spaces among the semiconductor layer, the bit lines and the word lines to obtain storage areas.

In the embodiment of the present application, step S10 may include:

s11: a peripheral circuit, a metal contact layer with a metal contact post and a metal interconnection layer with a metal wire are sequentially arranged on one side of the substrate, the peripheral circuit comprises a first gating transistor group and a second gating transistor group, the first gating transistor group comprises at least one first gating transistor, the second gating transistor group comprises at least one second gating transistor, the metal contact post comprises a first metal contact post and a second metal contact post, and the metal wire comprises a first metal wire and a second metal wire;

S12: and electrically connecting one end of the first metal wire with the first gating transistor through the first metal contact post, and electrically connecting one end of the second metal wire with the second gating transistor through the second metal contact post to obtain the peripheral circuit region.

In the embodiment of the present application, step S80 may include: electrically connecting one end of the first metal wire far away from the first metal contact post with the bit line, and electrically connecting one end of the second metal wire far away from the second metal contact post with the word line;

step S30 further includes aligning the bit line slot with the first metal line; step S50 further includes aligning the gate with the second metal line.

Fig. 8-1A to 8-5B are schematic front view cross-sectional structures and schematic top view schematic views of intermediate products obtained in intermediate steps of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present application. As shown in fig. 8-1A to 8-5B and fig. 3A to 5B, in an exemplary embodiment, the method of manufacturing a semiconductor device may include:

s11: a peripheral circuit 500, a metal contact layer 600 with a metal contact post and a metal interconnection layer 700 with a metal wire are sequentially arranged on one side of a substrate 100, wherein the peripheral circuit comprises a first gating transistor group and a second gating transistor group, the first gating transistor group comprises at least one first gating transistor 501, the second gating transistor group comprises at least one second gating transistor 502, the metal contact post comprises a first metal contact post 601 and a second metal contact post 602, and the metal wire comprises a first metal wire 701 and a second metal wire 702;

S12: one end of the first metal line 701 is electrically connected to the first gate transistor 501 through the first metal contact post 601, and one end of the second metal line 702 is electrically connected to the second gate transistor 502 through the second metal contact post 602, so as to obtain a peripheral circuit region a as shown in fig. 6A and 6B;

s20: a plurality of composite layers consisting of the sacrificial layer 800 and the channel layer 11 'are stacked along a first direction on one side of the metal interconnection layer 700 of the peripheral circuit area A far away from the substrate 100 in the staggered sequence of the sacrificial layer 800 and the channel layer 11', so as to obtain an intermediate product shown in figures 8-1A and 8-1B;

s31: defining a memory cell region 1 'in a plurality of composite layers consisting of a sacrificial layer 800 and a channel layer 11', and etching a memory cell isolation trench 3 'and a bit line trench 300' at intervals along a first direction;

s32: performing side etching on the portion of the bit line groove 300' corresponding to the sacrificial layer 800 along the second direction to obtain an inner supporting groove 4', and filling the inner supporting groove 4' with the inner supporting layer 4;

s33: performing side etching on the portion, corresponding to the sacrificial layer 800, of the memory cell isolation groove 3' along the second direction to obtain an inner support groove 4', and filling the inner support groove 4' with the inner support layer 4;

S34: filling a storage unit isolation column 3 in the storage unit isolation groove 3 'and filling an isolation material 5 in the bit line groove 300' to obtain an intermediate product shown in fig. 8-2A and 8-2B;

s40: removing the sacrificial layer 800, and forming a plurality of semiconductor layers 11 arrayed in the first direction and the third direction and extending in the second direction by the remaining channel layers 11', wherein the semiconductor layers 11 include a source region 111 and a drain region 113, and a channel region 112 between the source region 111 and the drain region 113, resulting in an intermediate product as shown in fig. 8-3A and 8-3B;

s51: a gate insulating layer (not shown) and a gate electrode 12 surrounding the channel region 112 are sequentially arranged around the channel region 112 of the semiconductor layer 11, so that the semiconductor layer 11 and the gate electrode 12 form the transistor 10; and, there is one of the semiconductor layers 11 arranged in the third direction, so that the gate electrode 12 on the one semiconductor layer 11 serves as the word line 400; alternatively, there are a plurality of semiconductor layers 11 arranged in the third direction, so that the gate electrodes 12 on the plurality of semiconductor layers 11 arranged in the third direction are connected together in the third direction to form the word line 400;

s52: the plurality of word lines 400 arranged in the first direction are provided in different lengths such that the plurality of word lines 400 arranged in the first direction at different layers exhibit a stepped shape;

S53: an interlayer isolation layer 2 is provided between two semiconductor layers 11 adjacent in the first direction, so that the gate electrodes 12 on the two semiconductor layers 11 adjacent in the first direction are isolated, resulting in an intermediate product as shown in fig. 8-4A and 8-4B;

s60: a first electrode plate 21, a dielectric layer 23 and a second electrode plate 22 which surround one end of the drain region 113 are sequentially arranged around one end of the drain region 113 of the semiconductor layer 11 far away from the channel region 112, and the first electrode plate 21, the dielectric layer 23 and the second electrode plate 22 form a capacitor 20, so that intermediate products shown in fig. 8-5A and fig. 8-5B are obtained;

s71: removing isolation material in the bit line trench 300', filling bit line material in the bit line trench 300', forming a bit line 300 extending in a first direction, connecting the bit line 300 with the source regions 111 of the plurality of semiconductor layers 11 in contact with the bit line 300 such that the source regions 111 of the plurality of semiconductor layers 11 share the one bit line 300, resulting in a storage region as shown in fig. 4A and 4B;

s72: filling an isolation material in the empty space between the semiconductor layer 11, the bit line 300 and the word line 400, resulting in a storage region as shown in fig. 5A and 5B;

s80: one end of the first metal line 701, which is far from the first metal contact pillar 601, is electrically connected to the bit line 300, and one end of the second metal line 702, which is far from the second metal contact pillar 602, is electrically connected to the word line 400, resulting in the semiconductor device shown in fig. 3A and 3B.

In the embodiment of the present application, the first gate transistor and the second gate transistor may be formed through a conventional CMOS process in step S10, and then a metal contact layer and a metal interconnection layer are fabricated on the peripheral circuit. The metal contact layer can be formed by a metal contact column and an insulating medium, a whole layer of the insulating medium can be arranged first, then a through hole is formed in the insulating medium, and metal is filled in the through hole to form the metal contact column. The metal interconnection layer can be formed by metal wires and insulating media, a whole layer of insulating media can be arranged first, then through holes are formed in the insulating media, and metal is filled in the through holes to form the metal wires. The entire layer of insulating medium may be formed using an atomic layer deposition (Atomic layer deposition, ALD) process.

In an embodiment of the present application, step S20 may include disposing the sacrificial layer and the channel layer using an ALD process.

In the embodiment of the present application, the material of the sacrificial layer may be selected from any one or more of other conductive materials with similar properties, such as Aluminum-doped Zinc Oxide (AZO). The thickness of the sacrificial layer may be 30nm to 50nm, for example, 30nm, 35nm, 40nm, 45nm, 50nm.

In this embodiment of the present application, in step S31, patterning and etching may be performed by using the same layer of pattern mask (Photo mask) through light exposure, so as to form trenches arranged along the third direction and extending along the second direction, thereby isolating the multiple sacrificial layers/channel layers in the third direction, and obtaining the memory cell region.

In this embodiment, in step S32 or S33, a side etching may be performed on a portion of the bit line trench or the memory cell isolation trench corresponding to the sacrificial layer by wet etching.

In the embodiment of the present application, in step S32 or S33, the internal support layer may be filled in the internal support layer groove by an ALD process, for example, siN may be filled in the internal support layer groove by an ALD process, to form an internal support layer.

In the embodiment of the present application, in step S34, the memory cell isolation pillars may be filled in the memory cell isolation trenches and the isolation material may be filled in the bit line trenches by a SOD, HDP or HARP process, for example, a silicon oxide film may be formed in the memory cell isolation trenches and the bit line trenches by a SOD, HDP or HARP process.

In the embodiment of the present application, in step S40, the sacrificial layer may be etched away by an etching method, which may be dry etching or wet etching, and selecting an ultra-high sacrificial layer/channel layer etching ratio to leave the channel layer.

In the embodiment of the present application, step-shaped word lines (staircase WL) may be obtained by trim etching (trim etch) in step S52.

In the embodiment of the present application, the interlayer isolation layer may be provided by ALD or a chemical vapor deposition (Chemical Vapor Deposition, CVD) process in step S53, for example, siO may be filled by ALD or CVD process ₂ An interlayer isolation layer is formed.

In the embodiment of the present application, the isolation material may be filled in the empty space through the SOD, HDP or HARP process in step S72, for example, any one or more of the SOD silicon oxide film, the HDP silicon oxide film and the HARP silicon oxide film may be formed in the empty space through the SOD, HDP or HARP process.

The embodiment of the application also provides another manufacturing method of the semiconductor device, and the semiconductor device provided by the embodiment of the application can be obtained through the manufacturing method. The manufacturing method comprises the following steps:

s10': a peripheral circuit is arranged on one side of the substrate to form a peripheral circuit area;

s20': a plurality of composite layers consisting of a sacrificial layer and a channel layer are stacked along a first direction on one side of the peripheral circuit, which is far away from the substrate, in an staggered sequence of the sacrificial layer and the channel layer;

S30': defining memory cell regions in the plurality of composite layers, etching memory cell isolation grooves (without etching bit line grooves) along a first direction, and filling memory cell isolation columns in the memory cell isolation grooves;

s40': removing the sacrificial layer, and forming a plurality of semiconductor layers which are arrayed along the first direction and the third direction and extend along the second direction by the residual channel layers, wherein the semiconductor layers sequentially comprise a source region, a channel region and a drain region;

s50': a grid insulating layer and a grid electrode which encircle the channel region are sequentially arranged around the channel region of the semiconductor layer, and the semiconductor layer and the grid electrode form a transistor; and one of the semiconductor layers arranged in the third direction, the gate electrode on the one semiconductor layer being made to be a word line; alternatively, the semiconductor layers arranged in the third direction are plural, and the gates on the plural semiconductor layers arranged in the third direction are connected together in the third direction to form the word line;

s60': a first electrode plate, a dielectric layer and a second electrode plate which surround one end of the drain region are sequentially arranged around one end of the drain region of the semiconductor layer, which is far away from the channel region, and the first electrode plate, the dielectric layer and the second electrode plate form a capacitor;

S70': bit line grooves penetrating through the semiconductor layers are formed in bit line areas of the semiconductor layers arranged along the first direction, bit line materials are filled in the bit line grooves and between the bit line grooves of the semiconductor layers arranged along the first direction to form bit lines extending along the first direction, and the bit lines are connected with source electrode areas of the semiconductor layers contacted with the bit lines, so that the source electrode areas of the semiconductor layers share one bit line, and a storage area is obtained;

s80': the circuitry of the memory region and the circuitry of the peripheral circuit region are electrically connected.

In the embodiment of the present application, step S10' may include:

s11': a peripheral circuit, a metal contact layer with a metal contact post and a metal interconnection layer with a metal wire are sequentially arranged on one side of the substrate, the peripheral circuit comprises a first gating transistor group and a second gating transistor group, the first gating transistor group comprises at least one first gating transistor, the second gating transistor group comprises at least one second gating transistor, the metal contact post comprises a first metal contact post and a second metal contact post, and the metal wire comprises a first metal wire and a second metal wire;

S12': and electrically connecting one end of the first metal wire with the first gating transistor through the first metal contact post, and electrically connecting one end of the second metal wire with the second gating transistor through the second metal contact post to obtain the peripheral circuit region.

In the embodiment of the present application, step S30' includes:

s31': defining memory cell areas in the composite layers, and etching memory cell isolation grooves at intervals along a first direction;

s32': performing side etching on the part, corresponding to the sacrificial layer, of the storage unit isolation groove along the second direction to obtain an inner support groove, and filling an inner support layer in the inner support groove;

s33': and filling the storage unit isolation column in the storage unit isolation groove.

In an embodiment of the present application, step S50' may include:

s51': a grid insulating layer and a grid electrode which encircle the channel region are sequentially arranged around the channel region of the semiconductor layer, and the semiconductor layer and the grid electrode form a transistor; and one of the semiconductor layers arranged in the third direction, the gate electrode on the one semiconductor layer being made to be a word line; alternatively, the semiconductor layers arranged in the third direction are plural, and the gates on the plural semiconductor layers arranged in the third direction are connected together in the third direction to form the word line;

Optionally, S52': setting a plurality of word lines arranged along a first direction to be different in length, so that the plurality of word lines arranged along the first direction and located at different layers are in a ladder shape;

optionally, S53': an interlayer isolation layer is provided between two semiconductor layers adjacent in the first direction, thereby isolating the gates on the two semiconductor layers adjacent in the first direction.

In the embodiment of the present application, step S80' may include: electrically connecting one end of the first metal wire far away from the first metal contact post with the bit line, and electrically connecting one end of the second metal wire far away from the second metal contact post with the word line;

step S50' further includes aligning the gate with the second metal line; step S70' further includes aligning the bit line groove with the first metal line.

In an embodiment of the present application, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

In the description herein, it should be noted that the directions or positional relationships indicated by the terms "upper", "lower", "one side", "the other side", "one end", "the other end", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the structures referred to have a specific direction, are configured and operated in a specific direction, and thus are not to be construed as limiting the present application.

In the description of the embodiments of the present application, unless explicitly stated and limited otherwise, the terms "connected," "disposed," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; the terms "connected" and "disposed" may be directly connected or indirectly connected through intervening media, or may be in communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

Although the embodiments disclosed in the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the application is still subject to the scope of the claims that follow.

Claims

1. A method of manufacturing a semiconductor device, comprising:

2. A semiconductor device obtained by the manufacturing method according to claim 1, comprising: the substrate, peripheral circuit area and storage area that the cascade is set up in one side of the said substrate sequentially, the circuit of the said peripheral circuit area is connected with circuit of the said storage area electrically;

the storage area includes:

3. The semiconductor device according to claim 2, wherein lengths of the plurality of word lines arranged in the first direction are different, and the plurality of word lines arranged in the first direction at different layers are formed in a stepped shape.

4. The semiconductor device of claim 2, wherein the material of the semiconductor layer is a metal oxide semiconductor material and the material of the word line is a metal oxide conductor material.

5. The semiconductor device of claim 2, wherein the first electrode plate is an inner electrode plate and the second electrode plate is an outer electrode plate, and the drain region is connected to the inner electrode plate.

6. The semiconductor device of any of claims 2-5, wherein the memory cell column further comprises an interlayer isolation layer disposed between gates of transistors of adjacent two memory cells in the memory cell column, the gates of transistors of adjacent two memory cells being isolated.

7. The semiconductor device according to any one of claims 2 to 5, further comprising one or more memory cell isolation pillars extending in the first direction, one of the memory cell isolation pillars being provided every two memory cell columns in the second direction.

8. The semiconductor device of any of claims 2-5, further comprising an internal support layer disposed between two semiconductor layers adjacent in a first direction configured to provide support to the semiconductor layers.

9. The semiconductor device of any of claims 2-5, wherein the peripheral circuit region further comprises a metal contact layer and a metal interconnect layer; the peripheral circuit is arranged on one side of the substrate, the metal contact layer is arranged on one side of the peripheral circuit far away from the substrate, a metal contact column is arranged in the metal contact layer, the metal interconnection layer is arranged on one side of the metal contact layer far away from the substrate, and a metal wire is arranged in the metal interconnection layer; the memory cell columns are arranged on one side of the metal interconnection layer away from the substrate; the metal wire comprises a first metal wire and a second metal wire, the metal contact column comprises a first metal contact column and a second metal contact column, one end of the first metal wire is electrically connected with the bit line of the storage area, the other end of the first metal wire is electrically connected with the first gating transistor through the first metal contact column, one end of the second metal wire is electrically connected with the word line of the storage area, and the other end of the second metal wire is electrically connected with the second gating transistor through the second metal contact column.

10. An electronic device characterized by comprising the semiconductor device according to any one of claims 2-9.