CN116234304B

CN116234304B - Semiconductor device structure, manufacturing method thereof, DRAM (dynamic random Access memory) and electronic equipment

Info

Publication number: CN116234304B
Application number: CN202210542087.XA
Authority: CN
Inventors: 王祥升; 王桂磊; 赵超
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2022-05-17
Filing date: 2022-05-17
Publication date: 2024-03-15
Anticipated expiration: 2042-05-17
Also published as: CN116234304A

Abstract

A semiconductor device structure and a method of manufacturing the same, a DRAM and an electronic device, the semiconductor device structure including a substrate, a peripheral circuit region and a memory region disposed on a first side and a second side of the substrate, respectively, the peripheral circuit region and the memory region being electrically connected; the peripheral circuit region includes peripheral circuits, and the memory region includes: a metal interconnection layer; a plurality of memory cell columns, each memory cell column including a plurality of memory cells; the memory cell includes a transistor and a capacitor, and the structures of the transistor and the capacitor are the same as the definitions of the specification; a plurality of bit lines, source regions of transistors of the plurality of memory cells being connected to a common bit line; a plurality of word lines. According to the semiconductor device structure, a plurality of memory cells are stacked, and the peripheral circuit and the memory cells are arranged by adopting the CuA structure, so that the substrate area can be saved, and the memory density of the semiconductor memory can be effectively improved.

Description

Semiconductor device structure, manufacturing method thereof, DRAM (dynamic random Access memory) and electronic equipment

Technical Field

The present application relates to the field of semiconductor devices, and more particularly, to a semiconductor device structure and a method for manufacturing the same, a DRAM, and an electronic device.

Background

Computers and various electronic devices are widely used in various aspects of modern life, and there is an increasing demand for memory products. Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a common system memory that stores data in memory cells having capacitors and array transistors. The capacitor may be set to a charged state or a discharged state, taking both states to represent "0" and "1". The DRAM further includes peripheral transistors to form peripheral circuits. Peripheral circuits and array transistors handle data input/output (I/O) and memory cell operations (e.g., write or read).

As DRAM technology moves toward higher density and higher capacity, the miniaturization of semiconductor structures encounters bottlenecks, and the number of capacitors increases sharply, the size decreases sharply, resulting in longer process time and more complex process flows for the fabrication of capacitors.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the application.

The embodiment of the application provides a semiconductor device structure, a manufacturing method thereof, a DRAM and electronic equipment, wherein a plurality of memory cells are stacked in the semiconductor device structure, a peripheral circuit and the memory cells are arranged by adopting a CuA structure to form a three-dimensional stacked structure, more memory cells can be arranged on a limited substrate area, and the memory density of a semiconductor memory is improved.

The embodiment of the application provides a semiconductor device structure, which comprises the following components: a substrate having opposite first and second sides, a peripheral circuit region disposed on the first side of the substrate, and a storage region disposed on the second side of the substrate, the peripheral circuit region and the storage region being electrically connected; the peripheral circuit region includes a peripheral circuit; the storage area includes:

a metal interconnection layer disposed on the second side of the substrate, the metal interconnection layer having a metal line disposed therein;

a plurality of memory cell columns each including a plurality of memory cells stacked in a first direction on a side of the metal interconnect layer remote from the substrate, the plurality of memory cell columns being arranged in a second direction and a third direction on the metal interconnect layer to form an array; the memory cell includes a transistor and a capacitor, the transistor includes a semiconductor pillar extending in a second direction and including a source region, a channel region, and a drain region, the source region and the drain region being located at both ends of the semiconductor pillar, respectively, the channel region being located between the source region and the drain region, the gate surrounding the channel region; the capacitor surrounds the drain region at the end far away from the channel region;

A plurality of bit lines extending in the first direction, source regions of transistors of a plurality of memory cells of two adjacent memory cell columns in the second direction being connected to one common bit line;

a plurality of word lines extending in a third direction, wherein the metal interconnection layer is provided with one memory cell column in the third direction, and each of the word lines is formed of a gate of a transistor of one memory cell column arranged in the third direction; alternatively, the metal interconnection layer is provided with a plurality of memory cell columns in the third direction, in which case each of the word lines is formed by connecting together gates of transistors of a plurality of memory cells arranged in the third direction;

one end of the metal line is electrically connected with the bit line, the word line or the capacitor, and the other end of the metal line is electrically connected with a peripheral circuit of the peripheral circuit region.

In the embodiment of the present application, lengths of the plurality of word lines arranged along the first direction may be different, forming a step shape.

In the embodiment of the present application, the material of the word line may be ITO.

In an embodiment of the present application, the material of the semiconductor pillar may be selected from IGZO, ZTO, IZO, znO _x 、InWO、IZTO、InO _x 、In ₂ O ₃ 、SnO ₂ 、TiO _x 、Zn _x O _y N _z 、Mg _x Zn _y O _z 、Zr _x In _y Zn _z O _a 、Hf _x In _y Zn _z O _a 、Al _x Sn _y In _z Zn _a O _d 、Si _x In _y Zn _z O _a 、Al _x Zn _y Sn _z O _a 、Ga _x Zn _y Sn _z O _a 、Zr _x Zn _y Sn _z O _a And any one or more of InGaSiO.

In an embodiment of the present application, the capacitor may include an inner electrode plate, an outer electrode plate, and a dielectric layer disposed between the inner electrode plate and the outer electrode plate, and the drain region is connected to the inner electrode plate.

In embodiments of the present application, the metal wire may be electrically connected to the outer electrode plate.

In an embodiment of the present application, the memory cell column may further include an interlayer isolation strip disposed between gates of transistors of two adjacent memory cells in the memory cell column, and isolating the gates of the transistors of the two adjacent memory cells.

In an embodiment of the present application, the semiconductor device structure may further include one or more memory cell isolation pillars extending along the first direction. One of the memory cell isolation pillars may be provided every two memory cell columns in the second direction.

In the embodiment of the application, the material of the interlayer isolation belt and the memory cell isolation column may be silicon oxide.

In embodiments of the present application, the transistor may further include a gate dielectric layer disposed between the channel region and the gate.

In the embodiment of the application, the material of the gate dielectric layer can be selected from silicon dioxide, hfO ₂ ZrO and Al ₂ O ₃ Any one or more of the following.

In embodiments of the present application, the semiconductor device structure may further include an internal support layer, which may be disposed between two semiconductor pillars adjacent in the first direction, configured to provide support for the semiconductor pillars.

In the embodiment of the application, the internal supporting layer may be located at two sides of the bit line, or may be located at two sides of the bit line and two sides of the memory cell isolation pillar.

In an embodiment of the present application, the material of the inner support layer may be SiN.

In the embodiment of the application, the peripheral circuit can be a CMOS transistor, and the peripheral circuit region can further include a metal contact layer and a metal contact post; the peripheral circuit is arranged on the first side of the substrate, the metal contact layer is arranged on one side, far away from the substrate, of the peripheral circuit, one end of the metal contact column is arranged in the metal contact layer and is electrically connected with the peripheral circuit, and the other end of the metal contact column penetrates through the substrate and is electrically connected with the metal wire.

In an embodiment of the present application, the peripheral circuit region may further include a protection layer for encapsulating the peripheral circuit region, where the protection layer is disposed on a surface of the peripheral circuit region.

In an embodiment of the present application, the protective layer may include SiO ₂ A layer and a SiN layer.

The embodiment of the application also provides a manufacturing method of the semiconductor device structure, which comprises the following steps:

s10: disposing a peripheral circuit region including peripheral circuits on a first side of the substrate;

s20: providing a metal interconnection layer with a metal wire on a second side of the substrate, and electrically connecting one end of the metal wire with the peripheral circuit;

s30: stacking a plurality of sacrificial layers/channel layers in the first direction on a side of the metal interconnection layer away from the substrate in the order of the sacrificial layers and the channel layers;

s40: defining a storage unit area in the sacrificial layers/channel layers, and etching a bit line groove along a first direction;

s50: filling isolation materials in the bit line grooves, removing the sacrificial layers, and forming a plurality of semiconductor columns which are arrayed along the first direction and the third direction and extend along the second direction by the residual channel layers, wherein the semiconductor columns comprise source regions and drain regions at two ends and a channel region between the source regions and the drain regions;

S60: setting a grid electrode surrounding a channel region of the semiconductor column around the channel region to obtain a plurality of transistors formed by the semiconductor column and the grid electrode; and if one semiconductor column is arranged in the third direction, the grid electrode on the semiconductor column is used as a word line; or if the semiconductor columns arranged in the third direction are multiple, connecting the grid electrodes on the multiple semiconductor columns arranged in the third direction together in the third direction to form a word line;

s70: a capacitor surrounding one end of the drain region is arranged on the periphery of one end, far away from the channel region, of the drain region of the semiconductor column;

s80: removing isolation materials in the bit line grooves, filling bit line materials in the bit line grooves to form bit lines extending along a first direction, and connecting the bit lines with the source electrode areas of the semiconductor columns in contact with the bit lines so that the source electrode areas of the semiconductor columns share one bit line to obtain storage areas;

s90: one end of the metal line away from the peripheral circuit is electrically connected to the bit line, the word line, or the capacitor.

In the embodiment of the present application, step S40 may include:

S41: defining a memory cell region in the plurality of sacrificial layers/channel layers, and etching a memory cell isolation groove and a bit line groove at intervals along a first direction;

s42: performing side etching on the part, corresponding to the sacrificial layer, of the bit line groove along the second direction to obtain an inner supporting groove, and filling an inner supporting layer in the inner supporting groove;

optionally, S43: and carrying out side etching on the part, corresponding to the sacrificial layer, of the storage unit isolation groove along the second direction to obtain an inner supporting groove, and filling the inner supporting layer in the inner supporting groove.

In the embodiment of the present application, step S50 may include:

s51: filling storage unit isolation columns in the storage unit isolation grooves and filling isolation materials in the bit line grooves;

s52: the sacrificial layer is removed, and the remaining channel layer forms a plurality of semiconductor pillars arranged in an array in a first direction and a third direction and extending in a second direction, the semiconductor pillars including source and drain regions at both ends, and a channel region between the source and drain regions.

In the embodiment of the present application, the material of the sacrificial layer may be AZO.

In the embodiment of the present application, step S60 may include:

S61: sequentially arranging a grid dielectric layer and a grid around a channel region of the semiconductor column to obtain a plurality of transistors formed by the semiconductor column and the grid; and if one semiconductor column is arranged in the third direction, the grid electrode on the semiconductor column is used as a word line; or if the semiconductor columns arranged in the third direction are multiple, connecting the grid electrodes on the multiple semiconductor columns arranged in the third direction together in the third direction to form a word line;

optionally, S62: setting a plurality of word lines arranged in a first direction to be different in length so that the plurality of word lines arranged in the first direction take on a stepwise shape;

optionally, S63: an interlayer isolation tape is provided between two semiconductor pillars adjacent in the first direction, thereby isolating gates on the two semiconductor pillars adjacent in the first direction.

In the embodiment of the present application, step S70 may include: and an inner electrode plate, a dielectric layer and an outer electrode plate which encircle one end of the drain electrode region are sequentially arranged on the periphery of the drain electrode region of the semiconductor column, which is far away from one end of the channel region, so that a capacitor encircling one end of the drain electrode region is obtained.

In the embodiment of the present application, step S80 may include:

s81: removing isolation materials in the bit line grooves, filling bit line materials in the bit line grooves to form bit lines extending along a first direction, and connecting the bit lines with the source electrode regions of a plurality of semiconductor columns in contact with the bit lines so that the source electrode regions of the semiconductor columns share one bit line;

s82: and filling an isolation material in a blank space among the semiconductor column, the bit line and the word line.

In the embodiment of the present application, step S10 may include:

s11: sequentially arranging a peripheral circuit, a metal contact layer and an optional protective layer on a first side of the substrate;

s12: polishing a second side of the substrate;

s13: and arranging through holes with one ends starting from the metal contact layer and the other ends penetrating through the substrate in the metal contact layer and the substrate, and filling conductive metal in the through holes to form metal contact columns so as to obtain the peripheral circuit region.

In the embodiment of the present application, step S20 may further include: and electrically connecting the metal contact posts with the metal wires.

In the embodiment of the present application, step S90 may include: electrically connecting one end of the metal line far away from the peripheral circuit with the bit line; at this time, step S40 further includes aligning the bit line groove with the metal line;

Alternatively, step S90 may include: electrically connecting one end of the metal line far away from the peripheral circuit with the word line; at this time, step S60 further includes aligning the word line with the metal line;

alternatively, step S90 may include: and electrically connecting one end of the metal wire far away from the peripheral circuit with the capacitor.

In the embodiment of the present application, step S90 may include: electrically connecting an end of the metal wire remote from the peripheral circuit with an outer electrode plate of the capacitor; at this time, step S70 further includes aligning the outer electrode plate of the capacitor with the metal line.

Embodiments also provide a Dynamic Random Access Memory (DRAM) including a semiconductor device structure as described above.

The embodiment of the application also provides electronic equipment comprising the DRAM.

In an embodiment of the present application, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

The semiconductor device structure and the manufacturing method of the semiconductor device structure of the embodiment of the present application increase the storage density of the semiconductor memory by employing the lateral transistor semiconductor pillars (i.e., the transistor semiconductor pillars extending in the second direction) and the lateral capacitors (i.e., the capacitors are disposed between the transistor semiconductor pillars instead of on the left and right sides of the transistor) so that the transistor and the capacitor can form a three-dimensional stacked structure, and the memory cells formed by the transistor and the capacitor can be stacked together; in addition, the CuA (CMOS under Array) structure is adopted to arrange the peripheral circuit below the memory cell array, so that the occupied area of the peripheral circuit can be greatly saved, more memory cells can be arranged on a limited substrate area, and the memory density of the semiconductor memory is increased; and the sources of the transistors of the memory cells of two adjacent memory cell columns share one bit line in the second direction, so that the size of the semiconductor device structure can be reduced, the storage density of the semiconductor device structure can be further increased, the manufacturing cost of a unit Gb is reduced, and a new technology development direction is provided for the DRAM under the bottleneck of miniaturization.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.

Fig. 1A is a schematic structural diagram of a semiconductor device structure according to an exemplary embodiment of the present application;

fig. 1B is a schematic view of another angle of a semiconductor device structure according to an exemplary embodiment of the present application;

fig. 2 is a schematic front view cross-sectional structure diagram and a schematic top view cross-sectional structure diagram of a memory region of a semiconductor device structure according to an exemplary embodiment of the present application, wherein an upper diagram is a schematic front view cross-sectional structure diagram and a lower diagram is a schematic top view cross-sectional structure diagram;

fig. 3 is a schematic front view cross-sectional structure and a schematic top view cross-sectional structure of a memory region of a semiconductor device structure according to another exemplary embodiment of the present application, wherein an upper diagram is a schematic front view cross-sectional structure and a lower diagram is a schematic top view cross-sectional structure;

Fig. 4 is a schematic structural view of a peripheral circuit region of a semiconductor device structure according to an exemplary embodiment of the present application;

fig. 5 is a schematic structural diagram of a peripheral circuit region of a semiconductor device structure according to an embodiment of the present application;

fig. 6 is a process flow diagram of a method of fabricating a semiconductor device structure according to an embodiment of the present application;

fig. 7 is a schematic structural view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor device structure according to an exemplary embodiment of the present application;

fig. 8 is a schematic structural view of an intermediate product obtained at an intermediate step of a method of manufacturing a semiconductor device structure according to an exemplary embodiment of the present application;

fig. 9 is a schematic structural view of an intermediate product obtained at an intermediate step of a method of manufacturing a semiconductor device structure according to an exemplary embodiment of the present application;

fig. 10 is a schematic structural view of an intermediate product obtained at an intermediate step of a method of manufacturing a semiconductor device structure according to an exemplary embodiment of the present application;

fig. 11 is a schematic structural view of an intermediate product obtained in an intermediate step of a method of manufacturing a semiconductor device structure according to an exemplary embodiment of the present application;

fig. 12 is a schematic structural view of an intermediate product obtained at an intermediate step of a method of manufacturing a semiconductor device structure according to an exemplary embodiment of the present application.

The meaning of the reference symbols in the drawings is:

a-a peripheral circuit region; b-storage area; 100-a substrate; 200-columns of memory cells; 300-bit line; 300' -slot; 400-word lines; 500-peripheral circuits; 501-a first transistor; 5011—a first source; 5012—a first drain; 5013—a first channel; 5014—a first gate; 502-a second transistor; 5021-a second source; 5022-a second drain; 5023-second channel; 5024-second gate; 503-P-type well; 504-N type well; 600-metal contact layer; 601-metal contact pillars; 700-metal interconnect layer; 701-metal lines; 800-a protective layer; 900-sacrificial layer; 1-a memory cell; 1' -memory cell region; a 10-transistor; 11-semiconductor pillars; 11' -channel layer; 111-source regions; 112-a channel region; 113-drain region; 12-grid; 20-a capacitor; 21-an inner electrode plate; 22-an outer electrode plate; 23-a dielectric layer; 2-interlayer isolation belts; 3-memory cell isolation columns; 3' -memory cell isolation trenches; 4-an inner support layer; 4' -internal support slots; 5-isolating material.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.

In the description of the present application, ordinal numbers such as "first", "second", etc., are provided to avoid intermixing of constituent elements, and are not intended to be limiting in terms of number.

The embodiment of the application provides a semiconductor device structure. Fig. 1A is a schematic structural diagram of a semiconductor device structure according to an exemplary embodiment of the present application; fig. 1B is a schematic view of another angle of a semiconductor device structure according to an exemplary embodiment of the present application. As shown in fig. 1A and 1B, the semiconductor device structure may include: a substrate 100, a peripheral circuit region a and a memory region B, the substrate 100 having opposite first and second sides, the peripheral circuit region a being disposed on the first side of the substrate 100, the memory region B being disposed on the second side of the substrate 100, the peripheral circuit region a and the memory region B being electrically connected.

As shown in fig. 1A, the peripheral circuit region a includes peripheral circuits 500 disposed on a first side of the substrate 100.

Fig. 2 is a schematic front view cross-sectional structure and a schematic top view structure of a memory region of a semiconductor device structure according to an exemplary embodiment of the present application. As shown in fig. 2, the storage area B includes: a plurality of memory cell columns 200, a plurality of Bit lines 300 (BL) extending in a first direction, a plurality of Word lines 400 (WL) extending in a third direction, and a metal interconnection layer 700;

The metal interconnection layer 700 is disposed on the second side of the substrate 100, and the metal interconnection layer 700 has the metal line 701 disposed therein;

each of the memory cell columns 200 includes a plurality of memory cells 1 stacked in a first direction on a side of the metal interconnection layer 700 remote from the substrate 100, the plurality of memory cell columns 200 being arranged in a second direction and a third direction on the metal interconnection layer 700 to form an array; the memory cell 1 comprises a transistor 10 and a capacitor 20, the transistor 10 comprises a semiconductor pillar 11 and a gate 12, the semiconductor pillar 11 extends along a second direction and comprises a source region 111, a channel region 112 and a drain region 113, the source region 111 and the drain region 113 are respectively positioned at two ends of the semiconductor pillar 11, the channel region 112 is positioned between the source region 111 and the drain region 113, and the gate 12 surrounds the channel region 112; the capacitor 20 surrounds the drain region 113 at the end far from the channel region 112;

the source regions 111 of the transistors 10 of the plurality of memory cells 1 of the two memory cell columns 200 adjacent in the second direction are each connected to one common bit line 300;

the metal interconnection layer 700 may be provided with one or more memory cell columns 200 in a third direction; when the metal interconnection layer 700 is provided with one memory cell column 200 in the third direction, each of the word lines 400 is formed of the gate electrode 12 of the transistor 10 of one memory cell 1 of one memory cell column 200 arranged in the third direction; alternatively, when the metal interconnection layer 700 is provided with a plurality of memory cell columns 200 in the third direction, each of the word lines 400 is formed by connecting together the gates 12 of the transistors 10 of the plurality of memory cells 1 arranged in the third direction;

One end of the metal line 701 is electrically connected to the bit line 300, the word line 400, or the capacitor 20, and the other end of the metal line 701 is electrically connected to the peripheral circuit 500 of the peripheral circuit region a.

In the description of the present application, the "first direction" is defined as a direction perpendicular to the plane in which the substrate is located, i.e., a direction in which the height of the semiconductor device structure is located; "second direction" is defined as the direction perpendicular to the "first direction" and in which the width of the substrate is located; the "third direction" is defined as the direction perpendicular to the "first direction" and in which the length of the substrate is located. The "first direction", "second direction" and "third direction" may be as shown in fig. 2.

The semiconductor device structure of the embodiment of the present application increases the storage density of the semiconductor device structure by adopting the lateral transistor semiconductor pillars (i.e., the transistor semiconductor pillars extending in the second direction) and the lateral capacitors (i.e., the capacitors are disposed between the transistor semiconductor pillars instead of on the left and right sides of the transistor), so that the transistor and the capacitor can form a three-dimensional stacked structure, and the memory cells formed by the transistor and the capacitor can be stacked together; in addition, the CuA (CMOS under Array) structure is adopted to arrange the peripheral circuit below the memory cell array, so that the occupied area of the peripheral circuit can be greatly saved, more memory cells can be arranged on a limited substrate area, and the memory density of the semiconductor memory is increased; and the sources of the transistors of the memory cells of two adjacent memory cell columns share one bit line in the second direction, so that the size of the semiconductor device structure can be reduced, the storage density of the semiconductor device structure can be further increased, the manufacturing cost of a unit Gb is reduced, and a new technology development direction is provided for the DRAM under the bottleneck of miniaturization.

In the embodiment of the present application, one memory cell column may include 2 to 100 memory cells, for example, 2, 3 (as shown in fig. 2), 4, 5, 10, 13, 15, 18, 20, 30, 40, 50, 60, 70, 80, 90, and 100 memory cells may be included.

In this embodiment, the metal interconnection layer may be provided with 2 to 1000 memory cell columns along the second direction, for example, 2, 4 (as shown in fig. 2), 6, 8, 10, 12, 14, 16, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100, 200, 300, 400, 500, 600, 700, 800, 900, and 1000 memory cell columns may be provided; the metal interconnection layer may be provided with 1 to 100 memory cell columns along the third direction, for example, 1, 2, 3 (as shown in fig. 2), 4, 5, 12, 14, 16, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100 memory cell columns may be provided.

In the embodiments of the present application, the substrate may be a semiconductor substrate, for example, may be a monocrystalline Silicon substrate, and may also be a semiconductor-On-insulator (Semiconductor On Insulator, SOI) substrate, for example, a Silicon-On-sapphire (Silicon On Sapphire, SOS) substrate, a Silicon-On-Glass (SOG) substrate, an epitaxial layer of Silicon On a base semiconductor basis, or other semiconductor or optoelectronic material, for example, silicon-germanium (Si) _1-x Ge _x Where x may be, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). The substrate may or may not be doped.

In the embodiment of the present application, the material of the word line may be a material compatible with the semiconductor pillar, for example, may be Indium Tin Oxide (ITO) or the like.

In the embodiment of the application, the material of the bit line may be selected from any one or more of tungsten, mo, co and other metal materials with similar properties.

In this embodiment of the present application, the height of the semiconductor pillar along the first direction may be set according to actual electrical requirements, for example, may be 10nm to 50nm.

In the embodiment of the present application, as shown in fig. 2, the capacitor 20 may include an inner electrode plate 21, an outer electrode plate 22, and a dielectric layer 23 disposed between the inner electrode plate 21 and the outer electrode plate 22, and the drain region 113 is connected to the inner electrode plate 21. The outer electrode plates 22 of the plurality of capacitors 20 arranged in the third direction may be connected together, but the inner electrode plates 21 thereof are separated.

In the embodiment of the application, when the metal wire is required to be electrically connected with the capacitor, the metal wire can be electrically connected with an external electrode plate of the capacitor.

In the embodiment of the present application, as shown in fig. 2, one transistor 10 may correspond to one capacitor 20, that is, the memory cell 1 may have a 1T1C structure.

In embodiments of the present application, two capacitors adjacent in the first direction may share one external electrode plate.

In the embodiment of the present application, the materials of the inner electrode plate and the outer electrode plate may be each independently selected from any one or more of other metal materials having similar properties, such as TiN, tiAl, taN. The thickness of the inner electrode plate can be 5nm-15nm, and the thickness of the outer electrode plate can be 5nm-15nm.

In an embodiment of the present application, the material of the dielectric layer may be a high dielectric constant (K) material, for example, may be selected from HfO ₂ 、Al ₂ O ₃ ZrO and strontium titanate (SrTiO) ₃ STO). The thickness of the dielectric layer may be 5nm to 15nm.

In this embodiment, as shown in fig. 2, the memory cell column 200 may further include an interlayer isolation strip 2, where the interlayer isolation strip 2 is disposed between the gates 12 of the transistors 10 of two adjacent memory cells 1 in the memory cell column 200, and separates the gates 12 of the transistors 10 of two adjacent memory cells 1.

In the embodiment of the present application, the material of the interlayer isolation belt may be silicon oxide, for example, may be SiO ₂ 。

In this embodiment, as shown in fig. 2, the semiconductor device structure may further include one or more memory cell isolation pillars 3 extending along the first direction. For example, two memory cell columns 200 at intervals in the second direction may be provided with one of the memory cell isolation pillars 3.

In an embodiment of the present application, the material of the memory cell isolation pillar may be silicon oxide, for example, may be any one or more selected from Spin-On Deposition (SOD) silicon oxide films, high density plasma (High Density Plasma, HDP) silicon oxide films, and high aspect ratio process (High Aspect Ratio Process, HARP) silicon oxide films.

In an embodiment of the present application, the transistor may further include a gate dielectric layer (not shown), where the gate dielectric layer is disposed between the channel region and the gate.

In the embodiment of the present application, the thickness of the gate dielectric layer may be set according to practical electrical requirements, for example, may be 2nm-5nm.

In the embodiment of the application, the material of the gate electrode can be selected from any one or more of ITO or other low-temperature semiconductor materials.

In this embodiment, as shown in fig. 2, the semiconductor device structure may further include an internal support layer 4, where the internal support layer 4 is disposed between two semiconductor pillars 11 adjacent in the first direction, and configured to provide support for the semiconductor pillars 11.

In this embodiment, the internal support layer 4 may also be located on both sides of the bit line 300 as shown in fig. 2, or may be located on both sides of the bit line 300 and both sides of the memory cell isolation pillar 3 as shown in fig. 2. It is possible to provide a more firm support for the semiconductor pillars 11 when both sides of the bit line 300 and both sides of the memory cell isolation pillar 3 are provided with the inner support layer 4.

In the embodiment of the present application, the material of the inner supporting layer may be a film material with a supporting function, for example, siN.

Fig. 3 is a schematic front view cross-sectional structure and a schematic top view structure of a storage region of a semiconductor device structure according to another exemplary embodiment of the present application. As shown in fig. 1A, 1B, and 3, in the exemplary embodiment of the present application, the empty spaces among the semiconductor pillars, the bit lines, and the word lines may be filled with an isolation material 5.

In the embodiment of the application, the isolation material may be selected from any one or more of a SOD silicon oxide film, a HDP silicon oxide film and a HARP silicon oxide film.

In an embodiment of the present application, the peripheral circuit may be a CMOS transistor.

Fig. 4 is a schematic structural diagram of a peripheral circuit region of a semiconductor device structure according to an exemplary embodiment of the present application. In the embodiment of the present application, as shown in fig. 4, the peripheral circuit area a may include a peripheral circuit 500, a metal contact layer 600, and a metal contact post 601; the peripheral circuit 500 may be a CMOS transistor disposed on a first side of the substrate 100; the metal contact layer 600 is disposed on a side of the peripheral circuit 500 away from the substrate 100, one end of the metal contact post 601 is disposed in the metal contact layer 600 and electrically connected to the peripheral circuit 500, and the other end of the metal contact post 601 penetrates through the substrate 100 and is electrically connected to the metal wire 701. The metal contact pillars 601 may be configured to guide a circuit connection on the first side of the substrate to the second side of the substrate, so as to connect a peripheral circuit with a metal line of the storage area, and further connect the peripheral circuit with a bit line or a word line.

One end of the metal contact post 601 disposed in the metal contact layer 600 may penetrate the metal contact layer 600 or be located inside the metal contact layer 600, and the metal contact layer 600 may include an insulating medium in addition to the metal contact post 601. As shown in fig. 4, the metal contact pillar 601 may include a peripheral circuit connection line 6011 directly connected to the peripheral circuit and a TSV structure 6012 penetrating the substrate 100; one end of the TSV structure 6012 is electrically connected to the peripheral circuit connection line 6011, and the other end is electrically connected to the metal line 701 through the substrate 100.

The metal interconnect layer 700 may include a metal line 701 and an insulating medium.

In the embodiment of the application, the material of the metal wire can be selected from any one or more of copper and aluminum, and for example, the material can be copper; the material of the metal contact stud may be selected from any one or more of tungsten and molybdenum, for example, may be tungsten.

In this embodiment, as shown in fig. 4, the peripheral circuit area a may further include a protective layer 800 for encapsulating the peripheral circuit area a, where the protective layer 800 is disposed on a surface of the peripheral circuit area a (since the protective layer 800 and the insulating medium of the metal contact layer 600 are both dielectric materials, a separate protective layer 800 is not directly shown in fig. 4).

Fig. 5 is a schematic structural diagram of a peripheral circuit region of a semiconductor device structure according to an embodiment of the present application. As shown in fig. 5, in the embodiment of the present application, the CMOS transistor may include a first transistor 501 and a second transistor 502, where the first transistor 501 and the second transistor 502 are disposed side by side on a first side of the substrate 100, and a P-type well (P well) 503 may be further disposed between the first transistor 501 and the substrate 100, and an N-type well (N well) 504 may be further disposed between the second transistor 502 and the substrate 100; the first transistor 501 includes a first source electrode 5011, a first drain electrode 5012, a first channel 5013 disposed between the first source electrode 5011 and the first drain electrode 5012, and a first gate electrode 5014 disposed on one side of the first channel 5013, wherein materials of the first source electrode 5011 and the first drain electrode 5012 may be N-type semiconductor materials, and materials of the first channel 5013 may be P-type semiconductor materials; a first gate dielectric layer (or gate oxide layer, not shown) may be further disposed between the first channel 5013 and the first gate 5014; the second transistor 502 includes a second source 5021, a second drain 5022, a second channel 5023 disposed between the second source 5021 and the second drain 5022, and a second gate 5024 disposed on one side of the second channel 5023, materials of the second source 5021 and the second drain 5022 may be P-type semiconductor materials, materials of the second channel 5023 may be N-type semiconductor materials, and a second gate dielectric layer (or called gate oxide layer, not shown) may be further disposed between the second channel 5023 and the second gate 5024.

The embodiment of the application also provides a manufacturing method of the semiconductor device structure. The semiconductor device structure provided by the embodiment of the application can be obtained through the manufacturing method.

Fig. 6 is a process flow diagram of a method of fabricating a semiconductor device structure according to an embodiment of the present application. As shown in fig. 6, the manufacturing method may include:

In the embodiment of the present application, step S40 may include:

For example, in the present exemplary embodiment, i) step S40 may include:

alternatively, ii) step S40 may include:

s43: performing side etching on the part, corresponding to the sacrificial layer, of the storage unit isolation groove along the second direction to obtain an inner support groove, and filling an inner support layer in the inner support groove;

in the embodiment of the present application, step S50 may include:

In the embodiment of the present application, step S60 may include:

For example, in the present exemplary embodiment, i) step S60 may include:

alternatively, ii) step S60 may include:

S62: setting a plurality of word lines arranged in a first direction to be different in length so that the plurality of word lines arranged in the first direction take on a stepwise shape;

alternatively, iii) step S60 may include:

s63: an interlayer isolation strip is arranged between two adjacent semiconductor columns along the first direction, so that the grid electrodes on the two adjacent semiconductor columns along the first direction are isolated;

alternatively, iii) step S60 may include:

s63: an interlayer isolation tape is provided between two semiconductor pillars adjacent in the first direction, thereby isolating gates on the two semiconductor pillars adjacent in the first direction.

In the embodiment of the present application, step S80 may include:

s82: and filling isolation materials in the blank spaces among the semiconductor columns, the bit lines and the word lines to obtain storage areas.

In the embodiment of the present application, step S10 may include:

s12: polishing a second side of the substrate;

s13: arranging through holes with one ends starting from the metal contact layer and the other ends penetrating through the substrate in the metal contact layer and the substrate, and filling conductive metal in the through holes to form metal contact columns so as to obtain the peripheral circuit region;

at this time, step S20 further includes: and electrically connecting the metal contact posts with the metal wires.

alternatively, step S90 may include: electrically connecting one end of the metal wire far away from the peripheral circuit with the capacitor; at this time, step S70 further includes aligning the capacitor with the metal line.

In an embodiment of the present application, when the metal line is required to be electrically connected to the capacitor, step S90 may include: electrically connecting an end of the metal wire remote from the peripheral circuit with an outer electrode plate of the capacitor; at this time, step S70 further includes aligning the outer electrode plate of the capacitor with the metal line.

The metal lines may be selectively electrically connected to bit lines, word lines, or capacitors (outer electrode plates) as desired.

In the embodiment of the present application, when step S90 includes electrically connecting the end of the metal line away from the peripheral circuit with the word line, step S90 may be performed after step S60 forms the word line, before step S70 starts, or after step S80 ends; alternatively, when step S90 includes electrically connecting an end of the metal wire remote from the peripheral circuit with the capacitor (external electrode plate), step S90 may be performed after step S70 forms the capacitor (external electrode plate), before step S80 starts, or after step S80 ends.

Fig. 7 to 12 are schematic structural views of intermediate products obtained in intermediate steps of a method for manufacturing a semiconductor device structure according to an exemplary embodiment of the present application. As shown in fig. 1 and 2 and fig. 7 to 12, in an exemplary embodiment, the method of manufacturing a semiconductor device structure may include:

S11: a peripheral circuit 500, a metal contact layer 600 and a protective layer 800 are sequentially arranged on the first side of the substrate 100, so as to obtain an intermediate product as shown in fig. 7;

s12: polishing (Polish) the second side of the substrate 100 to a suitable thickness of the second side of the substrate 100;

s13: a through hole with one end starting from the metal contact layer 600 and the other end penetrating through the substrate 100 is arranged in the metal contact layer 600 and the substrate 100, and conductive metal is filled in the through hole to form a metal contact post 601, so as to obtain the peripheral circuit area A shown in fig. 4;

s20: a metal interconnection layer 700 (not directly shown in fig. 8, and referring to fig. 2) with a metal line 701 is disposed on the second side of the substrate 100, and one end of the metal line 701 is electrically connected to the peripheral circuit 500;

s30: stacking a plurality of sacrificial layers 900/channel layers 11 'along a first direction on one side of the metal interconnection layer 700 away from the substrate 100 in the order of the sacrificial layers 900 and the channel layers 11', to obtain an intermediate product as shown in fig. 8;

s41: defining a memory cell region 1 'in the plurality of sacrificial layers 900/channel layers 11', and etching a memory cell isolation trench 3 'and a bit line trench 300' at intervals along a first direction;

S42: performing side etching on the portion of the bit line groove 300' corresponding to the sacrificial layer 900 along the second direction to obtain an inner supporting groove 4', and filling the inner supporting groove 4' with the inner supporting layer 4;

s43: performing side etching on the portion, corresponding to the sacrificial layer 900, of the storage unit isolation groove 3' along the second direction to obtain an inner support groove 4', and filling the inner support groove 4' with the inner support layer 4 to obtain an intermediate product as shown in fig. 9;

s51: filling memory cell isolation pillars 3 in the memory cell isolation trenches 3 'and filling isolation material 5 in the bit line trenches 300';

s52: removing the sacrificial layer 900, and forming a plurality of semiconductor pillars 11 arrayed in the first direction and the third direction and extending in the second direction by the remaining channel layer 11', wherein the semiconductor pillars 11 comprise source and drain regions 111 and 113 at both ends, and a channel region 112 between the source and drain regions 111 and 113, resulting in an intermediate product as shown in fig. 10;

s61: a gate dielectric layer (not shown) and a gate electrode 12 surrounding the channel region 112 are sequentially disposed around the channel region 112 of the semiconductor pillar 11, so as to obtain a plurality of transistors 10 formed by the semiconductor pillar 11 and the gate electrode 12; and, if there is one semiconductor column 11 arranged in the third direction, making the gate electrode 12 on the one semiconductor column 11 as the word line 400; alternatively, if there are a plurality of semiconductor pillars 11 arranged in the third direction, the gates 12 on the plurality of semiconductor pillars 11 arranged in the third direction are connected together in the third direction to form the word line 400;

S62: the plurality of word lines 400 arranged in the first direction are provided to be different lengths such that the plurality of word lines 400 arranged in the first direction take on a stepped shape;

s63: an interlayer isolation tape 2 is provided between two semiconductor pillars 11 adjacent in the first direction, so as to isolate the gate electrodes 12 on the two semiconductor pillars 11 adjacent in the first direction, resulting in an intermediate product as shown in fig. 11;

s70: an inner electrode plate 21, a dielectric layer 23 and an outer electrode plate 22 which surround one end of the drain region 113 are sequentially arranged around one end of the drain region 113 of the semiconductor pillar 11 far from the channel region 112, so as to obtain a capacitor 20 which surrounds one end of the drain region 113, and an intermediate product as shown in fig. 12 is obtained;

s81: removing isolation material in the bit line trench 300', filling bit line material in the bit line trench 300', forming a bit line 300 extending along a first direction, and connecting the bit line 300 with the source regions 111 of the plurality of semiconductor pillars 11 in contact with the bit line 300 such that the source regions 111 of the plurality of semiconductor pillars 11 share the one bit line 300;

s82: filling an isolation material 5 in a blank space among the semiconductor pillar 11, the bit line and the word line;

S90: an end of the metal line 701 remote from the peripheral circuit 500 is electrically connected to the bit line 300, the word line 400, or the external electrode plate 22 of the capacitor 20, resulting in the semiconductor device structure shown in fig. 1.

In the embodiment of the present application, the peripheral circuit may be formed through a conventional CMOS process in step S10, and then a metal contact layer and a protective layer are fabricated on the peripheral circuit.

In this embodiment, in step S13, a through-silicon via (Through Silicon Via, TSV) technology may be used to provide a through-hole in the metal contact layer and the substrate, where one end starts from the metal contact layer and the other end penetrates through the substrate.

In this embodiment of the present application, in step S20, the metal interconnection layer may be formed by a metal wire and an insulating medium, and a whole layer of insulating medium may be first provided, and then a via hole is opened in the insulating medium and filled with metal to form the metal wire.

In an embodiment of the present application, step S30 may include disposing the sacrificial layer and the channel layer using an atomic layer deposition (Atomic layer deposition, ALD) process.

In the embodiment of the present application, the material of the sacrificial layer may be selected from any one or more of other conductive materials with similar properties, such as Aluminum-doped Zinc Oxide (AZO). The thickness of the sacrificial layer may be 30nm to 50nm, for example, 30nm, 35nm, 40nm, 45nm, 50nm.

In this embodiment of the present application, in step S41, patterning and etching may be performed by using the same layer of pattern mask (Photo mask) through light exposure, so as to form trenches arranged along the third direction and extending along the second direction, thereby isolating the multiple sacrificial layers/channel layers in the third direction, and obtaining the memory cell region.

In this embodiment, in step S42 or S43, a side etching may be performed on a portion of the bit line trench or the memory cell isolation trench corresponding to the sacrificial layer by wet etching.

In the embodiment of the present application, in step S42 or S43, the internal support layer may be filled in the internal support layer groove by an ALD process, for example, siN may be filled in the internal support layer groove by an ALD process, to form an internal support layer.

In the embodiment of the present application, in step S51, the memory cell isolation pillars may be filled in the memory cell isolation trenches and the isolation material may be filled in the bit line trenches by a SOD, HDP or HARP process, for example, a silicon oxide film may be formed in the memory cell isolation trenches and the bit line trenches by a SOD, HDP or HARP process.

In the embodiment of the present application, in step S52, the sacrificial layer may be etched away by an etching method, which may be dry etching or wet etching, and selecting an ultra-high sacrificial layer/channel layer etching ratio to leave the channel layer.

In the embodiment of the present application, step-shaped word lines (staircase WL) may be obtained by trim etching (trim etch) in step S62.

In the embodiment of the present application, the interlayer isolation tape may be provided by an ALD or chemical vapor deposition (Chemical Vapor Deposition, CVD) process in step S63, for example, siO may be filled by an ALD or CVD process ₂ Forming an interlayer isolation belt.

In the embodiment of the present application, the isolation material may be filled in the empty space through the SOD, HDP or HARP process in step S82, for example, any one or more of the SOD silicon oxide film, the HDP silicon oxide film and the HARP silicon oxide film may be formed in the empty space through the SOD, HDP or HARP process.

In the description herein, it should be noted that the directions or positional relationships indicated by the terms "upper", "lower", "one side", "the other side", "one end", "the other end", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the structures referred to have a specific direction, are configured and operated in a specific direction, and thus are not to be construed as limiting the present application.

In the description of the embodiments of the present application, unless explicitly stated and limited otherwise, the terms "connected," "disposed," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; the terms "connected" and "disposed" may be directly connected or indirectly connected through intervening media, or may be in communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

Although the embodiments disclosed in the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the application is still subject to the scope of the claims that follow.

Claims

1. A method of fabricating a semiconductor device structure, comprising:

2. The manufacturing method according to claim 1, wherein step S40 includes:

s42: and carrying out side etching on the part of the bit line groove corresponding to the sacrificial layer along the second direction to obtain an internal supporting groove, and filling the internal supporting layer in the internal supporting groove.

3. The manufacturing method according to claim 2, wherein step S40 further includes: after the step S41 of the process,

S43: and carrying out side etching on the part, corresponding to the sacrificial layer, of the storage unit isolation groove along the second direction to obtain an inner supporting groove, and filling the inner supporting layer in the inner supporting groove.

4. A manufacturing method according to claim 3, wherein step S50 comprises:

5. The manufacturing method according to claim 1, wherein a material of the sacrificial layer is AZO.

6. The manufacturing method according to claim 1, wherein step S60 includes:

s61: sequentially arranging a grid dielectric layer and a grid around a channel region of the semiconductor column to obtain a plurality of transistors formed by the semiconductor column and the grid; and if one semiconductor column is arranged in the third direction, the grid electrode on the semiconductor column is used as a word line; alternatively, if there are a plurality of semiconductor pillars arranged in the third direction, the gates on the plurality of semiconductor pillars arranged in the third direction are connected together in the third direction to form a word line.

7. The manufacturing method according to claim 6, wherein step S60 includes at least one of steps S62 and S63:

8. The manufacturing method according to any one of claims 1 to 7, wherein step S70 includes: and an inner electrode plate, a dielectric layer and an outer electrode plate which encircle one end of the drain electrode region are sequentially arranged on the periphery of the drain electrode region of the semiconductor column, which is far away from one end of the channel region, so that a capacitor encircling one end of the drain electrode region is obtained.

9. The manufacturing method according to any one of claims 1 to 7, wherein step S80 includes:

S82: and filling isolation materials in the blank spaces among the semiconductor columns, the bit lines and the word lines to obtain the storage areas.

10. The manufacturing method according to any one of claims 1 to 7, wherein step S10 includes:

s11: a peripheral circuit, a metal contact layer and a protective layer are sequentially arranged on the first side of the substrate;

s12: polishing a second side of the substrate;

11. The manufacturing method according to any one of claims 1 to 7, wherein step S90 includes: electrically connecting one end of the metal line far away from the peripheral circuit with the bit line; at this time, step S40 further includes aligning the bit line groove with the metal line;

alternatively, step S90 includes: electrically connecting one end of the metal line far away from the peripheral circuit with the word line; at this time, step S60 further includes aligning the word line with the metal line;

Alternatively, step S90 includes: and electrically connecting one end of the metal wire far away from the peripheral circuit with the capacitor.

12. The manufacturing method according to claim 11, wherein step S90 includes: electrically connecting an end of the metal wire remote from the peripheral circuit with an outer electrode plate of the capacitor; at this time, step S70 further includes aligning the outer electrode plate of the capacitor with the metal line.

13. A semiconductor device structure obtained by the manufacturing method according to any one of claims 1 to 12, comprising: a substrate having opposite first and second sides, a peripheral circuit region disposed on the first side of the substrate, and a storage region disposed on the second side of the substrate, the peripheral circuit region and the storage region being electrically connected; the peripheral circuit region includes a peripheral circuit; the storage area includes:

14. The semiconductor device structure of claim 13, wherein a plurality of word lines arranged in the first direction are different in length, forming a step.

15. The semiconductor device structure of claim 14, wherein the material of the word line is ITO.

16. The semiconductor device structure of claim 13, wherein a material of the semiconductor pillars is selected from IGZO, ZTO, IZO, znO _x 、InWO、IZTO、InO _x 、In ₂ O ₃ 、SnO ₂ 、TiO _x 、Zn _x O _y N _z 、Mg _x Zn _y O _z 、Zr _x In _y Zn _z O _a 、Hf _x In _y Zn _z O _a 、Al _x Sn _y In _z Zn _a O _d 、Si _x In _y Zn _z O _a 、Al _x Zn _y Sn _z O _a 、Ga _x Zn _y Sn _z O _a 、Zr _x Zn _y Sn _z O _a And any one or more of InGaSiO.

17. The semiconductor device structure of claim 13, wherein the capacitor comprises an inner electrode plate, an outer electrode plate, a dielectric layer disposed between the inner electrode plate and the outer electrode plate, the drain region being connected to the inner electrode plate.

18. The semiconductor device structure of claim 17, wherein the metal line is electrically connected with the outer electrode plate.

19. The semiconductor device structure of any of claims 13-18, wherein the memory cell column further comprises an interlayer isolation strip disposed between gates of transistors of two adjacent memory cells in the memory cell column, the gates of transistors of two adjacent memory cells being isolated.

20. The semiconductor device structure of claim 19, wherein the semiconductor device structure further comprises one or more memory cell isolation pillars extending in a first direction, one of the memory cell isolation pillars being provided every two memory cell columns apart in a second direction.

21. The semiconductor device structure of claim 20, wherein a material of the interlayer isolation strap and the memory cell isolation post is silicon oxide.

22. The semiconductor device structure of any of claims 13-18, wherein the transistor further comprises a gate dielectric layer disposed between the channel region and the gate.

23. The semiconductor device structure of claim 22, wherein the gate dielectric layer material is selected from the group consisting of silicon dioxide, hfO ₂ ZrO and Al ₂ O ₃ Any one or more of the following.

24. The semiconductor device structure of any of claims 20 or 21, further comprising an internal support layer disposed between two semiconductor pillars adjacent in a first direction configured to provide support to the semiconductor pillars.

25. The semiconductor device structure of claim 24, wherein the internal support layer is located on both sides of the bit line or on both sides of the bit line and on both sides of the memory cell isolation pillar.

26. The semiconductor device structure of claim 25, wherein the material of the inner support layer is SiN.

27. The semiconductor device structure of any of claims 13-18, wherein the peripheral circuitry is a CMOS transistor, the peripheral circuitry region further comprising a metal contact layer and a metal contact pillar; the peripheral circuit is arranged on the first side of the substrate, the metal contact layer is arranged on one side, far away from the substrate, of the peripheral circuit, one end of the metal contact column is arranged in the metal contact layer and is electrically connected with the peripheral circuit, and the other end of the metal contact column penetrates through the substrate and is electrically connected with the metal wire.

28. The semiconductor device structure of any of claims 13-18, wherein the peripheral circuit region further comprises a protective layer for encapsulating the peripheral circuit region, the protective layer disposed on a surface of the peripheral circuit region.

29. The semiconductor device structure of claim 28, wherein the protective layer comprises SiO ₂ A layer and a SiN layer.

30. A DRAM comprising a semiconductor device structure according to any of claims 13-29.

31. An electronic device comprising the DRAM of claim 30.

32. The electronic device of claim 31, comprising a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.