KR20230163317A - Semiconductor device - Google Patents

Abstract

The present disclosure relates to a semiconductor device, and the semiconductor device according to one embodiment includes a substrate, a stacked structure including a plurality of layers stacked in a direction perpendicular to the substrate, and on one side of the stacked structure in a direction perpendicular to the substrate. and a bit line extending to, wherein the plurality of layers include a word line extending in a first direction parallel to the substrate, a channel layer, and a data storage element electrically connected to the channel layer, and the channel layer includes , covering opposing sides of adjacent word lines in a direction perpendicular to the substrate, contacting the bit line between the adjacent word lines, and facing a side of the word line and away from the bit line of the data storage element. It extends along a surface extending in two directions.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

This disclosure relates to semiconductor devices.

Technology to increase the integration of semiconductor devices is required. In the case of two-dimensional semiconductor devices, the degree of integration is mainly determined by the area occupied by a unit memory cell, and the degree of integration in this aspect may depend on the level of fine pattern formation technology.

However, fine pattern formation technology requires expensive equipment, so although the integration of two-dimensional semiconductor devices is increasing, it is still limited. Accordingly, three-dimensional semiconductor memory devices including memory cells arranged in three dimensions have been proposed.

Embodiments are intended to provide a semiconductor device that can improve operating characteristics by reducing leakage current.

A semiconductor device according to an embodiment includes a substrate, a stacked structure including a plurality of layers stacked in a direction perpendicular to the substrate, and a bit line extending in a direction perpendicular to the substrate on one side of the stacked structure, The plurality of layers include a word line extending in a first direction parallel to the substrate, a channel layer, and a data storage element electrically connected to the channel layer, and the channel layer is adjacent to the substrate in a direction perpendicular to the substrate. covering opposing sides of word lines, contacting the bit line between adjacent word lines, and extending along a side of the word line and a side extending in a second direction away from the bit line of the data storage element. do.

A semiconductor device according to an embodiment includes a substrate, a stacked structure including a plurality of layers stacked in a direction perpendicular to the substrate, and a bit line extending in a direction perpendicular to the substrate on one side of the stacked structure, Each of the plurality of layers includes a first word line and a second word line extending in a first direction parallel to the substrate, a first gate insulating film surrounding the first word line, and a second word line surrounding the second word line. It includes a gate insulating layer, a channel layer positioned between the first word line and the second word line and in contact with the bit line, and a data storage element electrically connected to the channel layer, wherein the channel layer is a two-dimensional material. and conformally covers the upper surface of the first gate insulating film, the lower surface of the second gate insulating film, and the side surface of the bit line.

According to embodiments, leakage current can be reduced and the operating characteristics of the semiconductor device can be improved.

1 is a perspective view schematically showing a semiconductor device according to an embodiment.
Figure 2 is a cross-sectional view of a semiconductor device according to an embodiment.
3 is a cross-sectional view of a semiconductor device according to one embodiment.
Figure 4 is a cross-sectional view of a semiconductor device according to one embodiment.
Figure 5 is a cross-sectional view of a semiconductor device according to one embodiment.
6 to 14 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment.
15 to 23 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment.

Hereinafter, with reference to the attached drawings, various embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention. The invention may be implemented in many different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts that are not relevant to the description are omitted, and identical or similar components are assigned the same reference numerals throughout the specification.

In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, so the present invention is not necessarily limited to what is shown. In the drawing, the thickness is enlarged to clearly express various layers and regions. And in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggerated.

Additionally, when a part of a layer, membrane, region, plate, etc. is said to be “on” or “on” another part, this includes not only cases where it is “directly above” another part, but also cases where there is another part in between. . Conversely, when a part is said to be “right on top” of another part, it means that there is no other part in between. In addition, being “on” or “on” a reference part means being located above or below the reference part, and does not necessarily mean being located “above” or “on” the direction opposite to gravity. .

In addition, throughout the specification, when a part is said to "include" a certain component, this means that it may further include other components rather than excluding other components, unless specifically stated to the contrary.

In addition, throughout the specification, when referring to “on a plane,” this means when the target portion is viewed from above, and when referring to “in cross section,” this means when a cross section of the target portion is cut vertically and viewed from the side.

Hereinafter, a semiconductor device according to an embodiment will be described with reference to FIGS. 1 and 2 . A semiconductor device according to an embodiment may include memory cells arranged in three dimensions. Memory cells may be arranged in the first direction DR1, the second direction DR2, and the third direction DR3. Memory cells may be stacked in the third direction DR3 perpendicular to the substrate 110 . Each memory cell may be connected to one bit line (BL) and two word lines (WL).

The bit line BL may extend along the third direction DR3. Memory cells stacked in the third direction DR3 may be commonly connected to one bit line BL. The plurality of bit lines BL may be arranged along the first direction DR1. Additionally, the plurality of bit lines BL may be arranged along the second direction DR2.

The word line WL may extend along the first direction DR1. Memory cells arranged along the first direction DR1 may be commonly connected to one word line WL. The plurality of word lines WL may be arranged along the third direction DR3. Each memory cell may be connected to two adjacent word lines WL arranged in the third direction DR3. Additionally, the plurality of word lines WL may be arranged along the second direction DR2.

1 is a perspective view schematically showing a semiconductor device according to an embodiment. Figure 1 shows one memory cell and one bit line (BL) and two word lines (WL) connected to the one memory cell, and other memory cells are omitted for convenience. In FIG. 1, only one cell of one layer of the laminate structure SS of FIG. 2, which will be described later, is shown.

Figure 2 is a cross-sectional view of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view of the semiconductor device according to the embodiment of FIG. 1 taken along the second direction DR2 and the third direction DR3. FIG. 2 shows three memory cells stacked in the third direction DR3 and commonly connected to one bit line BL of the semiconductor device according to the embodiment of FIG. 1 . FIG. 2 further illustrates memory cells arranged in the third direction DR3 omitted in FIG. 1 . The stacked structure SS shown in FIG. 2 includes, for example, three layers, and each layer may include one memory cell.

Referring to FIGS. 1 and 2 , a semiconductor device according to an embodiment includes a substrate 110, a stacked structure SS including a plurality of layers stacked in a third direction DR3 perpendicular to the substrate 110, and a bit line BL extending in a third direction DR3 perpendicular to the substrate 110 on one side of the stacked structure SS. According to one embodiment, the plurality of layers of the stacked structure SS include a word line WL, a channel film 210, and a channel film 210 extending in the first direction DR1 parallel to the substrate 110. It may include an electrically connected data storage element (DS).

Figure 1 shows one bit line (BL) and a portion of one layer of the stacked structure (SS) connected thereto, and some of the insulating layers are omitted for convenience. Although FIG. 1 shows one memory cell of the semiconductor device, the semiconductor device may include a memory cell array in which a plurality of memory cells are arranged and stacked. Although not shown, a plurality of bit lines BL may be arranged on the substrate 110 and spaced apart in the first direction DR1 and the second direction DR2. The second direction DR2 may be parallel to the substrate 110 and intersect the first direction DR1. Additionally, a plurality of word lines WL may be stacked on the substrate 110 and spaced apart in the third direction DR3.

Referring to FIG. 2 , a stacked structure SS may be provided on the substrate 110 . The substrate 110 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The stacked structure SS may form a memory cell array of a semiconductor device. Although not shown, peripheral circuitry for operating the memory cell array may be further provided on the substrate 110.

A bit line BL and a first interlayer insulating film 120 may be provided on one side of the stacked structure SS. The bit line BL may extend in the third direction DR3 perpendicular to the substrate 110 . The bit line BL may have a line shape or a pillar shape extending in the third direction DR3. The bit lines BL may be arranged along the first direction DR1.

The bit line BL may be electrically connected to the channel film 210. The bit line BL may contact the channel film 210 .

The bit line BL may include a conductive material. The conductive material may be, for example, a doped semiconductor material such as doped silicon or doped germanium, a conductive metal nitride such as titanium nitride or tantalum nitride, a metal such as tungsten, titanium, or tantalum, or tungsten silicide, cobalt silicide, Alternatively, it may be any one of metal-semiconductor compounds such as titanium silicide.

The first interlayer insulating film 120 may extend in the third direction DR3 perpendicular to the substrate 110 . Additionally, the first interlayer insulating film 120 may extend along the first direction DR1 parallel to the substrate 110 . The first interlayer insulating film 120 may cover the bit line BL. The first interlayer insulating film 120 may extend into the space between the bit lines BL arranged along the first direction DR1. By the first interlayer insulating film 120, bit lines BL arranged along the first direction DR1 may be insulated from each other.

The first interlayer insulating film 120 may include, for example, at least one of a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, or a carbon-containing silicon oxynitride film.

The layered structure SS may include a plurality of layers. It may include a first layer (L1), a second layer (L2), and a third layer (L3) sequentially stacked on the substrate 110. Although three layers are shown in FIG. 2, the present invention is not limited thereto, and the stacked structure SS may include more layers.

The first layer (L1), the second layer (L2), and the third layer (L3) may be stacked and spaced apart from each other in the third direction (DR3) perpendicular to the substrate 110. The first layer (L1), the second layer (L2), and the third layer (L3) each include a first word line (WL1) and a second word line (WL2), a channel film 210, and a data storage element ( DS) may be included.

Each of the plurality of layers may be spaced apart from each other by a second interlayer insulating film 150 . The first layer (L1), the second layer (L2), and the third layer (L3) may be spaced apart from each other by a second interlayer insulating film 150. The first and second word lines WL1 and WL2 of each layer, the channel layer 210, and the data storage element DS may be provided on the second interlayer insulating layer 150. The second interlayer insulating film 150 connects the first word line (WL1) and second word line (WL2) of the upper layer and the first word line (WL1) and second word line (WL2) of the lower layer in the third direction ( It can be separated by DR3). The second interlayer insulating layer 150 may separate the channel layer 210 of the upper layer from the channel layer 210 of the lower layer in the third direction DR3.

The second interlayer insulating film 150 may include, for example, at least one of a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, or a carbon-containing silicon oxynitride film.

The word line WL of each layer may extend along the first direction DR1. The word line WL may have a line shape extending in the first direction DR1. Each layer may include two word lines (WL). In each layer, the first word line WL1 and the second word line WL2 may be arranged to be spaced apart in the third direction DR3. The first word line WL1 may be closer to the substrate 110 than the second word line WL2.

The word line (WL) may include a conductive material. For example, the conductive material may be any of a semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound.

A spacer 140 may be located between the word line (WL) and the bit line (BL). The spacer 140 includes an insulating material and can insulate the bit line BL and the word line WL from each other.

The gate insulating layer Gox may surround the surface of the word line WL. The gate insulating layer (Gox) may conformally cover the word line (WL). The gate insulating layer Gox may cover the top, side, and bottom surfaces of the word line WL.

Additionally, the gate insulating layer Gox may surround the surface of the spacer 140. The gate insulating film Gox may cover the upper and lower surfaces of the spacer 140.

The gate insulating layer (Gox) may be in contact with the bit line (BL). A portion of the gate insulating film Gox covering the upper surface of the spacer 140 and a portion of the gate insulating film Gox covering the lower surface of the spacer 140 may contact the bit line BL.

The gate insulating layer Gox may include a first gate insulating layer Gox1 surrounding the first word line WL1 and a second gate insulating layer Gox2 surrounding the second word line WL2. The first gate insulating layer Gox1 may surround the first word line WL1 and the spacer 140 located between the first word line WL1 and the bit line BL. The second gate insulating layer Gox2 may surround the second word line WL2 and the spacer 140 located between the second word line WL2 and the bit line BL. The first gate insulating layer Gox1 and the second gate insulating layer Gox2 may contact the bit line BL.

The gate insulating layer Gox may include at least one of a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. High dielectric films include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, It may include at least one of lead scandium tantalum oxide, or lead zinc niobate.

Although not shown, each of the plurality of layers may include a plurality of channel films 210 arranged and spaced apart in the first direction DR1. Channel films 210 arranged in the first direction DR1 may be insulated by an interlayer insulating film (not shown).

According to one embodiment, the channel film 210 may cover opposing surfaces of adjacent word lines WL in the third direction DR3 perpendicular to the substrate 110 . The channel film 210 may cover opposing surfaces of the first word line (WL1) and the second word line (WL2) adjacent to each other in the third direction (DR3). The channel film 210 may cover the upper surface of the first word line (WL1) and the lower surface of the second word line (WL2).

The channel layer 210 may be separated from the word lines (WL) by the gate insulating layer (Gox). A first gate insulating layer (Gox1) may be located between the channel layer 210 and the first word line (WL1), and a second gate insulating layer (Gox2) may be located between the channel layer 210 and the second word line (WL2). This location can be

According to one embodiment, the channel film 210 may contact the bit line BL between adjacent word lines WL in the third direction DR3 perpendicular to the substrate 110. The channel film 210 may contact the bit line BL between the first word line WL1 and the second word line WL2. The portion of the channel film 210 that covers the upper surface of the first gate insulating film (Gox1) and the portion of the channel film 210 that covers the lower surface of the second gate insulating film (Gox2) are channels that cover the side surfaces of the bit line (BL). It may be connected by portions of the membrane 210. The channel film 210 may conformally cover the top surface of the first gate insulating film Gox1, the bottom surface of the second gate insulating film Gox2, and the side surfaces of the bit line BL.

According to one embodiment, an insulating film 220 is formed between a portion of the channel film 210 covering the upper surface of the first gate insulating film Gox1 and a portion of the channel film 210 covering the lower surface of the second gate insulating film Gox2. ) can be located. In other words, on a cross-section cut in the third direction DR3 perpendicular to the substrate 110, a first gate insulating layer Gox1 and a channel layer 210 are formed between the adjacent first word line WL1 and second word line WL2. ), the insulating film 220, the channel film 210, and the second gate insulating film (Gox2) may be positioned sequentially. The channel film 210 may be located between the insulating film 220 and the bit line BL on a cross-section cut in the second direction DR2 parallel to the substrate 110.

According to one embodiment, the channel film 210 may extend along the side of the word line (WL). The channel film 210 may extend along the side of the first word line (WL1) and the side of the second word line (WL2). The channel film 210 may extend in the third direction DR3 along the side surfaces of the first word line WL1 and the second word line WL2. The channel film 210 may extend in an upward direction along the side of the first word line (WL1) and may extend in a downward direction along the side of the second word line (WL2). Here, the upward direction may mean a direction away from the substrate 110, and the downward direction may mean a direction closer to the substrate 110.

The channel layer 210 may be spaced apart from the side of the first word line WL1 by the first gate insulating layer Gox1 and the etch stop layer 130. The channel layer 210 may be spaced apart from the side of the second word line WL2 by the second gate insulating layer Gox2 and the etch stop layer 130.

The etch stop layer 130 may be located on one side of the word lines WL. A gate insulating layer (Gox) may be positioned between the etch stop layer 130 and the word lines (WL). The etch stop layer 130 may cover a side surface of the first gate insulating layer Gox1, which covers a side surface of the first word line WL1. The etch stop layer 130 may cover a side surface of the second gate insulating layer Gox2, which covers a side surface of the second word line WL2. The etch stop layer 130 may have a shape extending in the third direction DR3.

The channel film 210 covers the top surface of the first gate insulating film Gox1 and the etch stop film 130, and may extend over the side surface of the etch stop film 130. The channel film 210 covers the second gate insulating film Gox2 and the lower surface of the etch stop film 130, and may extend over the side surface of the etch stop film 130.

The channel film 210 covers the side surface of the etch stop film 130 and may extend over the second interlayer insulating film 150 . The channel film 210 may cover the upper surface of the second interlayer insulating film 150 located below the layer including the channel film 210. The channel film 210 may cover the lower surface of the second interlayer insulating film 150 located on the layer including the channel film 210. The channel film 210 may extend along the top or bottom surface of the second interlayer insulating film 150 in the second direction DR2 away from the bit line BL.

According to one embodiment, the channel film 210 may include a first part covering the upper surface of the first gate insulating film Gox1 and a second part covering the lower surface of the second gate insulating film Gox2. The first portion extends perpendicularly to the substrate 110 between the side of the first word line WL1 and the data storage element DS, and includes a second interlayer insulating film 150 located below the first word line WL1. and may extend parallel to the substrate 110 between the data storage element DS. The second portion extends perpendicularly to the substrate 110 between the side of the second word line WL2 and the data storage element DS, and includes a second interlayer insulating film 150 located on the second word line WL2. It may extend parallel to the substrate 110 between the data storage elements DS. A detailed description of the data storage element (DS) will be described later.

According to one embodiment, the channel film 210 may include a two-dimensional material. The two-dimensional material is, for example, at least one of molybdenum disulfide (MoS ₂ ), molybdenum diselenide (MoSe ₂ ), tungsten disulfide (WS ₂ ), tungsten diselenide (WSe ₂ ), or black phosphorus (BP). It may include, but is not limited to this.

According to one embodiment, the channel film 210 may be electrically connected to the data storage element DS. A data storage element (DS) is a memory element capable of storing data, for example, a memory element using a capacitor, a memory element using a magnetic tunnel junction pattern, or a variable resistor containing a phase change material. It may be a memory element using .

According to one embodiment, the data storage element DS may be a capacitor. According to one embodiment, the data storage element DS includes a first electrode 310 and a second electrode 330 and a dielectric film 320 disposed between the first electrode 310 and the second electrode 330. can do.

Although not shown, each of the plurality of layers may include a plurality of first electrodes 310 arranged and spaced apart in the first direction DR1. The plurality of first electrodes 310 arranged in the first direction DR1 may be insulated by an interlayer insulating film (not shown).

According to one embodiment, the first electrode 310 may include a vertical portion and a horizontal portion. The vertical portion of the first electrode 310 covers the side surfaces of adjacent word lines WL in the third direction DR3 perpendicular to the substrate 110 and may extend in the third direction DR3. The horizontal portion of the first electrode 310 may extend from the vertical portion of the first electrode 310 in the second direction DR2 parallel to the substrate 110 and away from the bit line BL. The first electrode 310 may include a horizontal portion that overlaps the first word line (WL1) in the second direction (DR2) and a horizontal portion that overlaps the second word line (WL2) in the second direction (DR2). . That is, the first electrode 310 may include two horizontal portions spaced apart in the third direction DR3. The first electrode 310 extends in the second direction DR2 and may have the shape of a hollow cylinder.

According to one embodiment, the second electrode 330 may be inserted into the first electrode 310. The second electrode 330 may be inserted into the inner space of the cylindrical first electrode 310. The second electrode 330 may be connected to the outside of the cylindrical first electrodes 310 in the third direction DR3. The data storage elements DS of a plurality of layers stacked in the third direction DR3 may share one second electrode 330.

The first electrode 310 and the second electrode 330 are each made of a metal material such as titanium, tantalum, tungsten, copper, or aluminum, a conductive metal nitride such as titanium nitride or tantalum nitride, or doped silicon or doped germanium. It may include at least one of doped semiconductor materials such as.

The dielectric layer 320 may be positioned between the first electrode 310 and the second electrode 330. The dielectric layer 320 may include a high dielectric constant material. For example, the dielectric film 320 may be formed of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, and aluminum oxide. , lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

According to one embodiment, the data storage element DS may include a surface extending in the second direction DR2 away from the bit line BL. According to the above description, the horizontal portion of the first electrode 310 may extend in the second direction DR2 away from the bit line BL. According to one embodiment, the channel film 210 may extend along a surface extending in the second direction DR2 away from the bit line BL of the data storage element DS. In other words, the channel film 210 may extend along the upper and lower surfaces of the horizontal portion of the first electrode 310.

According to one embodiment, the data storage element DS may be electrically connected to the channel film 210. Specifically, the first electrode 310 may be connected to the channel film 210. The first electrode 310 may contact the channel film 210 . The vertical and horizontal portions of the first electrode 310 may contact the channel film 210 .

According to the above description, the channel film 210 may extend in the third direction DR3 along the side surfaces of the word lines WL. The vertical portion of the first electrode 310 may contact a portion of the channel film 210 extending in the third direction DR3 along the side surfaces of the word lines WL. According to one embodiment, the channel film 210 may be positioned between the vertical portion of the first electrode 310 and the side surfaces of the word lines (WL).

As described above, the channel film 210 may extend along the top or bottom surface of the second interlayer insulating film 150 in the second direction DR2 away from the bit line BL. The horizontal portion of the first electrode 310 may be in contact with a portion of the channel layer 210 extending in the second direction DR2 away from the bit line BL along the upper or lower surface of the second interlayer insulating layer 150. You can. According to one embodiment, the channel film 210 may be positioned between the horizontal portion of the first electrode 310 and the second interlayer insulating film 150.

According to one embodiment, the vertical portion of the first electrode 310 may contact the insulating film 220. In FIG. 2 , the vertical portion of the first electrode 310 includes a partially protruding portion in the bit line BL direction, and the protruding portion is shown as being in contact with the insulating film 220, but the present invention is not limited thereto. For example, the side surface of the vertical portion of the first electrode 310 that contacts the insulating film 220 may be flat.

According to one embodiment, an insulator 340 may be disposed between the second interlayer insulating film 150 and the dielectric film 320. The insulator 340 may insulate the channel film 210 and the first electrode 310 from the second electrode 330. The insulator 340 may include, for example, at least one of silicon nitride, silicon oxynitride, carbon-containing silicon oxide, carbon-containing silicon nitride, or carbon-containing silicon oxynitride.

Although not shown, wirings electrically connected to the bit lines BL and word lines WL may be provided on the stacked structure SS.

Although not shown, a stacked structure mirror-symmetrical with the stacked structure SS may be provided in the second direction DR2 on the substrate 110 . The stacked structure SS and the mirror-symmetrical stacked structure may share the second electrode 330 of the data storage element DS. A layered structure (SS) and a layered structure that is mirror symmetrical to the layered structure (SS) may form a pair.

According to the above-described embodiments, since the channel film 210 includes a two-dimensional material, the gate-induced drain leakage (GIDL) is reduced compared to the case where the channel film 210 includes polysilicon. As a result, the operating characteristics of the semiconductor device can be improved. Additionally, because the channel film 210 includes a two-dimensional material, carrier mobility and operational reliability can be improved compared to the case where the channel film 210 includes indium gallium zinc oxide (IGZO).

Hereinafter, semiconductor devices according to various embodiments will be described with reference to FIGS. 3 to 5.

3 is a cross-sectional view of a semiconductor device according to one embodiment. The semiconductor device according to the embodiment of FIG. 3 is different from the semiconductor device according to the embodiment of FIGS. 1 and 2 only in part in the structure of the channel film 210, but other components are the same. Accordingly, for convenience, the description will focus on the differences, and descriptions that overlap with those described above with reference to FIGS. 1 and 2 will be omitted or simplified.

Hereinafter, the channel film 210 included in one of the plurality of layers of the stacked structure SS will be described, focusing on the relationship between the channel film 210 and other components included in the same layer. do.

Referring to FIG. 3 , the channel film 210 may fill the space between the first word line (WL1) and the second word line (WL2) adjacent to each other in the third direction (DR3). The first word line WL1 may be surrounded by a first gate insulating layer Gox1, and the second word line WL2 may be surrounded by a second gate insulating layer Gox2. The channel film 210 may fill the space between the upper surface of the first gate insulating film Gox1 and the lower surface of the second gate insulating film Gox2.

According to one embodiment, a first gate insulating layer (Gox1) and a channel layer are formed between the first word line (WL1) and the second word line (WL2) on a cross-section cut in the third direction (DR3) perpendicular to the substrate 110. (210) and the second gate insulating layer (Gox2) may be located sequentially. In the embodiment shown in FIG. 3, unlike the embodiment shown in FIGS. 1 and 2, an insulating film (220 in FIGS. 1 and 2) is located between the first word line (WL1) and the second word line (WL2). You may not.

The channel film 210 may contact the bit line BL between the first word line WL1 and the second word line WL2. One side of the channel film 210 located between the first word line WL1 and the second word line WL2 may be in contact with the bit line BL.

According to one embodiment, the other side of the channel film 210 located between the first word line WL1 and the second word line WL2 may contact the data storage element DS. The other side of the channel film 210 located between the first word line WL1 and the second word line WL2 may contact the first electrode 310 of the data storage element DS.

According to one embodiment, the channel film 210 may be positioned between the bit line BL and the first electrode 310 on a cross-section cut in the second direction DR2 parallel to the substrate 110. According to the embodiment shown in FIG. 3, unlike the embodiment shown in FIGS. 1 and 2, an insulating film (220 in FIGS. 1 and 2) is not positioned between the bit line BL and the first electrode 310. It may not be possible.

In FIG. 3, the interface between the channel film 210 and the first electrode 310 is shown to be located on a straight line with the interface between the etch stop film 130 and the channel film 210 in the third direction DR3. However, it is not limited to this. The interface between the channel film 210 and the first electrode 310 may be further away from the bit line BL than the interface between the etch stop film 130 and the channel film 210.

The channel film 210 may extend in the third direction DR3 perpendicular to the substrate 110 along the side surfaces of the word lines WL. The channel film 210 may be positioned between the side surfaces of the word lines WL and the vertical portion of the first electrode 310 extending in the third direction DR3. The channel film 210 may extend along the side of the first word line WL1 in a direction closer to the substrate 110 . The channel film 210 may extend in a direction away from the substrate 110 along the side of the second word line WL2.

The channel film 210 may extend along the top or bottom surface of the second interlayer insulating film 150 in the second direction DR2 parallel to the substrate 110 . The channel film 210 may be positioned between the upper or lower surface of the second interlayer insulating film 150 and the horizontal portion of the first electrode 310 extending in the second direction DR2. The channel film 210 may extend in a direction away from the bit line BL along the upper surface of the second interlayer insulating film 150 located below the first word line WL1. The channel film 210 may extend in a direction away from the bit line BL along the lower surface of the second interlayer insulating film 150 located on the second word line WL2.

In the embodiment shown in FIG. 3 , like the embodiment shown in FIGS. 1 and 2 , the channel film 210 may include a two-dimensional material. In the embodiment shown in FIG. 3, the GIDL is reduced compared to the comparative example in which the channel film 210 includes polysilicon, so the operating characteristics of the semiconductor device can be improved. Additionally, the embodiment shown in FIG. 3 may have improved carrier mobility and operational reliability compared to the comparative example in which the channel film 210 includes IGZO.

Figure 4 is a cross-sectional view of a semiconductor device according to one embodiment. The semiconductor device according to the embodiment of FIG. 4 is different from the semiconductor device according to the embodiment of FIGS. 1 and 2 only in part in the structure of the channel film 210, but other components are the same. Accordingly, for convenience, the description will focus on the differences, and descriptions that overlap with those described above with reference to FIGS. 1 and 2 will be omitted or simplified.

Hereinafter, the channel film 210 included in one of the plurality of layers of the stacked structure SS will be described, focusing on the relationship between the channel film 210 and other components included in the same layer. do.

Referring to FIG. 4 , the channel film 210 may include a channel layer 212 including a two-dimensional material and a dipole layer 211 including a dipole material. In the embodiment shown in FIG. 4 , unlike the embodiment shown in FIGS. 1 and 2 , the channel film 210 may be formed as a multilayer film including a channel layer 212 and a dipole layer 211 . In FIG. 4 , the case where the channel film 210 is composed of two layers is shown, but the present invention is not limited to this, and a layer containing a two-dimensional material or a dipole material may be added in addition to the layers shown.

The two-dimensional material is, for example, at least one of molybdenum disulfide (MoS ₂ ), molybdenum diselenide (MoSe ₂ ), tungsten disulfide (WS ₂ ), tungsten diselenide (WSe ₂ ), or black phosphorus (BP). It may include, but is not limited to this.

Dipolar materials may include, but are not limited to, lithium fluoride (LiF), for example.

According to one embodiment, the channel layer 212 may be located on the dipole layer 211, but is not limited thereto. For example, the dipole layer 211 may be located on the channel layer 212.

The relationship with other components of the channel film 210 of the embodiment shown in FIG. 4 may be generally the same as the relationship with other components of the channel film 210 of the embodiment shown in FIGS. 1 and 2 .

According to one embodiment, the dipole layer 211 may be located between the channel layer 212 and the upper surface of the first word line (WL1). A dipole layer 211 may be located between the channel layer 212 and the lower surface of the second word line WL2. The dipole layer 211 may be separated from the first word line (WL1) by the first gate insulating layer (Gox1). The dipole layer 211 may be separated from the second word line (WL2) by the second gate insulating layer (Gox2).

According to one embodiment, the dipole layer 211 may be located between the channel layer 212 and the bit line BL. The dipole layer 211 may contact the bit line BL between the first word line WL1 and the second word line WL2. The portion of the dipole layer 211 covering the upper surface of the first gate insulating film Gox1 and the portion of the dipole layer 211 covering the lower surface of the second gate insulating film Gox2 are dipoles covering the side of the bit line BL. It may be connected by portions of layer 211.

According to one embodiment, the dipole layer 211 may conformally cover the upper surface of the first gate insulating film Gox1, the lower surface of the second gate insulating film Gox2, and the side surface of the bit line BL. The channel layer 212 may conformally cover the dipole layer 211.

According to one embodiment, a dipole layer ( An insulating film 220 may be positioned between portions of the channel layer 212 that cover portions of the channel layer 211).

According to one embodiment, a first gate insulating layer (Gox1) and a dipole layer are formed between the first word line (WL1) and the second word line (WL2) on a cross-section cut in the third direction (DR3) perpendicular to the substrate 110. (211), the channel layer 212, the insulating layer 220, the channel layer 212, the dipole layer 211, and the second gate insulating layer (Gox2) may be located sequentially.

According to one embodiment, a dipole layer 211, a channel layer 212, and an insulating layer are formed between the bit line BL and the first electrode 310 on a cross-section cut in the second direction DR2 parallel to the substrate 110. (220) may be located sequentially.

According to one embodiment, the dipole layer 211 covers the top surface of the first gate insulating layer Gox1 and the top surface of the etch stop layer 130 and may extend over the side of the etch stop layer 130. The dipole layer 211 covers the lower surface of the second gate insulating layer Gox2 and the upper surface of the etch stop layer 130 and may extend over the side of the etch stop layer 130. According to one embodiment, the dipole layer 211 may extend along the side of the etch stop layer 130 in the third direction DR3 perpendicular to the substrate 110.

According to one embodiment, the dipole layer 211 covers the side surface of the etch stop layer 130 and may extend over the upper surface of the second interlayer insulating layer 150 located below the first word line WL1. The dipole layer 211 is parallel to the substrate 110 along the upper surface of the second interlayer insulating film 150 located below the first word line WL1 and extends in a second direction DR2 away from the bit line BL. It may be extended.

According to one embodiment, the dipole layer 211 covers the side surface of the etch stop layer 130 and may extend over the lower surface of the second interlayer insulating layer 150 located on the second word line WL2. The dipole layer 211 is parallel to the substrate 110 along the lower surface of the second interlayer insulating film 150 located on the second word line WL2 and extends in the second direction DR2 away from the bit line BL. It can be.

As described above, the channel layer 212 may conformally cover the dipole layer 211. According to one embodiment, the channel layer 212 may be located between the dipole layer 211 and the first electrode 310. The channel layer 212 may contact the first electrode 310.

In the embodiment shown in FIG. 4 , unlike the embodiment shown in FIGS. 1 and 2 , the channel film 210 may further include a dipole material. As the channel film 210 further includes a dipole material, the threshold voltage can be lowered and power consumption can be reduced.

Figure 5 is a cross-sectional view of a semiconductor device according to one embodiment. The semiconductor device according to the embodiment of FIG. 5 is only partially different from the semiconductor device according to the embodiment of FIG. 4 only in the structure of the channel layer 210, and other components are the same. Accordingly, for convenience, the description will focus on the differences, and descriptions that overlap with those described above with reference to FIG. 4 will be omitted or simplified.

Hereinafter, the channel film 210 included in one of the plurality of layers of the stacked structure SS will be described, focusing on the relationship between the channel film 210 and other components included in the same layer. do.

Referring to FIG. 5 , the channel film 210 may fill the space between the first word line (WL1) and the second word line (WL2) adjacent to each other in the third direction (DR3). The first word line WL1 may be surrounded by a first gate insulating layer Gox1, and the second word line WL2 may be surrounded by a second gate insulating layer Gox2. The channel film 210 may fill the space between the upper surface of the first gate insulating film Gox1 and the lower surface of the second gate insulating film Gox2.

According to the embodiment shown in FIG. 5, like the embodiment shown in FIG. 4, the dipole layer 211 is formed on the upper surface of the first gate insulating film Gox1, the lower surface of the second gate insulating film Gox2, and the bit. The side of the line (BL) can be conformally covered. In the embodiment shown in FIG. 5, unlike the embodiment shown in FIG. 4, the channel layer 212 is covered with the dipole layer 211 and the remaining upper surface of the first gate insulating layer Gox1 and the second gate insulating layer Gox2. The space between the lower surfaces of can be filled.

According to one embodiment, a first gate insulating layer (Gox1) and a dipole layer are formed between the first word line (WL1) and the second word line (WL2) on a cross-section cut in the third direction (DR3) perpendicular to the substrate 110. (211), the channel layer 212, the dipole layer 211, and the second gate insulating layer (Gox2) may be located sequentially. In the embodiment shown in FIG. 5 , unlike the embodiment shown in FIG. 4 , the insulating film 220 in FIG. 4 may not be located between the first word line WL1 and the second word line WL2.

According to one embodiment, the dipole layer 211 and the channel layer 212 are sequentially formed between the bit line BL and the first electrode 310 on a cross-section cut in the second direction DR2 parallel to the substrate 110. can be located In the embodiment shown in FIG. 5 , unlike the embodiment shown in FIG. 4 , the insulating film 220 in FIG. 4 may not be located between the bit line BL and the first electrode 310 .

According to the embodiment shown in FIG. 5 , like the embodiment shown in FIG. 4 , the dipole layer 211 may conformally cover the etch stop layer 130 and the second interlayer insulating layer 150. The channel layer 212 may conformally cover a portion of the dipole layer 211 that covers the etch stop layer 130 and the second interlayer insulating layer 150. The channel layer 212 may be located between the dipole layer 211 and the first electrode 310. The channel layer 212 may be in contact with the first electrode 310.

In the embodiment shown in FIG. 5 , like the embodiment shown in FIG. 4 , the channel film 210 may include a two-dimensional material and a dipole material. In the embodiment shown in FIG. 5, as the channel film 210 includes a two-dimensional material, GIDL can be reduced, carrier mobility can be increased, and operational reliability can be improved. Additionally, as the channel film 210 further includes a dipole material, the threshold voltage can be lowered and power consumption can be reduced.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS. 6 to 14. 6 to 14 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment. 6 to 14 show a method of manufacturing a semiconductor device according to the embodiment of FIGS. 1 and 2.

Referring to FIG. 6 , a first interlayer insulating film 120 and a bit line BL extending in the third direction DR3 perpendicular to the substrate 110 may be provided on the substrate 110 . Although not shown, a plurality of bit lines BL may be arranged to be spaced apart in the first direction DR1.

The bit line BL may include a conductive material. The conductive material may be, for example, a doped semiconductor material such as doped silicon or doped germanium, a conductive metal nitride such as titanium nitride or tantalum nitride, a metal such as tungsten, titanium, or tantalum, or tungsten silicide, cobalt silicide, Alternatively, it may be any one of metal-semiconductor compounds such as titanium silicide.

Although not shown, the first interlayer insulating film 120 may extend in the first direction DR1 parallel to the substrate 110 . The first interlayer insulating film 120 may extend into the space between the bit lines BL arranged in the first direction DR1 to insulate the bit lines BL.

A second interlayer insulating film 150, a first sacrificial film 160, and a second sacrificial film 170 may be alternately stacked on one side of the bit line BL on the substrate 110. The second interlayer insulating film 150, the first sacrificial film 160, and the second sacrificial film 170 may be alternately stacked along the third direction DR3. The second interlayer insulating films 150 and the second sacrificial films 170 may contact the bit line BL. The first sacrificial layers 160 may be spaced apart from the bit line BL in the second direction DR2 parallel to the substrate 110 .

The first interlayer insulating film 120 and the second interlayer insulating film 150 each include, for example, at least one of a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, or a carbon-containing silicon oxynitride film. can do.

In some embodiments, the first sacrificial layer 160 may include silicon nitride, and the second sacrificial layer 170 may include polysilicon, but are not limited thereto.

The etch stop layer 130 may be positioned on the side of the first sacrificial layer 160 facing the bit line BL. The etch stop layer 130 may have a shape extending in the third direction DR3. For example, the etch stop layer 130 may include a material that has an etch selectivity with that of the first sacrificial layer 160 .

A gate insulating layer (Gox) may be provided in the space between the second interlayer insulating layer 150, the etch stop layer 130, and the second sacrificial layer 170. The gate insulating layer Gox may include at least one of a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. High dielectric films include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, It may include at least one of lead scandium tantalum oxide, or lead zinc niobate.

The first gate insulating film Gox1 is formed on the upper surface of the second interlayer insulating film 150, the lower surface of the second sacrificial film 170, and between the second interlayer insulating film 150 and the second sacrificial film 170. One side of the etch stop film 130 located at can be conformally covered. One side of the etch stop layer 130 may be a side facing the bit line BL.

The second gate insulating layer Gox2 is formed on the top surface of the second sacrificial layer 170, the top surface of the second interlayer insulating layer 150, and between the second sacrificial layer 170 and the second interlayer insulating layer 150. One side of the etch stop film 130 located at can be conformally covered. One side of the etch stop layer 130 may be a side facing the bit line BL.

Two word lines (WL) may be provided between the second interlayer insulating films 150. Although not shown, the word lines WL may extend along the first direction DR1. The word lines WL located between the second interlayer insulating films 150 may include a first word line WL1 and a second word line WL2. The first word line WL1 and the second word line WL2 may be spaced apart in the third direction DR3 by the second sacrificial layer 170 . The first word line WL1 may be closer to the substrate 110 than the second word line WL2.

Word lines (WL) may include conductive material. For example, the conductive material may be any of a semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound.

Each of the word lines (WL) may be surrounded by a gate insulating layer (Gox). The first word line WL1 may be surrounded by the first gate insulating layer Gox1. The second word line WL2 may be surrounded by the second gate insulating layer Gox2.

A spacer 140 including an insulating material may be provided between the first and second word lines WL1 and WL2 and the bit line BL. The spacer 140 may space the first word line WL1 and the second word line WL2 from the bit line BL in the second direction DR2. The first word line (WL1) and the second word line (WL2) may be insulated from the bit line (BL) by the spacer 140. The spacer 140 may be surrounded by a first gate insulating layer (Gox1) or a second gate insulating layer (Gox2).

Referring to FIG. 7 , first recesses R1 may be formed with the second interlayer insulating film 150 as the sidewall and the etch stop film 130 and the first sacrificial film pattern 160P as the bottom surface. .

For example, a trench penetrating the second interlayer insulating layer 150, the first sacrificial layer 160, and the second sacrificial layer 170 in the third direction DR3 is formed, and the first sacrificial layer is formed through the trench. (160) and the second sacrificial layer 170 may be selectively etched. The etching process may be performed until the etch stop layer 130 is exposed.

The second sacrificial layer 170 may be entirely removed through an etching process. The first sacrificial layer 160 may be partially removed through an etching process to form the first sacrificial layer pattern 160P. The side surface of the etch-stop film 130 may be exposed through an etching process.

The bottom surface of the first recess R1 may be defined as the side surface of the etch stop layer 130 and the side surface of the first sacrificial layer pattern 160P. One side wall of the first recess R1 may be defined as the upper surface of the second interlayer insulating film 150 that is relatively close to the substrate 110 among the second interlayer insulating films 150 adjacent in the third direction DR3. there is. The other side wall of the first recess (R1) will be defined as the lower surface of the second interlayer insulating film 150 that is relatively distant from the substrate 110 among the second interlayer insulating films 150 adjacent in the third direction DR3. You can.

Referring to FIG. 8 , second recesses R2 may be formed with the gate insulating layer Gox and the etch stop layer 130 as sidewalls and the bit line BL as the bottom surface.

For example, the first sacrificial layer pattern 160P may be selectively etched. The first sacrificial layer pattern 160P may be removed through an etching process. A side surface of the bit line BL may be exposed through an etching process.

The bottom surface of the second recess R2 may be defined as the side surface of the bit line BL. One side wall of the second recess R2 may be defined as the top surface of the first gate insulating film Gox1 and the top surface of the etch stop film 130 covering the side surface of the first gate insulating film Gox1. The other side wall of the second recess R2 may be defined as the lower surface of the second gate insulating film Gox2 and the lower surface of the etch stop film 130 covering the side surface of the second gate insulating film Gox2.

Referring to FIG. 9, a channel film material layer 210_L may be formed. For example, the channel film material layer 210_L may be formed by an atomic layer deposition process, but is not limited thereto.

According to one embodiment, the channel material layer 210_L may conformally cover the second interlayer insulating layer 150, the etch stop layer 130, the gate insulating layer (Gox), and the bit line (BL). The channel film material layer 210_L may cover the top, side, and bottom surfaces of the second interlayer insulating film 150 . The channel film material layer 210_L may cover the top, side, and bottom surfaces of the etch stop film 130 . The channel film material layer 210_L may cover the upper surface of the first gate insulating film Gox1. The channel film material layer 210_L may cover the lower surface of the second gate insulating film Gox2. The channel film material layer 210_L may cover the side surface of the bit line BL.

The channel film material layer 210_L covering the side surface of the bit line BL may extend over the top surface of the first gate insulating film Gox1. The channel film material layer 210_L covering the upper surface of the first gate insulating film Gox1 may extend over the upper surface of the etch stop film 130. The channel film material layer 210_L covering the upper surface of the etch stop film 130 may extend over the side surface of the etch stop film 130. The channel film material layer 210_L may extend along the side surface of the etch stop film 130 in the third direction DR3 closer to the substrate 110 . The channel film material layer 210_L covering the side surface of the etch stop film 130 may extend over the upper surface of the second interlayer insulating film 150. The channel film material layer 210_L may extend along the upper surface of the second interlayer insulating film 150 in the second direction DR2 away from the bit line BL.

The channel film material layer 210_L covering the side surface of the bit line BL may extend over the lower surface of the second gate insulating film Gox2. The channel film material layer 210_L covering the lower surface of the second gate insulating film Gox2 may extend over the lower surface of the etch stop film 130. The channel film material layer 210_L covering the lower surface of the etch stop film 130 may extend over the side surface of the etch stop film 130. It may extend along the side of the etch stop layer 130 in a third direction DR3 away from the substrate 110 . The channel film material layer 210_L covering the side surface of the etch stop film 130 may extend over the lower surface of the second interlayer insulating film 150. The channel film material layer 210_L may extend along the lower surface of the second interlayer insulating film 150 in the second direction DR2 away from the bit line BL.

According to one embodiment, the channel film material layer 210_L may include a two-dimensional material. The two-dimensional material is, for example, at least one of molybdenum disulfide (MoS ₂ ), molybdenum diselenide (MoSe ₂ ), tungsten disulfide (WS ₂ ), tungsten diselenide (WSe ₂ ), or black phosphorus (BP). It may include, but is not limited to this.

Referring to FIG. 10, between the portion of the channel film material layer 210_L covering the upper surface of the first gate insulating film Gox1 and the portion of the channel film material layer 210_L covering the lower surface of the second gate insulating film Gox2. An insulating film 220 may be formed.

For example, the insulating film 220 may be formed by a chemical vapor deposition (CVD), physical vapor deposition (PVD), or ALD process, but is not limited thereto.

The insulating film 220 may fill the space remaining after the channel film material layer 210_L is conformally formed in the second recess R2 of FIG. 8 . For example, the insulating film 220 may be formed to cover a portion of the channel film material layer 210_L that covers the side surface of the etch-stop film 130 in a deposition process, and then may be partially etched. A portion of the channel film material layer 210_L covering the side surface of the etch-stop film 130 may be exposed by partially etching the insulating film 220 .

As shown in FIG. 10, the exposed side of the insulating film 220 may be closer to the bit line BL than the exposed side of the channel film material layer 210_L covering the side of the etch stop film 130. It is not limited. As another example, the exposed side of the insulating film 220 may be positioned on a straight line with the exposed side of the channel film material layer 210_L covering the side of the etch stop film 130 in the third direction DR3.

Referring to FIG. 11 , a first electrode material layer 310_L and a dielectric material layer 320_L may be formed.

First, a first electrode material layer 310_L may be formed. For example, the first electrode material layer 310_L and the dielectric material layer 320_L may each be formed through an ALD process, but are not limited thereto.

According to one embodiment, the first electrode material layer 310_L may conformally cover the exposed surfaces of the channel film material layer 210_L and the insulating film 220.

According to one embodiment, the first electrode material layer 310_L has a portion extending in the third direction DR3 perpendicular to the substrate 110 and the substrate 110 along the profile of the channel film material layer 210_L. It may include a portion extending in a parallel second direction DR2.

The portion of the first electrode material layer 310_L extending in the third direction DR3 between adjacent second interlayer insulating layers 150 is a portion of the channel material layer 210_L covering the side surface of the etch stop layer 130. can cover them.

The portion of the first electrode material layer 310_L extending in the second direction DR2 may cover the portion of the channel film material layer 210_L that covers the upper or lower surface of the second interlayer insulating layer 150.

The first electrode material layer 310_L is, for example, a metal material such as titanium, tantalum, tungsten, copper, or aluminum, a conductive metal nitride such as titanium nitride or tantalum nitride, or a doped silicon or doped germanium. It may include at least one of doped semiconductor materials.

Subsequently, a dielectric material layer 320_L may be formed. For example, the dielectric material layer 320_L may be formed through an ALD process, but is not limited thereto.

According to one embodiment, the dielectric material layer 320_L may conformally cover the exposed surface of the first electrode material layer 310_L. According to one embodiment, the dielectric material layer 320_L may extend along the profile of the first electrode material layer 310_L.

The dielectric material layer 320_L may include a high dielectric constant material. For example, the dielectric material layer 320_L may be formed of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, It may include aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

Referring to FIG. 12 , after the dielectric material layer 320_L is formed and the remaining empty space is filled with a sacrificial layer material, a trench may be formed to separate the first electrodes 310. For example, the second interlayer insulating film 150, the channel film material layer 210_L, the first electrode material layer 310_L, the dielectric film material layer 320_L, and the sacrificial film material layer are placed in a third layer perpendicular to the substrate 110. A trench penetrating in the direction DR3 can be formed.

As the trench is formed, the channel film material layer 210_L, the first electrode material layer 310_L, the dielectric film material layer 320_L, and the sacrificial film material layer connected along the side of the second interlayer insulating film 150 are cut, respectively. You can. The layers may be divided by the second interlayer insulating film 150. A channel film 210, a first electrode 310, a dielectric film 320, and a sacrificial film pattern (SP) may be formed in each layer.

According to one embodiment, the first electrode 310 includes a vertical portion extending in a third direction DR3 perpendicular to the substrate 110 and a horizontal portion extending in a second direction DR2 parallel to the substrate 110. can do. The horizontal portion of the first electrode 310 may extend from the vertical portion of the first electrode 310 in the second direction DR2 away from the bit line BL. The first electrode 310 may include two horizontal portions spaced apart in the third direction DR3. The first electrode 310 extends in the second direction DR2 and may have the shape of a hollow cylinder.

According to one embodiment, the dielectric layer 320 may have a shape that covers the inner wall of the cylindrical first electrode 310. The sacrificial layer pattern SP may fill the inner space of the cylindrical first electrode 310 remaining after the dielectric layer 320 is formed. The sacrificial layer pattern SP may have a shape surrounded by the dielectric layer 320 .

Referring to FIG. 13, a portion of the channel film 210 and the first electrode 310 may be etched, and an insulator 340 may be formed on the etched portion.

For example, the channel film 210 and the first electrode 310 exposed by the trench formed in FIG. 12 may be selectively etched. By removing part of the channel film 210 and the first electrode 310, the second interlayer insulating film 150 and the dielectric film 320 are used as the sidewalls, and the channel film 210 and the first electrode 310 are used as the bottom surface. A recess may be formed. An insulator 340 may be formed within the recess.

The insulator 340 may include, for example, at least one of silicon nitride, silicon oxynitride, carbon-containing silicon oxide, carbon-containing silicon nitride, or carbon-containing silicon oxynitride.

Referring to FIG. 14 , the sacrificial layer pattern SP may be removed and the second electrode 330 may be formed. The sacrificial layer pattern (SP) may be removed by an etching process. After removing the sacrificial layer pattern (SP), the second electrode 330 may be deposited. The second electrode 330 may be formed by, for example, a PVD or CVD process, but is not limited thereto.

The second electrode 330 may be, for example, a metal material such as titanium, tantalum, tungsten, copper, or aluminum, a conductive metal nitride such as titanium nitride or tantalum nitride, or a doped material such as doped silicon or doped germanium. It may contain at least one semiconductor material.

The second electrode 330 may replace the sacrificial layer pattern SP and fill the internal space of the first electrode 310 having a cylindrical shape. According to one embodiment, the second electrode 330 may be inserted into the inner space of the cylindrical first electrode 310. The second electrode 330 may be surrounded by a dielectric layer 320. The portion of the second electrode 330 surrounded by the dielectric layer 320 may extend in the second direction DR2 parallel to the substrate 110.

A first electrode 310, a portion of the second electrode 330 inserted into the cylindrical first electrode 310, and a dielectric film disposed between the first electrode 310 and the second electrode 330 ( 320) may configure the data storage element (DS) of each layer.

According to one embodiment, the second electrode 330 covers the side of the dielectric film 320, the side of the insulator 340, and the side of the second interlayer insulating film 150, and is formed in a third direction perpendicular to the substrate 110 ( It can be extended to DR3). The data storage elements DS included in each of the plurality of layers stacked in the third direction DR3 may share one second electrode 330.

According to one embodiment, the second electrode 330 may be spaced apart from the channel film 210 and the first electrode 310 of each layer by the dielectric film 320 and the insulator 340. The dielectric layer 320 and the insulator 340 may insulate the second electrode 330 from the channel layer 210 and the first electrode 310 of each layer.

Meanwhile, the data storage element DS may be electrically connected to the channel film 210 as the first electrode 310 contacts the channel film 210.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS. 15 to 23. 15 to 23 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment. 15 to 23 show a method of manufacturing a semiconductor device according to the embodiment of FIG. 4.

Since the processes shown in FIGS. 15 to 17 are the same as the processes shown in FIGS. 6 to 8, duplicate descriptions will be omitted.

Referring to FIG. 18, a dipole material layer 211_L and a two-dimensional material layer 212_L may be formed.

According to one embodiment, after the dipole material layer 211_L is formed, the two-dimensional material layer 212_L may be formed, but the present invention is not limited thereto. In another embodiment, the dipole material layer 211_L may be formed after the two-dimensional material layer 212_L is formed.

According to one embodiment, a dipole material layer 211_L may be formed first. For example, the dipole material layer 211_L may be formed through an ALD process, but is not limited thereto.

According to one embodiment, the dipole material layer 211_L may conformally cover the second interlayer insulating layer 150, the etch stop layer 130, the gate insulating layer (Gox), and the bit line (BL). The dipole material layer 211_L may cover the top, side, and bottom surfaces of the second interlayer insulating film 150. The dipole material layer 211_L may cover the top, side, and bottom surfaces of the etch stop layer 130 . The dipole material layer 211_L may cover the upper surface of the first gate insulating layer Gox1. The dipole material layer 211_L may cover the lower surface of the second gate insulating layer Gox2. The dipole material layer 211_L may cover the side of the bit line BL.

The dipole material layer 211_L covering the side surface of the bit line BL may extend over the top surface of the first gate insulating layer Gox1. The dipole material layer 211_L covering the upper surface of the first gate insulating layer Gox1 may extend over the upper surface of the etch stop layer 130. The dipole material layer 211_L covering the upper surface of the etch stop layer 130 may extend over the side surface of the etch stop layer 130. The dipole material layer 211_L may extend along the side of the etch stop layer 130 in the third direction DR3 closer to the substrate 110 . The dipole material layer 211_L covering the side surface of the etch stop layer 130 may extend over the upper surface of the second interlayer insulating layer 150. The dipole material layer 211_L may extend along the upper surface of the second interlayer insulating film 150 in the second direction DR2 away from the bit line BL.

The dipole material layer 211_L covering the side surface of the bit line BL may extend over the lower surface of the second gate insulating layer Gox2. The dipole material layer 211_L covering the lower surface of the second gate insulating layer Gox2 may extend over the lower surface of the etch stop layer 130. The dipole material layer 211_L covering the lower surface of the etch stop layer 130 may extend over the side of the etch stop layer 130. It may extend along the side of the etch stop layer 130 in a third direction DR3 away from the substrate 110 . The dipole material layer 211_L covering the side surface of the etch stop layer 130 may extend over the lower surface of the second interlayer insulating layer 150. The dipole material layer 211_L may extend along the lower surface of the second interlayer insulating film 150 in the second direction DR2 away from the bit line BL.

According to one embodiment, the dipole material layer 211_L may include a dipole material. Dipolar materials may include, but are not limited to, lithium fluoride (LiF), for example.

Subsequently, a two-dimensional material layer 212_L may be formed on the dipole material layer 211_L. For example, the two-dimensional material layer 212_L may be formed by an ALD process, but is not limited thereto. The two-dimensional material layer 212_L may conformally cover the dipole material layer 211_L.

According to one embodiment, the two-dimensional material layer 212_L may include a two-dimensional material. The two-dimensional material is, for example, at least one of molybdenum disulfide (MoS ₂ ), molybdenum diselenide (MoSe ₂ ), tungsten disulfide (WS ₂ ), tungsten diselenide (WSe ₂ ), or black phosphorus (BP). It may include, but is not limited to this.

Referring to FIG. 19, a portion of the dipole material layer 211_L covering the upper surface of the first gate insulating layer Gox1, a portion of the two-dimensional material layer 212_L, and a dipole covering the lower surface of the second gate insulating layer Gox2. An insulating film 220 may be formed between a portion of the material layer 211_L and a portion of the two-dimensional material layer 212_L.

For example, the insulating film 220 may be formed by a CVD, PVD, or ALD process, but is not limited thereto.

The insulating film 220 may fill the space remaining after the dipole material layer 211_L and the two-dimensional material layer 212_L are conformally formed in the second recess R2 of FIG. 17 . For example, in the deposition process, the insulating film 220 is formed to cover a portion of the dipole material layer 211_L and a portion of the two-dimensional material layer 212_L that covers the side of the etch stop layer 130, and then is partially formed. Can be etched. By partially etching the insulating layer 220, a portion of the two-dimensional material layer 212_L covering the side surface of the etch-stop layer 130 may be exposed.

As shown in FIG. 19, the exposed side of the insulating film 220 may be closer to the bit line BL than the exposed side of the two-dimensional material layer 212_L covering the side of the etch stop film 130. It is not limited. As another example, the exposed side of the insulating film 220 may be positioned on a straight line with the exposed side of the two-dimensional material layer 212_L in the third direction DR3.

Referring to FIG. 20 , a first electrode material layer 310_L and a dielectric material layer 320_L may be formed.

First, a first electrode material layer 310_L may be formed. For example, the first electrode material layer 310_L and the dielectric material layer 320_L may each be formed through an ALD process, but are not limited thereto.

According to one embodiment, the first electrode material layer 310_L may conformally cover the exposed surfaces of the two-dimensional material layer 212_L and the insulating film 220.

According to one embodiment, the first electrode material layer 310_L has a portion extending in the third direction DR3 perpendicular to the substrate 110 and the substrate 110 along the profile of the two-dimensional material layer 212_L. It may include a portion extending in a parallel second direction DR2.

The portion of the first electrode material layer 310_L extending in the third direction DR3 between the adjacent second interlayer insulating layers 150 is the portion of the dipole material layer 211_L covering the side surface of the etch stop layer 130. and parts of the two-dimensional material layer 212_L.

The portion of the first electrode material layer 310_L extending in the second direction DR2 is the portion of the dipole material layer 211_L that covers the upper or lower surface of the second interlayer insulating film 150 and the two-dimensional material layer 212_L. ) can cover the part.

The first electrode material layer 310_L is, for example, a metal material such as titanium, tantalum, tungsten, copper, or aluminum, a conductive metal nitride such as titanium nitride or tantalum nitride, or a doped silicon or doped germanium. It may include at least one of doped semiconductor materials.

Subsequently, a dielectric material layer 320_L may be formed. For example, the dielectric material layer 320_L may be formed through an ALD process, but is not limited thereto.

According to one embodiment, the dielectric material layer 320_L may conformally cover the exposed surface of the first electrode material layer 310_L. According to one embodiment, the dielectric material layer 320_L may extend along the profile of the first electrode material layer 310_L.

The dielectric material layer 320_L may include a high dielectric constant material. For example, the dielectric material layer 320_L may be formed of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, It may include aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

Referring to FIG. 21 , after the dielectric material layer 320_L is formed and the remaining empty space is filled with a sacrificial material, a trench may be formed to separate the first electrodes 310. For example, the second interlayer insulating film 150, the dipole material layer 211_L, the two-dimensional material layer 212_L, the first electrode material layer 310_L, the dielectric material layer 320_L, and the sacrificial material layer are placed on the substrate ( A trench penetrating in the third direction DR3 perpendicular to 110) may be formed.

As the trench is formed, the dipole material layer 211_L, the two-dimensional material layer 212_L, the first electrode material layer 310_L, the dielectric material layer 320_L, and the sacrificial material layer are connected along the sides of the second interlayer insulating film 150. Each layer of membrane material may be cut. The layers may be divided by the second interlayer insulating film 150. A dipole layer 211, a channel layer 212, a first electrode 310, a dielectric layer 320, and a sacrificial layer pattern (SP) may be formed in each layer. The dipole layer 211 and the channel layer 212 may constitute the channel film 210 of each layer.

According to one embodiment, the first electrode 310 includes a vertical portion extending in a third direction DR3 perpendicular to the substrate 110 and a horizontal portion extending in a second direction DR2 parallel to the substrate 110. can do. The horizontal portion of the first electrode 310 may extend from the vertical portion of the first electrode 310 in the second direction DR2 away from the bit line BL. The first electrode 310 may include two horizontal portions spaced apart in the third direction DR3. The first electrode 310 extends in the second direction DR2 and may have the shape of a hollow cylinder.

According to one embodiment, the dielectric layer 320 may have a shape that covers the inner wall of the cylindrical first electrode 310. The sacrificial layer pattern SP may fill the inner space of the cylindrical first electrode 310 remaining after the dielectric layer 320 is formed. The sacrificial layer pattern SP may have a shape surrounded by the dielectric layer 320 .

Referring to FIG. 22, a portion of the channel film 210 and the first electrode 310 may be etched, and an insulator 340 may be formed on the etched portion.

For example, the channel film 210 and the first electrode 310 exposed by the trench formed in FIG. 21 may be selectively etched. By removing part of the channel film 210 and the first electrode 310, the second interlayer insulating film 150 and the dielectric film 320 are used as the sidewalls, and the channel film 210 and the first electrode 310 are used as the bottom surface. A recess may be formed. An insulator 340 may be formed within the recess.

The insulator 340 may include, for example, at least one of silicon nitride, silicon oxynitride, carbon-containing silicon oxide, carbon-containing silicon nitride, or carbon-containing silicon oxynitride.

Referring to FIG. 23 , the sacrificial layer pattern SP may be removed and the second electrode 330 may be formed. The sacrificial layer pattern (SP) may be removed by an etching process. After removing the sacrificial layer pattern (SP), the second electrode 330 may be deposited. The second electrode 330 may be formed by, for example, a PVD or CVD process, but is not limited thereto.

The second electrode 330 may be, for example, a metal material such as titanium, tantalum, tungsten, copper, or aluminum, a conductive metal nitride such as titanium nitride or tantalum nitride, or a doped material such as doped silicon or doped germanium. It may contain at least one semiconductor material.

The second electrode 330 may replace the sacrificial layer pattern SP and fill the internal space of the first electrode 310 having a cylindrical shape. According to one embodiment, the second electrode 330 may be inserted into the inner space of the cylindrical first electrode 310. The second electrode 330 may be surrounded by a dielectric layer 320. The portion of the second electrode 330 surrounded by the dielectric layer 320 may extend in the second direction DR2 parallel to the substrate 110.

A first electrode 310, a portion of the second electrode 330 inserted into the cylindrical first electrode 310, and a dielectric film disposed between the first electrode 310 and the second electrode 330 ( 320) may configure the data storage element (DS) of each layer.

According to one embodiment, the second electrode 330 covers the side of the dielectric film 320, the side of the insulator 340, and the side of the second interlayer insulating film 150, and is formed in a third direction perpendicular to the substrate 110 ( It can be extended to DR3). The data storage elements DS included in each of the plurality of layers stacked in the third direction DR3 may share one second electrode 330.

According to one embodiment, the second electrode 330 may be spaced apart from the channel film 210 and the first electrode 310 of each layer by the dielectric film 320 and the insulator 340. The dielectric layer 320 and the insulator 340 may insulate the second electrode 330 from the channel layer 210 and the first electrode 310 of each layer.

Meanwhile, the data storage element DS may be electrically connected to the channel film 210 as the first electrode 310 contacts the channel film 210.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims are also possible. It falls within the scope of rights.

110: substrate
130: Etch stop film
140: spacer
210: Channel membrane
220: insulating film
310: first electrode
320: dielectric film
330: second electrode
340: insulator
BL: bit line
DS: data storage element
Gox: Gate insulating film
WL: word line

Claims (10)

Board,
A laminated structure including a plurality of layers stacked in a direction perpendicular to the substrate, and
Includes a bit line extending in a direction perpendicular to the substrate on one side of the stacked structure,
Each of the plurality of layers,
Comprising a word line extending in a first direction parallel to the substrate, a channel film, and a data storage element electrically connected to the channel film,
The channel membrane is,
covering opposing surfaces of adjacent word lines in a direction perpendicular to the substrate and contacting the bit line between the adjacent word lines;
A semiconductor device extending along a side of the word line and a side extending in a second direction away from the bit line of the data storage element. According to paragraph 1,
The channel film includes a two-dimensional material,
The two-dimensional material is a semiconductor device containing at least one of molybdenum disulfide (MoS ₂ ), molybdenum diselenide (MoSe ₂ ), tungsten disulfide (WS ₂ ), tungsten diselenide (WSe ₂ ), or black phosphorus (BP). . According to paragraph 1,
The channel membrane is,
a channel layer comprising a two-dimensional material, and
comprising a dipole layer comprising a dipole material,
A semiconductor device wherein the channel layer is located on the dipole layer. According to paragraph 1,
A semiconductor device in which a first gate insulating layer, the channel layer, an insulating layer, the channel layer, and a second gate insulating layer are sequentially positioned between the adjacent word lines on a cross-section cut in a direction perpendicular to the substrate. According to paragraph 1,
A semiconductor device in which a first gate insulating layer, the channel layer, and a second gate insulating layer are sequentially positioned between the adjacent word lines on a cross-section cut in a direction perpendicular to the substrate. According to paragraph 1,
The data storage element is,
a first electrode including a vertical portion covering side surfaces of the adjacent word lines and extending in a direction perpendicular to the substrate, and a horizontal portion extending from the vertical portion in a direction parallel to the substrate and away from the bit line;
a second electrode inserted into the first electrode, and
A semiconductor device including a dielectric layer positioned between the first electrode and the second electrode. According to clause 6,
The plurality of layers includes a first layer and a second layer,
Each of the first layer and the second layer includes the adjacent word lines, the channel film, and the data storage element,
The first layer and the second layer are spaced apart by an interlayer insulating film,
The channel membrane is,
Located between the vertical portion of the first electrode and the side of the word line,
A semiconductor device positioned between the horizontal portion of the first electrode and the interlayer insulating film. Board,
A laminated structure including a plurality of layers stacked in a direction perpendicular to the substrate, and
Includes a bit line extending in a direction perpendicular to the substrate on one side of the stacked structure,
Each of the plurality of layers,
A first word line and a second word line extending in a first direction parallel to the substrate,
a first gate insulating film surrounding the first word line and a second gate insulating film surrounding the second word line;
a channel film located between the first word line and the second word line and in contact with the bit line, and
Includes a data storage element electrically connected to the channel film,
The channel film includes a two-dimensional material and conformally covers an upper surface of the first gate insulating film, a lower surface of the second gate insulating film, and a side surface of the bit line. According to clause 8,
A semiconductor device wherein an insulating film is further positioned between a first part of the channel film covering an upper surface of the first gate insulating film and a second part of the channel film covering a lower surface of the second gate insulating film. According to clause 9,
Each of the plurality of layers is spaced apart by an interlayer insulating film,
The first part is,
extending perpendicular to the substrate between a side of the first word line and the data storage element, and extending parallel to the substrate between the data storage element and an interlayer insulating film located below the first word line,
The second part is,
A semiconductor device extending perpendicularly to the substrate between a side of the second word line and the data storage element, and extending parallel to the substrate between the data storage element and an interlayer insulating layer located above the second word line.