RU2808029C1 - Semiconductor structure and method of its manufacture - Google Patents

Abstract

FIELD: microelectronics.

SUBSTANCE: according to the invention, a semiconductor structure and a method for its manufacture are proposed. The semiconductor structure includes a base and a storage unit located on the base. The storage unit includes: a first dielectric layer and a metal bit line located in the first dielectric layer; a semiconductor channel located on a partial surface of the metal bit line; a line of words located around a partial region of the semiconductor channel; a second dielectric layer located between the metal bit line and the word line, and also located on the word line side away from the base; a first lower electrode layer and a second lower electrode layer stacked on an upper surface of the semiconductor channel remotely from the metal bit line, the first lower electrode layer being in contact with the upper surface of the semiconductor channel; an upper electrode layer located on the upper surface of the second lower electrode layer and surrounding the first lower electrode layer and the second lower electrode layer; and a capacitor dielectric layer located between the upper electrode layer and the first lower electrode layer, and also located between the upper electrode layer and the second lower electrode layer.

EFFECT: invention provides an increase in the degree of integration of the semiconductor structure due to a semiconductor device in which the capacitance is increased and the dimensional accuracy of the capacitor is increased.

17 cl, 22 dwg

Description

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is based upon and claims the benefit of Chinese Patent Application No. 202110807121.7, entitled “SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THEREOF,” filed July 16, 2021, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to a semiconductor structure and a method for manufacturing it.

BACKGROUND OF THE ART

[0003] As the demand for semiconductor devices with high performance and low costs increases, the demand for semiconductor devices with high integration and high storage capacity increases.

[0004] However, as the degree of integration of the semiconductor device increases, when the capacitance of the capacitor in the semiconductor device increases, the aspect ratio of the capacitor also becomes increasingly higher. Limited by the processing equipment and the dimensions of the semiconductor device, a capacitor that is manufactured with a high aspect ratio suffers from insufficient dimensional accuracy, which consequently affects the electrical performance of the capacitor.

[0005] Thus, while the degree of integration of the semiconductor structure is increasing, it is necessary to develop a semiconductor device in which the capacitance is increased and the dimensional accuracy of the capacitor is improved.

DISCLOSURE OF THE INVENTION

[0006] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.

[0007] Embodiments of the present disclosure provide a semiconductor structure including a substrate and a storage unit located on the substrate. The storage unit includes: a first dielectric layer and a metal bit line disposed in the first dielectric layer, the first dielectric layer exposing a surface of the metal bit line; a semiconductor channel located on a partial surface of the metal bit line, the semiconductor channel facing the bottom surface of the metal bit line and electrically connected to the metal bit line; a word line, or word line, located around a partial region of the semiconductor channel; a second dielectric layer located between the metal bit line and the word line, and also located on the word line side away from the base; a first lower electrode layer and a second lower electrode layer stacked on an upper surface of the semiconductor channel remote from the metal bit line, the first lower electrode layer being in contact with the upper surface of the semiconductor channel; an upper electrode layer located on the upper surface of the second lower electrode layer and surrounding the first lower electrode layer and the second lower electrode layer; and a capacitor dielectric layer located between the upper electrode layer and the first lower electrode layer, and also located between the upper electrode layer and the second lower electrode layer.

[0008] Accordingly, embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, which includes the following steps. Provide the foundation. A storage block is formed on the basis, wherein the formation of the storage block includes the following operations. A first dielectric layer and a metal bit line located in the first dielectric layer are provided, with the first dielectric layer exposing the surface of the metal bit line. A semiconductor channel is formed located on a partial surface of the metal bit line, wherein the semiconductor channel is open on the side of the lower surface of the metal bit line and is electrically connected to the metal bit line. A word line is formed that is located around a partial region of the semiconductor channel. A second dielectric layer is formed, which is located between the metal line of bits and the line of words, and is also located on the side of the line of words at a distance from the base. A first lower electrode layer is formed, which is in contact with the upper surface of the semiconductor channel. A second lower electrode layer is formed, which is located on the upper surface of the first lower electrode layer. An upper electrode layer is formed, which is located on the upper surface of the second lower electrode layer, and the upper electrode layer is formed around the first lower electrode and the second lower electrode layer. A dielectric layer of the capacitor is formed, which is located between the upper electrode layer and the first lower electrode layer, and is also located between the upper electrode layer and the second lower electrode layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] One or more embodiments are described by way of example using diagrams in the corresponding accompanying drawings. Unless specifically stated otherwise, the diagrams in the accompanying drawings do not establish any restrictions on proportions.

[0010] In FIG. 1 is a schematic cross-sectional structural view corresponding to a semiconductor structure according to one embodiment of the present disclosure;

[0011] in FIG. 2 to 6 are schematic cross-sectional structural views of structures of five types jointly formed by a first lower electrode layer, a second lower electrode layer, and a capacitor dielectric layer in a semiconductor structure according to one embodiment of the present disclosure; And

[0012] in FIG. 7 to 22 are schematic cross-sectional views corresponding to operations in a method for manufacturing a semiconductor structure according to another embodiment of the present invention.

IMPLEMENTATION OF THE INVENTION

[0013] As can be seen from the prior art, as the degree of integration of a semiconductor device increases, it is necessary to improve both the capacitance and the dimensional accuracy of the capacitor in the semiconductor structure.

[0014] To solve the above problem, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same. In a semiconductor structure, the channel region of a semiconductor channel is located vertically on the surface of a metal bit line, so that the semiconductor structure may include a vertical Gate-All-Around (GAA) transistor. This helps to save space for arranging the semiconductor channel in a direction (usually in the horizontal direction) parallel to the surface of the metal bit line, and thus increases the degree of integration of the semiconductor structure in the horizontal direction. In addition, the structure of the lower electrode layer in the capacitor changes. Specifically, the first lower electrode layer and the second lower electrode layer are stacked on top of each other to form the lower electrode layer. This allows the overall height of the lower electrode layer of the capacitor to be increased to increase the aspect ratio of the capacitor, thereby increasing the opposing area between the upper electrode layer and the lower electrode layer in the capacitor so that the capacitance of the capacitor is increased. In addition, the orthogonal projection of the lower surface of the second lower electrode layer on the base is located in the orthogonal projection of the upper surface of the first lower electrode layer on the base, which allows the second lower electrode layer to be aligned with the first lower electrode layer, i.e. ensure complete contact between the lower surface of the second lower electrode layer and the upper surface of the first lower electrode layer, and thus avoid inaccurate registration between the lower surface of the second lower electrode layer and the upper surface of the first lower electrode layer, thereby improving both capacity and accuracy size of the capacitor, and the quality of manufacture of the capacitor is improved, as a result of which the capacitor is guaranteed to have acceptable electrical characteristics. In addition, the dielectric layer of the capacitor also covers the upper surface of the first lower electrode layer exposed by the second lower electrode layer to prevent the upper electrode layer from contacting the first lower electrode layer through the upper surface of the first lower electrode layer exposed by the second lower electrode layer, thereby further ensuring acceptable electrical characteristics of the capacitor.

[0015] To more precisely describe the objectives, technical solutions and advantages of embodiments of the present disclosure, embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. However, it will be apparent to one skilled in the art that many technical details are provided to the reader to better understand the disclosure in embodiments of the present invention. However, even in the absence of these technical details, as well as various changes and modifications, the technical solutions claimed in the disclosure can be implemented based on the following embodiments.

[0016] In one embodiment of the present disclosure, a semiconductor structure is provided. The semiconductor structure proposed in the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings. In fig. 1 is a schematic cross-sectional structural view corresponding to a semiconductor structure according to one embodiment of the present disclosure. In fig. 2-6 are schematic cross-sectional structural views of five types of structures jointly formed by a first lower electrode layer, a second lower electrode layer, and a capacitor dielectric layer in a semiconductor structure according to one embodiment of the present disclosure.

[0017] With reference to FIG. 1-6, the semiconductor structure includes a base 110 and a storage unit 100 located on the base 110. The storage unit 100 includes: a first dielectric layer 103 and a metal bit line 101 located in the first dielectric layer 103, wherein the first dielectric layer 103 opens metal line surface 101 bits; a semiconductor channel 102 located on a partial surface of the metal bit line 101, the semiconductor channel 102 facing the bottom surface of the metal bit line 101 and electrically connected to the metal bit line 101; a word line 104 located around a partial region of the semiconductor channel 102; a second dielectric layer 105 located between the metal bit line 101 and the word line 104, and also located on the side of the word line 104 away from the base 110; a first lower electrode layer 116 and a second lower electrode layer 126 stacked on an upper surface of the semiconductor channel 102 away from the metal bit line 101, the first lower electrode layer 116 contacting the upper surface of the semiconductor channel 102; an upper electrode layer 146 located on the upper surface of the second lower electrode layer 126 and surrounding the first lower electrode layer 116 and the second lower electrode layer 126; and a dielectric capacitor layer 136 located between the upper electrode layer 146 and the first lower electrode layer 116, and also located between the upper electrode layer 146 and the second lower electrode layer 126.

[0018] Specifically, the orthogonal projection of the bottom surface of the second bottom electrode layer 126 onto the substrate 110 is located in the orthogonal projection of the top surface of the first bottom electrode layer 116 onto the substrate 110. The dielectric capacitor layer 136 covers the top surface and sides of the second bottom electrode layer 126, as well as covers the sides of the first lower electrode layer 116 and the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126.

[0019] In the direction from the substrate 110 to the metal bit line 101, the semiconductor channel 102 includes a first doped region I, a channel region II, and a second doped region III, which are arranged in series. The first doped region I is electrically connected to the metal bit line 101. The 104 word line is located around channel area II. The first lower electrode layer 116 is in contact with a side of the second doped region III located away from the channel region II.

[0020] Since the semiconductor structure includes a vertical circular gate transistor and the metal bit line 101 is located between the base 110 and the circular gate transistor, a three-dimensional (3D) layered storage device can be formed. This makes it possible to increase the degree of integration of the semiconductor structure. In addition, the capacitor in the semiconductor structure is jointly formed by the first lower electrode layer 116, the second lower electrode layer 126, the dielectric capacitor layer 136, and the upper electrode layer 146. In other words, the lower electrode layer of the capacitor is formed by layering the first lower electrode layer 116 and the second lower electrode layer 126. On the one hand, in the direction perpendicular to the surface of the base 110, to produce a lower electrode layer with a relatively large height, the first lower electrode layer 116 and the second lower electrode layer 126 with a relatively small height can be formed by performing separate operations. Since the first lower electrode layer 116 and the second lower electrode layer 126 have a relatively small height, it is possible to prevent the first lower electrode layer 116 and the second lower electrode layer 126 from tilting or shrinking, thereby improving the overall stability of the lower electrode layer, and a capacitor can be formed with large aspect ratio and large capacity. On the other hand, the orthogonal projection of the bottom surface of the second lower electrode layer 126 on the base 110 is located in the orthogonal projection of the top surface of the first lower electrode layer 116 on the base 110 so as to enable the second lower electrode layer 126 to be aligned with the first lower electrode layer 116, i.e. .e. avoiding misalignment between the lower surface of the second lower electrode layer 126 and the upper surface of the first lower electrode layer 116, thereby improving both the capacitance and the dimensional accuracy of the capacitor, so that the manufacturing quality of the capacitor is improved, resulting in the capacitor being guaranteed to have acceptable electrical characteristics.

[0021] The semiconductor structure is described below in more detail with reference to FIG. 1.

[0022] In this embodiment, the substrate 110 may be a logic circuit structure layer and a plurality of logic circuits are arranged thereon.

[0023] The first dielectric layer 103 may include: an intermediate dielectric layer 120 that is located on a surface of the substrate 110, and a metal bit line 101 is located on a partial surface of the intermediate dielectric layer 120 remote from the substrate 110; and an insulating layer 130, which is located on the surface of the intermediate dielectric layer 120, exposed by the metal bit line 101, and covers the side walls of the metal bit line 101.

[0024] In particular, the logic circuit structure layer may be a multi-layer structure. On a partial surface of the intermediate dielectric layer 120 located away from the logic circuit structure layer, a plurality of metal bit lines 101 spaced apart from each other may be provided. Each metal bit line 101 may be in contact with and electrically connected to at least one first doped region I. As shown as an example in FIG. 1, each metal bit line 101 is in contact with two first alloyed regions I. The number of first alloyed areas I contacting and electrically connected with each metal bit line 101 can be suitably set according to the actual electrical requirement. The top surfaces of the metal bit lines 101 may be positioned flush with the top surface of the insulating layer 130. This allows for sufficient support to be provided for other structures located on the top surfaces of the metal bit lines 101 and the top surface of the insulating layer 130.

[0025] The intermediate dielectric layer 120 is used to provide insulation between the logic circuit structure layer and the metal bit lines 101. The intermediate dielectric layer 120 prevents electrical leakage between any two adjacent metal bit lines 101. The material of the intermediate dielectric layer 120 includes at least one of silicon oxide, silicon nitride, silicon carbon nitride, or silicon carbon oxynitride.

[0026] An insulating layer 130 is located between two adjacent metal bit lines 101 and is used to provide insulation between adjacent metal bit lines 101. The material of the insulating layer 130 includes at least one of silicon oxide, silicon nitride, silicon carbon nitride, or silicon carbon oxynitride.

[0027] In this embodiment, the intermediate dielectric layer 120 and the insulating layer 130 are integral structures, thereby reducing defects in the interface state between the intermediate dielectric layer 120 and the insulating layer 130, and improving the performance of the semiconductor structure. In addition, the material of the intermediate dielectric layer 120 is the same as the material of the insulating layer 130, which can reduce the manufacturing processes of the semiconductor structure, as well as reduce the cost and complexity of manufacturing the semiconductor structure. In other embodiments, the intermediate dielectric layer and the insulating layer may be layered structures. The material of the intermediate dielectric layer may differ from the material of the insulating layer.

[0028] The material of the metal bit lines 101 is metal. The advantages of this arrangement are as follows. On the one hand, the metal bit line 101 made of metal material generally has a relatively small resistivity, thereby reducing the resistance of the metal bit line 101 and thus increasing the transmission speed of electrical signals in the metal bit line 101, reducing the parasitic capacitance of the metal 101-bit lines, and also reduces thermal losses and reduces power consumption. On the other hand, the semiconductor structure may also include a circuit structure that is provided with a metal conductive layer used for electrical connections, for example, a so-called M0 layer, M1 layer, M2 layer or the like, known to those skilled in the art. Metal conductive layer processes can be used to produce metal bit lines 101 at the same time as forming the metal conductive layer. In this way, it is possible to shorten the manufacturing steps of the semiconductor structure and reduce the cost of the semiconductor structure.

[0029] The material of the metal bit lines 101 may be a metal, a metal-containing compound, or an alloy. The metal may be copper, aluminum, tungsten, gold, silver or the like. The metal-containing compound may be tantalum nitride or titanium nitride. An alloy may be an alloy material formed by at least two metals of copper, aluminum, tungsten, gold or silver. In addition, the material of the metal bit lines 101 may also be at least one of nickel, cobalt, or platinum.

[0030] In some embodiments, the material of the metal bit lines 101 is copper.

[0031] The semiconductor structure may include a plurality of metal bit lines 101 spaced apart from each other. Each metal line 101 bits runs in the first direction. Each metal bit line 101 may be electrically coupled to at least two semiconductor channels 102.

[0032] The semiconductor channel material 102 includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Tungsten Oxide (IWO), or Indium Tin Oxide (ITO) ). When the semiconductor channels 102 are formed by the above materials, it is possible to increase the mobility of carriers in the semiconductor channels 102 and thus provide more efficient electrical signal transmission in the semiconductor channels 102.

[0033] In one example, the material of the semiconductor channels 102 is indium gallium zinc oxide. The carrier mobility of indium gallium zinc oxide is 20 to 50 times greater than that of polycrystalline silicon, which allows for increased carrier mobility in channel regions II in semiconductor channels 102 and thus provides a reduction in leakage current during operation of the semiconductor structure in this manner. , to reduce the power consumption of the semiconductor structure and improve the operating efficiency of the semiconductor structure. In addition, the storage time in the storage unit of the circular gate transistor formed by the indium gallium zinc oxide semiconductor channels 102 may exceed 400 seconds. This allows you to reduce the refresh rate and power consumption of the storage device.

[0034] In this embodiment, each of the semiconductor channels 102 has a cylindrical structure, in which the side of the semiconductor channel 102 is a smooth transition surface, which can prevent the phenomenon of point discharge or electrical leakage in the semiconductor channel 102 and thus further improve the electrical performance semiconductor structure. It should be noted that in other embodiments, the semiconductor channel may have an elliptical columnar structure, a parallelepiped columnar structure, or other irregular structures. It should be understood that when the semiconductor channel structure is a parallelepiped columnar structure, the corners formed by adjacent surfaces of the side walls of the parallelepiped columnar structure can be rounded corners, which avoids the problem of point discharge. The parallelepiped columnar structure may be a cubic columnar structure or a rectangular parallelepiped columnar structure.

[0035] The first doped region I forms one of the source or drain of the transistor device, and the second doped region III forms the other of the source or drain of the transistor device. The first doped region I, the channel region II and the second doped region III have the same semiconductor element. In other words, the first doped region I, the channel region II, and the second doped region III are an integral structure. This makes it possible to reduce the interface state defect between the first doped region I and the channel region II and to reduce the interface state defect between the channel region II and the second doped region III, and thus improve the performance of the semiconductor structure. It should be understood that in other embodiments, the semiconductor channel may be a three-layer structure, and the three layers are respectively used as the first doped region, the channel region, and the third doped region.

[0036] The first doped region I may include a first metal semiconductor layer 112. The first metal semiconductor layer 112 is in contact with the metal bit line 101, and the resistivity of the first metal semiconductor layer 112 is less than the resistivity of the first doped region I different from the first metal semiconductor layer 112. Thus, the resistivity of the first doped region I can be reduced, and the first metal semiconductor layer 112 and the first doped region I other than the first metal semiconductor layer 112 form an ohmic contact, thereby preventing direct contact of the metal lines 101 bits with semiconductor material and thus avoid forming contact with the Schottky barrier. The ohmic contact makes it possible to reduce the contact resistance between the first doped region I and the metal bit line 101 such that the power consumption of the semiconductor structure during operation is reduced and the RC delay effect is reduced, and thus the electrical performance of the semiconductor structure is improved. It should be understood that in other embodiments, the semiconductor material of the first doped region may be in direct contact with the metal bit line. In other words, the first doped region does not include the first metallic semiconductor layer.

[0037] In particular, the metal element in the first metal semiconductor layer 112 includes at least one of cobalt, nickel or platinum. For example, the material of the semiconductor channel 102 is indium gallium zinc oxide. Accordingly, the material of the first metal semiconductor layer 112 may be nickel-containing indium gallium zinc oxide, cobalt containing indium gallium zinc oxide, cobalt and nickel containing indium gallium zinc oxide, platinum containing indium gallium zinc oxide, or the like. In addition, the first metal semiconductor layer 112 may be further doped with nitrogen.

[0038] The semiconductor element in the first metal semiconductor layer 112 is the same as the semiconductor element in the first doped region I, different from the first metal semiconductor layer 112. In other words, the first doped region I is generally a solid structure. Thus, the first metal semiconductor layer 112 is part of the first doped region I, which makes it possible to reduce the interface state defect between the first metal semiconductor layer 112 and the first doped region I other than the first metal semiconductor layer 112, and thus improve the performance of the semiconductor layer 112. structures. It should be noted that in other embodiments, the semiconductor element in the first metal semiconductor layer may be different from the semiconductor element in the first doped region different from the first metal semiconductor layer. For example, the semiconductor element in the first metal semiconductor layer may be silicon or germanium. Accordingly, the first doped region I is a two-layer structure including a first metal semiconductor layer.

[0039] In some embodiments, semiconductor channel 102 is in contact with metal bit line 101. In other words, the first doped region I is located on the surface of the metal bit line 101. In addition, the semiconductor structure may further include a metal layer 108 that is located on the surface of the metal bit line 101 not covered by the semiconductor channel 102. The metal layer 108 is formed by a metal element in the first metal semiconductor layer 112. It should be understood that the metal layer 108 is formed simultaneously in the step of forming the first metal semiconductor layer 112, and the material of the metal layer 108 may be at least one of cobalt, nickel or platinum.

[0040] Additionally, in some other embodiments, the material of the metal bit line 101 is at least one of nickel, cobalt, or platinum. Accordingly, in semiconductor structure fabrication processes, a partial region of the metal bit line 101 in contact with the first doped region I reacts with the first doped region I to form the first metal semiconductor layer 112. Thus, the metal bit line 101 and the first metal semiconductor layer 112 are an integral structure that can further reduce the resistance in contact between the metal bit line 101 and the first metal semiconductor layer 112. In other words, the metal bit line 101 can provide a metal element for forming the first metal semiconductor layer 112.

[0041] The second doped region III may include a second metal semiconductor layer 122 that is in contact with the first lower electrode layer 116, and the material resistivity of the second metal semiconductor layer 122 is less than the resistivity of the second doped region III different from the second metal semiconductor layer 122. Thus, this makes it possible to reduce the resistivity of the second doped region III. An ohmic contact is formed between the second metal semiconductor layer 122 and the capacitor structure, which makes it possible to reduce the contact resistance between the second doped region III and the capacitor structure so as to reduce the power consumption of the semiconductor structure during operation, and thus improve the performance of the semiconductor structure.

[0042] The metal element in the second metal semiconductor layer 122 includes at least one of cobalt, nickel, or platinum. In this embodiment, the metal element in the first metal semiconductor layer 112 may be the same as the metal element in the second metal semiconductor layer 122. In other embodiments, the metal element in the first metal semiconductor layer may be different from the metal element in the second metal semiconductor layer.

[0043] In addition, the semiconductor element in the second metal semiconductor layer 122 is the same as the semiconductor element in the second doped region III different from the second metal semiconductor layer 122. In other words, the second doped region III is a whole structure. The second metal semiconductor layer 122 is part of the second doped region III. This makes it possible to reduce defects in the interface state between the second metal semiconductor layer 122 and the second doped region III other than the second metal semiconductor layer 122, and thus improve the performance of the semiconductor structure. It should be noted that in other embodiments, the semiconductor element in the second metal semiconductor layer may be different from the semiconductor element in a second doped region different from the second metal semiconductor layer. For example, the semiconductor element in the second metallic semiconductor layer may be silicon or germanium. Accordingly, the second doped region I is a two-layer structure including a second metal semiconductor layer.

[0044] In the case where the semiconductor element is silicon as an example, the second metal semiconductor layer 122 includes at least one of cobalt silicide, nickel silicide or platinum silicide. In addition, the second metal semiconductor layer 122 may be further doped with nitrogen.

[0045] In the direction in which the metal bit lines 101 extend, when the semiconductor channel 102 is used to form a junctionless transistor channel, the width of the semiconductor channel 102 is within the nanoscale range, which facilitates the formation of a nanoscale junctionless transistor channel. In other words, the first doped region I, the channel region II, and the second doped region III have the same type of doped ions. For example, all doped ions are N-type ions or P-type ions. In addition, the first doped region I, the channel region II, and the second doped region III may have the same doped ions. The term "junctionless" as used herein refers to the absence of a PN junction. In other words, there is no PN junction in the transistor formed by the semiconductor channel 102. The benefits of this are as follows. In one aspect, the first doped region I and the second doped region III do not need to be further doped, which avoids the problem that it is difficult to control the doping process of the first doped region I and the second doped region III. In particular, as the size of the transistor is further reduced by further doping the first doped region I and the second doped region III, it is more difficult to control the doping concentration. In yet another aspect, since the device is a junctionless transistor, there is no need to fabricate the hyperabrupt PN junction in the nanoscale range, thereby avoiding the use of a concentration gradient doping process of the hyperabrupt drain-source junction. In this way, problems such as threshold voltage drift, increase in leakage current, etc. caused by sudden doping changes can be avoided. This also allows the short channel effect to be inhibited and the device can still operate at the nanometer scale. This is preferable for increasing the degree of integration and improving the electrical characteristics of the semiconductor structure. It should be understood that the additional doping herein refers to performing the doping in such a way that the doped ions in the first doped region I and the second doped region III can be doped of a different type from the type of doped ions in the channel region.

[0046] In addition, the doped ion concentration in the first doped region I and the doped ion concentration in the second doped region III may be greater than the doped ion doping concentration in the channel region II. Doped ions are N-type ions or P-type ions. In particular, the N-type ions are arsenic ions, phosphorus ions or antimony ions of at least one type. The P-type ions are boron ions, indium ions or gallium ions of at least one type.

[0047] The word line 104 includes a gate dielectric layer 114 that may surround the entire surface of the side wall of the semiconductor channel 102. Thus, it is possible to prevent electrical leakage in the semiconductor channel 102, and thus improve the electrical performance of the circular gate transistor .

[0048] In other embodiments, the gate dielectric layer may cover only a portion of the channel side wall surface of the channel region, or the gate dielectric layer covers a portion of the side wall surface of the channel region semiconductor channels and the first doped region, or the gate dielectric layer covers a portion of the side wall surface of the channel region semiconductor. a channel region and a second doped region, in which the gate dielectric layer is disposed around the second doped regions. In other words, when a second doped region is located on a portion of the side wall surface of the semiconductor channel, the gate dielectric layer can protect the surface of the second doped region, thereby avoiding process damage to the surface of the second doped region during the manufacturing process. This makes it possible to further improve the electrical characteristics of the semiconductor structure.

[0049] In addition, the word line 104 includes a gate conductive layer 124. The gate conductive layer 124 is located around a partial region of the semiconductor channel 102. The gate dielectric layer 114 is located between the semiconductor channel 102 and the gate conductive layer 124.

[0050] Specifically, the gate conductive layer 124 is arranged around the channel region II and is located on the side wall surface of the gate dielectric layer 114 corresponding to the channel region II.

[0051] The material of the gate dielectric layer 114 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride. The material of the gate conductive layer 124 includes at least one of polycrystalline silicon, titanium nitride, tantalum nitride, copper, tungsten, or aluminum.

[0052] In this embodiment, the semiconductor structure may include a plurality of word lines 104 spaced. Each line of 104 words runs in the second direction. The second direction is different from the first direction. For example, the first direction may be perpendicular to the second direction. In addition, each of the word lines 104 may be located around the channel region II of at least one semiconductor channel 102. As shown as an example in FIG. 1, each word line 104 surrounds two semiconductor channels 102. The number of semiconductor channels 102 surrounded by each word line 104 can be suitably set according to the actual electrical requirement.

[0053] The second dielectric layer 105 is used to isolate metal layers 108 from word lines 104, to isolate metal bit lines 101 from word lines 104, and to isolate adjacent word lines 104 and adjacent metal layers 108. In other words, the second dielectric layer 105 located between the metal layers 108 and the word lines 104, and also located in the spaces between adjacent word lines 104 and in the spaces between adjacent metal layers 108.

[0054] The second dielectric layer 105 may include a third dielectric layer 115 and a fourth dielectric layer 125. The third dielectric layer 115 is located between the metal layers 108 and the word lines 104, and at intervals between adjacent metal layers 108 to provide insulation between the metal layers 108 and word lines 104, and thus prevent electrical interference from occurring between the metal layers 108 and the word lines 104, and also preventing electrical noise from occurring between the metal bit lines 101 and the word lines 104. A fourth dielectric layer 125 is located between adjacent word lines 104 and is in contact with a third dielectric layer 115, which is used to provide insulation between adjacent word lines 104, thereby preventing electrical noise from occurring between adjacent word lines 104. A fourth dielectric layer 125 is also located on the surfaces of the word lines 104 remote from the substrate 110 and is used to support other conductive structures located on the surface of the fourth dielectric layer 125 remote from the substrate 110 to provide insulation between the word lines 104 and the other conductive structures.

[0055] The top surface of the fourth dielectric layer 125 may be positioned flush with the top surfaces of the second doped regions III. This allows for sufficient support to be provided for other structures located on the top surface of the fourth dielectric layer 125 and on the top surfaces of the second doped regions III.

[0056] In this embodiment, the material of the third dielectric layer 115 and the material of the fourth dielectric layer 125 are the same, and may be at least one of silicon oxide, silicon nitride, silicon carbon oxynitride, or silicon oxynitride. In other embodiments, the material of the third dielectric layer and the material of the fourth dielectric layer may be different.

[0057] It should be understood that in other embodiments, the second dielectric layer may be other layered film layer structures. The specific design of the layered structure of the film layer is related to aspects of the manufacturing process, as long as the second dielectric layer can provide insulation.

[0058] The capacitor includes a first lower electrode layer 116, a second lower electrode layer 126, a dielectric capacitor layer 136, and an upper electrode layer 146. The capacitor is described in detail below with reference to FIG. 1-6.

[0059] In this embodiment, the first lower electrode layer 116 and the second lower electrode layer 126 form the lower electrode layer of the capacitor. Each line of 104 words runs in the second direction. As shown as an example in FIG. 1, each word line 104 surrounds two semiconductor channels 102, and the first lower electrode layer 116 and the second lower electrode layer 126 also extend in the second direction. Specifically, each bottom electrode layer corresponds to one line of 104 words. In other words, each lower electrode layer is in contact with a side located away from the channel region II of the second doped region III surrounded by a word line 104 corresponding to the lower electrode layer. As shown as an example in FIG. 1, the lower electrode layers are respectively in contact with the upper surfaces of the second doped regions III of the two semiconductor channels 102.

[0060] In some examples, in a direction perpendicular to the surface of the substrate 110, the thickness of the first lower electrode layers 116 may be greater than the thickness of the second lower electrode layers 126. In some other examples, in a direction perpendicular to the surface of the substrate 110, the thickness of the first lower electrode layers 116 may be less. or equal to the thickness of the second lower electrode layers 126. In addition, the material of the first lower electrode layers 116 may be the same as the material of the second lower electrode layers 126. Moreover, since the first lower electrode layers 116 and the second lower electrode layers 126 are manufactured during individual steps, the material of the first lower electrode layers 116 may be different from the material of the second lower electrode layers 126.

[0061] In addition, the upper electrode layers 146 also extend in the second direction. The upper electrode layers 146 correspond one-to-one to the lower electrode layers. The orthogonal projection of each upper electrode layer 146 onto the base 110 covers the orthogonal projection of each lower electrode layer onto the base 110. The orthogonal projection of each lower electrode layer onto the base 110 is located on the orthogonal projection of each word line 104 onto the base 110.

[0062] In other embodiments, each bottom electrode layer may be in contact with a side away from the channel regions of only one second doped region, and each top electrode layer may correspond one-to-one to each bottom electrode layer, or one top electrode layer corresponds to multiple lower electrode layers. Or, one bottom electrode layer may be in contact with sides remote from the channel regions of the plurality of second doped regions, and each top electrode layer may correspond to only one semiconductor channel. In other words, one lower electrode layer corresponds to a plurality of upper electrode layers. Thus, in adjacent capacitors, the upper electrode layers may be connected to different electrical potentials or the lower electrode layers may be connected to different electrical potentials. This allows for diversified control of adjacent capacitors.

[0063] The lower electrode layer is formed by layering the first lower electrode layer 116 and the second lower electrode layer 126, thereby increasing the overall height of the lower electrode layer. Thus, when increasing the capacitance of the capacitor, the first lower electrode layer 116 and the second lower electrode layer 126 with a relatively small height can be formed in separate steps to prevent the first lower electrode layer 116 and the second lower electrode layer 126 from tilting or shrinking, thereby increasing general stability of the lower electrode layer. The orthogonal projection of the bottom surface of the second bottom electrode layer 126 on the base 110 is located in the orthogonal projection of the top surface of the first bottom electrode layer 116 on the base 110 so as to provide complete contact between the bottom surface of the second bottom electrode layer 126 and the top surface of the first bottom electrode layer 116, and thus avoid misregistration between the lower surface of the second lower electrode layer 126 and the upper surface of the first lower electrode layer 116 so as to improve the dimensional accuracy of the capacitor.

[0064] In some examples, in the direction in which the metal bit line 101 extends, the width of the bottom surface of the first bottom electrode layer 116 is less than the maximum width of the semiconductor channel 102. In other embodiments, the width of the bottom surface of the first bottom electrode layer may exceed the maximum width of the semiconductor channel or may be equal to it.

[0065] With reference to FIG. 1-4, the first lower electrode layer 116 includes a first lower conductive post 113 and a first lower conductive block 123. The first lower conductive post 113 is in contact with the second doped region III. One end of the first lower conductive block 123 is in contact with the first lower conductive post 113, and the other end is in contact with the second lower electrode layer 126. The second lower electrode layer 126 includes a second lower conductive post 133 and a second lower conductive block 143. The second lower conductive post 133 is in contact with the first lower conductive block 123. One end of the second lower conductive block 143 is in contact with the second lower conductive post 133, and the other end is in contact with the dielectric layer 136 of the capacitor. In some examples, the first lower conductive column 113 covers the entire upper surface of the second doped region III. In addition, in the direction from the base 110, the cross-sectional area of the first lower conductive post 113 in the direction parallel to the surface of the base 110 gradually increases, and the orthogonal projection of the upper surface of the first lower conductive post 113 onto the base 110 coincides with the orthogonal projection of the lower surface of the first lower conductive block 123 onto the base 110 such that the largest contact area is provided between the second doped region III and the first lower electrode layer 116, and the volume of the first lower electrode layer 116 is increased such that the resistance of the first lower electrode layer 116 is reduced, thereby facilitating reducing the resistance in contact between the second doped region III and the first lower electrode layer 116.

[0066] In the direction from the base 110, the cross-sectional area of the second lower conductive post 133 in the direction parallel to the surface of the base 110 gradually increases, and the orthogonal projection of the lower surface of the second lower conductive post 133 onto the base 110 is located in the orthogonal projection of the lower surface of the first lower conductive block 123 onto the base 110 such that misregistration between the lower surface of the second lower electrode layer 126 and the upper surface of the first lower electrode layer 116 is prevented, and the volume of the second lower electrode layer 126 is increased such that the resistance of the second lower electrode layer 126 is reduced, such that, thus helping to reduce the resistance in contact between the second lower electrode layer 126 and the first lower electrode layer 116. In addition, the orthogonal projection of the upper surface of the second lower conductive column 133 on the base 110 coincides with the orthogonal projection of the lower surface of the second lower conductive block 143 on the base 110 .

[0067] In other embodiments, an orthogonal projection of the upper surface of the first lower conductive block onto the substrate may cover an orthogonal projection of the lower surface of the first lower conductive block onto the substrate, and an orthogonal projection of the upper surface of the second lower conductive block onto the substrate may cover an orthogonal projection of the lower surface of the second lower conductive block. block onto the base.

[0068] In this embodiment, the first lower conductive post 113 and the first lower conductive block 123 are a one-piece structure, and the second lower conductive post 133 and the second lower conductive block 143 are a one-piece structure, which makes it possible to reduce defects in the interface condition between the first lower conductive post 113 and the first lower conductive block 123, as well as defects in the interface state of the second lower conductive post 133 and the second lower conductive block 143, and thus improve the performance of the semiconductor structure. The first lower conductive post 113, the first lower conductive block 123, the second lower conductive post 133, and the second lower conductive block 143 may comprise the same material. Thus, it can reduce steps in the semiconductor structure fabrication process, as well as reduce the cost and complexity of semiconductor structure fabrication. The materials of the first lower conductive post 113, the first lower conductive block 123, the second lower conductive post 133, and the second lower conductive block 143 may, respectively, be at least one of nickel-platinum, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium or ruthenium nitride.

[0069] In other embodiments, the first lower conductive post and the first lower conductive block may not be a solid structure, and the second lower conductive post and the second lower conducting block may not be a single structure. In other words, the materials of the first lower conductive post, the first lower conductive block, the second lower conductive post, and the second lower conductive block may be different.

[0070] In other embodiments, with reference to FIG. 5, the cross-sectional shape of the first lower electrode layer 116 and the cross-sectional shape of the second lower electrode layer 126 may be rectangular. With reference to FIG. 6, a cross-section of the first lower electrode layer 116 and a cross-section of the second lower electrode layer 126 may be in the shape of an inverted trapezoid.

[0071] With reference to FIG. 2-6, the dielectric capacitor layer 136 includes a first dielectric capacitor layer 156, a second dielectric capacitor layer 166, and a third dielectric capacitor layer 176. A first dielectric capacitor layer 156 covers the sides of the first bottom electrode layer 116. A second dielectric capacitor layer 166 covers the top surface of the first bottom electrode layer 116 exposed by the second bottom electrode layer 126. A third dielectric capacitor layer 176 covers the top surface and sides of the second bottom electrode layer 126.

[0072] The first dielectric capacitor layer 156, the second dielectric capacitor layer 166, and the third dielectric capacitor layer 176 collectively cover the surfaces of the first lower electrode layer 116 and the second lower electrode layer 126 so as to isolate the upper electrode layer 146 from the first lower electrode layer 116 and second lower electrode layer 126. In addition, a second dielectric capacitor layer 166 covers the upper surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 to prevent the upper electrode layer 146 from contacting the first lower electrode layer 116 through the upper surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126, thereby further providing acceptable electrical performance of the capacitor.

[0073] In addition, the dielectric capacitor layer 136 may also include a fourth dielectric capacitor layer 186. A fourth capacitor dielectric layer 186 is coupled to the bottom surface of the first capacitor dielectric layer 156 and extends in a direction away from the axis of the first bottom electrode layer 116 perpendicular to the surface of the substrate 110. A top electrode layer 146 (with reference to FIG. 1) is also located on the surface of the fourth dielectric layer 186 capacitor. In some examples, in the direction in which the metal bit line 101 extends, when the width of the lower surface of the first lower electrode layer 116 is less than the maximum width of the semiconductor channel 102, the first lower electrode layer 116 exposes a portion of the upper surface of the second doped region III. The fourth dielectric capacitor layer 186 is connected to the lower surface of the first dielectric capacitor layer 156 and extends in a direction from the axis of the first lower electrode layer 116 perpendicular to the surface of the substrate 110. Thus, it is preferable to provide insulation between the upper electrode layer 146 and the second doped region III by the fourth dielectric layer 186 capacitor, thereby ensuring acceptable electrical performance of the semiconductor structure.

[0074] In this embodiment, the fourth capacitor dielectric layer 186 and the first capacitor dielectric layer 156 are an integrally formed structure that can reduce defects in the interface state between the fourth capacitor dielectric layer 186 and the first capacitor dielectric layer 156, and thus thus improving the overall insulation effect of the fourth capacitor dielectric layer 186 and the first capacitor dielectric layer 156. The material of the fourth capacitor dielectric layer 186 is the same as the material of the first capacitor dielectric layer 156. Thus, it is preferable to shorten the manufacturing process of the semiconductor structure, as well as reduce the cost and complexity of manufacturing the semiconductor structure. In other embodiments, the fourth capacitor dielectric layer and the first capacitor dielectric layer may be layered structures. The material of the fourth dielectric layer of the capacitor may be different from the material of the first dielectric layer of the capacitor.

[0075] In some embodiments, with reference to FIG. 2, the upper surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 is provided with a first dielectric capacitor layer 156. The second capacitor dielectric layer 166 is disposed on the top surface of the first capacitor dielectric layer 156 so as to cover the top surface of the first bottom electrode layer 116 exposed by the second bottom electrode layer 126. In addition, the second capacitor dielectric layer 166 also extends in an off-axis direction. the second lower electrode layer 126 perpendicular to the surface of the base 110, thereby further enhancing the insulating effect between the upper electrode layer 146 and the upper surface of the first lower electrode layer 116.

[0076] In some other embodiments, with reference to FIG. 3, the second dielectric capacitor layer 166 is in contact with the upper surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126, and extends in a direction away from the axis of the second lower electrode layer 126 perpendicular to the surface of the substrate 110, thereby providing insulation between the upper electrode layer 146 and the upper surface of the first lower electrode layer 116.

[0077] The second dielectric capacitor layer 166 and the third dielectric capacitor layer 176 may be an integrally formed structure that can reduce defects in the interface state between the second dielectric capacitor layer 166 and the third dielectric capacitor layer 176, thereby enhancing the overall insulation effect a second dielectric capacitor layer 166 and a third dielectric capacitor layer 176. The material of the second capacitor dielectric layer 166 is the same as the material of the third capacitor dielectric layer 176. Thus, it is preferable to reduce steps in the semiconductor structure manufacturing process, as well as reduce the cost and complexity of manufacturing the semiconductor structure. In other embodiments, the second capacitor dielectric layer and the third capacitor dielectric layer may be a layered structure. The material of the second dielectric layer of the capacitor may be different from the material of the third dielectric layer of the capacitor.

[0078] In some other examples, with reference to FIGS. 4-6, the upper surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 is provided with a first dielectric capacitor layer 156. The first dielectric capacitor layer 156 and the second dielectric capacitor layer 166 are an integrally formed structure that can reduce defects in the interface state between the first dielectric capacitor layer 156 and the second dielectric capacitor layer 166, and thus enhance the overall insulation effect of the first a dielectric capacitor layer 156 and a second capacitor dielectric layer 166. The material of the first capacitor dielectric layer 156 is the same as the material of the second capacitor dielectric layer 166. Thus, it is preferable to reduce steps in the semiconductor structure manufacturing process, as well as reduce the cost and complexity of manufacturing the semiconductor structure. In other embodiments of the invention, the first dielectric layer of the capacitor and the second dielectric layer of the capacitor may be a layered structure, the material of the first dielectric layer of the capacitor may be different from the material of the second dielectric layer of the capacitor.

[0079] It should be noted that in FIG. 2-6, a structure other than the first lower electrode layer 116 in the dotted frame a is the fourth capacitor dielectric layer 186, and a structure different from the second lower electrode layer 126 in the dotted frame b is the second dielectric layer 166 of the capacitor.

[0080] In this embodiment, the relative dielectric constant of the material of the capacitor dielectric layer 136 is greater than the relative dielectric constant of the material of the second dielectric layer 105, which can further improve the insulation effect between the first lower electrode layer 116 and the second lower electrode layer 126, and the upper electrode layer 146, and thus improve the electrical performance of the capacitor in the semiconductor structure.

[0081] The materials of the first dielectric capacitor layer 156, the second dielectric capacitor layer 166, the third dielectric capacitor layer 176, and the fourth dielectric capacitor layer 186, respectively, include a high dielectric constant material such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium titanate.

[0082] It should be noted that, in FIG. 2-6, as examples, the second dielectric layers 166 of adjacent capacitors are separated from each other. As such, second dielectric layers 166 of adjacent capacitors may be in contact with each other and may be connected to each other. As examples, the fourth dielectric layers 186 of adjacent capacitors are separated from each other. As such, the fourth dielectric layers 186 of adjacent capacitors may be in contact with each other and may be connected to each other.

[0083] Also with reference to FIG. 1, each upper electrode layer 146 includes a first upper electrode layer 196 and a second upper electrode layer 106. The first upper electrode layer 196 surrounding the first lower electrode layer 116 is located on the side of the first dielectric layer 156 of the capacitor. The second upper electrode layer 106 surrounding the second lower electrode layer 126 is located on the surface of the third capacitor dielectric layer 176, and the lower surface of the second upper electrode layer 106 is in contact with the upper surface of the first upper electrode layer 196.

[0084] The materials of the first top electrode layer 196 and the second top electrode layer 106 may, respectively, be at least one of nickel-platinum, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium . In other embodiments, the material of the first top electrode layer may be different from the material of the second top electrode layer.

[0085] In this embodiment, the material of the entire lower electrode layer may be the same as the material of the entire upper electrode layer 146. In other embodiments, the material of the lower electrode layer may be different from the material of the upper electrode layer.

[0086] In some embodiments, the semiconductor structure may include two storage units 100 stacked on each other on the base 110. As shown by way of example in FIG. 1, two storage units 100 are stacked on each other on the base 110. The number of storage units 100 stacked on each other on the base 110 can be suitably set according to the actual electrical requirement. Since multiple storage units 100 can be stacked on the same substrate 110, by increasing the size of the semiconductor structure in the thickness direction, the array density of the semiconductor structure can be increased, and thus the storage performance of the semiconductor structure can be improved and the two-dimensional size of the semiconductor structure can be reduced. structures to implement a three-dimensional (3D) stack. It should be understood that the term "array extent" refers to the extent of storage units 100 located in the semiconductor structure.

[0087] In addition, the semiconductor structure also includes an insulating layer 107. The insulating layer 107 is located on the surface of the second dielectric layer 105. A capacitor formed by the first lower electrode layer 116, the second lower electrode layer 126, the dielectric capacitor layer 136 and the upper electrode layer 146, located in the insulating layer 107. The insulating layer 107 is used to support the capacitor, to prevent the capacitor from shrinking, and is also used to insulate the upper electrode layers 146 of adjacent capacitors.

[0088] In this embodiment, the insulating layer 107 is a layered film layer structure and includes a first insulating layer 117 and a second insulating layer 127. The first insulating layer 117 is located between adjacent first top electrode layers 196 and is used to provide electrical insulation between adjacent first top electrode layers 196. A second insulating layer 127 is located between the adjacent second top electrode layers 106 and covers the top surface of the first insulating layer 117, which is used to provide electrical insulation between the adjacent second top electrode layers 106.

[0089] The material of the first insulating layer 117 and the material of the second insulating layer 127 are the same and may be at least one of silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon oxide. In other embodiments, the material of the first insulating layer may be different from the material of the second insulating layer.

[0090] Thus, the channel area II of the semiconductor channel 102 is arranged vertically on the metal bit line 101 so as to provide a semiconductor structure with a circular gate transistor, thus a 3D stack memory device can be formed. This makes it possible to increase the integration density in the semiconductor structure. Here, the lower electrode layer of the capacitor in the semiconductor structure is formed by layering the first lower electrode layer 116 and the second lower electrode layer 126. This makes it possible to increase the overall height of the lower electrode layer of the capacitor so as to increase the capacitance of the capacitor. In addition, the orthogonal projection of the bottom surface of the second lower electrode layer 126 on the base 110 is located in the orthogonal projection of the top surface of the first lower electrode layer 116 on the base 110 so as to allow the second lower electrode layer 126 to be aligned with the first lower electrode layer 116 to avoid imprecise alignment between the lower surface of the second lower electrode layer 126 and the upper surface of the first lower electrode layer 116, thereby increasing both the capacitance and the dimensional accuracy of the capacitor, thereby improving the quality of the capacitor, resulting in the capacitor being guaranteed to have acceptable electrical characteristics.

[0091] In addition, the semiconductor structure proposed in this embodiment can be applied to a memory device 4F ² in which F is an element size. This memory device may be a Static Random Access Memory (RRAM), a Magnetoresistive Random Access Memory (MRAM), or a Phase Change Random Access Memory. Memory, PCRAM), Dynamic Random Access Memory (DRAM), or Static Random Access Memory (SRAM), and this memory can also be used to perform in-memory computations (In Memory Computing (IMC), in which the user is allowed to store data in a storage device and process information at a higher speed. In a specific embodiment, the storage device may be DRAM, wherein the metal bit lines 101 mentioned in the previous embodiments are DRAM bit lines, the word lines 104 are DRAM word lines, and the capacitor structures are DRAM storage capacitors.

[0092] Accordingly, in another embodiment of the present invention, there is provided a semiconductor structure manufacturing method that can be used to form the above-mentioned semiconductor structure.

[0093] In FIG. 7 to 22 are schematic structure views corresponding to operations in a method for manufacturing a semiconductor structure according to another embodiment of the present invention. The method for manufacturing a semiconductor structure proposed in this embodiment is described in detail below with reference to the accompanying drawings. Parts that are the same as or consistent with the previous embodiments are not described in detail again below.

[0094] With reference to FIG. 7-22 provide a base 110, and a storage unit 100 is formed thereon. In particular, the formation of the storage unit 100 includes the following operations.

[0095] With reference to FIG. 7, the base 110 may be a logic circuit structure layer. A first dielectric layer 103 and metal bit lines 101 disposed thereon are provided, with the first dielectric layer 103 exposing the surfaces of the metal bit lines 101.

[0096] Specifically, an intermediate dielectric layer 120 is formed that completely covers the surface of the logic circuit structure layer, which is used to protect the logic circuit structure layer to prevent electrical interference between the logic circuit structure layer and the metal bit lines 101 that are subsequently formed on the intermediate dielectric layer 120.

[0097] A plurality of metal bit lines 101 separated from each other are formed on the surface of the intermediate dielectric layer 120. The metal bit lines 101 expose a partial surface of the intermediate dielectric layer 120. An insulating layer 130 is formed. The insulating layer 130 is located on the surface of the intermediate dielectric layer 120 exposed on the side of the metal bit line 101 and covers the side walls of the metal bit lines 101.

[0098] For the material of the metal bit lines 101, reference may be made to the corresponding description in the above embodiments. The detailed description is not repeated at this point in this document.

[0099] It should be understood that in other embodiments, a parent dielectric layer may also be provided on the surface of the logic circuit structure layer. The original dielectric layer is structured to form a plurality of grooves that are separated from each other in the original dielectric layer. The original dielectric layer located below the grooves is used as an intermediate dielectric layer. The original dielectric layer located between adjacent grooves is used as an insulating layer. Thus, the insulating layer and the original dielectric layer constitute a single structure. Metal bit lines are then formed to fill the grooves.

[00100] With reference to FIG. 8, a first metal layer 118 is formed on the surface of each metal bit line 101.

[00101] The first metal layer 118 is used to react with a region of the subsequently formed semiconductor channel in the vicinity of the metal bit line 101 to provide a metal element for subsequent formation of the first metal semiconductor layer, thereby reducing the resistivity of the semiconductor channel. The material of the first metal layer 118 includes at least one of cobalt, nickel, or platinum.

[00102] In this embodiment, the first metal layer 118 covers the entire surface of the metal bit line 101, which can prevent a corrosion process of the first metal layer 118 causing corrosion damage to the metal bit line 101. In other embodiments, the first metal layer may be located on only a partial surface of each metal bit line, and the position of the first metal layer corresponds to the position at which the semiconductor channel will subsequently be formed.

[00103] In other embodiments, the first metal layer cannot be formed on the surface of each metal bit line, and subsequently a semiconductor channel is directly formed on a partial surface of the metal bit line. Additionally, in some embodiments, the metal bit line material is at least one of nickel, cobalt, or platinum. In other words, the metal bit line can provide a metal element for subsequently forming the first metal semiconductor layer, and thus there is no need to form the first metal layer on the surface of the metal bit line.

[00104] With reference to FIG. 9 and fig. 10, form a semiconductor channel 102 that is located on a partial surface of the metal bit line 101. This semiconductor channel 102 faces the bottom surface of the metal bit line 101 and is electrically connected to the metal bit line 101. In this embodiment, the semiconductor channel 102 is in contact with the first metal layer 118. In other embodiments, the semiconductor channel may be in direct contact with the metal bit line.

[00105] In particular, the processes for forming the semiconductor channels 102 include the following operations.

[00106] With reference to FIG. 9, form the original channel layer 132, which is located on the metal bit line 101 and the substrate 110.

[00107] In some embodiments, an insulating layer 130 is provided between adjacent metal bit lines 101 such that the original channel layer 132 covers the surface of the insulating layer 130.

[00108] In this embodiment, the first metal layer 118 is formed on the surface of the metal bit line 101 such that the original channel layer 132 covers the surface of the first metal layer 118. In other embodiments, the original channel layer may directly cover the surface of the metal bit lines.

[00109] In particular, the method of forming the initial channel layer 132 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or organometallic chemical vapor deposition. The material of the initial channel layer 132 is indium gallium zinc oxide, indium tungsten oxide, or indium tin oxide.

[00110] Also with reference to FIG. 9, a structured mask layer 109 is formed on the surface of the original channel layer 132.

[00111] Masking layer 109 is used to determine the positions and sizes of subsequently formed semiconductor channels 102. The material of masking layer 109 may be silicon nitride, silicon carbon nitride, or silicon carbon oxynitride. In other embodiments, the mask layer material may be a photoresist.

[00112] With reference to FIG. 10, the original channel layer 132 (with reference to FIG. 8) is structured using the masking layer 109 as a mask to form the semiconductor channels 102.

[00113] In the direction from the substrate 110 to the metal bit lines 101, each semiconductor channel 102 includes a first doped region I, a channel region II, and a second doped region III, which are arranged in series.

[00114] All of the first doped region I, channel region II, and second doped region III in the semiconductor channel 102 are doped using the same type of doped ions. Such a semiconductor channel 102 can be used to form the channels of a junctionless transistor. This avoids problems such as threshold voltage drift and increased leakage current caused by sudden changes in doping. This also allows the short channel effect to be inhibited.

[00115] It should be understood that the original channel layer 132 may be pre-doped prior to cross-linking. The doping may be N-type ion doping or P-type ion doping. The original channel layer 132 may be doped after structuring to form semiconductor channels 102 with an appropriate ion distribution.

[00116] In this embodiment, to form the semiconductor channels 102 with a cylindrical structure, corner radius machining can be performed on the semiconductor channels 102 using thermal oxidation, etching and/or annealing in a hydrogen atmosphere. This makes it possible to prevent the phenomenon of point discharge or electrical leakage in the semiconductor channels 102 during operation of the semiconductor structure.

[00117] With reference to FIG. 11, a gate dielectric layer 114 is formed on the entire side wall of each semiconductor channel 102. The gate dielectric layer 114 exposes a surface of the first metal layer 118 other than the position immediately below the semiconductor channels 102. The gate dielectric layers 114 are used to protect the semiconductor channels 102 in a subsequent annealing process. to prevent the material of the semiconductor channels 102 from subsequently reacting with the metal material.

[00118] In this embodiment, the gate dielectric layer 114 is also located on the end surface of the second doped region III at a distance from the substrate 110. In the step of subsequent formation of the fourth dielectric layer, the gate dielectric layer 114 located on the end surface of the second doped region III is simultaneously removed away from the substrate 110 to facilitate subsequent formation of a metal layer on the end surface of the second doped region III located away from the substrate 110. In other embodiments, the dielectric gate layer covering the end surface of the second doped region may be removed by etching.

[00119] In other embodiments, the gate dielectric layer may be formed on only a portion of the side wall surface corresponding to the channel region of the semiconductor channel. Or, the gate dielectric layer may be formed on a portion of the side wall surface corresponding to the channel region and the first doped region of the semiconductor channel. Or, the gate dielectric layer may be formed on a portion of the side wall surface corresponding to the channel region and the second doped region of the semiconductor channel.

[00120] Also with reference to FIG. 11, form a third dielectric layer 115. The third dielectric layer 115 is located on the surface of the first metal layer 118 at a distance from the substrate 110 and is located at intervals between adjacent first metal layers 118.

[00121] Specifically, a third dielectric layer 115 is disposed on the surface of the insulating layer 130 and a portion of the side wall surface of the gate dielectric layer 114 corresponding to each first doped region I (with reference to FIG. 9) to isolate the first metal layers 118 from subsequently formed lines of words. The third dielectric layer 115 is a solid film layer structure and is used to prevent electrical interference between the first metal layers 118 and the metal bit lines 101 and subsequently generated word lines.

[00122] Forming the third dielectric layer 115 includes forming the original first dielectric layer on the surface of the metal bit line 101 away from the substrate 110; and planarization and back-etching of the original first dielectric layer to a specified thickness to form the third dielectric layer 115.

[00123] With reference to FIG. 12, the initial conductive gate layer 134 surrounding the channel regions II is formed on the side wall surfaces of the gate dielectric layers 114 corresponding to the channel regions II (with reference to FIG. 10). The original gate conductive layer 134 is a complete film layer structure.

[00124] Specifically, the method of forming the initial conductive gate layer 134 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or organometallic chemical vapor deposition. In addition, the original gate conductive layer 134 is planarized and etched to enable the original gate conductive layer 134 to be positioned on a portion of the side wall surface of each gate dielectric layer 114 corresponding to the channel region II.

[00125] With reference to FIG. 13, the original gate conductive layer 134 (with reference to FIG. 12) is structured to form gate conductive layers 124 that are spaced apart to allow connection of gate conductive layers 124 of different semiconductor channels 102 located on the same metal line 101 bits, with different electrical potentials, thus realizing diversified control of semiconductor channels. The structuring method includes photolithography.

[00126] Each gate dielectric layer 114 may be located around at least one channel region II of the semiconductor channel 102. In FIG. 13, as an example, each gate dielectric layer 114 surrounds two semiconductor channels 102. The number of semiconductor channels 102 surrounded by each gate dielectric layer 114 can be suitably set according to the actual electrical requirement.

[00127] The dielectric gate layer 114 and the conductive gate layer 124 together form a word line 104. Thus, the word line 104 is also located around the two semiconductor channels 102.

[00128] With reference to FIG. 14, form a fourth dielectric layer 125. The fourth dielectric layer 125 is located at intervals between adjacent conductive gate layers 124 and is used to prevent electrical noise from occurring between adjacent conductive gate layers 124. A fourth dielectric layer 125 is also located on the surfaces of the gate conductive layers 124 remote from the substrate 110, which are used to support other conductive structures subsequently formed on the surface of the fourth dielectric layer 125 remote from the substrate 110, and provides insulation between the gate conductive layers 124 and the others. conducting structures.

[00129] In addition, after the fourth dielectric layer 125 is formed, the fourth dielectric layer 125 is planarized. The gate dielectric layer 114 located on the end surfaces of the masking layers 109 away from the substrate 110 is removed so that the fourth dielectric layer 125 exposes the mask layer 109 located on the end surfaces of the second doped regions III away from the substrate 110.

[00130] In this embodiment, the third dielectric layer 115 and the fourth dielectric layer 125 together form the second dielectric layer 105. The second dielectric layer 105 is located between the metal bit lines 101 and the word lines 104, and is also located on the sides of the word lines 104 away from the base 110. The material of the third dielectric layer 115 is the same as the material of the fourth dielectric layer 125. Thus, it is preferable to reduce the number of types of materials required in the semiconductor structure manufacturing process, as well as to reduce the cost and complexity of semiconductor structure manufacturing. In addition, the second dielectric layer 105 also exposes the top surface of the mask layer 109.

[00131] With reference to FIG. 14-15, the mask layer 109 is removed to reveal the top surfaces of the second doped regions III (with reference to FIG. 10). A second metal layer is formed on the open upper surface of every second alloyed region III.

[00132] The second metal layer is used to react with the second doped region III to provide a metal element for subsequent formation of the second metal semiconductor layers 122, thereby reducing the resistivity of the semiconductor channel 102. The material of the second metal layer includes at least one of cobalt, nickel or platinum.

[00133] The manufacturing method may also include the following steps. Carry out the first annealing. The first metal layers 118 react with the first doped regions I to convert a partial thickness of each first doped region I facing the metal bit lines 101 into a first metal semiconductor layer 112. The resistivity of the material of each first metal semiconductor layer 112 is less than the resistivity of the material of the first doped region I different from the first metal semiconductor layer 112.

[00134] The portions of each first metal layer 118 that react with the first I doped regions become portions of each first I doped region, and the portion of each first metal layer 118 that does not react with the first I doped regions is used as the metal layer 108. It should be understood that a partial thickness of each first metal layer 118 may also remain between the metal bit line 101 and the first metal semiconductor layers 112. The remaining first metal layer 118 is used as the metal layer 108. In other words, each metal layer 108 may be located on a partial surface of each of the metal bit lines 101 different from the first metal semiconductor layers 112, and may also be located between the first metal semiconductor layers 112 and the metal bit line 101.

[00135] In this embodiment, when performing the first annealing, a second annealing is performed, and each second metal layer reacts with each second doped region III to convert a partial thickness of each exposed second doped region III into a second metal semiconductor layer 122, and the resistivity of the second metal material semiconductor layer 122 is less than the resistivity of a portion of every second doped region III other than the second metallic semiconductor layer 122.

[00136] In particular, rapid thermal annealing is performed. The following rapid thermal annealing process parameters are used: the semiconductor structure is annealed in an N ₂ atmosphere, the annealing temperature is from 600°C to 850°C, and the annealing time is from 10 seconds to 60 seconds. Since the annealing temperature is moderate, the first metal layers 118 can more easily react completely with the first doped regions I, and the second metal layers can completely react with the second doped regions III, thereby forming the first metal semiconductor layers 112 and the second metal semiconductor layers 122 with relatively low resistivity. In addition, since the annealing temperature is moderate, diffusion of metal elements in the first metal layer 118 and the second metal layer into the channel regions II can be prevented. In addition, annealing is carried out in an N ₂ atmosphere, which prevents oxidation of the first metal layers 118, second metal layers and semiconductor channels 102.

[00137] In this embodiment, the first annealing and the second annealing are performed simultaneously, thereby simplifying the manufacturing processes of the semiconductor structure. In other embodiments, after forming the semiconductor channels, a first annealing may be performed on the first metal layer. After the second metal layers are formed on the second alloyed areas, a second annealing is performed.

[00138] Additionally, in other embodiments, a first semiconductor layer may be formed on the surface of each first metal layer before forming the semiconductor channels. The material of the first semiconductor layer is silicon or germanium. The first semiconductor layer reacts with the first metal layer during the first annealing to form the first metal semiconductor layer. Before forming the second metal layer, a second semiconductor layer is formed on the top surface of each second doped region. The material of the second semiconductor layer is silicon or germanium. The second semiconductor layer reacts with the second metal layers during a second annealing to form second metal semiconductor layers.

[00139] With reference to FIG. 16-22, form a first lower electrode layer 116, which is in contact with the upper surface of the semiconductor channel 102. Form a second lower electrode layer 126, which is located on the upper surface of the first lower electrode layer 116. Form an upper electrode layer 146, which is located on the upper surface of the second lower electrode layer 126 and surrounds the first lower electrode layer 116 and the second lower electrode layer 126. A dielectric capacitor layer 136 is formed, which is located between the upper electrode layer 146 and the first lower electrode layer 116, and is also located between the upper electrode layer 146 and the second lower electrode layer 126. layer 126.

[00140] Specifically, the orthogonal projection of the bottom surface of the second bottom electrode layer 126 onto the base 110 is located in the orthogonal projection of the top surface of the first bottom electrode layer 116 onto the base 110. The dielectric capacitor layer 136 covers the top surface and sides of the second bottom electrode layer 126, as well as covers the sides of the first lower electrode layer 116 and the portion of the upper surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126.

[00141] Specifically, forming the first lower electrode layer 116, the second lower electrode layer 126, the dielectric capacitor layer 136, and the upper electrode layer 146 includes the following operations.

[00142] With reference to FIG. 16, form the first lower electrode layer 116. The upper surface of the first lower electrode layer 116 includes a central region c and a peripheral region d surrounding the central region c.

[00143] Specifically, on the side of the second doped region III located away from the channel region II, a sacrificial layer 137 is formed. A first through hole e is provided in the sacrificial layer 137 to penetrate the sacrificial layer 137 and expose the second doped region III. A first lower electrode layer 116 is formed to fill the first through holes.

[00144] The first through hole e includes a first groove and a second groove that communicate with each other. The first groove exposes the surface of the second doped region III.

[00145] In particular, forming the first groove and the second groove may include the following operations. An initial sacrificial layer is formed on the surface of the second dielectric layer 105. A structured masking layer is formed on the surface of the original sacrificial layer. A partial thickness of the original sacrificial layer is etched away using a structured masking layer as a mask to form a second groove. In the region corresponding to the second groove, a portion of the original sacrificial layer exposed from the second groove is etched until the surface of the second alloyed region III is exposed to form a first groove with a cross-sectional area gradually increasing in a direction parallel to the surface of the base 110 .

[00146] In other embodiments, the cross-section at the first through hole e may be rectangular or inverted trapezoidal.

[00147] In this embodiment, each word line 104 extends in the second direction. Each word line 104 surrounds two semiconductor channels 102. The first groove and the second groove also extend in the second direction. Specifically, the first through hole e formed by the first groove and the second groove corresponds to one word line 104. In other words, each first through hole e exposes a side located away from the channel region II of every second doped region III surrounded by a word line 104 corresponding to the first through hole e. In fig. 16, for example, each first through-hole e exposes the top surfaces of second doped regions III of two semiconductor channels 102.

[00148] In other embodiments, each first through hole may expose the side of only one second doped region located away from the channel region.

[00149] With reference to FIG. 17, form a first capacitor dielectric film 119 that covers the top surface and sides of the first bottom electrode layer 116.

[00150] In some embodiments, forming the first capacitor dielectric film 119 includes the following steps. The sacrificial layer 137 is removed, and then the first initial capacitor dielectric film is formed with a completely continuous surface. The first capacitor source dielectric film also covers the top surface and sides of the first bottom electrode layer 116. In other words, the first capacitor source dielectric film also covers the fourth dielectric layer 125 exposed to the side of the first bottom electrode layer 116, the top surfaces of the gate dielectric layer 114, and the second doped region III (with reference to Fig. 10).

[00151] The first initial capacitor dielectric film is structured to form a first capacitor dielectric film 119 and a fourth capacitor dielectric layer 186. The fourth capacitor dielectric layer 186 is connected to the bottom surface of the first capacitor dielectric film 119 and extends in a direction away from the axis of the first bottom electrode layer 116 perpendicular to the surface of the base 110.

[00152] The second lower electrode layer 126 is then formed. Thus, in a direction perpendicular to the surface of the substrate 110, the aspect ratio of the first lower electrode layer 116 can be relatively small to improve the structure stability of the first lower electrode layer 116. During subsequent formation of other film layers and etching other film layers, the first lower electrode layer 116 can be tilted or compressed less likely, thereby improving the overall stability of the semiconductor structure.

[00153] In some other embodiments of the invention, with reference to FIGS. 18, before forming the first lower electrode layer 116, the method also includes the following steps. On the second dielectric layer 105, a fourth capacitor dielectric layer 186 is formed. In the fourth dielectric layer 186 of the capacitor, an opening is formed that penetrates into the fourth dielectric layer 186 of the capacitor. This opening exposes at least a portion of the upper surface of the second alloyed region III (with reference to FIG. 10). During the formation of the first lower electrode layer 116, the first lower electrode layer 116 fills this opening. A first capacitor dielectric film 119 is formed covering the top surface and sides of the first bottom electrode layer 116.

[00154] In other embodiments, a third through-hole may be formed that penetrates the sacrificial layer and at least exposes the entire top surface of the second doped region. The original first dielectric layer of the capacitor is formed on the side wall and the bottom of the third through hole. A portion of the original first capacitor dielectric layer located at the bottom of the third through hole is removed, and the remaining portion of the first capacitor dielectric layer is used as the first capacitor dielectric layer defining the fourth through hole. The first lower electrode layer is formed, filling the fourth through hole. In other words, there is no second dielectric capacitor layer on the upper surface of the first lower electrode layer. The remaining part of the sacrificial layer is used as the first insulating layer.

[00155] With reference to FIG. 17 and fig. 18, form a first insulating layer 117 covering the first dielectric film 119 of the capacitor. The first insulating layer 117 exposes the top surface of the first dielectric film 119 of the capacitor.

[00156] In this embodiment, the fourth dielectric capacitor layers 186 of adjacent capacitors are separated from each other. In other words, the first insulating layer 117 is provided between adjacent fourth dielectric layers 186 of the capacitor. In other embodiments, after forming the first initial capacitor dielectric film with a completely continuous surface, the first initial capacitor dielectric film may not be structured. In other words, the first capacitor source dielectric film includes a first capacitor dielectric layer and a fourth capacitor dielectric layer, and the fourth capacitor dielectric layers of adjacent capacitors are in contact and connected to each other.

[00157] With reference to FIG. 19, form the first upper electrode layer 196. The first upper electrode layer 196 surrounds the first lower electrode layer 116. The first capacitor dielectric film 119 is disposed between the first upper electrode layer 196 and the first lower electrode layer 116.

[00158] Specifically, the first insulating layer 117 is structured to form a second through-hole f surrounding the first lower electrode layer 116. The second through-hole f exposes the sides of the first dielectric film 119 of the capacitor. A first upper electrode layer 196 is formed to fill the second through hole f.

[00159] With reference to the combination of FIG. 19 and 20, the first capacitor dielectric film 119 located in the central region c (with reference to FIG. 16) is removed to expose the upper surface of the first lower electrode layer 116 in the central region c.

[00160] With reference to FIG. 20-22, form a second lower electrode layer 126, which is in contact with the upper surface of the first lower electrode layer 116 in the central region c (with reference to FIG. 16). A third capacitor dielectric layer 176 is formed that covers the top surface and sides of the second bottom electrode layer 126.

[00161] In some embodiments, with reference to FIG. 21, a portion of the first capacitor dielectric film 119 located on the side surfaces of the first lower electrode layer 116 is used as the first capacitor dielectric layer 156. The remaining part of the first capacitor dielectric film 119 located on the upper surface of the first lower electrode layer 116 is used as the second capacitor dielectric layer 166. In other words, the first capacitor dielectric layer 156 and the second capacitor dielectric layer 166 are a structure formed integrally.

[00162] In particular, with reference to FIG. 20, the support layer 147 is formed on a surface jointly formed by the upper surface of the first insulating layer 117, the upper surface of the first upper electrode layer 196, the upper surface of the second dielectric capacitor layer 166, and the upper surface of the first lower electrode layer 116. A fifth through hole g that penetrates through the support layer 147 and exposes the central region c (with reference to FIG. 16) of the first lower electrode layer 116. The orthogonal projection of the fifth through hole g on the base 110 is located in the orthogonal projection of the upper surface of the first lower electrode layer 116 on the base 110. The orthogonal projection of the lower The surface of the subsequently formed second lower electrode layer 126 in the fifth through hole g on the base 110 is located in the orthogonal projection of the upper surface of the first lower electrode layer 116 on the base 110. This makes it possible to improve the alignment accuracy between the second lower electrode layer 126 and the first lower electrode layer 116 so that avoiding imprecise alignment between the second lower electrode layer 126 and the upper surface of the first lower electrode layer 116, thereby improving the dimensional accuracy of the finally formed capacitor, so as to improve the manufacturing quality of the capacitor and ensure acceptable electrical performance of the capacitor.

[00163] The processes for forming the fifth through hole g are the same as the processes for forming the first through hole e. Their detailed description is not repeated at this point in this document.

[00164] With reference to FIG. 21, a third capacitor dielectric layer 176 is formed on the exposed surfaces of the second lower electrode layer 126.

[00165] Specifically, the support layer 147 (with reference to FIG. 20) is removed and a third initial capacitor dielectric film with a completely continuous surface is formed. In other words, the third initial capacitor dielectric film covers the exposed surfaces of the second lower electrode layer 126, and also covers the surface jointly formed by the top surface of the first insulating layer 117, the top surface of the first top electrode layer 196, and the top surface of the second capacitor dielectric layer 166. The third initial dielectric film of the capacitor is structured. As the third capacitor dielectric layer 176, only the third original capacitor dielectric films stored on the side walls and the top surface of the second lower electrode layer 126 are used.

[00166] In some other embodiments, with reference to FIGS. 22, the remaining part of the first capacitor dielectric film 119 located on the side surfaces and the top surface of the first lower electrode layer 116 is used as the first capacitor dielectric layer 156.

[00167] Specifically, processes for forming the second lower electrode layer 126 and the third capacitor source dielectric film are the same as the methods in the previous embodiments. Their detailed description is not repeated at this point in this document.

[00168] During the structuring of the third capacitor base dielectric film, the third capacitor base dielectric film on the side walls and the top surface of the second lower electrode layer 126 is stored as the third capacitor dielectric layer 176 and the third capacitor base dielectric film located on the top surface of the first dielectric layer 156 capacitor and a portion of the upper surface of the first upper electrode layer 196 also remains as a second dielectric capacitor layer 166. In other words, the second capacitor dielectric layer 166 and the third capacitor dielectric layer 176 are a structure formed integrally. The second dielectric capacitor layer 166 extends in a direction away from the axis of the second lower electrode layer 126, perpendicular to the surface of the base 110. Thus, this helps to enhance the insulation effect between the subsequently formed second upper electrode layer 106 and the first lower electrode layer 116.

[00169] In other embodiments, when a second capacitor dielectric layer is not provided on the upper surface of the first lower electrode layer, at least film of the second dielectric layer of the capacitor, and then forming a second lower electrode layer. Or, during the formation of the third capacitor dielectric layer 176, the third original capacitor dielectric film is not structured. Or, during the formation of the third capacitor dielectric layer 176, at least a third original capacitor dielectric film located on the side walls and top surface of the second lower electrode layer 126 and a peripheral region of the upper surface of the first lower electrode layer are retained.

[00170] It should be noted that, as shown by way of example in FIG. 22, the second capacitor dielectric layers 166 of adjacent capacitors are separated from each other. In other words, a second insulating layer 127 is provided between adjacent second capacitor dielectric layers 166. As such, the second capacitor dielectric layers 166 between adjacent capacitors may be in contact and may be connected to each other.

[00171] Additionally, with reference to FIG. 21 and fig. 22, a second insulating layer 127 is formed covering the third dielectric layer 176 of the capacitor. The second insulating layer 127 is structured to form a sixth through hole surrounding the second bottom electrode layers 126. The sixth through hole exposes the side surfaces and top surface of the third capacitor dielectric layer 176 and exposes the top surface of the first top electrode layer 196. A second top electrode layer 106 is formed, filling sixth through hole.

[00172] The first insulating layer 117 and the second insulating layer 127 together form an insulating layer 107. The first insulating layer 117 is located between the adjacent first top electrode layers 196 and is used to provide electrical insulation between the adjacent first top electrode layers 196. The second insulating layer 127 is located between adjacent second top electrode layers 106 and covers the top surface of the first insulating layer 117 so as to be used to provide electrical insulation between adjacent second top electrode layers 106.

[00173] The first top electrode layer 196 and the second top electrode layer 106 collectively form the top electrode layer 146. The first dielectric capacitor layer 156, the second dielectric capacitor layer 166, the third dielectric capacitor layer 176, and the fourth dielectric capacitor layer 186 collectively form the dielectric capacitor layer 136 . The first lower electrode layer 116, the second lower electrode layer 126, the dielectric capacitor layer 136, and the upper electrode layer 146 together form a capacitor in the semiconductor structure.

[00174] Additionally, with reference to FIG. 1, after one storage block 100 is formed, a next storage block 100 may be formed on a side of the storage block 100 located away from the base 110.

[00175] Thus, the lower electrode layer of the capacitor is formed using separate steps, i.e. the first lower electrode layer 116 and the second lower electrode layer 126 are formed in separate steps so that the stability of the structure of the lower electrode layers is increased, the aspect ratio of the capacitor is increased, and thus the capacitance of the capacitor is increased. In addition, by providing an orthogonal projection of the lower surface of the second lower electrode layer 126 onto the substrate 110 within the orthogonal projection of the upper surface of the first lower electrode layer 116 onto the substrate 110, misalignment between the lower surface of the second lower electrode layer and the upper surface of the first lower electrode layer is prevented by which can be achieved both by increasing the capacitance and increasing the dimensional accuracy of the capacitor, as a result of which the capacitor is guaranteed to have acceptable electrical characteristics.

[00176] It may be apparent to one skilled in the art that the above embodiments are specific embodiments for implementing the present invention, and in actual application, various changes in shapes and details may be made without departing from the spirit and scope of the present invention. Changes and modifications may be made by anyone skilled in the art without departing from the spirit and scope of the present invention, and the scope of protection of the present invention shall be determined by the scope of the claims.

[00177] Industrial applicability

[00178] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing it. In the technical solution presented in the embodiments of the present disclosure, the lower electrode layer of the capacitor in the semiconductor structure is formed by layer-by-layer stacking of the first lower electrode layer and the second lower electrode layer. This allows the overall height of the lower electrode layer of the capacitor to be increased and the aspect ratio of the capacitor to be increased, thereby increasing the opposing area between the upper electrode layer and the lower electrode layer in the capacitor so that the capacitance of the capacitor is increased. In addition, the channel region of the semiconductor channel is located vertically on the surface of the metal bit line. In other words, the direction in which the channel region runs is perpendicular to the surface of the metal bit line. Space is saved for arranging the semiconductor channel in a direction (usually the horizontal direction) parallel to the surface of the metal bit line without reducing the size of the semiconductor channel, and thus the degree of integration of the semiconductor structure in the horizontal direction is increased.

Claims (57)

1. Semiconductor structure containing: a base and a storage unit located on the base, the storage unit comprising: a first dielectric layer and a metal bit line disposed in the first dielectric layer, the first dielectric layer exposing a surface of the metal bit line; a semiconductor channel located on a partial surface of the metal bit line, the semiconductor channel facing the bottom surface of the metal bit line and electrically connected to the metal bit line; a line of words located around a partial region of the semiconductor channel; a second dielectric layer located between the metal bit line and the word line, and also located on the word line side away from the base; a first lower electrode layer and a second lower electrode layer stacked on an upper surface of the semiconductor channel remote from the metal bit line, the first lower electrode layer being in contact with the upper surface of the semiconductor channel; an upper electrode layer located on the upper surface of the second lower electrode layer and surrounding the first lower electrode layer and the second lower electrode layer; And a dielectric layer of a capacitor located between the upper electrode layer and the first lower electrode layer, and also located between the upper electrode layer and the second lower electrode layer. 2. The semiconductor structure according to claim 1, in which the orthogonal projection of the lower surface of the second lower electrode layer on the base is located in the orthogonal projection of the upper surface of the first lower electrode layer on the base. 3. The semiconductor structure of claim 1, wherein the capacitor dielectric layer covers the top surface and side surfaces of the second bottom electrode layer, and also covers the side surfaces of the first bottom electrode layer and the top surface of the first bottom electrode layer exposed by the second bottom electrode layer. 4. Semiconductor structure according to claim 1, in which the dielectric layer of the capacitor contains: a first capacitor dielectric layer covering a side surface of the first lower electrode layer; a second dielectric capacitor layer covering an upper surface of the first lower electrode layer exposed to the second lower electrode layer; And a third dielectric capacitor layer covering the top surface and side surface of the second bottom electrode layer, wherein preferably, the first dielectric layer of the capacitor and the second dielectric layer of the capacitor are a structure formed integrally. 5. The semiconductor structure of claim 4, wherein the dielectric capacitor layer further comprises: a fourth dielectric capacitor layer connected to a bottom surface of the first dielectric capacitor layer and extending in a direction away from the axis of the first bottom electrode layer, perpendicular to the surface of the base; and the upper electrode layer is also located on the surface of the fourth dielectric layer of the capacitor, wherein preferably the fourth dielectric layer of the capacitor and the first dielectric layer of the capacitor are a structure formed integrally. 6. The semiconductor structure according to claim 4, in which the second dielectric layer of the capacitor is also located on the upper surface of the first dielectric layer of the capacitor and extends in the direction from the axis of the second lower electrode layer perpendicular to the surface of the base. 7. Semiconductor structure according to claim 4, in which the upper electrode layer contains: a first upper electrode layer surrounding the first lower electrode layer and located on a side surface of the first dielectric layer of the capacitor; And a second upper electrode layer surrounding a second lower electrode layer located on a surface of a third dielectric layer of the capacitor, and a lower surface of the second upper electrode layer in contact with an upper surface of the first upper electrode layer. 8. The semiconductor structure according to claim 1, wherein the relative dielectric constant of the material of the dielectric layer of the capacitor exceeds the relative dielectric constant of the material of the second dielectric layer. 9. The semiconductor structure of claim 1, wherein the semiconductor structure comprises at least two storage units stacked on a substrate. 10. The semiconductor structure according to claim 1, wherein the semiconductor channel material at least contains one or more of indium gallium zinc oxide, indium tungsten oxide or indium tin oxide; and the semiconductor channel is used to form the channel of the junctionless transistor. 11. The semiconductor structure according to claim 1, wherein in the direction from the substrate to the metal bit line, the semiconductor channel comprises a first doped region, a channel region and a second doped region, which are arranged in series; wherein the first doped region is electrically connected to the metal bit line; the word line is located around the channel area; and the first lower electrode layer is in contact with a side of the second doped region located away from the channel region. 12. Semiconductor structure according to claim 1, in which the line of words contains: a dielectric gate layer surrounding the entire surface of the side wall of the semiconductor channel; And a conductive gate layer located around a partial region of the semiconductor channel, wherein the dielectric gate layer is located between the semiconductor channel and the conductive gate layer. 13. A method for manufacturing a semiconductor structure, including: providing the basis; formation based on a storage block, including: providing a first dielectric layer and a metal bit line disposed in the first dielectric layer, the first dielectric layer exposing a surface of the metal bit line; forming a semiconductor channel located on a partial surface of the metal bit line, the semiconductor channel facing the bottom surface of the metal bit line and electrically connected to the metal bit line; forming a line of words, wherein the line of words is located around a partial region of the semiconductor channel; forming a second dielectric layer, wherein the second dielectric layer is located between the metal bit line and the word line, and is also located on the word line side away from the base; forming a first lower electrode layer, the first lower electrode layer being in contact with an upper surface of the semiconductor channel; forming a second lower electrode layer, the second lower electrode layer being located on an upper surface of the first lower electrode layer; forming an upper electrode layer, the upper electrode layer being located on an upper surface of the second lower electrode layer and surrounding the first lower electrode layer and the second lower electrode layer; And forming a dielectric layer of the capacitor, wherein the dielectric layer of the capacitor is located between the upper electrode layer and the first lower electrode layer, and is also located between the upper electrode layer and the second lower electrode layer. 14. The manufacturing method according to claim 13, according to which the formation of the first lower electrode layer, the second lower electrode layer, the dielectric layer of the capacitor and the upper electrode layer includes: forming a first lower electrode layer, wherein an upper surface of the first lower electrode layer comprises a central region and a peripheral region surrounding the central region; forming a first capacitor dielectric film, the first capacitor dielectric film covering an upper surface and side surfaces of the first lower electrode layer; forming a first upper electrode layer, the first upper electrode layer surrounding the first lower electrode layer, and the first capacitor dielectric film being disposed between the first upper electrode layer and the first lower electrode layer; removing the first dielectric film of the capacitor located in the central region to expose the upper surface of the first lower electrode layer in the central region, wherein the first dielectric film of the capacitor located on the side surfaces of the first lower electrode layer is used as the first dielectric layer of the capacitor, and the remaining part of the first a capacitor dielectric film located on an upper surface of the first lower electrode layer is used as a second capacitor dielectric layer; forming a second lower electrode layer, the second lower electrode layer being in contact with an upper surface of the first lower electrode layer in a central region; And forming a third dielectric layer of the capacitor, the third dielectric layer of the capacitor covering the top surface and side surfaces of the second bottom electrode layer. 15. The manufacturing method according to claim 14, according to which the formation of the first dielectric film of the capacitor includes: forming a first capacitor parent dielectric film with a completely continuous surface, the first capacitor parent dielectric film also covering an upper surface and a side surface of the first lower electrode layer; And structuring the first capacitor base dielectric film to form a first capacitor dielectric film and a fourth capacitor dielectric layer, wherein the fourth capacitor dielectric layer is connected to a bottom surface of the first capacitor dielectric film and extends in a direction away from the axis of the first bottom electrode layer perpendicular to the base surface. 16. The manufacturing method according to claim 14, wherein in the direction from the base to the metal bit line, the semiconductor channel comprises a first doped region, a channel region and a second doped region, which are arranged in series; wherein the formation of the first lower electrode layer, the first dielectric film of the capacitor and the first upper electrode layer includes: forming a sacrificial layer on a side of a second doped region located away from the channel region, wherein a first through hole is provided in the sacrificial layer to penetrate the sacrificial layer and expose the second doped region; forming a first lower electrode layer filling the first through hole; removing the sacrificial layer and forming a first dielectric film of the capacitor; forming a first insulating layer covering the first dielectric film of the capacitor, the first insulating layer exposing an upper surface of the first dielectric film of the capacitor; structuring the first insulating layer to form a second through-hole surrounding the first lower electrode layer, the second through-hole exposing the side surfaces of the first dielectric film of the capacitor; And forming a first upper electrode layer filling the second through hole. 17. The manufacturing method of claim 14, wherein before forming the first lower electrode layer, the method also includes: forming a fourth dielectric capacitor layer on the second dielectric layer, the fourth dielectric capacitor layer having an opening penetrating the fourth dielectric capacitor layer; and in the process of forming the first lower electrode layer, the first lower electrode layer fills this opening.