CN114927497A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN114927497A
CN114927497A CN202210133314.3A CN202210133314A CN114927497A CN 114927497 A CN114927497 A CN 114927497A CN 202210133314 A CN202210133314 A CN 202210133314A CN 114927497 A CN114927497 A CN 114927497A
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Prior art keywords
layer
planarization
passivation layer
top surface
metal pad
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CN202210133314.3A
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陈怡秀
邱文智
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN114927497A publication Critical patent/CN114927497A/zh
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Abstract

方法包括：形成第一钝化层；在第一钝化层上方形成金属焊盘；在金属焊盘上方形成具有平坦顶面的平坦化层；以及对平坦化层进行图案化以形成第一开口。金属焊盘的顶面通过第一开口露出。该方法还包括形成延伸至第一开口中的聚合物层，以及对聚合物层进行图案化以形成第二开口。金属焊盘的顶面通过第二开口露出。本申请的实施例还涉及半导体结构及其形成方法。

Description

半导体结构及其形成方法
技术领域
本申请的一些实施例涉及半导体结构及其形成方法。
背景技术
在集成电路的形成中，诸如晶体管的集成电路器件形成在晶圆中的半导体衬底的表面处。然后在集成电路器件上方形成互连结构。金属焊盘形成在互连结构上方并电耦合至互连结构。钝化层和聚合物层形成在金属焊盘上方，金属焊盘通过钝化层和聚合物层中的开口暴露。
发明内容
本申请的一些实施例提供了一种形成半导体结构的方法，包括：形成第一钝化层；在所述第一钝化层上方形成金属焊盘；在所述金属焊盘上方形成包括平坦顶面的平坦化层；对所述平坦化层进行图案化，以形成第一开口，其中，所述金属焊盘的顶面通过所述第一开口露出；形成延伸至所述第一开口中的聚合物层；以及对所述聚合物层进行图案化，以形成第二开口，其中，所述金属焊盘的所述顶面通过所述第二开口露出。
本申请的另一些实施例提供了一种半导体结构，包括：第一钝化层；金属焊盘，位于所述第一钝化层上方；平坦化层，其至少一部分位于所述金属焊盘上方，其中，所述平坦化层包括平坦顶面和非平坦底面；第二钝化层，位于所述金属焊盘和所述第一钝化层上方；以及聚合物层，包括在所述平坦化层和所述第二钝化层上方的上部分，其中，所述聚合物层延伸至所述平坦化层和所述第二钝化层中的开口中以接触所述金属焊盘。
本申请的又一些实施例提供了一种半导体结构，包括：第一钝化层；导电部件，包括延伸至所述第一钝化层中的导电通孔和位于所述第一钝化层上方的导电焊盘；第二钝化层，包括位于所述第一钝化层上方并与所述第一钝化层接触的第一部分，和位于所述导电焊盘上方并与所述导电焊盘接触的第二部分，其中，所述第二部分包括第一顶面；平坦化层，位于所述第二钝化层的所述第一部分上方并与所述第二钝化层的所述第一部分接触，其中，所述平坦化层包括与所述第一顶面共面的第二顶面；以及聚合物层，包括位于所述导电焊盘上方并接触所述导电焊盘的一部分。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图12、图13A、图13B和图14示出根据一些实施例的封装组件的形成中的中间阶段的截面图。
图15至图20示出根据一些实施例的封装组件的形成中的中间阶段的截面图。
图21至图25示出根据一些实施例的封装组件的形成中的中间阶段的截面图。
图26至图30示出根据一些实施例的封装组件的形成中的中间阶段的截面图。
图31至图35示出根据一些实施例的封装组件的形成中的中间阶段的截面图。
图36示出根据一些实施例的两个封装组件的面对背接合。
图37示出根据一些实施例的两个封装组件的面对面接合。
图38和图39示出根据一些实施例的具有钝化结构和接合结构的管芯堆叠件。
图40、图41和图42示出根据一些实施例的封装组件的使用。
图43示出根据一些实施例的用于形成封装组件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，提供了包括钝化结构、接合结构的封装组件及其形成方法。封装组件包括金属焊盘、金属焊盘上的钝化层以及钝化层上的聚合物层。在聚合物层形成于其上之前形成平坦的顶面，以使得聚合物层的顶面更加平坦。本文讨论的实施例将提供实例，以使得能够进行或使用本发明的主题，并且本领域技术人员将容易理解可进行同时保持在不同实施例的预期范围内的修改。贯穿各个视图和说明性实施例，相似的参考标号用于指示相似的元件。尽管方法实施例可被讨论为以特定顺序执行，但其他方法实施例可以任何逻辑顺序执行。
图1至图12、图13A、图13B和图14示出根据本发明的一些实施例的包括钝化结构和接合结构的封装组件的形成中的中间阶段的截面图。也在图43所示的工艺流程中示意性地反映对应工艺。
图1示出集成电路器件20的截面图。根据本发明的一些实施例，器件20可以是或可包括器件晶圆，该器件晶圆包括有源器件和可能的无源器件，它们被表示为集成电路器件26。器件20可在其中包括多个芯片22，示出了芯片22中的一个。根据本发明的可选的实施例，器件20是中介层晶圆，该中介层晶圆不含有源器件并可包括也可不包括无源器件。根据本发明的又一可选的实施例，器件20是或包括封装衬底带，该封装衬底带包括无芯封装衬底或其中具有芯的芯封装衬底。在后续讨论中，器件晶圆用作器件20的实例，并且器件20也可被称为晶圆20。本发明的实施例还可应用于中介层晶圆、封装衬底、封装件等。
根据本发明的一些实施例，晶圆20包括半导体衬底24和形成在半导体衬底24的顶面处的部件。半导体衬底24可由晶体硅、晶体锗、硅锗、碳掺杂硅或诸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等III-V族化合物半导体形成或可包括以上材料。半导体衬底24也可以是体半导体衬底或绝缘体上半导体(SOI)衬底。浅沟槽隔离(STI)区(未示出)可以形成在半导体衬底24中，以隔离半导体衬底24中的有源区。尽管未示出，但是可以(或可以不)形成延伸至半导体衬底24中的贯穿通孔，其中，贯穿通孔用于将晶圆20的相对侧上的部件相互电耦合。
根据本发明的一些实施例，晶圆20包括集成电路器件26，该集成电路器件形成在半导体衬底24的顶面处。根据一些实施例，集成电路器件26可包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。此处未示出集成电路器件26的细节。根据可选的实施例，晶圆20用于形成中介层(不含有源器件)，并且衬底24可以是半导体衬底或介电衬底。
层间电介质(ILD)28形成在半导体衬底24上方并填充集成电路器件26中晶体管(未示出)的栅极堆叠件之间的空间。根据一些实施例，ILD 28由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)、氟掺杂硅酸盐玻璃(FSG)、氧化硅、氮化硅、氮氧化硅(SiOxNy)、低k介电材料等形成。ILD 28可使用旋涂、流动化学气相沉积(FCVD)等来形成。根据本发明的一些实施例，使用诸如等离子增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)等沉积方法来形成ILD 28。
接触插塞30形成在ILD 28中，并用于将集成电路器件26电连接至上面的金属线和通孔。根据本发明的一些实施例，接触插塞30由选自钨、铝、铜、钛、钽、氮化钛、氮化钽、其合金和/或其多层的导电材料形成或包括以上材料。接触插塞30的形成可包括在ILD 28中形成接触开口、将一种或多种导电材料填充至接触开口中以及执行平坦化工艺(诸如化学机械抛光(CMP)工艺或机械研磨工艺)以使接触插塞30的顶面和ILD 28的顶面齐平。
互连结构32驻留在ILD 28和接触插塞30上方。互连结构32包括金属线34和通孔36，金属线34和通孔36形成在介电层38(也称为金属间电介质(IMD))中。下面将同一层的金属线统称为金属层。根据本发明的一些实施例，互连结构32包括多个金属层，金属层包括通过贯穿通孔36互连的金属线34。金属线34和通孔36可由铜或铜合金形成，也可由其他金属形成。根据本发明的一些实施例，介电层38由低k介电材料形成。例如，低k介电材料的介电常数(k值)可低于约3.0。介电层38可包括含碳的低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等。根据本发明的一些实施例，形成介电层38包括在介电层38中沉积含成孔剂的介电材料，然后执行固化工艺以驱除成孔剂，因此剩余的介电层38是多孔的。
在介电层38中形成金属线34和通孔36可包括单镶嵌工艺和/或双镶嵌工艺。在用于形成金属线或通孔的单镶嵌工艺中，首先在介电层38中的一个中形成沟槽或通孔开口，然后用导电材料填充沟槽或通孔开口。然后执行诸如CMP工艺的平坦化工艺以去除高于介电层顶面的导电材料的过量部分，从而在对应沟槽或通孔开口中留下金属线或通孔。在双镶嵌工艺中，沟槽和通孔开口都形成在介电层中，通孔开口位于沟槽下方并连接至沟槽。然后将导电材料填充至沟槽和通孔开口中以分别形成金属线和通孔。导电材料可包括扩散阻挡层和扩散阻挡层上方的含铜金属材料。扩散阻挡层可包括钛、氮化钛、钽、氮化钽等。
金属线34包括顶部导电(金属)部件，诸如金属线、金属焊盘或顶部介电层(表示为介电层38A)中的通孔(表示为34A)，该顶部介电层是介电层38的顶层。根据一些实施例，介电层38A由类似于介电层38中的下介电层的材料的低k介电材料形成。根据其他实施例，介电层38A由非低k介电材料形成，该材料可包括氮化硅、非掺杂硅酸盐玻璃(USG)、氧化硅等。介电层38A也可具有多层结构，例如包括两个USG层和其之间的氮化硅层。顶金属部件34A也可由铜或铜合金形成，并可具有双镶嵌结构或单镶嵌结构。介电层38A有时被称为顶部介电层。顶部介电层38A和顶部介电层38A正下方的下面的介电层38可形成为单个连续介电层，或可使用彼此不同的工艺形成为不同的介电层，和/或可以有彼此不同的材料形成。
钝化层40(有时称为passivation-1或pass-1)形成在互连结构32上方。在如图43所示的工艺流程200中，相应工艺被示出为工艺202。根据一些实施例，钝化层40由介电常数等于或大于氧化硅的介电常数的非低k介电材料形成。钝化层40可由无机介电材料形成或包括无机介电材料，该无机介电材料可包括选自但不限于氮化硅(SiNx)、氧化硅(SiO2)、氮氧化硅(SiONx)、碳氮氧化硅(SiOCx)、碳氮化硅(SiCN)等、其组合和/或其多层的材料。值“x”表示相对原子比。根据一些实施例，钝化层40包括由SiN或SiCN形成或包括SiN或SiCN的下子层(厚度介于约
Figure BDA0003501720420000061
与约
Figure BDA0003501720420000062
之间的范围内)以及由SiO2形成或包括SiO2的上层(厚度介于约
Figure BDA0003501720420000063
与约
Figure BDA0003501720420000064
之间的范围内)。根据一些实施例，顶部介电层38A的顶面与金属线34A的顶面是共面的。因此，钝化层40可以是平坦层。根据可选的实施例，顶部导电部件突出高于顶部介电层38A的顶面，并且钝化层40是非平坦的。
参考图2，钝化层40在蚀刻工艺中被图案化以形成开口42。在如图43所示的工艺流程200中，相应工艺被示出为工艺204。蚀刻工艺可包括干蚀刻工艺，包括形成图案化的蚀刻掩模(未示出)，诸如图案化光刻胶，然后蚀刻钝化层40。然后去除图案化蚀刻掩模。金属线/焊盘34A通过开口42暴露。
图3示出金属晶种层44的沉积。在如图43所示的工艺流程200中，相应工艺被示出为工艺206。根据一些实施例，金属晶种层44包括钛层和钛层上方的铜层。根据可选的实施例，金属晶种层44包括与钝化层40接触的铜层。可使用物理气相沉积(PVD)、化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)等来执行沉积工艺。
图4示出图案化镀覆掩模46的形成。在如图43所示的工艺流程200中，相应工艺被示出为工艺208。根据一些实施例，镀覆掩模46由光刻胶形成，因此可以可选地称为光刻胶46。开口48形成在图案化镀覆掩模46中以露出金属晶种层44。
图5示出将导电材料(部件)52镀覆至开口48中和金属晶种层44上。在如图43所示的工艺流程200中，相应工艺被示出为工艺210。根据本发明的一些实施例，导电部件52的形成包括镀覆工艺，该镀覆工艺可包括电化学镀覆工艺、化学镀工艺等。导电部件52可包括铝铜、铜、铝、镍、钨等或其合金。根据一些实施例，导电部件52包括铜并不含铝。
接下来，去除图5所示的光刻胶(镀覆掩模)46，并且在图6中示出所得结构。在后续工艺中，执行蚀刻工艺以去除金属晶种层44的未被覆盖的导电部件52保护的部分。在如图43所示的工艺流程200中，相应工艺被示出为工艺212。在图7中示出所得结构。在整个说明书中，导电部件52和对应的下面的金属晶种层44统称为再分布线(RDL)54。RDL 54可包括延伸至钝化层40中的通孔54V和钝化层40上方的金属焊盘54P。
参考图8，沉积钝化层56。在如图43所示的工艺流程200中，相应工艺被示出为工艺214。钝化层56(有时称为passivation-2或pass-2)形成为毯式层。根据一些实施例，钝化层56由无机介电材料形成或包括无机介电材料，该无机介电材料可包括但不限于氮化硅、氧化硅、氮氧化硅、碳氧化硅等、其组合或其多层。根据一些实施例，钝化层56包括由SiO2形成或包括SiO2的下子层(厚度介于约
Figure BDA0003501720420000071
(因此不形成下子层)与约
Figure BDA0003501720420000072
之间的范围内)以及由SiN、SiCN、SiON等形成或包括SiN、SiCN、SiON等的上层(厚度介于约
Figure BDA0003501720420000073
与约
Figure BDA0003501720420000074
之间的范围内)。沉积可通过诸如ALD、CVD等共形沉积工艺来执行。因此，钝化层56的垂直部分与水平部分具有相同的厚度或基本相同的厚度，例如，变化小于约10％。
参考图9，例如使用光刻工艺来通过蚀刻对钝化层56进行图案化。因此暴露金属焊盘54P。在如图43所示的工艺流程200中，相应工艺被示出为工艺216。接下来，探测晶圆20以确定诸如器件管芯的封装组件是否有缺陷。在如图43所示的工艺流程200中，相应工艺被示出为工艺218。可通过将包括多个探针引脚的探针卡与晶圆20的金属焊盘接触以确定对应封装组件的电性能来执行探测。探针引脚53是探针卡的一部分，并与金属焊盘54P接触。探测可能导致不期望地产生凸块55(探测标记)。
参考图10，沉积平坦化层58。在如图43所示的工艺流程200中，相应工艺被示出为工艺220。平坦化层58可由SiO2形成或可包括SiO2，同时也可使用诸如SiOC、SiON等其他介电材料。使用沉积方法来形成平坦化层58以具有平坦顶面，该沉积方法可在沉积时实现平坦的顶面。因此，沉积方法是非共形的，并可以是自底向上的沉积方法，诸如等离子增强化学气相沉积(PECVD)、高密度等离子化学气相沉积(HDPCVD)、旋涂、流动化学气相沉积(FCVD)等。沉积时的平坦化层58的顶面(在没有经过任何平坦化工艺的情况下)是平坦的。例如，贯穿整个晶圆20的平坦化层58的最高点和最低点可具有小于约
Figure BDA0003501720420000081
(0.5μm)的高度差。为了使平坦化层58平坦且高度差较小，厚度T1可大于约0.8μm，并且可介于约2.5μm与约7μm之间的范围内。另一方面，由于下面的部件的拓扑结构，平坦化层58的底面是非共形的。
根据一些实施例，在平坦化层58的沉积工艺与隔离层60的沉积之间不对平坦化层58执行平坦化工艺。根据可选的实施例，在沉积隔离层60之前对平坦化层58执行平坦化工艺。
进一步参考图10，隔离层60沉积在平坦化层58上并与平坦化层58接触。在如图43所示的工艺流程200中，相应工艺被示出为工艺222。根据一些实施例，隔离层60由具有良好的湿气阻挡和隔离能力以防止诸如湿气的有害物质渗透的材料形成或包括该材料。例如，隔离层60可由SiN、SiCN等形成或包括SiN、SiCN等。根据一些实施例，隔离层60使用诸如CVD、ALD等共形沉积工艺来形成，并且因此隔离层60是共形的。由于平坦化层58的顶面是平坦的，因此隔离层60的顶面也是平坦的。根据又一可选的实施例，不形成隔离层60，并且随后施加的聚合物层68与平坦化层58接触。
参考图11，形成可包括图案化光刻胶的图案化蚀刻掩模62。执行蚀刻工艺以蚀刻穿过隔离层60、平坦化层58和可能的钝化层56，以使得形成开口66，从而再次暴露金属焊盘54P。在如图43所示的工艺流程200中，相应工艺被示出为工艺224。根据一些实施例，蚀刻工艺通过反应性离子蚀刻(RIE)工艺执行。
参考图12，分配聚合物层68。在如图43所示的工艺流程200中，相应工艺被示出为工艺226。由于平坦化层58的平坦顶面，整个晶圆20的聚合物层68的顶面比未形成平坦化层58的情况更平坦。然后对聚合物层68进行图案化，从而形成开口70。在如图43所示的工艺流程200中，相应工艺被示出为工艺228。聚合物层68中的聚合物可以是感光的或非感光的。用于形成聚合物层68的感光聚合物可包括聚酰亚胺、聚苯并噁唑(PBO)、苯并环丁烯(BCB)等。当聚合物层68为感光时，对它的图案化可包括对聚合物层68执行曝光工艺，然后使聚合物层68显影以形成开口70。根据聚合物层68是非感光的可选的实施例，例如，当聚合物层68包括非感光环氧树脂/聚合物时，对聚合物层68的图案化可包括在聚合物层68上方施加光刻胶并对光刻胶进行图案化，并使用图案化光刻胶来蚀刻聚合物层68以限定开口的图案。由于平坦化层58的平坦顶面，聚合物层68的顶面是平坦的而无需增加聚合物层68的厚度。例如，根据一些实施例，聚合物层68的厚度可大于约2,000nm(2μm)，并且可小于约10,000nm(10μm)。
图13A和图13B示出在开口70中形成接合部件72。在如图43所示的工艺流程200中，相应工艺被示出为工艺230。根据一些实施例，如图13A所示，接合部件72包括粘附层72A和粘附层72A上的金属材料72B。粘附层72A可包括Ti、TiN、Ta、TaN等。金属材料72B可包括铜或铜合金、钯、镍等或其复合层。接合部件72可在化学机械抛光(CMP)工艺中平坦化，以使得其顶面与聚合物层68的顶面共面。根据可选的实施例，接合部件72包括高于聚合物层68的顶面的部分，该部分由虚线72’表示。
根据可选的实施例，如图13B所示，接合部件72包括焊料区域，该焊料区域可通过镀覆然后回流焊料、或通过将焊料区域放置到开口70中然后回流焊料区域来形成。
在后续工艺中，如图13A和图13B所示，晶圆20被切割，例如，沿着划线74锯切，以形成单个器件管芯22。在如图43所示的工艺流程200中，相应工艺被示出为工艺232。器件管芯22也被称为器件22或封装组件22，因为器件22可用于接合至其他封装组件以形成封装件。如前所述，器件22可以是器件管芯、中介层、封装衬底、封装件等。
参考图14，器件22与封装组件76接合以形成封装件78。在如图43所示的工艺流程200中，相应工艺被示出为工艺234。根据一些实施例，封装组件76是或包括中介层、封装衬底、印刷电路板、封装件等。封装组件76中的电连接件80可通过焊接区82接合至封装组件76。底部填充剂84分配在器件22与封装组件76之间。
图15至图20、图21至图25、图26至图30和图31至图35示出根据本发明的可选的实施例的钝化层和接合结构的形成中的中间阶段的截面图。除非另有说明，否则这些实施例中的部件的材料和形成工艺与图1至图12、图13A、图13B和图14所示的前述实施例中相同的参考数字表示的相同部件基本相同。关于图15至图20、图21至图25、图26至图30和图31至图35所示的部件的形成工艺和材料的细节因此可在前述实施例的讨论中找到。
图15至图20示出根据一些实施例的用于形成平坦钝化结构的工艺。这些实施例类似于图1至图12、图13A、图13B和图14所示的实施例，不同之处在于未形成如图14所示的隔离层60，并且在平坦化工艺中对平坦化层58进行平坦化。
这些实施例的初始工艺与图1至图8所示的相同。接下来，如图15所示，使用探针引脚53来执行探测工艺，该工艺与图9所示的探测工艺相同，并且在本文不再重复细节。可产生探测标记55。接下来，参考图16，沉积平坦化层58。平坦化层58可由SiO2形成或可包括SiO2，同时也可使用诸如SiOC、SiON等其他介电材料。平坦化层58也可由对诸如湿气的有害物质具有隔离能力的材料形成，该材料可包括SiN、SiCN等。因此，平坦化层58可集成平坦化层和隔离层两者的功能。平坦化层58可使用产生平坦顶面的选定沉积方法来形成。例如，沉积方法可包括非共形沉积方法，其也可以是自底向上沉积方法，诸如PECVD、HDPCVD、旋涂、流动化学气相沉积(FCVD)等。在沉积之后，平坦化层58不被平坦化，而它也可被平坦化以具有更平坦的表面。
接下来，如图17所示，在蚀刻工艺中对平坦化层58进行图案化，该工艺使用光刻掩模执行。在蚀刻工艺中，钝化层56也可被图案化，使得平坦化层58的边缘与钝化层56的对应边缘垂直对准。
参考图18，施加聚合物层68。由于平坦化层58的顶面是平坦的，因此聚合物层68的顶面比未形成平坦化层58的情况更平坦。接下来，如图19所示，聚合物层68被图案化以形成开口70，例如，在聚合物层68感光时通过曝光工艺和显影工艺。否则，当聚合物层68不感光时，聚合物层68通过光刻工艺被蚀刻。
图20示出根据一些实施例的接合部件72。根据可选的实施例，接合部件72可以是焊料区域，如图13B所示。在后续工艺中，晶圆20被切割成分立器件22。器件22可接合至另一封装组件76，如图14所示。
图21至图25示出根据一些实施例的用于形成平坦钝化结构的工艺。这些实施例类似于图1至图12、图13A、图13B和图14所示的实施例，不同之处在于平坦化层58被平坦化，并且未形成如图14所示的隔离层60。
这些实施例的初始工艺与图1至图8所示的相同。接下来，如图21所示，执行探测工艺，该工艺与图9所示的探测工艺相同，并且在本文不再重复细节。可产生探测标记55。接下来，参考图22，沉积平坦化层58。平坦化层58可包括SiO2或可由SiO2形成，同时也可使用诸如SiOC、SiON等其他介电材料。平坦化层58也可由对诸如湿气的有害物质具有隔离能力的材料形成，该材料可包括SiN、SiCN等。因此，平坦化层58集成平坦化层和隔离层两者的功能。平坦化层58通过诸如CVD、ALD等共形沉积工艺或者诸如PECVD、HDPCVD、旋涂、流动化学气相沉积(FCVD)等非共形沉积工艺来形成。
然后执行诸如化学机械抛光(CMP)工艺或机械抛光工艺等平坦化工艺以使平坦化层58的顶面和钝化层56的顶面齐平，如图23所示。由于平坦化工艺，平坦化层58的顶面和钝化层56的顶面都包含划痕，这些划痕是由于浆料在平坦化层58和钝化层56上的划痕而引起的平行浅凹槽。这可用于识别是否执行平坦化工艺。划痕位于平坦化层58和钝化层56表面的局部区域(不在非晶圆级)中，在不同的局部区域划痕的方向和深度可不同。如图24所示，然后形成蚀刻掩模71并对其图案化，并使用蚀刻掩模71以去除位于金属焊盘54P正上方的平坦化层58的部分。可使用蚀刻平坦化层58但不蚀刻钝化层56的蚀刻化学剂来执行蚀刻。因此，钝化层56可横向延伸超过平坦化层58的边缘。然后去除蚀刻掩模71。
参考图25，施加聚合物层68。由于平坦化层58和钝化层56的顶面是共面的，所以聚合物层68的顶面是平坦的。接下来，当聚合物层68感光时，例如通过曝光工艺和显影工艺来对聚合物层68进行图案化。否则，当聚合物层68不感光时，通过光刻工艺蚀刻聚合物层68。
图25还示出根据一些实施例的接合部件72的形成。根据可选的实施例，接合部件72可以是焊料区域，如图13B所示。在后续工艺中，晶圆20被切割成分立器件22。器件22可接合至另一封装组件76，如图14所示。
图26至图30示出根据一些实施例的用于形成平坦钝化结构的工艺。这些实施例类似于图1至图12、图13A、图13B和图14所示的实施例，不同之处在于通过平坦化工艺对平坦化层58进行了平坦化，并且未形成如图14所示的隔离层60。由于平坦化工艺，平坦化层58的顶面包括划痕，这些划痕是由于浆料在平坦化层58上的划痕而产生的平行浅凹槽。这可用于识别是否执行平坦化工艺。
这些实施例的初始工艺与图1至图8所示的相同。接下来，如图26所示，形成钝化层56并对其图案化。使用探针引脚53来执行探测工艺，该工艺与图9所示的探测工艺相同，并且在本文不再重复细节。可产生探测标记55。接下来，参考图27，沉积平坦化层58。平坦化层58可由SiO2形成或可包括SiO2，同时也可使用诸如SiOC、SiON等其他介电材料。平坦化层58也可由对诸如湿气的有害物质具有隔离能力的材料形成，该材料可包括SiN、SiCN等。因此，平坦化层58集成平坦化层和隔离层两者的功能。平坦化层58通过诸如CVD、ALD等共形沉积工艺或者诸如PECVD、HDPCVD、旋涂、流动化学气相沉积(FCVD)等非共形沉积工艺来形成。因此，平坦化层58的顶面可具有下层部件的拓扑结构，或可比下层部件更平坦。
然后执行平坦化工艺以使平坦化层58的顶面齐平，如图28所示。与图23所示的实施例不同，平坦化工艺在钝化层56的顶面之上停止，以使得在钝化层56的正上方留下钝化层58的层。接下来，参考图29，形成蚀刻掩模71并对其图案化，并使用蚀刻掩模71以去除平坦化层58的位于金属焊盘54P正上方的第一部分，同时使平坦化层58的位于金属焊盘54P正上方的第二部分未被去除。然后去除蚀刻掩模71。
参考图30，施加聚合物层68。由于平坦化层58的顶面是平坦的，因此聚合物层68的顶面比未形成平坦化层58的情况更平坦。接下来，当聚合物层68感光时，例如通过曝光工艺和显影工艺来对聚合物层68进行图案化。否则，当聚合物层68不感光时，通过光刻工艺蚀刻聚合物层68。
图30还示出根据一些实施例的接合部件72。根据可选的实施例，接合部件72可以是焊料区域，如图13B所示。在后续工艺中，晶圆20被切割成分立器件22。器件22可接合至另一封装组件76，如图14所示。
图31至图35示出根据一些实施例的用于形成平坦钝化结构的工艺。这些实施例类似于图1至图12、图13A、图13B和图14所示的实施例，不同之处在于在钝化层56形成之前执行探测，并且钝化层56形成在平坦化层58上方而不是下方。此外，未形成如图14所示的隔离层60。
这些实施例的初始工艺与图1至图7所示的相同。接下来，如图31所示，使用探针引脚53来执行探测工艺，该工艺与图9所示的探测工艺相同，并且在本文不再重复细节。可产生探测标记55。接下来，参考图32，沉积平坦化层58。平坦化层58可由SiO2形成或可包括SiO2，同时可使用诸如SiOC、SiON等其他介电材料。平坦化层58也可由对诸如湿气的有害物质具有隔离能力的材料形成，该材料可包括SiN、SiCN等。因此，平坦化层58集成平坦化层和隔离层两者的功能。平坦化层58通过诸如CVD、ALD等共形沉积工艺或者诸如PECVD、HDPCVD、旋涂、流动化学气相沉积(FCVD)等非共形沉积工艺来形成。
然后执行平坦化工艺以使平坦化层58的顶面齐平，如图32所示。由于平坦化工艺，平坦化层58的顶面包括划痕，这些划痕是由于浆料在平坦化层58上的划痕而产生的平行浅凹槽。这可用于识别是否执行平坦化工艺。虚线顶面58T1和58T2分别代表平坦化工艺之前和之后的平坦化层58的顶面。平坦化工艺在金属焊盘54P的顶面之上停止，以使得钝化层58的层留在金属焊盘54P正上方。
接下来，如图33所示，钝化层56通过共形沉积工艺沉积，同时也可采用非共形沉积工艺。由于钝化层58的顶面是平坦的，所以钝化层56的顶面是平坦的。
参考图34，蚀刻掩模71被形成和图案化，并用于去除钝化层56和平坦化层58的位于金属焊盘54P正上方的第一部分，同时使钝化层56和平坦化层58的位于金属焊盘正上方的第二部分54P未被去除。然后去除蚀刻掩模71。
参考图35，施加聚合物层68。由于钝化层56的顶面是平坦的，所以聚合物层68的顶面是平坦的。接下来，当聚合物层68感光时，例如通过曝光工艺和显影工艺来对聚合物层68进行图案化。否则，当聚合物层68不感光时，通过光刻工艺蚀刻聚合物层68。
图35还示出根据一些实施例的接合部件72。根据可选的实施例，接合部件72可以是焊料区域，如图13B所示。在后续工艺中，晶圆20被切割成分立器件22。器件22可接合至另一封装组件76，如图14所示。
图36和图37示出将器件22(如在前述实施例中形成)接合至另一器件22A-1以形成封装件86。根据一些实施例，器件22A-1是器件管芯，该器件管芯可包括半导体衬底124、互连结构132和半导体衬底124上方的接合结构134。在图36中，器件22的正面朝上，有源器件(图36未示出，参考图1中的集成电路器件26)形成在半导体衬底24的顶面处。示意性地示出前述实施例中呈现的介电层58/58/60/68，并且还示意性地示出前述实施例中呈现的金属焊盘54和接合部件72。在图36的实施例中，介电层58/58/60/68、金属焊盘54和接合部件72形成在器件22的正面上，并且接合是面对背接合。在图37的实施例中，介电层58/58/60/68和接合部件72形成在器件22的背面上，并且接合是面对面接合。
图38示出根据一些实施例的管芯堆叠件86的形成。管芯堆叠件86包括接合至器件22A-1至22A-n的器件22(如在前述实施例中形成)，整数n大于1。在图38中，接合部件72可包括如图13A所示的结构。
图39示出根据一些实施例的封装件86(包括管芯堆叠件)的形成。管芯堆叠件86包括接合至器件22A-1至22A-n的器件22(如在前述实施例中形成)。在图39中，接合部件72可包括如图13B所示的结构。
图40、图41和图42示出根据一些实施例的器件22和对应封装件86的使用和相应的应用。在图40中，封装件86(在其中包括器件22)接合至封装衬底88，并密封在可以是模塑料、模制底部填充剂等的密封剂90中。在图41中，封装件86(在其中包括器件22)接合至中介层92，该中介层进一步接合至封装衬底88。封装件86密封在密封剂90中，该密封剂可以是模塑料、模制底部填充剂等。在图42中，扇出再分布结构94形成在封装件86上。形成工艺可包括将封装件86(在其中包括器件22)密封在密封剂90中，将封装件86和密封剂90中的器件22平坦化直到露出接合部件72(图13A)为止，并形成扇出再分布结构94。
本发明的实施例具有一些有利特征。在常规接合结构中，聚合物层形成在非平坦介电层和金属焊盘上。由于所使用的聚合物的粘度较高，为了使聚合物层的顶面平坦以具有良好的晶圆对晶圆接合，聚合物需要非常厚。这会影响最终器件管芯的整体厚度。根据本发明的一些实施例，在施加对应聚合物之前，首先为介电层形成平坦的顶面。因此，对应聚合物的顶面可以是平坦的，而无需增加聚合物层的厚度。
根据本发明的一些实施例，方法包括：形成第一钝化层；在所述第一钝化层上方形成金属焊盘；在所述金属焊盘上方形成包括平坦顶面的平坦化层；对所述平坦化层进行图案化，以形成第一开口，其中，所述金属焊盘的顶面通过所述第一开口露出；形成延伸至所述第一开口中的聚合物层；以及对所述聚合物层进行图案化，以形成第二开口，其中，所述金属焊盘的所述顶面通过所述第二开口露出。根据实施例，所述结构还包括：在所述金属焊盘上沉积第二钝化层，其中，所述平坦化层沉积在所述第二钝化层上方；以及对所述平坦化层执行平坦化工艺。根据实施例，当所述第二钝化层的第一顶面露出并且当所述第二钝化层的第二顶面位于所述平坦化层之下时，停止所述平坦化工艺。根据实施例，所述第一顶面与所述金属焊盘重叠。根据实施例，当整个所述第二钝化层位于所述平坦化层之下时，停止所述平坦化工艺。根据实施例，所述结构还包括：在所述金属焊盘上沉积第二钝化层，其中，所述平坦化层沉积在所述第二钝化层上方，并且所述平坦化层沉积为具有所述平坦顶面和非平坦底面。根据实施例，在沉积所述平坦化层与分配所述聚合物层之间不执行平坦化工艺。根据实施例，所述结构还包括：在所述形成所述金属焊盘之后，并且在所述形成所述平坦化层之前，探测所述金属焊盘。根据实施例，所述第一钝化层和所述平坦化层中的每个是无机层。
根据本发明的一些实施例，结构包括：第一钝化层；金属焊盘，位于所述第一钝化层上方；平坦化层，其至少一部分位于所述金属焊盘上方，其中，所述平坦化层包括平坦顶面和非平坦底面；第二钝化层，位于所述金属焊盘和所述第一钝化层上方；以及聚合物层，包括在所述平坦化层和所述第二钝化层上方的上部分，其中，所述聚合物层延伸至所述平坦化层和所述第二钝化层中的开口中以接触所述金属焊盘。根据实施例，所述平坦化层位于所述第二钝化层上方。根据实施例，所述结构还包括位于所述平坦化层上方的共形介电层，其中，所述共形介电层和所述平坦化层由不同材料形成。根据实施例，所述平坦化层包括第一顶面，所述第二钝化层包括与所述第一顶面共面的第二顶面，并且其中，所述第二顶面的第一部分与所述金属焊盘重叠。根据实施例，所述第二顶面的第二部分从所述金属焊盘垂直偏移。根据实施例，整个所述第二钝化层位于所述平坦化层之下。根据实施例，所述平坦化层位于所述第二钝化层下面，并与所述金属焊盘接触。根据实施例，所述平坦化层包括面向所述开口的第一边缘，所述第二钝化层包括面向所述开口的第二边缘，并且其中，所述第一边缘和所述第二边缘彼此垂直对准。
根据本发明的一些实施例，结构包括：第一钝化层；导电部件，包括延伸至所述第一钝化层中的导电通孔和位于所述第一钝化层上方的导电焊盘；第二钝化层，包括位于所述第一钝化层上方并与所述第一钝化层接触的第一部分，和位于所述导电焊盘上方并与所述导电焊盘接触的第二部分，其中，所述第二部分包括第一顶面；平坦化层，位于所述第二钝化层的所述第一部分上方并与所述第二钝化层的所述第一部分接触，其中，所述平坦化层包括与所述第一顶面共面的第二顶面；以及聚合物层，包括位于所述导电焊盘上方并接触所述导电焊盘的一部分。根据实施例，整个所述平坦化层从所述导电焊盘垂直偏移。根据实施例，所述聚合物层与所述第一顶面和所述第二顶面均接触。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体结构的方法，包括：
形成第一钝化层；
在所述第一钝化层上方形成金属焊盘；
在所述金属焊盘上方形成包括平坦顶面的平坦化层；
对所述平坦化层进行图案化，以形成第一开口，其中，所述金属焊盘的顶面通过所述第一开口露出；
形成延伸至所述第一开口中的聚合物层；以及
对所述聚合物层进行图案化，以形成第二开口，其中，所述金属焊盘的所述顶面通过所述第二开口露出。
2.根据权利要求1所述的方法，还包括：
在所述金属焊盘上沉积第二钝化层，其中，所述平坦化层沉积在所述第二钝化层上方；以及
对所述平坦化层执行平坦化工艺。
3.根据权利要求2所述的方法，其中，当所述第二钝化层的第一顶面露出并且当所述第二钝化层的第二顶面位于所述平坦化层之下时，停止所述平坦化工艺。
4.根据权利要求3所述的方法，其中，所述第一顶面与所述金属焊盘重叠。
5.根据权利要求2所述的方法，其中，当整个所述第二钝化层位于所述平坦化层之下时，停止所述平坦化工艺。
6.根据权利要求1所述的方法，还包括：
在所述金属焊盘上沉积第二钝化层，其中，所述平坦化层沉积在所述第二钝化层上方，并且所述平坦化层沉积为具有所述平坦顶面和非平坦底面。
7.根据权利要求6所述的方法，其中，在沉积所述平坦化层与分配所述聚合物层之间不执行平坦化工艺。
8.根据权利要求1所述的方法，还包括：
在所述形成所述金属焊盘之后，并且在所述形成所述平坦化层之前，探测所述金属焊盘。
9.一种半导体结构，包括：
第一钝化层；
金属焊盘，位于所述第一钝化层上方；
平坦化层，其至少一部分位于所述金属焊盘上方，其中，所述平坦化层包括平坦顶面和非平坦底面；
第二钝化层，位于所述金属焊盘和所述第一钝化层上方；以及
聚合物层，包括在所述平坦化层和所述第二钝化层上方的上部分，其中，所述聚合物层延伸至所述平坦化层和所述第二钝化层中的开口中以接触所述金属焊盘。
10.一种半导体结构，包括：
第一钝化层；
导电部件，包括延伸至所述第一钝化层中的导电通孔和位于所述第一钝化层上方的导电焊盘；
第二钝化层，包括位于所述第一钝化层上方并与所述第一钝化层接触的第一部分，和位于所述导电焊盘上方并与所述导电焊盘接触的第二部分，其中，所述第二部分包括第一顶面；
平坦化层，位于所述第二钝化层的所述第一部分上方并与所述第二钝化层的所述第一部分接触，其中，所述平坦化层包括与所述第一顶面共面的第二顶面；以及
聚合物层，包括位于所述导电焊盘上方并接触所述导电焊盘的一部分。
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