CN114927420A - Method for improving anti-static capability of fast recovery diode - Google Patents
Method for improving anti-static capability of fast recovery diode Download PDFInfo
- Publication number
- CN114927420A CN114927420A CN202210536682.2A CN202210536682A CN114927420A CN 114927420 A CN114927420 A CN 114927420A CN 202210536682 A CN202210536682 A CN 202210536682A CN 114927420 A CN114927420 A CN 114927420A
- Authority
- CN
- China
- Prior art keywords
- recovery diode
- fast recovery
- type
- improving
- platinum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011084 recovery Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 25
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 26
- 238000001259 photo etching Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000005260 corrosion Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000001556 precipitation Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 230000017525 heat dissipation Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method for improving the anti-static capability of a fast recovery diode, belongs to the technical field of semiconductor manufacturing processes, and aims to solve the technical problems that in the prior art, the effective concentration of a device is reduced due to the compensation doping effect after platinum doping, the conduction resistance of a base region is increased, the electrostatic current is not discharged easily, and the electrostatic capability of the device is reduced. The main region of the invention is provided with the antistatic hole which can increase the perimeter of the PN junction and provide a static discharge channel. The contact hole is used for realizing interconnection of the metal connecting wire and the PN junction, the platinum doped region is used for realizing minority carrier lifetime control, and the switching speed of the device is improved. After the anode is formed, the anode is connected with the packaging shell through an aluminum wire, and finally the antistatic capability of the fast recovery diode is improved. Secondly, the area of the main region is designed to be beneficial to heat dissipation of the device and improve reliability; then, 8 antistatic holes with certain sizes are added, the effective PN junction is increased by about 1 time, and the electrostatic discharge capacity is effectively improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing processes, and relates to a method for improving the anti-static capacity of a fast recovery diode.
Background
The fast recovery diode adopts a silicon-based epitaxial PIN structure, and platinum is introduced into the device to form a properly distributed recombination center in order to improve the switching speed, so that the minority carrier lifetime is effectively shortened. However, the effective concentration of the device is reduced due to the compensation doping effect after the platinum doping, so that the on-resistance of the base region is increased, the electrostatic current is not discharged easily, and the electrostatic capacity of the device is reduced.
Disclosure of Invention
The invention aims to solve the technical problems of the prior art that the effective concentration of a device is reduced due to the compensation doping effect after platinum doping, so that the conduction resistance of a base region is increased, the electrostatic current is not easy to discharge, and the electrostatic capacity of the device is reduced, and provides a method for improving the anti-electrostatic capacity of a fast recovery diode.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
the invention provides a method for improving the anti-static capability of a fast recovery diode, which comprises the following steps:
s1, forming an N-type epitaxial layer on an N-type silicon substrate, photoetching a dielectric layer of the silicon N-type epitaxial layer, and forming a main junction region and a terminal region on the photoetching dielectric layer by a corrosion or etching method; wherein the main junction region is provided with an antistatic hole;
s2, performing P-type ion implantation and high-temperature annealing in the main region and the terminal region to form a P-type doped region and a P-type dielectric layer;
s3, forming a contact hole area on the P-type dielectric layer through photoetching and etching, and annealing the platinum layer at high temperature to form a platinum doped area after forming a platinum layer on the back of the N-type silicon substrate;
s4, etching off the redundant platinum layer on the back of the N-type silicon substrate, depositing or evaporating metal on the front of the N-type silicon substrate, and forming an anode through annealing after photoetching and etching; and depositing on the back of the N-type silicon substrate to form a cathode, thus obtaining the fast recovery diode with the antistatic capability.
Preferably, a dielectric layer is formed on the surface of the N-type epitaxial layer through oxidation or precipitation; the dielectric layer is SiO 2 And (3) a layer.
Preferably, the resistivity of the N type silicon substrate is 0.001. omega. cm to 0.004. omega. cm.
Preferably, the resistivity of the N type epitaxial layer is 5 Ω & cm to 6 Ω & cm.
Preferably, the main area is 2900 μm × 2900 μm.
Preferably, the number of the antistatic holes is 8, and the size of the antistatic holes is 453 μm × 453 μm.
Preferably, the impurity for the P-type ion implantation is boron, the implantation energy is 50keV-90keV, and the implantation dosage is 1E 14-1E 16 per square centimeter.
Preferably, the thickness of the evaporated platinum is 30 ± 3 nm.
Preferably, the metal of the anode is AL.
Preferably, the metal of the cathode is Cr, Ni or Au.
Compared with the prior art, the invention has the following beneficial effects:
the core of the method for improving the anti-static capability of the fast recovery diode is that an anti-static hole design structure is adopted, the perimeter of a PN junction is increased, more channels are provided for static leakage, and the anti-static capability of a device can reach more than 4000V. Specifically, the main junction area is provided with the antistatic holes, the perimeter of the PN junction can be increased through the antistatic holes, and an electrostatic discharge channel is provided. The contact hole is used for realizing interconnection of the metal connecting wire and the PN junction, the platinum doped region is used for realizing minority carrier lifetime control, and the switching speed of the device is improved. After the anode is formed, the anode is connected with the packaging shell through an aluminum wire, and finally the antistatic capability of the fast recovery diode is improved.
Further, the resistivity of the N type silicon substrate is set to be small and set to 0.001 to 0.004 Ω cm, and the contact resistance is reduced to reduce the forward voltage drop.
Furthermore, the resistivity of the N type epitaxial layer is in the range of 5. omega. cm to 6. omega. cm, and the withstand voltage of the device is secured to be 200V to 300V.
Further, according to the current capacity of 3A/mm 2 The main area is designed to be 2900 mu m multiplied by 2900 mu m, which is beneficial to heat dissipation of the device and improvement of reliability.
Furthermore, the perimeter of the original PN junction is 4x2900 μm, 8 453 μm x 453 μm antistatic holes are added, the effective PN junction is increased by about 1 time, and the electrostatic discharge capacity is effectively improved.
Furthermore, the impurity of the P-type ion implantation is boron, the implantation energy is 50keV-90keV, the implantation dosage is 1E 14-1E 16 per square centimeter, the concentration of emitted majority carriers of the main structure can be improved, and the forward voltage drop of the device is effectively reduced by utilizing the PN junction large implantation modulation effect.
Further, the device platinum doping concentration reaches about 10 15 Per cm 2 The minority carrier lifetime is effectively controlled, and meanwhile, the thickness of the platinum layer cannot be too thick, otherwise, the electric leakage is increased due to too much platinum doping. The aluminum is used as the electrode, which is beneficial to the realization of the process.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
FIG. 1 is a flow chart of the present invention for improving the anti-static capability of a recovery diode.
Fig. 2 is a diagram based on photolithography in accordance with the present invention.
Fig. 3 is a graph based on implantation and push junction of the present invention.
FIG. 4 is a diagram of a lithographic contact hole of the present invention.
FIG. 5 is a diagram of platinum doping according to the present invention.
FIG. 6 is a photo-lithographic drawing of platinum wire according to the present invention.
Fig. 7 is a diagram of the front and back side metallization of an N-type silicon substrate of the present invention.
Wherein: 1-a termination region; 2-main junction; 3-a dielectric layer of an epitaxial layer; 4-doping layer; 5-a dielectric layer; 6-contact hole area; a 7-platinum doped region; 8-an anode; 9-cathode.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is usually arranged when the product of the present invention is used, the description is merely for convenience and simplicity, and the indication or suggestion that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, cannot be understood as limiting the present invention. Furthermore, the terms "first," "second," and the like are used solely to distinguish one from another, and are not to be construed as indicating or implying relative importance.
Furthermore, the term "horizontal", if present, does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the embodiments of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" should be broadly construed and interpreted as including, for example, fixed connections, detachable connections, or integral connections; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The invention is described in further detail below with reference to the accompanying drawings:
the invention discloses a method for improving the anti-static capacity of a fast recovery diode, which comprises the following steps as shown in figure 1:
s1, forming an N-type epitaxial layer on an N-type silicon substrate, photoetching a dielectric layer 3 of the silicon N-type epitaxial layer, and forming a main region 2 and a terminal region 1 on the photoetching dielectric layer 3 by a corrosion or etching method; wherein, the main region 2 is provided with antistatic holes;
s2, performing P-type ion implantation and high-temperature annealing in the main region 2 and the terminal region 1 to form a P-type doped region 4 and a P-type dielectric layer 5;
s3, forming a contact hole area 6 on the P-type dielectric layer 5 through photoetching and etching; after a platinum layer is formed on the back surface of the N-type silicon substrate, annealing the platinum layer at high temperature to form a platinum doped region 7;
s4, etching off the redundant platinum layer on the back of the N-type silicon substrate, depositing or evaporating metal on the front of the N-type silicon substrate, and forming an anode 8 by annealing after photoetching and etching; and depositing on the back of the N-type silicon substrate to form a cathode 9, thus obtaining the fast recovery diode with the antistatic capability.
As shown in fig. 2 to 7, the specific steps are as follows:
1) forming an N-type epitaxial layer on an N-type silicon substrate, forming a dielectric layer 3 with a certain thickness on the surface of the N-type epitaxial layer through oxidation or precipitation, photoetching the dielectric layer 3 of the silicon N-type epitaxial layer, and forming a main junction 2 and a terminal region 1 on the photoetching dielectric layer 3 through a corrosion or etching method; wherein the main region 2 has antistatic holes, and the dielectric layer 3 is SiO 2 A layer;
the resistivity of the N type silicon substrate is 0.001 to 0.004 Ω & cm. The N type silicon substrate is set to be small in resistivity of 0.001 to 0.004 Ω cm, and contact resistance is reduced to reduce a forward voltage drop.
The resistivity of the N type epitaxial layer is within the range of 5. omega. cm to 6. omega. cm, and the withstand voltage of the device is secured within the range of 200V to 300V.
According to current capacity 3A/mm 2 The area of the main region 2 is designed to be 2900 μm × 2900 μm, which is beneficial to heat dissipation and reliability improvement of the device.
The perimeter of the original PN junction is 4x2900 mu m, 8 453-mum antistatic holes are added, the effective PN junction is increased by about 1 time, and the electrostatic discharge capacity is effectively improved.
2) Performing P-type ion implantation and high-temperature annealing in the main region 2 and the terminal region 1 to form a P-type doped region 4 and a P-type dielectric layer 5;
the impurity of P type ion implantation is boron, the implantation energy is 50keV-90keV, the implantation dosage is 1E 14-1E 16 per square centimeter, the concentration of majority electron emitted by a main junction can be improved, and the forward voltage drop of the device is effectively reduced by utilizing the PN junction large implantation modulation effect.
3) Photoetching and etching the P-type dielectric layer 5 to form a contact hole region 6;
4) forming a platinum layer with a certain thickness on the back of the N-type silicon substrate, and then annealing the platinum layer at high temperature to form a platinum doping area 7;
the platinum doping concentration of the device reaches about 10 15 Per cm 2 The minority carrier lifetime is effectively controlled, meanwhile, the thickness of the platinum layer cannot be too thick, otherwise, the electric leakage is increased due to too much platinum doping; wherein the thickness of the evaporated platinum is 30 +/-3 nm.
5) Corroding the redundant platinum layer on the back of the N-type silicon substrate, depositing or evaporating metal with a certain thickness on the front of the N-type silicon substrate, and forming an anode 8 through annealing after photoetching and corrosion; and depositing on the back of the N-type silicon substrate to form a cathode 9, and finishing the manufacture of the fast recovery diode.
The metal of the anode 5 is AL, the metal of the cathode 8 is Cr, Ni or Au, and aluminum is used as an electrode to facilitate the realization of the process.
The invention provides a method for improving the anti-static capability of a fast recovery diode, which solves the technical problems of the prior art that the effective concentration of a device is reduced due to the compensation doping effect after platinum doping, so that the conduction resistance of a base region is increased, the electrostatic current is not easy to discharge, and the electrostatic capability of the device is reduced. By adopting the antistatic hole design structure, the perimeter of the PN junction is increased, more channels are provided for electrostatic discharge, and the antistatic capacity of the device can reach more than 4000V.
The present invention has been described in terms of the preferred embodiment, and it is not intended to be limited to the embodiment. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method of improving the anti-static capability of a fast recovery diode, comprising the steps of:
s1, forming an N-type epitaxial layer on an N-type silicon substrate, photoetching a dielectric layer (3) of the silicon N-type epitaxial layer, and forming a main junction region (2) and a terminal region (1) on the photoetching dielectric layer (3) by a corrosion or etching method; wherein the main region (2) is provided with antistatic holes;
s2, performing P-type ion implantation and high-temperature annealing in the main junction region (2) and the terminal region (1) to form a P-type doped region (4) and a P-type dielectric layer (5);
s3, forming a contact hole area (6) on the P-type dielectric layer (5) through photoetching and etching, and annealing the platinum layer at high temperature to form a platinum doped area (7) after forming the platinum layer on the back of the N-type silicon substrate;
s4, etching off the redundant platinum layer on the back of the N-type silicon substrate, depositing or evaporating metal on the front of the N-type silicon substrate, and forming an anode (8) by annealing after photoetching and etching; and depositing on the back of the N-type silicon substrate to form a cathode (9) so as to obtain the fast recovery diode with the antistatic capability.
2. The method for improving the anti-static capability of a fast recovery diode according to claim 1, wherein a dielectric layer (3) is formed on the surface of the N-type epitaxial layer by oxidation or precipitation; the dielectric layer (3) is SiO 2 And (3) a layer.
3. The method for improving the anti-static capability of a fast recovery diode according to claim 1, wherein the resistivity of the N-type silicon substrate is 0.001 Ω & cm to 0.004 Ω & cm.
4. The method for improving the anti-static capability of a fast recovery diode according to claim 1, wherein the resistivity of the N type epitaxial layer is 5 Ω & cm to 6 Ω & cm.
5. The method for improving the anti-static capability of a fast recovery diode according to claim 1, wherein the main junction (2) has an area of 2900 μm x2900 μm.
6. The method for improving the anti-static capability of a fast recovery diode according to claim 1, wherein the number of the anti-static holes is 8, and the size of the anti-static holes is 453 μm x 453 μm.
7. The method of claim 1, wherein the P-type ion implantation impurity is boron, the implantation energy is 50keV to 90keV, and the implantation dose is 1E14 to 1E16 per square centimeter.
8. The method for improving the anti-static capability of a fast recovery diode according to claim 1, wherein the vaporized platinum thickness is 30 ± 3 nm.
9. The method for improving the antistatic ability of a fast recovery diode according to claim 1 wherein the metal of the anode (5) is AL.
10. The method for improving the antistatic ability of a fast recovery diode according to claim 1, wherein the metal of the cathode (8) is Cr, Ni or Au.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210536682.2A CN114927420A (en) | 2022-05-17 | 2022-05-17 | Method for improving anti-static capability of fast recovery diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210536682.2A CN114927420A (en) | 2022-05-17 | 2022-05-17 | Method for improving anti-static capability of fast recovery diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114927420A true CN114927420A (en) | 2022-08-19 |
Family
ID=82807877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210536682.2A Pending CN114927420A (en) | 2022-05-17 | 2022-05-17 | Method for improving anti-static capability of fast recovery diode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114927420A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117594438A (en) * | 2023-11-23 | 2024-02-23 | 扬州国宇电子有限公司 | Manganese doping method of fast recovery diode and fast recovery diode |
-
2022
- 2022-05-17 CN CN202210536682.2A patent/CN114927420A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117594438A (en) * | 2023-11-23 | 2024-02-23 | 扬州国宇电子有限公司 | Manganese doping method of fast recovery diode and fast recovery diode |
| CN117594438B (en) * | 2023-11-23 | 2024-06-07 | 扬州国宇电子有限公司 | Manganese doping method of fast recovery diode and fast recovery diode |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5928438A (en) | Structure and fabrication process for self-aligned locally deep-diffused emitter (SALDE) solar cell | |
| US20050242411A1 (en) | [superjunction schottky device and fabrication thereof] | |
| US20010035560A1 (en) | Diode and method for manufacturing the same | |
| JP4193993B2 (en) | JBS and manufacturing method thereof | |
| US7816167B2 (en) | Method of fabricating a differential doped solar cell | |
| CN103515451B (en) | Double-concave groove type Schottky barrier element | |
| US7867809B2 (en) | One-step diffusion method for fabricating a differential doped solar cell | |
| CN111211168B (en) | RC-IGBT chip and manufacturing method thereof | |
| CN111430453A (en) | RC-IGBT chip with good reverse recovery characteristic and manufacturing method thereof | |
| JP6454443B2 (en) | Flat gate commutation thyristor | |
| CN211017091U (en) | Vertical GaN-based groove junction barrier Schottky diode | |
| CN114927420A (en) | Method for improving anti-static capability of fast recovery diode | |
| CN109148605B (en) | Fast recovery diode, preparation method and electronic equipment | |
| CN110931571A (en) | Vertical GaN-based groove junction barrier Schottky diode and manufacturing method thereof | |
| CN107887450B (en) | Structure of Schottky diode for improving peak current and preparation method thereof | |
| CN215527734U (en) | Junction barrier Schottky power device | |
| CN115458610A (en) | Silicon carbide power device with concentration gradient epitaxial layer structure | |
| CN115224105A (en) | Fast recovery diode and manufacturing method and application thereof | |
| CN111799336B (en) | SiC MPS diode device and preparation method thereof | |
| CN114823332A (en) | Preparation process and structure of semi-super junction fast recovery diode device | |
| CN114171607A (en) | Silicon carbide junction barrier schottky diode | |
| CN111799338A (en) | Groove type SiC JBS diode device and preparation method thereof | |
| CN113299732A (en) | Semiconductor device, chip, apparatus and manufacturing method | |
| CN216698373U (en) | Schottky diode | |
| CN108461549A (en) | A kind of silicon carbide diode device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |