CN114914238A - 半导体装置与其制造方法 - Google Patents

半导体装置与其制造方法 Download PDF

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Publication number
CN114914238A
CN114914238A CN202110628352.1A CN202110628352A CN114914238A CN 114914238 A CN114914238 A CN 114914238A CN 202110628352 A CN202110628352 A CN 202110628352A CN 114914238 A CN114914238 A CN 114914238A
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layer
substrate
source
dielectric
bottom dielectric
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曾国弼
陈德芳
陈昭成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置与其制造方法，半导体装置包含一基板、一通道层、一栅极结构、一源极/漏极磊晶结构及一底部介电质结构。通道层在基板上。栅极结构在基板上且包围通道层。源极/漏极磊晶结构在基板上且连接至通道层。底部介电质结构介于源极/漏极磊晶结构与基板之间。

Description

半导体装置与其制造方法
技术领域
本揭露的一些实施方式是关于一种半导体装置与其制造方法，尤其是关于源极/漏极磊晶结构的半导体装置与其制造方法。
背景技术
半导体集成电路(integrated circuit，IC)工业经历了指数增长。集成电路材料及设计中的技术进步产生了IC的多个世代，其中每个世代具有相较于前一世代的较小及较复杂电路。在集成电路演化的过程中，功能密度(亦即，每晶片区域互连装置的数目)通常已增加，而几何形状大小(亦即，可使用制造制程创造的最小元件(或接线))已减小。这个按比例缩小制程通常通过提高生产效率及降低相关联的成本来提供效益。
发明内容
根据一些实施例，半导体装置包含基板、通道层、栅极结构、源极/漏极磊晶结构及底部介电质结构。通道层在基板上。栅极结构在基板上且包围通道层。源极/漏极磊晶结构在基板上且连接至通道层。底部介电质结构介于源极/漏极磊晶结构与基板之间。
根据一些实施例，半导体装置包含多个通道层、栅极结构、源极/漏极磊晶结构、内介电质间隔物及底部介电质结构。通道层以间隔开的方式一个在另一个上方地排列在基板上。栅极结构包围多个通道层中的每一个。源极/漏极磊晶结构连接至通道层。内介电质间隔物介于源极/漏极磊晶结构与栅极结构之间。底部介电质结构在源极/漏极磊晶结构以下。
根据一些实施例，制造半导体装置的方法包含形成鳍片结构，鳍片结构包含多个第一半导体层及多个第二半导体层，多个第一半导体层及多个第二半导体层交替地堆叠在基板上。虚拟栅极结构横跨鳍片结构形成，使得虚拟栅极结构覆盖鳍片结构的第一部分，而鳍片结构的第二部分暴露。移除鳍片结构的暴露的第二部分。移除鳍片结构的暴露的第二部分下方的基板的一部分以在基板中形成凹部。底部介电质结构形成在基板的凹部中。在形成底部介电质结构之后，源极/漏极磊晶结构形成于鳍片结构的第一部分中的第二半导体层的多个相反末端表面上。移除虚拟栅极结构以暴露鳍片结构的第一部分。移除鳍片结构的暴露的第一部分中的第一半导体层，而留下鳍片结构的暴露的第一部分中的第二半导体层，第二半导体层悬挂基板上。栅极结构形成以包围悬挂的第二半导体层中的每一个。
附图说明
本揭示案的态样当与随附附图一起阅读时，自以下详细描述更好地理解。应注意，根据工业中的标准实习，各种特征未按比例描绘。实际上，各种特征的尺寸可出于论述的清晰性而任意地增加或减小。
图1至图14例示根据本揭示案的一些实施例的集成电路结构的形成中的中间阶段的立体图及横截面图；
图15为根据本揭示案的一些实施例的集成电路结构的横截面图；
图16及图17为根据本揭示案的一些实施例的集成电路结构的横截面图；
图18为根据本揭示案的一些实施例的集成电路结构的横截面图；
图19至图22例示根据本揭示案的一些其他实施例的用于制造集成电路结构的各种阶段的示范性横截面图。
【符号说明】
100：集成电路结构
100a：集成电路结构
100b：集成电路结构
100c：集成电路结构
100d：集成电路结构
100e：集成电路结构
102：沟槽
110：基板
111：顶表面
112：基板部分
120：磊晶堆叠
122：磊晶层
124：磊晶层/通道层
130：半导体鳍片/鳍片结构
140：隔离区域
150：虚拟栅极结构
152：虚拟栅极介电质层
154：虚拟栅极电极层
156：层
158：层
160：间隔物/间隔物材料层
162：第一间隔物层
164：第二间隔物层
170’：间隔物材料层
172：内介电质间隔物
174：底部介电质结构
174a：顶表面
175：孔隙
180：源极/漏极磊晶结构
182：孔隙
190’：间隔物材料层
192：底部介电质结构
210：层间介电质层
220：栅极结构
222：栅极介电质层
224：功函数金属层
226：填充金属
230：介电质帽
240：源极/漏极触点
910：硬遮罩层
912：氧化物层
914：氮化物层
A：区域
ET1：非等向性蚀刻制程
ET1’：非等向性蚀刻制程
ET2：非等向性蚀刻制程
GT1：栅极沟槽
H1：深度
H2：厚度
Hb：深度
Hc：深度
Hd：深度
O1：开口
X-X：切割线
Y-Y：切割线
R1：凹部
R1’：凹部
R2：侧向凹部
S/D：源极/漏极区域
W1：宽度
具体实施方式
以下揭示内容提供用于实行所提供的主题的不同特征的许多不同实施例或实例。以下描述元件及配置的特定实例以简化本揭示案。当然，这些仅为实例且不欲为限制性的。例如，以下描述中的第二特征之上或第二特征上的第一特征的形成可包含其中第一特征及第二特征直接接触地形成的实施例，且可亦包含其中额外特征可形成在第一特征与第二特征之间，使得第一特征及第二特征可不直接接触的实施例。另外，本揭示案可在各种实例中重复元件符号及/或字母。这个重复是出于简单性及清晰性的目的，且并不实质上规定所论述的各种实施例及/或组态之间的关系。
此外，诸如“在......下方”、“在......以下”、“下”、“在......上方”、“上”等的空间相对术语可在本文中使用于便于描述，以描述如附图中所例示的一个元素或特征与另一元素(多个)或特征(多个)的关系。除附图中所描绘的取向之外，空间相对术语意欲涵盖使用或操作中的装置的不同取向。设备可以其他方式定向(旋转90度或以其他取向定向)，且同样可据此解释本文所使用的空间相对描述符。
如本文所使用，“大约”、“约”、“近似”或“实质上”将通常意谓在给定值或范围的20％内，或10％内，或5％内。本文给出的数值量为近似的，意谓若未明确陈述，则术语“大约”、“约”、“近似”或“实质上”可经推断。此项技术中的一般技术者将了解尺寸可根据不同技术节点加以变化。此项技术中的一般技术者将认识到，尺寸取决于特定装置类型、技术产生、最小特征大小等。因此，术语意欲根据正评估的技术加以解释。
纳米结构晶体管(例如全环绕栅极(gate all around，GAA)晶体管结构)可通过任何合适的方法图案化。例如，可使用一或多个光微影制程图案化结构，此一或多个光微影制程包含双重图案化或多重图案化制程。通常，双重图案化或多重图案化制程结合光微影及自我对准制程，从而允许创造出具有小节距的图案，例如节距小于可使用单个直接光微影制程或其他方式获得的节距的图案。例如，在实施例中，牺牲层形成在基板上且使用光微影制程加以图案化。使用自我对准制程与图案化的牺牲层并排形成间隔物。接着移除牺牲层，且剩余间隔物可接着用来图案化全环绕栅极结构。
本揭示案与集成电路结构及形成这些集成电路结构的方法有关。更具体而言，本揭示案的一些实施例与包含源极/漏极磊晶结构下方的介电质结构的全环绕栅极装置有关。介电质结构用以改良源极/漏极磊晶结构的电流漏泄问题。
图1至图14例示根据本揭示案的一些实施例的集成电路结构(或半导体装置)100的形成中的中间阶段的立体图及横截面图。除集成电路结构之外，图1至图4A、图5A及图6A描绘X轴、Y轴与Z轴方向。形成的晶体管可包含根据一些示范性实施例的p型晶体管(诸如p型全环绕栅极鳍式场效晶体管)及/或n型晶体管(诸如n型全环绕栅极鳍式场效晶体管)。综观各种视图及例示性实施例，相似元件符号用来指定相似元素。应理解，可在通过图1至图14所示的制程之前、期间及之后提供额外的操作，且对于方法的额外实施例，可替换或消除以下描述的一些操作。操作/制程的顺序可为可互换的。
图1至图4A、图5A及图6A为处于制造期间的中间阶段处的集成电路结构100的一些实施例的立体图。图4B、图5B、图6B至图12A及图13至图14为沿着第一切割线(例如，图4A中的切割线X-X)的处于制造期间的中间阶段处的集成电路结构100的一些实施例的横截面图，该第一切割线沿着通道的纵向方向且垂直于基板的顶表面。图12B为沿着第二切割线(例如，图4A中的切割线Y-Y)的处于制造期间的中间阶段处的集成电路结构100的一些实施例的横截面图，该第二切割线在栅极区域中且垂直于通道的纵向方向。
参考图1，磊晶堆叠120形成在基板110上。在一些实施例中，基板110可包含硅(Si)。或者，基板110可包含锗(Ge)、硅锗(SiGe)、第三-五(III-V)族材料(例如，砷化镓(GaAs)、磷化镓(GaP)、砷磷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化铟镓(GaInAs)、砷化铟(InAs)、磷化镓铟(GaInP)、磷化铟(InP)、锑化铟(InSb)与/或砷磷化镓铟(GaInAsP)或其组合)或其他适当的半导体材料。在一些实施例中，基板110可包含诸如埋入式介电质层的绝缘体上半导体(semiconductor-on-insulator，SOI)结构。或者，基板110可包含诸如埋入式氧化物(buried oxide，BOX)层的埋入式介电质层，诸如通过被称为氧植入分离(separation by implantation of oxygen，SIMOX)技术的方法、晶圆粘接、选择性磊晶生长(selectively epitaxial growth，SEG)或另一适当方法形成的埋入式介电质层。
磊晶堆叠120包含有第二组成物的磊晶层124穿插其中的第一组成物的磊晶层122。第一组成物及第二组成物可为不同的。在一些实施例中，磊晶层122为硅锗且磊晶层124为硅(Si)。然而，其他实施例为可能的，其他实施例包含提供具有不同氧化速度及/或蚀刻选择性的第一组成物及第二组成物。在一些实施例中，磊晶层122包含硅锗且其中磊晶层124包含硅，磊晶层124的硅氧化速度小于磊晶层122的硅锗氧化速度。
磊晶层124或其部分可形成纳米结构晶体管的纳米结构通道。术语纳米结构在本文中用来指定具有纳米尺度或甚至微米尺度尺寸且具有狭长形状的任何材料部分，而无论此部分的横截面形状如何。因而，此术语指定圆形及实质上圆形横截面的狭长材料部分，及包含例如形状为圆柱形或实质上矩形横截面的横梁或棒形材料部分。例如，纳米结构为纳米片、纳米线、纳米板或纳米环，取决于其几何形状。以下进一步论述磊晶层124对于定义装置的通道或多个通道的使用。
应注意，磊晶层122的三个层及磊晶层124的三个层如图1中所例示地交替排列，此仅出于例示性目的且不欲为限制在超过权利要求书中所具体叙述的范围。可了解，任何数目的磊晶层可形成在磊晶堆叠120中；层的数目取决于用于晶体管的通道区域所要的数目。在一些实施例中，磊晶层124的数目在2与10之间。
如以下更详细地描述的，磊晶层124可作为用于随后形成的半导体装置的通道区域，且厚度是基于装置效能考虑来选择。通道区域中的磊晶层122最终可被移除且用来定义用于随后形成的多栅极装置的相邻通道区域之间的垂直距离，且厚度是基于装置效能考虑来选择。因此，磊晶层122亦可称为牺牲层，且磊晶层124亦可称为通道层。
举例而言，磊晶堆叠120的层的磊晶生长可通过分子束磊晶(molecular beamepitaxy，MBE)制程、金属有机化学气相沉积(metalorganic chemical vapor deposition，MOCVD)制程及/或其他合适的磊晶生长制程执行。在一些实施例中，诸如磊晶层124的磊晶生长层包含与基板110相同的材料。在一些实施例中，磊晶层122及124包含与基板110不同的材料。如以上所述，在至少一些实例中，磊晶层122包含磊晶生长硅锗(SiGe)层且磊晶层124包含磊晶生长硅(Si)层。或者，在一些实施例中，磊晶层122及124中的任一者可包含诸如锗的其他材料、诸如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟的化合物半导体、诸如硅锗、砷磷化镓、砷化铝铟、砷化铝镓、砷化铟镓、磷化镓铟与/或砷磷化镓铟或其组合的合金半导体。如所论述，可基于所提供的不同的氧化及/或蚀刻选择性性质选择磊晶层122及124的材料。在一些实施例中，磊晶层122及124为实质上无掺杂剂的(亦即，具有自约0/立方厘米至约1×1018/立方厘米的外来掺杂剂浓度)，其中例如，在磊晶生长制程期间不执行意向性掺杂。
参考图2，形成自基板110延伸的多个半导体鳍片130。在各种实施例中，鳍片130中的每一个包含由基板110形成的基板部分112及包含磊晶层122及124的磊晶堆叠的磊晶层中的每一个的部分。鳍片130可使用包含双重图案化及多重图案化制程的合适的制程制造。通常，双重图案化或多重图案化制程结合光微影及自我对准制程，从而允许创造出具有小节距的图案，例如节距小于可使用单个直接光微影制程或其他方式获得的节距的图案。例如，在一个实施例中，牺牲层形成在基板上且使用光微影制程加以图案化。使用自我对准制程与图案化的牺牲层并排形成间隔物。然后移除牺牲层，且剩余间隔物或心轴可接着用来通过蚀刻初始磊晶堆叠120图案化鳍片130。蚀刻制程可包含干式蚀刻、湿式蚀刻、反应性离子蚀刻(reactive ion etching，RIE)及/或其他合适的制程。
在如图1及图2中所例示的实施例中，在图案化鳍片130之前在磊晶堆叠120上形成硬遮罩(hard mask，HM)层910。在一些实施例中，硬遮罩层包含氧化物层912(例如，可包含二氧化硅的氧化物垫层)及形成在氧化物层上的氮化物层914(例如，可包含氮化硅(Si3N4)的氮化物垫层)。氧化物层912可作为磊晶堆叠120与氮化物层914之间的粘合层且可作为用于蚀刻氮化物层914的蚀刻终止层。在一些实例中，硬遮罩氧化物层912包含热生长氧化物、化学气相沉积(chemical vapor deposition，CVD)沉积的氧化物及/或原子层沉积(atomiclayer deposition，ALD)沉积的氧化物。在一些实施例中，硬遮罩氮化物层914通过化学气相沉积及/或其他合适的技术沉积在硬遮罩氧化物层912上。
随后可使用包含光微影及蚀刻制程的合适的制程制造鳍片130。光微影制程可包含将光阻剂层(未示出)形成在硬遮罩层910上、在图案下曝光光阻剂、执行曝光后烘烤制程及显影光阻剂以形成包含光阻剂的图案化的遮罩。在一些实施例中，图案化光阻剂以形成图案化的遮罩元件可使用电子束微影术制程或极紫外线(extreme ultraviolet，EUV)微影术制程执行，该极紫外线微影术制程使用具有例如约1至200纳米的波长的极紫外线区域内的光。图案化的遮罩可接着用来在蚀刻制程使沟槽102形成于贯穿硬遮罩层910、贯穿磊晶堆叠120且进入基板110中的未保护区域中时，保护基板110的区域及形成在上方的层，借此留下多个延伸鳍片130。可使用干式蚀刻(例如，反应离子蚀刻)、湿式蚀刻及/或其组合蚀刻沟槽102。亦可使用用以将鳍片形成在基板上的方法的许多其他实施例，包含例如定义鳍片区域(例如，通过遮罩或隔离区域)及磊晶生长呈鳍片130形式的磊晶堆叠120。
接下来，如图3中所例示，形成插在鳍片130中间的隔离区域140。隔离区域140可包含衬垫氧化物(未示出)。衬垫氧化物可由通过基板110的表面层的热氧化形成的热氧化物形成。衬垫氧化物亦可为使用例如原子层沉积(Atomic Layer Deposition，ALD)、高密度电浆化学气相沉积(High-Density Plasma Chemical Vapor Deposition，HDPCVD)或化学气相沉积(Chemical Vapor Deposition，CVD)形成的沉积氧化硅层。隔离区域140亦可包含衬垫氧化物上的介电质材料，且可使用可流动化学气相沉积(flowable chemical vapordeposition，FCVD)、旋涂涂布或类似者形成介电质材料。
然后凹入隔离区域140，使得磊晶堆叠120的顶部部分突出高于相邻隔离区域140的顶表面以形成突出鳍片130。可使用干式蚀刻制程执行蚀刻，其中将氨(NH3)及三氟化氮(NF3)用作蚀刻气体。在蚀刻制程期间，可产生电浆。氩亦可包含在内。根据本揭示案的替代性实施例，使用湿式蚀刻制程执行隔离区域140的凹入。蚀刻化学品可包含例如稀释的氟化氢(HF)。
参考图4A及图4B。虚拟栅极结构150形成在基板110上且至少部分地置于鳍片130上。置于虚拟栅极结构150下方的鳍片130的部分可称为通道区域。虚拟栅极结构150可亦定义鳍片130的源极/漏极(source/drain，S/D)区域，例如，与通道区域相邻且在通道区域的相对侧上的鳍片130的区域。
虚拟栅极形成操作首先将虚拟栅极介电质层152形成在鳍片130上。随后，虚拟栅极电极层154及可包含多个层156及158(例如，氧化物层156及氮化物层158)的硬遮罩形成在虚拟栅极介电质层152上。然后图案化硬遮罩，接着通过使用图案化的硬遮罩作为蚀刻遮罩来图案化虚拟栅极介电质层152。在一些实施例中，在图案化虚拟栅极电极层154之后，自鳍片130的源极/漏极区域移除虚拟栅极介电质层152。蚀刻制程可包含湿式蚀刻、干式蚀刻及/或其组合。蚀刻制程经选择来选择性地蚀刻虚拟栅极介电质层152而实质上不蚀刻鳍片130、虚拟栅极电极层154、氧化物遮罩层156及氮化物遮罩层158。
在虚拟栅极结构150的形成完成之后，在虚拟栅极结构150的侧壁上形成栅极间隔物160。例如，在基板110上沉积间隔物材料层。间隔物材料层可为共形层，该共形层随后经回蚀以形成栅极侧壁间隔物。在例示的实施例中，间隔物材料层160共形地置于虚拟栅极结构150的顶部及侧壁上。间隔物材料层160可包含诸如氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅(SiCN)膜、碳氧化硅、碳氮氧化硅(SiOCN)膜及/或其组合的介电质材料。在一些实施例中，间隔物材料层160包含多个层，诸如第一间隔物层162及形成在第一间隔物层162上的第二间隔物层164(例示于图4B中)。举例而言，可通过使用合适的沉积制程将介电质材料沉积在虚拟栅极结构150上以形成间隔物材料层160。然后对沉积的间隔物材料层160执行非等向性蚀刻制程以暴露未被虚拟栅极结构150(例如，鳍片130的源极/漏极区域中的虚拟栅极结构)覆盖的鳍片130的部分。直接在虚拟栅极结构150上方的间隔物材料层的部分可通过此非等向性蚀刻制程完全移除。虚拟栅极结构150的侧壁上的间隔物材料层的部分可保留，从而形成栅极侧壁间隔物，为简单起见，这些栅极侧壁间隔物经标示为栅极间隔物160。应注意，尽管栅极间隔物160为图4B的横截面图中的多层结构，但为简单起见，这些栅极间隔物经例示为图4A的立体图中的单层结构。
接下来，如图5A及图5B中所例示，通过使用例如非等向性蚀刻制程蚀刻侧向延伸超过栅极间隔物160(例如，在鳍片130的源极/漏极区域S/D中)的半导体鳍片130的暴露部分，该非等向性蚀刻制程使用虚拟栅极结构150及栅极间隔物160作为蚀刻遮罩，从而形成进入半导体鳍片130中及介于对应的虚拟栅极结构150之间的凹部R1。在非等向性蚀刻之后，磊晶层122及通道层124的末端表面及栅极间隔物160的各别最外侧壁由于非等向性蚀刻的关系而为实质上相连的。在一些实施例中，非等向性蚀刻可通过具有电浆源及反应气体的干式化学蚀刻执行。电浆源可为感应耦合电浆(inductively coupled plasma，ICR)源、变压器耦合电浆(transformer coupled plasma，TCP)源、电子回旋共振(electroncyclotron resonance，ECR)源或类似者，且反应气体可为例如以氟为主的气体(诸如六氟化硫(SF6)、二氟甲烷(CH2F2)、氟甲烷(CH3F)、三氟甲烷(CHF3)或类似者)、以氯为主的气体(例如，氯气(Cl2))、溴化氢气体(HBr)、氧气(O2)、类似者或其组合。
基板部分112亦在此非等向性蚀刻制程中凹入以形成凹部R1’。在一些实施例中，用于蚀刻基板部分112的反应气体为溴化氢及氦(He)的气体混合物。在此非等向性蚀刻制程中，气体混合物以垂直蚀刻速度及比垂直蚀刻速度较缓慢的侧向蚀刻速度蚀刻基板部分112。在更多溴化氢的情况下，垂直蚀刻速度增加；在更多氦的情况下，侧向蚀刻速度增加。因而，可通过调谐溴化氢与氦的比调整凹部R1’的形状。例如，溴化氢∶氦在自约1∶1至约1∶8的范围内以获得横截面图(参见图5B)中的V形凹部R1’。若溴化氢∶氦大于约1∶8，则凹部R1’具有横截面图中的U形(亦即，侧向蚀刻速度增加)。若溴化氢∶氦小于约1∶1，则凹部R1’不足以深到可容纳底部介电质结构174(参见图8)。
在一些其他实施例中，可通过调谐反应气体的压力调整凹部R1’的形状。例如，反应气体的压力在自约3毫托至约10毫托的范围内。若压力大于约10毫托，则蚀刻速度可能太缓慢；若压力小于约3毫托，则凹部R1’可能具有横截面图中的U形。
在一些实施例中，每一个凹部R1’具有深度H1。例如，深度H1在自约1纳米至约500纳米的范围内。若深度H1大于约500纳米，则源极/漏极磊晶结构180(参见图9A)可能不容易沉积在底部介电质结构174(参见图9A)上；若深度H1小于约1纳米，则没有空间容纳底部介电质结构174，且源极/漏极磊晶结构180可能具有电流漏泄问题。在一些实施例中，凹部R1’具有大于约1.3，例如，在自约1.3至约15的范围内的深宽比(对于凹部定义为凹部深度H1/宽度W1的比)。凹部R1在高深宽比的情况下更像横截面图中的V形，且在低深宽比的情况下更像横截面图中的U形。
接下来，在图6A及图6B中，使用合适的蚀刻技术侧向地或水平地凹入磊晶层122，从而导致每个垂直地介于对应的通道层124之间的侧向凹部R2。此操作可通过使用选择性蚀刻制程来执行。举例而言且不限于，磊晶层122为硅锗且通道层124为硅，从而允许磊晶层122的选择性蚀刻。在一些实施例中，选择性湿式蚀刻包含APM蚀刻(例如，氢氧化氨-过氧化氢-水混合物)，该氢氧化氨-过氧化氢-水混合物蚀刻以相较于其蚀刻硅的较快蚀刻速度蚀刻硅锗。在一些实施例中，选择性蚀刻包含硅锗氧化，接着是硅锗氧化物(SiGeOx)移除。例如，氧化可通过臭氧(O3)清洁提供，然后通过诸如氨水(NH4OH)的蚀刻剂移除硅锗氧化物(SiGeOx)，该蚀刻剂以相较于其蚀刻硅的较快蚀刻速度选择性地蚀刻硅锗氧化物(SiGeOx)。此外，因为硅的氧化速度比硅锗的氧化速度低得多(有时低30倍)，所以使磊晶层122侧向地凹入的制程并未显著地蚀刻通道层124。因此，通道层124侧向地延伸超过磊晶层122的相对末端表面。
在图7中，形成间隔物材料层170’以填充通过以上参考图6A及图6B所论述的磊晶层122的侧向蚀刻留下的凹部R2。间隔物材料层170’的部分亦沉积在凹部R1’中。间隔物材料层170’可为低介电常数(k)介电质材料，诸如二氧化硅、氮化硅、碳化硅、碳氮化硅、氮氧化硅或碳氮氧化硅，且可通过诸如原子层沉积的合适的沉积方法形成。在一些实施例中，内介电质间隔物材料层170’为本质的，或未以杂质掺杂的。间隔物材料层170’可使用包含低压化学气相沉积(low pressure chemical vapor deposition，LPCVD)及电浆增强化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)的化学气相沉积、物理气相沉积(physical vapor deposition，PVD)、原子层沉积，或其他合适的制程形成。在一些实施例中，尽管间隔物材料层170’共形地形成在凹部R1’中，但间隔物材料层170’在V形凹部R1’中比在U形凹部中更容易合并。合并的间隔物材料层170’导致厚的底部介电质结构174形成(参见图8)。
参考图8，在间隔物材料层170’的沉积之后，可执行非等向性蚀刻制程ET1来修整沉积的间隔物材料层170’，留下使得填充通过磊晶层122的侧向蚀刻留下的凹部R2的沉积的间隔物材料层170’的部分，且留下沉积在凹部R1’的底部中的沉积的间隔物材料层170’的另一部分，凹部R1’是在鳍片结构130的蚀刻后留下的。在修整制程之后，为简单起见，将沉积的间隔物材料的剩余部分标示为凹部R2中的内介电质间隔物172及凹部R1’中的底部介电质结构174。内介电质间隔物172用来隔离金属栅极与在后续处理中形成的源极/漏极磊晶结构，且底部介电质结构174用来隔离源极/漏极磊晶结构与基板110。在图8的实例中，内介电质间隔物172的侧壁实质上对准通道层124的侧壁。
在一些实施例中，非等向性蚀刻制程ET1为电浆蚀刻。具有图7中所例示的结构的基板110可装载至电浆工具中，且暴露于在诸如三氟甲烷(CHF3)、四氟甲烷(CF4)、八氟环丁烷(C4F8)、八氟环戊烯(C5F8)、六氟丁二烯(C4F6)或类似物种的含氟气体、诸如氩或氦的惰性气体的气体混合物中通过射频(radiofrequency，RF)或微波功率产生的电浆环境，持续足以蚀刻凹部R1’及R2外侧的间隔物材料层170’的部分的持续时间。在包含三氟甲烷、四氟甲烷及氩的气体混合物中产生的电浆可用来调谐底部介电质结构174的形状。在较多氟的情况下，电浆蚀刻的侧向蚀刻速度增加，且剩下较多的底部介电质结构174。电浆通过具有大于0且等于或小于约30伏特的偏压的射频功率产生。若偏压大于约30伏特，则底部介电质结构174可能完全移除；若偏压不存在，则内介电质间隔物172可能会被过度蚀刻。
在图9A中，源极/漏极磊晶结构180形成在半导体鳍片130的源极/漏极区域S/D上。源极/漏极磊晶结构180可通过执行磊晶生长制程来形成，该磊晶生长制程将磊晶材料提供在鳍片130上。在磊晶生长制程期间，虚拟栅极结构150、栅极侧壁间隔物160、内介电质间隔物172及底部介电质结构174将源极/漏极磊晶结构180限制于源极/漏极区域S/D。在一些实施例中，源极/漏极磊晶结构180的晶格常数不同于磊晶层124的晶格常数，使得磊晶层124可通过源极/漏极磊晶结构180加应变或加应力以改良半导体装置的载子迁移率且增强装置效能。磊晶制程包含化学气相沉积技术(例如，电浆增强化学气相沉积、气相磊晶(vapor-phase epitaxy，VPE)及/或超高真空化学气相沉积(ultra-high vacuum CVD，UHV-CVD))、分子束磊晶及/或其他合适的制程。磊晶制程可使用气体及/或液体前驱物，这些气体及/或液体前驱物与磊晶层124的组成物相互作用。
在一些实施例中，源极/漏极磊晶结构180可包含锗、硅、砷化镓、砷化铝镓、硅锗、砷磷化镓、磷化硅(SiP)或其他合适的材料。源极/漏极磊晶结构180可在磊晶制程期间通过引入掺杂物种原位掺杂，掺杂物种包含：p型掺杂剂，诸如硼或二氟化硼(BF2)；n型掺杂剂，诸如磷或砷；及/或包含其组合的其他合适的掺杂剂。若源极/漏极磊晶结构180并非原位掺杂的，则执行植入制程(亦即，接合面布植制程)来掺杂源极/漏极磊晶结构180。在一些示范性实施例中，n型晶体管中的源极/漏极磊晶结构180包含磷化硅，而p型中的源极/漏极磊晶结构180包含GeSnB及/或SiGeSnB。在具有不同装置类型的实施例中，诸如光阻剂的遮罩可形成在n型装置区域上，而暴露p型装置区域，且p型磊晶结构可形成在p型装置区域中的底部介电质结构174上。然后可移除遮罩。随后，诸如光阻剂的遮罩可形成在p型装置区域上，而暴露n型装置区域，且n型磊晶结构可形成在n型装置区域中的底部介电质结构174上。然后可移除遮罩。
一旦形成源极/漏极磊晶结构180，可执行退火制程来活化源极/漏极磊晶结构180中的p型掺杂剂或n型掺杂剂。退火制程可为例如快速热退火(rapid thermal anneal，RTA)、雷射退火、毫秒热退火(millisecond thermal annealing，MSA)制程或类似者。
图9B及图9C为根据一些实施例的图9A中的区域A的放大视图。在图9B中，内介电质间隔物172愈低，内介电质间隔物172的大小愈大。在一些实施例中，内介电质间隔物172的大小通过可在图6B中所示的侧向凹入制程期间调谐的凹部R2(参见图6B)的大小决定。此外，底部介电质结构174暴露凹部R1’的内表面的部分。在此组态的情况下，源极/漏极磊晶结构180可填充凹部R1’的剩余部分。亦即，源极/漏极磊晶结构180与基板110接触；如此，图9B中的底部介电质结构174亦改善源极/漏极磊晶结构180的电流漏泄问题。在图9C中，内介电质间隔物172及/或底部介电质结构174中的至少一个具有其中的孔隙175。孔隙175通过内介电质间隔物172及源极/漏极磊晶结构180或通过底部介电质结构174及源极/漏极磊晶结构180定义。因为间隔物材料层170’(参见图7)共形地形成于凹部R1’及R2中，所以若间隔物材料层170’为薄的，则间隔物材料层170’可能无法填充凹部R1’及/或R2。因而，在图8中的非等向性蚀刻制程ET1之后，孔隙175可形成于内介电质间隔物172及/或底部介电质结构174中。
在图10中，层间介电质(interlayer dielectric，ILD)层210形成于基板110上。在一些实施例中，触点蚀刻终止层(contact etch stop layer，CESL)亦在形成层间介电质层210之前形成。在一些实例中，触点蚀刻终止层包含氮化硅层、氧化硅层、氧氮化硅及/或具有与层间介电质层210的蚀刻选择性不同的其他合适的材料。触点蚀刻终止层可通过电浆增强化学气相沉积(plasma-enhanced chemical vapor deposition，PECVD)制程及/或其他合适的沉积或氧化制程形成。在一些实施例中，层间介电质层210包含诸如四乙基硅酸盐(tetraethylorthosilicate，TEOS)形成的氧化物、未掺杂的硅酸盐玻璃或诸如硼磷硅玻璃(borophosphosilicate glass，BPSG)、熔融硅石玻璃(fused silica glass，FSG)、磷硅玻璃(phosphosilicate glass，PSG)、硼掺杂的硅玻璃(boron doped silicon glass，BSG)的掺杂的氧化硅的材料，及/或具有与触点蚀刻终止层的蚀刻选择性不同的其他合适的介电质材料。层间介电质层210可通过电浆增强化学气相沉积制程或其他合适的沉积技术沉积。在一些实施例中，在层间介电质层210形成之后，晶圆可经过高热预算(thermal budget)制程以退火层间介电质层210。
在一些实例中，在沉积层间介电质层210之后，可执行平坦化制程来移除层间介电质层210的过量材料。例如，平坦化制程包含化学机械平坦化(chemical mechanicalplanarization，CMP)制程，该化学机械平坦化制程移除覆盖在虚拟栅极结构150上的层间介电质层210(及触点蚀刻终止层层，若存在)的部分且平坦化集成电路结构100的顶表面。在一些实施例中，化学机械平坦化制程亦移除硬遮罩层156及158(如图9A中所示)且暴露虚拟栅极电极层154。
此后，首先移除虚拟栅极结构150(如图9A中所示)，且然后移除磊晶层(亦即，牺牲层)122(如图10中所示)。所得结构例示于图11中。在一些实施例中，通过使用选择性蚀刻制程(例如，选择性干式蚀刻、选择性湿式蚀刻或其组合)移除虚拟栅极结构150，该选择性蚀刻制程以相较于其蚀刻其他材料(例如，栅极侧壁间隔物160及/或层间介电质层210)较快的蚀刻速度蚀刻虚拟栅极结构150中的材料，因而产生介于对应的栅极侧壁间隔物160之间的栅极沟槽GT1，并且磊晶层122暴露在栅极沟槽GT1中。随后，通过使用另一选择性蚀刻制程移除栅极沟槽GT1中的磊晶层122，该另一选择性蚀刻制程以相较于其蚀刻通道层124的较快蚀刻速度蚀刻磊晶层122，因而形成介于相邻磊晶层(亦即，通道层)124之间的开口O1。以此方式，磊晶层124成为悬挂在基板110上及源极/漏极磊晶结构180之间的纳米片。此操作亦称为通道释放制程。在此中间处理操作终，磊晶层(亦即，纳米片)124之间的开口O1可充满周围环境条件(例如，空气、氮等)。在一些实施例中，磊晶层124可互换地称为纳米结构(纳米线、纳米板及纳米环、纳米片等，取决于其几何形状)。例如，在一些其他实施例中，由于用于完全移除磊晶层122的选择性蚀刻制程，磊晶层124可经修整以具有实质圆形形状(亦即，圆柱形)。在那一状况下，所得磊晶层124可称为纳米线。
在一些实施例中，通过使用选择性湿式蚀刻制程移除磊晶层122。在一些实施例中，磊晶层122为硅锗且磊晶层124为硅，从而允许磊晶层122的选择性移除。在一些实施例中，选择性湿式蚀刻包含APM蚀刻(例如，氢氧化氨-过氧化氢-水混合物)。在一些实施例中，选择性移除包含硅锗氧化，接着是硅锗氧化物(SiGeOx)移除。例如，氧化可通过臭氧清洁提供，然后通过诸如氨水的蚀刻剂移除硅锗氧化物(SiGeOx)，该蚀刻剂以相较于其蚀刻硅的较快蚀刻速度选择性地蚀刻硅锗氧化物(SiGeOx)。此外，因为硅的氧化速度比硅锗的氧化速度低得多(有时低30倍)，所以通道释放制程可能不会显著地蚀刻硅锗。可注意到，通道释放操作及侧向地凹入牺牲层的先前操作(如图6A及图6B中所示的操作)皆使用以相较于蚀刻硅的较快蚀刻速度蚀刻硅锗的选择性蚀刻制程，且因此这两个操作可在一些实施例中使用相同蚀刻剂化学品。在此状况下，通道释放操作的蚀刻时间/持续时间比侧向地凹入牺牲层的先前操作的蚀刻时间/持续时间更长，以便完全移除牺牲硅锗层。
在图12A及图12B中，替换栅极结构220分别形成于栅极沟槽GT1中以包围悬挂在栅极沟槽GT1中的每一个磊晶层124。栅极结构220可为全环绕栅极鳍式场效晶体管的最终栅极。最终栅极结构可为高介电常数/金属栅极堆叠，然而其他组成物为可能的。在一些实施例中，每一个栅极结构220形成与通过多个磊晶层124提供的多通道相关联的栅极。例如，高介电常数/金属栅极结构220形成在通过释放磊晶层124而提供的开口O1(如图12A中所例示)内。在各种实施例中，高介电常数/金属栅极结构220包含形成在磊晶层124周围的栅极介电质层222、形成在栅极介电质层222周围的功函数金属层224及形成在功函数金属层224周围且填充栅极沟槽GT1的剩余部分的填充金属226。栅极介电质层222包含界面层(例如，氧化硅层)及界面层上的高介电常数栅极介电质层。高介电常数栅极介电质包含具有例如大于热氧化硅的介电常数(～3.9)的高介电常数的介电质材料。使用在高介电常数/金属栅极结构220内的功函数金属层224及/或填充金属226可包含金属、金属合金或金属硅化物。高介电常数/金属栅极结构220的形成可包含用以形成各种栅极材料、一或多个衬垫层的沉积，及用以移除过量栅极材料的一或多个化学机械平坦化制程。如沿着高介电常数/金属栅极结构220的纵向轴线取得的图12B的横截面图中所例示，高介电常数/金属栅极结构220包围每一个磊晶层124，且因而称为全环绕栅极鳍式场效晶体管的栅极。
在一些实施例中，栅极介电质层222的界面层可包含诸如氧化硅(SiO2)、氧化铪硅(HfSiO)或氮氧化硅(SiON)的介电质材料。界面层可通过化学氧化、热氧化、原子层沉积(atomic layer deposition，ALD)、化学气相沉积(chemical vapor deposition，CVD)及/或其他合适的方法形成。栅极介电质层222的高介电常数介电质层可包含氧化铪(HfO2)。或者，栅极介电质层222可包含其他高介电常数介电质，诸如氧化铪硅(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、氧化镧(LaO)、氧化锆(ZrO)、氧化钛(TiO)、氧化钽(Ta2O5)、氧化钇(Y2O3)、氧化锶钛(SrTiO3，STO)、氧化钡钛(BaTiO3，BTO)、氧化钡锆(BaZrO)、氧化铪镧(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化铝(Al2O3)、氮化硅(Si3N4)、氮氧化硅(SiON)及其组合。
功函数金属层224可包含用以提供用于高介电常数/金属栅极结构220的合适的功函数的功函数金属。对于n型鳍式场效晶体管，功函数金属层224可包含一或多个n型功函数金属(N金属)。n型功函数金属可示范性地包含但不限于：钛铝(TiAl)、氮化钛铝(TiAlN)、碳氮化钽(TaCN)、铪(Hf)、锆(Zr)、钛(Ti)、钽(Ta)、铝(Al)、金属碳化物(例如，碳化铪(HfC)、碳化锆(ZrC)、碳化钛(TiC)、碳化铝(AlC))、铝化物及/或其他合适的材料。另一方面，对于p型鳍式场效晶体管，功函数金属层134可包含一或多个p型功函数金属(P金属)。p型功函数金属可示范性地包含但不限于：氮化钛(TiN)、氮化钨(WN)、钨(W)、钌(Ru)、钯(Pd)、铂(Pt)、钴(Co)、镍(Ni)、导电金属氧化物及/或其他合适的材料。
在一些实施例中，填充金属226可示范性地包含但不限于：钨、铝、铜、镍、钴、钛、钽、氮化钛、氮化钽、硅化镍、硅化钴、碳化钛(TaC)、硅氮化钽(TaSiN)、碳氮化钽、钛铝、氮化钛铝或其他合适的材料。
在图13中，视情况地，执行回蚀制程来回蚀替换栅极结构220，从而形成回蚀的栅极结构220上的凹部。在一些实施例中，因为替换栅极结构220的材料具有与栅极间隔物160不同的蚀刻选择性，所以替换栅极结构220的顶表面高度可低于栅极间隔物160的顶表面高度。
介电质帽230可视情况地形成在回蚀的栅极结构220上。介电质帽层230包含氮化硅(SiNx)、氧化铝(AlxOy)、氮氧化铝(AlON)、碳氧化硅(SiOxCy)、碳氮化硅(SiCxNy)、其组合或类似者，且是通过诸如化学气相沉积、电浆增强化学气相沉积(plasma-enhanced CVD，PECVD)、原子层沉积、远端电浆原子层沉积(remote plasma原子层沉积，RPALD)、电浆增强原子层沉积(plasma-enhanced ALD，PEALD)、其组合或类似者的合适的沉积技术形成。然后执行化学机械平坦化制程来移除凹部外侧的帽层，从而留下凹部中的介电质帽层的部分以作为介电质帽230。
在图14中，形成源极/漏极触点240，源极/漏极触点240延伸贯穿层间介电质层210(及触点蚀刻终止层层，若存在)。举例而言但不限制，源极/漏极触点240的形成包含执行一或多个蚀刻制程以形成延伸贯穿层间介电质层210的触点开口，以暴露源极/漏极磊晶结构180、沉积超填触点开口的一或多个金属材料，然后执行化学机械平坦化制程以移除触点开口外侧的过量金属材料。在一些实施例中，一或多个蚀刻制程为选择性蚀刻，该选择性蚀刻以相较于蚀刻介电质帽230及栅极间隔物160的较快蚀刻速度蚀刻层间介电质层210。因此，选择性蚀刻是使用介电质帽230及栅极间隔物160作为蚀刻遮罩来执行，使得在不使用额外光微影制程的情况下形成自我对准至源极/漏极磊晶结构180的触点开口及源极/漏极触点240。在那一状况下，允许形成自我对准的源极/漏极触点240的介电质帽230可称为SAC帽230。
集成电路结构100包含基板110、以间隔开的方式一个在另一个上方地排列在基板110上的通道层124、包围/包裹每一个通道层124的栅极结构220、连接至通道层124的源极/漏极磊晶结构180及介于源极/漏极磊晶结构180与基板110之间的底部介电质结构174。亦即，源极/漏极磊晶结构180通过底部介电质结构174与基板110分离。底部介电质结构174分别位于源极/漏极磊晶结构180以下以防止源极/漏极磊晶结构180的电流泄漏至基板110中，然后泄漏至其他源极/漏极磊晶结构180。
在一些实施例中，底部介电质结构174嵌入基板110中且与基板110的凹部R1’的内表面共形。亦即，底部介电质结构174具有弯曲(凸形)底表面及弯曲(凹形)顶表面。底部介电质结构174的顶表面174a低于基板110的顶表面111。底部介电质结构174的最大厚度H2在自约1纳米至约500纳米的范围内。若厚度H2大于约500纳米，则源极/漏极磊晶结构180可能不容易沉积在底部介电质结构174上；若厚度H2小于约1纳米，则源极/漏极磊晶结构180可能具有电流漏泄问题。
在一些实施例中，集成电路结构100还包含介于栅极结构220与源极/漏极磊晶结构180之间的内介电质间隔物172。如图7至图8中所描述，因为内介电质间隔物172及底部介电质结构174是在相同制程中形成，所以内介电质间隔物172及底部介电质结构174具有相同材料。
图15为根据本揭示案的一些实施例的集成电路结构(或半导体装置)100a的横截面图。图15中的集成电路结构100a与图14中的集成电路结构100之间的差异是关于源极/漏极磊晶结构180的形状。在图15中，至少一个孔隙(或气隙)182形成在源极/漏极磊晶结构180与底部介电质结构174之间。孔隙182可形成于图9A中所描述的磊晶生长制程中。磊晶生长制程可为选择性磊晶生长(selectively epitaxial growth，SEG)制程，相较于在介电质材料上(例如，底部介电质结构174及内介电质间隔物172)，该选择性磊晶生长制程具有在半导体材料(例如，通道层124)上较高的生长速度。因而，源极/漏极磊晶结构180的至少一部分可悬挂在底部介电质结构174上且在源极/漏极磊晶结构180下方形成孔隙。在一些实施例中，可通过调谐磊晶生长制程的配方来调整源极/漏极磊晶结构180的形状。集成电路结构100a的其他相关结构及制造细节与图14的集成电路结构100实质上相同或类似，且因此，在下文中将不重复在此方面的描述。
图16及图17为根据本揭示案的一些实施例的集成电路结构(或半导体装置)100b及100c的横截面图。图16中的集成电路结构100b、图17中的集成电路结构100c及图14中的集成电路结构100之间的差异是关于底部介电质结构174的形状。在图16中，底部介电质结构174具有实质上平坦的顶表面，且在图17中，底部介电质结构174具有凸形顶表面。亦即，底部介电质结构174的顶表面174a与图16中的基板110的顶表面111实质上齐平，且底部介电质结构174的顶表面174a高于图17中的基板110的顶表面111。在一些实施例中，通过调谐凹部R1’的深度来调整底部介电质结构174的形状。例如，图16及图17中的凹部R1’的深度Hb及Hc比图5B中的凹部R1’的深度H1浅。因此，间隔物材料层170’(参见图7)较容易填充图16及图17中的凹部R1’。因而，在图8中所示的非等向性蚀刻制程ET1之后，更多间隔物材料层170’留在图16及图17的凹部R1’中。替代地或另外，可添加更多氟在用于蚀刻间隔物材料层170’的电浆中以形成图16及图17中所示的底部介电质结构174。集成电路结构100b及100c的其他相关结构及制造细节与图14的集成电路结构100实质上相同或类似，且因此，在下文中将不重复在此方面的描述。
图18为根据本揭示案的一些实施例的集成电路结构(或半导体装置)100d的横截面图。图18中的集成电路结构100d及图14中的集成电路结构100之间的差异是关于底部介电质结构174的形状。在图18中，底部介电质结构174形成于凹部R1’的底部中且暴露凹部R1’的内表面的部分。在一些实施例中，通过调谐凹部R1’的深度来调整底部介电质结构174的形状。例如，图18中的凹部R1’的深度Hd比图5B中的凹部R1’的深度H1深。因此，间隔物材料层170’(参见图7)可形成在图18中的凹部R1’的底部处。因而，在图8中所示的非等向性蚀刻制程ET1之后，较少间隔物材料层170’留在图18的凹部R1’中。替代地或另外，添加较少氟在用于蚀刻间隔物材料层170’的电浆中以形成图18中所示的底部介电质结构174。在此组态的情况下，源极/漏极磊晶结构180可填充凹部R1’的剩余部分。亦即，源极/漏极磊晶结构180与基板110接触；如此，图18中的底部介电质结构174亦改善源极/漏极磊晶结构180的电流漏泄问题。集成电路结构100d的其他相关结构及制造细节与图14的集成电路结构100实质上相同或类似，且因此，在下文中将不重复在此方面的描述。
在一些实施例中，内介电质间隔物172及底部介电质结构174可包含不同的材料。因而，内介电质间隔物172及底部介电质结构174是在不同的制程中形成。图19至图22例示根据本揭示案的一些其他实施例的用于制造集成电路结构(或半导体装置)100e的各种阶段的示范性横截面图。应理解，可在图19至图22所示的制程之前、期间及之后提供额外的操作，且对于方法的额外实施例，可替换或消除以下描述的一些操作。操作/制程的顺序可为可互换的。与在图1至图14的情况下描述的相同或类似的组态、材料、制程及/或操作可使用在以下实施例中，且可省略详细解释。
在如图7中所示的结构形成之后，执行非等向性蚀刻制程ET1’来修整如图19中所示的沉积的间隔物材料层170’，留下填充凹部R2的沉积的间隔物材料层170’的部分，其中凹部R2是在侧向蚀刻磊晶层122后留下的，且移除沉积在凹部R1’的底部中的沉积的间隔物材料层170’的另一部分，其中凹部R1’是在蚀刻鳍片结构130后留下的。为简单起见，在修整制程之后，将沉积的间隔物材料的剩余部分指示为凹部R2中的内介电质间隔物172。在此非等向性蚀刻制程ET1’期间，在电浆蚀刻制程中使用较少的氟，使得凹部R1’中的间隔物材料层170’的部分可被移除。
在图20中，形成间隔物材料层190’以填充凹部R1’。间隔物材料层190’可为低介电常数介电质材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅、探氧化硅或碳氮氧化硅，且可通过诸如原子层沉积的合适的沉积方法形成。间隔物材料层190’可使用包含低压化学气相沉积及电浆加强化学气相沉积的化学气相沉积、物理气相沉积、原子层沉积或其他合适的制程形成。间隔物材料层190’及间隔物材料层170’是由不同材料制成。
参考图21，在间隔物材料层190’的沉积之后，可执行另一非等向性蚀刻制程ET2来修整沉积的间隔物材料层190’，留下沉积在凹部R1’的底部中的沉积的间隔物材料层190’的部分，其中凹部R1’是在蚀刻鳍片结构130后留下的。在修整制程之后，为简单起见，将沉积的间隔物材料的剩余部分指示为凹部R1’中的底部介电质结构192。
在一些实施例中，非等向性蚀刻制程ET2为电浆蚀刻。具有图20中所例示的结构的基板110可装载至电浆工具中，且暴露于在诸如三氟甲烷、四氟甲烷、八氟环丁烷、八氟环戊烯、六氟丁二烯或类似物种的含氟气体、诸如氩或氦的惰性气体的气体混合物中通过射频或微波功率产生的电浆环境，持续足以蚀刻凹部R1’外侧的间隔物材料层190’的部分的持续时间。在包含三氟甲烷、四氟甲烷及氩的气体混合物中产生的电浆可用来调谐底部介电质结构192的形状。在较多氟的情况下，电浆蚀刻的侧向蚀刻速度增加，且剩下较多的底部介电质结构192。电浆通过具有大于0且等于或小于约30伏特的偏压的射频功率产生。若偏压大于约30伏特，则底部介电质结构192可能会被完全移除；若偏压不存在，则内介电质间隔物172可能会被蚀刻。
参考图22，在图21中的蚀刻制程ET2完成之后，图21的结构经历类似于图9A至图14的制程。亦即，源极/漏极磊晶结构180形成在半导体鳍片130的源极/漏极区域S/D及底部介电质结构192上。层间介电质层210形成于基板110上。以栅极结构220替换虚拟栅极结构150。介电质帽230视情况地形成在回蚀的栅极结构220上。形成源极/漏极触点240，源极/漏极触点240延伸贯穿层间介电质层210(及触点蚀刻终止层层，若存在)。关于前面提到的制程/元件的材料及制造制程细节类似于图9A至图14中所示的那些，且因而为简洁起见在本文中不重复这些材料及制造制程细节。
如以上提到的，底部介电质结构192可由不同于内介电质间隔物172的材料的材料制成。在一些实施例中，内介电质间隔物172及底部介电质结构192具有蚀刻选择性，使得图21中的非等向性蚀刻制程ET2不损坏内介电质间隔物172。替代地或另外，内介电质间隔物172包含高介电常数介电质材料，且底部介电质结构192包含低介电常数介电质材料。例如，内介电质间隔物172包含碳氮氧化硅、氮化硅、其组合或类似者，且底部介电质结构192包含氧化硅、碳化硅、其组合或类似者。因为底部介电质结构192为低介电常数介电质材料，所以可降低集成电路结构100e的寄生电容。集成电路结构100e的其他相关结构及制造细节与图14的集成电路结构100实质上相同或类似，且因此，在下文中将不重复在此方面的描述。
基于以上论述，可看出本揭示案提供优点。然而，应理解，其他实施例可提供额外优点，且并非所有优点在本文中必定予以揭示，且无特定优点为所有实施例需要的。其中一个优点在于底部介电质结构改善贯穿基板的源极/漏极磊晶结构之间的电流漏泄问题，借此亦改善集成电路结构的漏极引发能障降低(drain induced barrier lowering，DIBL)问题。另一个优点在于底部介电质结构的材料可经选择以降低集成电路结构的寄生电容。
根据一些实施例，半导体装置包含基板、通道层、栅极结构、源极/漏极磊晶结构及底部介电质结构。通道层在基板上。栅极结构在基板上且包围通道层。源极/漏极磊晶结构在基板上且连接至通道层。底部介电质结构介于源极/漏极磊晶结构与基板之间。
根据一些实施例，底部介电质结构嵌入基板中。
根据一些实施例，底部介电质结构的顶表面低于基板的顶表面。
根据一些实施例，底部介电质结构的顶表面高于基板的顶表面。
根据一些实施例，源极/漏极磊晶结构与基板间隔开。
根据一些实施例，源极/漏极磊晶结构及底部介电质结构一起定义在源极/漏极磊晶结构及底部介电质结构之间的孔隙。
根据一些实施例，半导体装置包含多个通道层、栅极结构、源极/漏极磊晶结构、内介电质间隔物及底部介电质结构。通道层以间隔开的方式一个在另一个上方地排列在基板上。栅极结构包围多个通道层中的每一个。源极/漏极磊晶结构连接至通道层。内介电质间隔物介于源极/漏极磊晶结构与栅极结构之间。底部介电质结构在源极/漏极磊晶结构以下。
根据一些实施例，内介电质间隔物及底部介电质结构是由不同的材料制成。
根据一些实施例，底部介电质结构的介电常数低于内介电质间隔物的介电常数。
根据一些实施例，源极/漏极磊晶结构及内介电质间隔物定义在源极/漏极磊晶结构及内介电质间隔物之间的孔隙。
根据一些实施例，制造半导体装置的方法包含形成鳍片结构，鳍片结构包含多个第一半导体层及多个第二半导体层，多个第一半导体层及多个第二半导体层交替地堆叠在基板上。虚拟栅极结构横跨鳍片结构形成，使得虚拟栅极结构覆盖鳍片结构的第一部分，而鳍片结构的第二部分暴露。移除鳍片结构的暴露的第二部分。移除鳍片结构的暴露的第二部分下方的基板的一部分以在基板中形成凹部。底部介电质结构形成在基板的凹部中。在形成底部介电质结构之后，源极/漏极磊晶结构形成于鳍片结构的第一部分中的第二半导体层的相反末端表面上。移除虚拟栅极结构以暴露鳍片结构的第一部分。移除鳍片结构的暴露的第一部分中的第一半导体层，而留下鳍片结构的暴露的第一部分中的第二半导体层，第二半导体层悬挂基板上。栅极结构形成以包围悬挂的第二半导体层中的每一个。
根据一些实施例，形成底部介电质结构包含在凹部中及第二半导体层的末端表面上形成介电质层。蚀刻介电质层以形成底部介电质结构。
根据一些实施例，蚀刻介电质层是以电浆蚀刻制程执行，且电浆蚀刻制程是在具有大于0且等于或小于约30伏特的偏压的射频功率下执行。
根据一些实施例，蚀刻介电质层是以电浆蚀刻制程执行，且电浆蚀刻制程的电浆是自包含三氟甲烷、四氟甲烷及氩的气体混合物产生。
根据一些实施例，方法还包含在移除基板的部分之后，侧向地凹入第一半导体层。在侧向地凹入的第一半导体层的多个末端表面上形成内介电质间隔物。
根据一些实施例，在基板中形成底部介电质结构及在侧向地凹入的第一半导体层的末端表面上形成内介电质间隔物是同时执行。
根据一些实施例，在侧向地凹入的第一半导体层的末端表面上形成内介电质间隔物是在形成底部介电质结构之前执行。
根据一些实施例，底部介电质结构的介电常数低于内介电质间隔物的介电常数。
根据一些实施例，在基板中形成凹部是在具有溴化氢及氦的气体混合物的情况下通过非等向性蚀刻制程执行，且溴化氢∶氦在自约1∶1至约1∶8的范围内。
根据一些实施例，在基板中形成凹部使凹部具有在自约1.3至约15的范围内的深宽比。
先前内容概括若干实施例的特征，使得熟悉此项技术者可更好地理解本揭示案的态样。熟悉此项技术者应了解，他们可容易地将本揭示案用作用于设计或修改用于执行相同目的及/或达成本文引入的实施例的相同优点的其他制程及结构的基础。熟悉此项技术者亦应意识到，此类等效构造不脱离本揭示案的精神及范畴，且他们可在不脱离本揭示案的精神及范畴的情况下在本文中做出各种变化、置换，及变更。

Claims (10)

1.一种半导体装置，其特征在于，包含：
一基板；
一通道层，该通道层在该基板上；
一栅极结构，该栅极结构在该基板上且包围该通道层；
一源极/漏极磊晶结构，该源极/漏极磊晶结构在该基板上且连接至该通道层；以及
一底部介电质结构，该底部介电质结构介于该源极/漏极磊晶结构与该基板之间。
2.根据权利要求1所述的装置，其特征在于，该底部介电质结构嵌入该基板中。
3.根据权利要求1所述的装置，其特征在于，该源极/漏极磊晶结构及该底部介电质结构一起定义在该源极/漏极磊晶结构及该底部介电质结构之间的一孔隙。
4.一种半导体装置，其特征在于，包含：
多个通道层，该些通道层以一个置于另一个上方，且间隔开的方式排列在一基板上；
一栅极结构，该栅极结构包围该些通道层中的每一个；
一源极/漏极磊晶结构，该源极/漏极磊晶结构连接至该些通道层；
一内介电质间隔物，该内介电质间隔物介于该源极/漏极磊晶结构与该栅极结构之间；以及
一底部介电质结构，该底部介电质结构在该源极/漏极磊晶结构以下。
5.根据权利要求4所述的装置，其特征在于，该内介电质间隔物及该底部介电质结构是由不同的材料制成。
6.一种制造半导体装置的方法，其特征在于，包含：
形成一鳍片结构，该鳍片结构包含多个第一半导体层及多个第二半导体层，该些第一半导体层及该些第二半导体层交替地堆叠在一基板上；
形成横跨该鳍片结构的一虚拟栅极结构，使得该虚拟栅极结构覆盖该鳍片结构的一第一部分，且暴露该鳍片结构的多个第二部分；
移除该鳍片结构的该些暴露的第二部分；
移除该鳍片结构的该些暴露的第二部分下方的该基板的一部分以在该基板中形成一凹部；
形成一底部介电质结构在该基板的该凹部中；
在形成该底部介电质结构之后，形成一源极/漏极磊晶结构在该鳍片结构的该第一部分中的该些第二半导体层的多个相对末端表面上；
移除该虚拟栅极结构以暴露该鳍片结构的该第一部分；
移除该鳍片结构的该暴露的第一部分中的该些第一半导体层，而留下该鳍片结构的该暴露的第一部分中的该些第二半导体层，该些第二半导体层悬挂该基板上；以及
形成一栅极结构以包围该些悬挂的第二半导体层中的每一个。
7.根据权利要求6所述的方法，其特征在于，形成该底部介电质结构包含：
形成一介电质层于该凹部中及该些第二半导体层的该些末端表面上；以及
蚀刻该介电质层以形成该底部介电质结构。
8.根据权利要求6所述的方法，其特征在于，还包含：
在移除该基板的该部分之后，侧向地凹入该第一半导体层；以及
形成一内介电质间隔物在该些侧向地凹入的第一半导体层的多个末端表面上。
9.根据权利要求8所述的方法，其特征在于，形成该底部介电质结构在该基板中及形成该内介电质间隔物在该些侧向地凹入的第一半导体层的该些末端表面上是同时执行。
10.根据权利要求6所述的方法，其特征在于，在该基板中形成该凹部是在具有溴化氢及氦的一气体混合物的情况下通过一非等向性蚀刻制程执行，且溴化氢:氦在自1:1至1:8的一范围内。
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