TW202240774A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202240774A
TW202240774A TW110121021A TW110121021A TW202240774A TW 202240774 A TW202240774 A TW 202240774A TW 110121021 A TW110121021 A TW 110121021A TW 110121021 A TW110121021 A TW 110121021A TW 202240774 A TW202240774 A TW 202240774A
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Taiwan
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layer
substrate
dielectric
source
bottom dielectric
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TW110121021A
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English (en)
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曾國弼
陳德芳
陳昭成
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置包含一基板、一通道層、一閘極結構、一源極/汲極磊晶結構及一底部介電質結構。通道層在基板上。閘極結構在基板上且包圍通道層。源極/汲極磊晶結構在基板上且連接至通道層。底部介電質結構介於源極/汲極磊晶結構與基板之間。

Description

半導體裝置與其製造方法
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半導體積體電路(integrated circuit，IC)工業經歷了指數增長。積體電路材料及設計中的技術進步產生了IC之多個世代，其中每個世代具有相較於前一世代的較小及較複雜電路。在積體電路演化的過程中，功能密度(亦即，每晶片區域互連裝置之數目)通常已增加，而幾何形狀大小(亦即，可使用製造製程創造的最小元件(或接線))已減小。這個按比例縮小製程通常藉由提高生產效率及降低相關聯的成本來提供效益。
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以下揭示內容提供用於實行所提供的主題之不同特徵的許多不同實施例或實例。以下描述元件及配置的特定實例以簡化本揭示案。當然，這些僅為實例且不欲為限制性的。例如，以下描述中的第二特徵之上或第二特徵上的第一特徵之形成可包含其中第一特徵及第二特徵直接接觸地形成的實施例，且可亦包含其中額外特徵可形成在第一特徵與第二特徵之間，使得第一特徵及第二特徵可不直接接觸的實施例。另外，本揭示案可在各種實例中重複元件符號及/或字母。這個重複係出於簡單性及清晰性之目的，且並不實質上規定所論述的各種實施例及/或組態之間的關係。
此外，諸如「在……下方」、「在……以下」、「下」、「在……上方」、「上」等的空間相對術語可在本文中使用於便於描述，以描述如圖式中所例示的一個元素或特徵與另一元素(多個)或特徵(多個)之關係。除圖式中所描繪的取向之外，空間相對術語意欲涵蓋使用或操作中的裝置之不同取向。設備可以其他方式定向(旋轉90度或以其他取向定向)，且同樣可據此解釋本文所使用的空間相對描述符。
如本文所使用，「大約」、「約」、「近似」或「實質上」將通常意謂在給定值或範圍之20%內，或10%內，或5%內。本文給出的數值量為近似的，意謂若未明確陳述，則術語「大約」、「約」、「近似」或「實質上」可經推斷。此項技術中之一般技術者將瞭解尺寸可根據不同技術節點加以變化。此項技術中之一般技術者將認識到，尺寸取決於特定裝置類型、技術產生、最小特徵大小等。因此，術語意欲根據正評估的技術加以解釋。
奈米結構電晶體(例如全環繞閘極(gate all around，GAA)電晶體結構)可藉由任何合適的方法圖案化。例如，可使用一或多個光微影製程圖案化結構，此一或多個光微影製程包含雙重圖案化或多重圖案化製程。通常，雙重圖案化或多重圖案化製程結合光微影及自我對準製程，從而允許創造出具有小節距的圖案，例如節距小於可使用單個直接光微影製程或其他方式獲得的節距的圖案。例如，在實施例中，犧牲層形成在基板上且使用光微影製程加以圖案化。使用自我對準製程與圖案化的犧牲層並排形成間隔物。接著移除犧牲層，且剩餘間隔物可接著用來圖案化全環繞閘極結構。
本揭示案與積體電路結構及形成這些積體電路結構之方法有關。更具體而言，本揭示案之一些實施例與包含源極/汲極磊晶結構下方之介電質結構的全環繞閘極裝置有關。介電質結構用以改良源極/汲極磊晶結構之電流漏泄問題。
第1圖至第14圖例示根據本揭示案之一些實施例的積體電路結構(或半導體裝置) 100之形成中之中間階段的立體圖及橫截面圖。除積體電路結構之外，第1圖至第4A圖、第5A圖及第6A圖描繪X軸、Y軸與Z軸方向。形成的電晶體可包含根據一些示範性實施例的p型電晶體(諸如p型全環繞閘極鰭式場效電晶體)及/或n型電晶體(諸如n型全環繞閘極鰭式場效電晶體)。綜觀各種視圖及例示性實施例，相似元件符號用來指定相似元素。應理解，可在藉由第1圖至第14圖所示的製程之前、期間及之後提供額外的操作，且對於方法之額外實施例，可替換或消除以下描述的一些操作。操作/製程之順序可為可互換的。
第1圖至第4A圖、第5A圖及第6A圖為處於製造期間之中間階段處的積體電路結構100之一些實施例的立體圖。第4B圖、第5B圖、第6B圖至第12A圖及第13圖至第14圖為沿著第一切割線(例如，第4A圖中的切割線X-X)的處於製造期間之中間階段處的積體電路結構100之一些實施例的橫截面圖，該第一切割線沿著通道之縱向方向且垂直於基板之頂表面。第12B圖為沿著第二切割線(例如，第4A圖中之切割線Y-Y)的處於製造期間之中間階段處的積體電路結構100之一些實施例的橫截面圖，該第二切割線在閘極區域中且垂直於通道之縱向方向。
參考第1圖，磊晶堆疊120形成在基板110上。在一些實施例中，基板110可包含矽(Si)。或者，基板110可包含鍺(Ge)、矽鍺(SiGe)、第三-五(III-V)族材料(例如，砷化鎵(GaAs)、磷化鎵(GaP)、砷磷化鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化銦鎵(GaInAs)、砷化銦(InAs)、磷化鎵銦(GaInP)、磷化銦(InP)、銻化銦(InSb)與/或砷磷化鎵銦(GaInAsP)或其組合)或其他適當的半導體材料。在一些實施例中，基板110可包含諸如埋入式介電質層的絕緣體上半導體(semiconductor-on-insulator，SOI)結構。或者，基板110可包含諸如埋入式氧化物(buried oxide，BOX)層的埋入式介電質層，諸如藉由被稱為氧植入分離(separation by implantation of oxygen，SIMOX)技術的方法、晶圓黏接、選擇性磊晶生長(selectively epitaxial growth，SEG)或另一適當方法形成的埋入式介電質層。
磊晶堆疊120包含有第二組成物之磊晶層124穿插其中的第一組成物之磊晶層122。第一組成物及第二組成物可為不同的。在一些實施例中，磊晶層122為矽鍺且磊晶層124為矽(Si)。然而，其他實施例為可能的，其他實施例包含提供具有不同氧化速度及/或蝕刻選擇性的第一組成物及第二組成物。在一些實施例中，磊晶層122包含矽鍺且其中磊晶層124包含矽，磊晶層124之矽氧化速度小於磊晶層122之矽鍺氧化速度。
磊晶層124或其部分可形成奈米結構電晶體之奈米結構通道。術語奈米結構在本文中用來指定具有奈米尺度或甚至微米尺度尺寸且具有狹長形狀的任何材料部分，而無論此部分之橫截面形狀如何。因而，此術語指定圓形及實質上圓形橫截面的狹長材料部分，及包含例如形狀為圓柱形或實質上矩形橫截面的橫樑或棒形材料部分。例如，奈米結構為奈米片、奈米線、奈米板或奈米環，取決於其幾何形狀。以下進一步論述磊晶層124對於定義裝置之通道或多個通道之使用。
應注意，磊晶層122之三個層及磊晶層124之三個層如第1圖中所例示地交替排列，此僅出於例示性目的且不欲為限制在超過申請專利範圍中所具體敘述的範圍。可瞭解，任何數目的磊晶層可形成在磊晶堆疊120中；層之數目取決於用於電晶體之通道區域所要的數目。在一些實施例中，磊晶層124之數目在2與10之間。
如以下更詳細地描述的，磊晶層124可作為用於隨後形成的半導體裝置之通道區域，且厚度係基於裝置效能考慮來選擇。通道區域中之磊晶層122最終可被移除且用來定義用於隨後形成的多閘極裝置之相鄰通道區域之間的垂直距離，且厚度係基於裝置效能考慮來選擇。因此，磊晶層122亦可稱為犧牲層，且磊晶層124亦可稱為通道層。
舉例而言，磊晶堆疊120之層之磊晶生長可藉由分子束磊晶(molecular beam epitaxy，MBE)製程、金屬有機化學氣相沈積(metalorganic chemical vapor deposition，MOCVD)製程及/或其他合適的磊晶生長製程執行。在一些實施例中，諸如磊晶層124的磊晶生長層包含與基板110相同的材料。在一些實施例中，磊晶層122及124包含與基板110不同的材料。如以上所述，在至少一些實例中，磊晶層122包含磊晶生長矽鍺(SiGe)層且磊晶層124包含磊晶生長矽(Si)層。或者，在一些實施例中，磊晶層122及124中之任一者可包含諸如鍺的其他材料、諸如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦的化合物半導體、諸如矽鍺、砷磷化鎵、砷化鋁銦、砷化鋁鎵、砷化銦鎵、磷化鎵銦與/或砷磷化鎵銦或其組合的合金半導體。如所論述，可基於所提供的不同的氧化及/或蝕刻選擇性性質選擇磊晶層122及124之材料。在一些實施例中，磊晶層122及124為實質上無摻雜劑的(亦即，具有自約0/立方公分至約1×10 18/立方公分之外來摻雜劑濃度)，其中例如，在磊晶生長製程期間不執行意向性摻雜。
參考第2圖，形成自基板110延伸的複數個半導體鰭片130。在各種實施例中，鰭片130中之每一個包含由基板110形成的基板部分112及包含磊晶層122及124的磊晶堆疊之磊晶層中之每一個之部分。鰭片130可使用包含雙重圖案化及多重圖案化製程的合適的製程製造。通常，雙重圖案化或多重圖案化製程結合光微影及自我對準製程，從而允許創造出具有小節距的圖案，例如節距小於可使用單個直接光微影製程或其他方式獲得的節距的圖案。例如，在一個實施例中，犧牲層形成在基板上且使用光微影製程加以圖案化。使用自我對準製程與圖案化的犧牲層並排形成間隔物。然後移除犧牲層，且剩餘間隔物或心軸可接著用來藉由蝕刻初始磊晶堆疊120圖案化鰭片130。蝕刻製程可包含乾式蝕刻、濕式蝕刻、反應性離子蝕刻(reactive ion etching，RIE)及/或其他合適的製程。
在如第1圖及第2圖中所例示的實施例中，在圖案化鰭片130之前在磊晶堆疊120上形成硬遮罩(hard mask，HM)層910。在一些實施例中，硬遮罩層包含氧化物層912 (例如，可包含二氧化矽的氧化物墊層)及形成在氧化物層上的氮化物層914 (例如，可包含氮化矽(Si 3N 4)的氮化物墊層)。氧化物層912可作為磊晶堆疊120與氮化物層914之間的黏合層且可作為用於蝕刻氮化物層914的蝕刻終止層。在一些實例中，硬遮罩氧化物層912包含熱生長氧化物、化學氣相沈積(chemical vapor deposition，CVD)沉積的氧化物及/或原子層沈積(atomic layer deposition，ALD)沉積的氧化物。在一些實施例中，硬遮罩氮化物層914藉由化學氣相沈積及/或其他合適的技術沉積在硬遮罩氧化物層912上。
隨後可使用包含光微影及蝕刻製程的合適的製程製造鰭片130。光微影製程可包含將光阻劑層(未示出)形成在硬遮罩層910上、在圖案下曝光光阻劑、執行曝光後烘烤製程及顯影光阻劑以形成包含光阻劑的圖案化的遮罩。在一些實施例中，圖案化光阻劑以形成圖案化的遮罩元件可使用電子束微影術製程或極紫外線(extreme ultraviolet，EUV)微影術製程執行，該極紫外線微影術製程使用具有例如約1至200奈米之波長的極紫外線區域內之光。圖案化的遮罩可接著用來在蝕刻製程使溝槽102形成於貫穿硬遮罩層910、貫穿磊晶堆疊120且進入基板110中的未保護區域中時，保護基板110之區域及形成在上方的層，藉此留下複數個延伸鰭片130。可使用乾式蝕刻(例如，反應離子蝕刻)、濕式蝕刻及/或其組合蝕刻溝槽102。亦可使用用以將鰭片形成在基板上的方法之許多其他實施例，包含例如定義鰭片區域(例如，藉由遮罩或隔離區域)及磊晶生長呈鰭片130形式的磊晶堆疊120。
接下來，如第3圖中所例示，形成插在鰭片130中間的隔離區域140。隔離區域140可包含襯墊氧化物(未示出)。襯墊氧化物可由藉由基板110之表面層之熱氧化形成的熱氧化物形成。襯墊氧化物亦可為使用例如原子層沈積(Atomic Layer Deposition，ALD)、高密度電漿化學氣相沈積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)或化學氣相沈積(Chemical Vapor Deposition，CVD)形成的沉積氧化矽層。隔離區域140亦可包含襯墊氧化物上的介電質材料，且可使用可流動化學氣相沈積(flowable chemical vapor deposition，FCVD)、旋塗塗佈或類似者形成介電質材料。
然後凹入隔離區域140，使得磊晶堆疊120之頂部部分突出高於相鄰隔離區域140之頂表面以形成突出鰭片130。可使用乾式蝕刻製程執行蝕刻，其中將氨(NH 3)及三氟化氮(NF 3)用作蝕刻氣體。在蝕刻製程期間，可產生電漿。氬亦可包含在內。根據本揭示案之替代性實施例，使用濕式蝕刻製程執行隔離區域140之凹入。蝕刻化學品可包含例如稀釋的氟化氫(HF)。
參考第4A圖及第4B圖。虛擬閘極結構150形成在基板110上且至少部分地置於鰭片130上。置於虛擬閘極結構150下方的鰭片130之部分可稱為通道區域。虛擬閘極結構150可亦定義鰭片130之源極/汲極(source/drain，S/D)區域，例如，與通道區域相鄰且在通道區域之相對側上的鰭片130之區域。
虛擬閘極形成操作首先將虛擬閘極介電質層152形成在鰭片130上。隨後，虛擬閘極電極層154及可包含多個層156及158 (例如，氧化物層156及氮化物層158)的硬遮罩形成在虛擬閘極介電質層152上。然後圖案化硬遮罩，接著藉由使用圖案化的硬遮罩作為蝕刻遮罩來圖案化虛擬閘極介電質層152。在一些實施例中，在圖案化虛擬閘極電極層154之後，自鰭片130之源極/汲極區域移除虛擬閘極介電質層152。蝕刻製程可包含濕式蝕刻、乾式蝕刻及/或其組合。蝕刻製程經選擇來選擇性地蝕刻虛擬閘極介電質層152而實質上不蝕刻鰭片130、虛擬閘極電極層154、氧化物遮罩層156及氮化物遮罩層158。
在虛擬閘極結構150之形成完成之後，在虛擬閘極結構150之側壁上形成閘極間隔物160。例如，在基板110上沉積間隔物材料層。間隔物材料層可為共形層，該共形層隨後經回蝕以形成閘極側壁間隔物。在例示的實施例中，間隔物材料層160共形地置於虛擬閘極結構150之頂部及側壁上。間隔物材料層160可包含諸如氧化矽、氮化矽、碳化矽、氮氧化矽、碳氮化矽(SiCN)膜、碳氧化矽、碳氮氧化矽(SiOCN)膜及/或其組合的介電質材料。在一些實施例中，間隔物材料層160包含多個層，諸如第一間隔物層162及形成在第一間隔物層162上的第二間隔物層164 (例示於第4B圖中)。舉例而言，可藉由使用合適的沉積製程將介電質材料沉積在虛擬閘極結構150上以形成間隔物材料層160。然後對沉積的間隔物材料層160執行非等向性蝕刻製程以暴露未被虛擬閘極結構150 (例如，鰭片130之源極/汲極區域中的虛擬閘極結構)覆蓋的鰭片130之部分。直接在虛擬閘極結構150上方的間隔物材料層之部分可藉由此非等向性蝕刻製程完全移除。虛擬閘極結構150之側壁上的間隔物材料層之部分可保留，從而形成閘極側壁間隔物，為簡單起見，該等閘極側壁間隔物經標示為閘極間隔物160。應注意，儘管閘極間隔物160為第4B圖之橫截面圖中的多層結構，但為簡單起見，該等閘極間隔物經例示為第4A圖之立體圖中的單層結構。
接下來，如第5A圖及第5B圖中所例示，藉由使用例如非等向性蝕刻製程蝕刻側向延伸超過閘極間隔物160 (例如，在鰭片130之源極/汲極區域S/D中)的半導體鰭片130之暴露部分，該非等向性蝕刻製程使用虛擬閘極結構150及閘極間隔物160作為蝕刻遮罩，從而形成進入半導體鰭片130中及介於對應的虛擬閘極結構150之間的凹部R1。在非等向性蝕刻之後，磊晶層122及通道層124之末端表面及閘極間隔物160之各別最外側壁由於非等向性蝕刻的關係而為實質上相連的。在一些實施例中，非等向性蝕刻可藉由具有電漿源及反應氣體之乾式化學蝕刻執行。電漿源可為感應耦合電漿(inductively coupled plasma，ICR)源、變壓器耦合電漿(transformer coupled plasma，TCP)源、電子迴旋共振(electron cyclotron resonance，ECR)源或類似者，且反應氣體可為例如以氟為主的氣體(諸如六氟化硫(SF 6)、二氟甲烷(CH 2F 2)、氟甲烷(CH 3F)、三氟甲烷(CHF 3)或類似者)、以氯為主的氣體(例如，氯氣(Cl 2))、溴化氫氣體(HBr)、氧氣(O 2)、類似者或其組合。
基板部分112亦在此非等向性蝕刻製程中凹入以形成凹部R1’。在一些實施例中，用於蝕刻基板部分112的反應氣體為溴化氫及氦(He)之氣體混合物。在此非等向性蝕刻製程中，氣體混合物以垂直蝕刻速度及比垂直蝕刻速度較緩慢的側向蝕刻速度蝕刻基板部分112。在更多溴化氫的情況下，垂直蝕刻速度增加；在更多氦的情況下，側向蝕刻速度增加。因而，可藉由調諧溴化氫與氦之比調整凹部R1’之形狀。例如，溴化氫:氦在自約1:1至約1:8之範圍內以獲得橫截面圖(參見第5B圖)中之V形凹部R1’。若溴化氫:氦大於約1:8，則凹部R1’具有橫截面圖中之U形(亦即，側向蝕刻速度增加)。若溴化氫:氦小於約1:1，則凹部R1’不足以深到可容納底部介電質結構174 (參見第8圖)。
在一些其他實施例中，可藉由調諧反應氣體之壓力調整凹部R1’之形狀。例如，反應氣體之壓力在自約3毫托至約10毫托之範圍內。若壓力大於約10毫托，則蝕刻速度可能太緩慢；若壓力小於約3毫托，則凹部R1’可能具有橫截面圖中之U形。
在一些實施例中，每一個凹部R1’具有深度H1。例如，深度H1在自約1奈米至約500奈米之範圍內。若深度H1大於約500奈米，則源極/汲極磊晶結構180 (參見第9A圖)可能不容易沉積在底部介電質結構174 (參見第9A圖)上；若深度H1小於約1 奈米，則沒有空間容納底部介電質結構174，且源極/汲極磊晶結構180可能具有電流漏泄問題。在一些實施例中，凹部R1’具有大於約1.3，例如，在自約1.3至約15之範圍內的深寬比(對於凹部定義為凹部深度H1/寬度W1之比)。凹部R1在高深寬比的情況下更像橫截面圖中之V形，且在低深寬比的情況下更像橫截面圖中之U形。
接下來，在第6A圖及第6B圖中，使用合適的蝕刻技術側向地或水平地凹入磊晶層122，從而導致每個垂直地介於對應的通道層124之間的側向凹部R2。此操作可藉由使用選擇性蝕刻製程來執行。舉例而言且不限於，磊晶層122為矽鍺且通道層124為矽，從而允許磊晶層122之選擇性蝕刻。在一些實施例中，選擇性濕式蝕刻包含APM蝕刻(例如，氫氧化氨-過氧化氫-水混合物)，該氫氧化氨-過氧化氫-水混合物蝕刻以相較於其蝕刻矽的較快蝕刻速度蝕刻矽鍺。在一些實施例中，選擇性蝕刻包含矽鍺氧化，接著是矽鍺氧化物(SiGeO x)移除。例如，氧化可藉由臭氧(O 3)清潔提供，然後藉由諸如氨水(NH 4OH)的蝕刻劑移除矽鍺氧化物(SiGeO x)，該蝕刻劑以相較於其蝕刻矽的較快蝕刻速度選擇性地蝕刻矽鍺氧化物(SiGeO x)。此外，因為矽之氧化速度比矽鍺之氧化速度低得多(有時低30倍)，所以使磊晶層122側向地凹入的製程並未顯著地蝕刻通道層124。因此，通道層124側向地延伸超過磊晶層122之相對末端表面。
在第7圖中，形成間隔物材料層170’以填充藉由以上參考第6A圖及第6B圖所論述的磊晶層122之側向蝕刻留下的凹部R2。間隔物材料層170’之部分亦沉積在凹部R1’中。間隔物材料層170’可為低介電常數(k)介電質材料，諸如二氧化矽、氮化矽、碳化矽、碳氮化矽、氮氧化矽或碳氮氧化矽，且可藉由諸如原子層沈積的合適的沈積方法形成。在一些實施例中，內介電質間隔物材料層170’為本質的，或未以雜質摻雜的。間隔物材料層170’可使用包含低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)及電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)的化學氣相沉積、物理氣相沉積(physical vapor deposition，PVD)、原子層沈積，或其他合適的製程形成。在一些實施例中，儘管間隔物材料層170’共形地形成在凹部R1’中，但間隔物材料層170’在V形凹部R1’中比在U形凹部中更容易合併。合併的間隔物材料層170’導致厚的底部介電質結構174形成 (參見第8圖)。
參考第8圖，在間隔物材料層170’之沈積之後，可執行非等向性蝕刻製程ET1來修整沉積的間隔物材料層170’，留下使得填充藉由磊晶層122之側向蝕刻留下的凹部R2的沉積的間隔物材料層170’之部分，且留下沉積在凹部R1’之底部中的沉積的間隔物材料層170’之另一部分，凹部R1’係在鰭片結構130的蝕刻後留下的。在修整製程之後，為簡單起見，將沉積的間隔物材料之剩餘部分標示為凹部R2中之內介電質間隔物172及凹部R1’中之底部介電質結構174。內介電質間隔物172用來隔離金屬閘極與在後續處理中形成的源極/汲極磊晶結構，且底部介電質結構174用來隔離源極/汲極磊晶結構與基板110。在第8圖之實例中，內介電質間隔物172之側壁實質上對準通道層124之側壁。
在一些實施例中，非等向性蝕刻製程ET1為電漿蝕刻。具有第7圖中所例示之結構的基板110可裝載至電漿工具中，且暴露於在諸如三氟甲烷(CHF 3)、四氟甲烷(CF 4)、八氟環丁烷(C 4F 8)、八氟環戊烯(C 5F 8)、六氟丁二烯(C 4F 6)或類似物種的含氟氣體、諸如氬或氦的惰性氣體之氣體混合物中藉由射頻(radiofrequency，RF)或微波功率產生的電漿環境，持續足以蝕刻凹部R1’及R2外側的間隔物材料層170’之部分的持續時間。在包含三氟甲烷、四氟甲烷及氬的氣體混合物中產生的電漿可用來調諧底部介電質結構174之形狀。在較多氟的情況下，電漿蝕刻之側向蝕刻速度增加，且剩下較多的底部介電質結構174。電漿藉由具有大於0且等於或小於約30伏特之偏壓之射頻功率產生。若偏壓大於約30伏特，則底部介電質結構174可能完全移除；若偏壓不存在，則內介電質間隔物172可能會被過度蝕刻。
在第9A圖中，源極/汲極磊晶結構180形成在半導體鰭片130之源極/汲極區域S/D上。源極/汲極磊晶結構180可藉由執行磊晶生長製程來形成，該磊晶生長製程將磊晶材料提供在鰭片130上。在磊晶生長製程期間，虛擬閘極結構150、閘極側壁間隔物160、內介電質間隔物172及底部介電質結構174將源極/汲極磊晶結構180限制於源極/汲極區域S/D。在一些實施例中，源極/汲極磊晶結構180之晶格常數不同於磊晶層124之晶格常數，使得磊晶層124可藉由源極/汲極磊晶結構180加應變或加應力以改良半導體裝置之載子遷移率且增強裝置效能。磊晶製程包含化學氣相沈積技術(例如，電漿增強化學氣相沉積、氣相磊晶(vapor-phase epitaxy，VPE)及/或超高真空化學氣相沈積 (ultra-high vacuum CVD，UHV-CVD))、分子束磊晶及/或其他合適的製程。磊晶製程可使用氣體及/或液體前驅物，這些氣體及/或液體前驅物與磊晶層124之組成物相互作用。
在一些實施例中，源極/汲極磊晶結構180可包含鍺、矽、砷化鎵、砷化鋁鎵、矽鍺、砷磷化鎵、磷化矽(SiP)或其他合適的材料。源極/汲極磊晶結構180可在磊晶製程期間藉由引入摻雜物種原位摻雜，摻雜物種包含：p型摻雜劑，諸如硼或二氟化硼(BF 2)；n型摻雜劑，諸如磷或砷；及/或包含其組合的其他合適的摻雜劑。若源極/汲極磊晶結構180並非原位摻雜的，則執行植入製程(亦即，接合面佈植製程)來摻雜源極/汲極磊晶結構180。在一些示範性實施例中，n型電晶體中的源極/汲極磊晶結構180包含磷化矽，而p型中的源極/汲極磊晶結構180包含GeSnB及/或SiGeSnB。在具有不同裝置類型的實施例中，諸如光阻劑的遮罩可形成在n型裝置區域上，而暴露p型裝置區域，且p型磊晶結構可形成在p型裝置區域中之底部介電質結構174上。然後可移除遮罩。隨後，諸如光阻劑的遮罩可形成在p型裝置區域上，而暴露n型裝置區域，且n型磊晶結構可形成在n型裝置區域中之底部介電質結構174上。然後可移除遮罩。
一旦形成源極/汲極磊晶結構180，可執行退火製程來活化源極/汲極磊晶結構180中之p型摻雜劑或n型摻雜劑。退火製程可為例如快速熱退火(rapid thermal anneal，RTA)、雷射退火、毫秒熱退火(millisecond thermal annealing，MSA)製程或類似者。
第9B圖及第9C圖為根據一些實施例的第9A圖中之區域A的放大視圖。在第9B圖中，內介電質間隔物172愈低，內介電質間隔物172之大小愈大。在一些實施例中，內介電質間隔物172之大小藉由可在第6B圖中所示之側向凹入製程期間調諧的凹部R2 (參見第6B圖)之大小決定。此外，底部介電質結構174暴露凹部R1’之內表面之部分。在此組態的情況下，源極/汲極磊晶結構180可填充凹部R1’之剩餘部分。亦即，源極/汲極磊晶結構180與基板110接觸；如此，第9B圖中之底部介電質結構174亦改善源極/汲極磊晶結構180之電流漏泄問題。在第9C圖中，內介電質間隔物172及/或底部介電質結構174中之至少一個具有其中之孔隙175。孔隙175藉由內介電質間隔物172及源極/汲極磊晶結構180或藉由底部介電質結構174及源極/汲極磊晶結構180定義。因為間隔物材料層170’(參見第7圖)共形地形成於凹部R1’及R2中，所以若間隔物材料層170’為薄的，則間隔物材料層170’可能無法填充凹部R1’及/或R2。因而，在第8圖中之非等向性蝕刻製程ET1之後，孔隙175可形成於內介電質間隔物172及/或底部介電質結構174中。
在第10圖中，層間介電質(interlayer dielectric，ILD)層210形成於基板110上。在一些實施例中，觸點蝕刻終止層(contact etch stop layer，CESL)亦在形成層間介電質層210之前形成。在一些實例中，觸點蝕刻終止層包含氮化矽層、氧化矽層、氧氮化矽及/或具有與層間介電質層210的蝕刻選擇性不同之其他合適的材料。觸點蝕刻終止層可藉由電漿增強化學氣相沈積(plasma-enhanced chemical vapor deposition，PECVD)製程及/或其他合適的沈積或氧化製程形成。在一些實施例中，層間介電質層210包含諸如四乙基矽酸鹽(tetraethylorthosilicate，TEOS)形成的氧化物、未摻雜的矽酸鹽玻璃或諸如硼磷矽玻璃(borophosphosilicate glass，BPSG)、熔融矽石玻璃(fused silica glass，FSG)、磷矽玻璃(phosphosilicate glass，PSG)、硼摻雜的矽玻璃(boron doped silicon glass，BSG)之摻雜的氧化矽之材料，及/或具有與觸點蝕刻終止層的蝕刻選擇性不同的其他合適的介電質材料。層間介電質層210可藉由電漿增強化學氣相沈積製程或其他合適的沈積技術沉積。在一些實施例中，在層間介電質層210形成之後，晶圓可經過高熱預算(thermal budget)製程以退火層間介電質層210。
在一些實例中，在沉積層間介電質層210之後，可執行平坦化製程來移除層間介電質層210之過量材料。例如，平坦化製程包含化學機械平坦化(chemical mechanical planarization，CMP)製程，該化學機械平坦化製程移除覆蓋在虛擬閘極結構150上的層間介電質層210 (及觸點蝕刻終止層層，若存在)之部分且平坦化積體電路結構100之頂表面。在一些實施例中，化學機械平坦化製程亦移除硬遮罩層156及158 (如第9A圖中所示)且暴露虛擬閘極電極層154。
此後，首先移除虛擬閘極結構150 (如第9A圖中所示)，且然後移除磊晶層(亦即，犧牲層) 122 (如第10圖中所示)。所得結構例示於第11圖中。在一些實施例中，藉由使用選擇性蝕刻製程(例如，選擇性乾式蝕刻、選擇性濕式蝕刻或其組合)移除虛擬閘極結構150，該選擇性蝕刻製程以相較於其蝕刻其他材料(例如，閘極側壁間隔物160及/或層間介電質層210)較快的蝕刻速度蝕刻虛擬閘極結構150中之材料，因而產生介於對應的閘極側壁間隔物160之間的閘極溝槽GT1，並且磊晶層122暴露在閘極溝槽GT1中。隨後，藉由使用另一選擇性蝕刻製程移除閘極溝槽GT1中之磊晶層122，該另一選擇性蝕刻製程以相較於其蝕刻通道層124的較快蝕刻速度蝕刻磊晶層122，因而形成介於相鄰磊晶層(亦即，通道層) 124之間的開口O1。以此方式，磊晶層124成為懸掛在基板110上及源極/汲極磊晶結構180之間的奈米片。此操作亦稱為通道釋放製程。在此中間處理操作終，磊晶層(亦即，奈米片) 124之間的開口O1可充滿周圍環境條件(例如，空氣、氮等)。在一些實施例中，磊晶層124可互換地稱為奈米結構(奈米線、奈米板及奈米環、奈米片等，取決於其幾何形狀)。例如，在一些其他實施例中，由於用於完全移除磊晶層122之選擇性蝕刻製程，磊晶層124可經修整以具有實質圓形形狀(亦即，圓柱形)。在那一狀況下，所得磊晶層124可稱為奈米線。
在一些實施例中，藉由使用選擇性濕式蝕刻製程移除磊晶層122。在一些實施例中，磊晶層122為矽鍺且磊晶層124為矽，從而允許磊晶層122之選擇性移除。在一些實施例中，選擇性濕式蝕刻包含APM蝕刻(例如，氫氧化氨-過氧化氫-水混合物)。在一些實施例中，選擇性移除包含矽鍺氧化，接著是矽鍺氧化物(SiGeO x)移除。例如，氧化可藉由臭氧清潔提供，然後藉由諸如氨水的蝕刻劑移除矽鍺氧化物(SiGeO x)，該蝕刻劑以相較於其蝕刻矽的較快蝕刻速度選擇性地蝕刻矽鍺氧化物(SiGeO x)。此外，因為矽之氧化速度比矽鍺之氧化速度低得多(有時低30倍)，所以通道釋放製程可能不會顯著地蝕刻矽鍺。可注意到，通道釋放操作及側向地凹入犧牲層之先前操作(如第6A圖及第6B圖中所示之操作)皆使用以相較於蝕刻矽的較快蝕刻速度蝕刻矽鍺的選擇性蝕刻製程，且因此這兩個操作可在一些實施例中使用相同蝕刻劑化學品。在此狀況下，通道釋放操作之蝕刻時間/持續時間比側向地凹入犧牲層之先前操作之蝕刻時間/持續時間更長，以便完全移除犧牲矽鍺層。
在第12A圖及第12B圖中，替換閘極結構220分別形成於閘極溝槽GT1中以包圍懸掛在閘極溝槽GT1中的每一個磊晶層124。閘極結構220可為全環繞閘極鰭式場效電晶體之最終閘極。最終閘極結構可為高介電常數/金屬閘極堆疊，然而其他組成物為可能的。在一些實施例中，每一個閘極結構220形成與藉由複數個磊晶層124提供的多通道相關聯的閘極。例如，高介電常數/金屬閘極結構220形成在藉由釋放磊晶層124而提供的開口O1 (如第12A圖中所例示)內。在各種實施例中，高介電常數/金屬閘極結構220包含形成在磊晶層124周圍的閘極介電質層222、形成在閘極介電質層222周圍的功函數金屬層224及形成在功函數金屬層224周圍且填充閘極溝槽GT1之剩餘部分的填充金屬226。閘極介電質層222包含界面層(例如，氧化矽層)及界面層上之高介電常數閘極介電質層。高介電常數閘極介電質包含具有例如大於熱氧化矽之介電常數(~3.9)之高介電常數的介電質材料。使用在高介電常數/金屬閘極結構220內的功函數金屬層224及/或填充金屬226可包含金屬、金屬合金或金屬矽化物。高介電常數/金屬閘極結構220之形成可包含用以形成各種閘極材料、一或多個襯墊層的沈積，及用以移除過量閘極材料的一或多個化學機械平坦化製程。如沿著高介電常數/金屬閘極結構220之縱向軸線取得的第12B圖之橫截面圖中所例示，高介電常數/金屬閘極結構220包圍每一個磊晶層124，且因而稱為全環繞閘極鰭式場效電晶體之閘極。
在一些實施例中，閘極介電質層222之界面層可包含諸如氧化矽(SiO 2)、氧化鉿矽(HfSiO)或氮氧化矽(SiON)之介電質材料。界面層可藉由化學氧化、熱氧化、原子層沈積(atomic layer deposition，ALD)、化學氣相沈積(chemical vapor deposition，CVD)及/或其他合適的方法形成。閘極介電質層222之高介電常數介電質層可包含氧化鉿(HfO 2)。或者，閘極介電質層222可包含其他高介電常數介電質，諸如氧化鉿矽(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、氧化鉿鋯(HfZrO)、氧化鑭(LaO)、氧化鋯(ZrO)、氧化鈦(TiO)、氧化鉭(Ta 2O 5)、氧化釔(Y 2O 3)、氧化鍶鈦(SrTiO 3，STO)、氧化鋇鈦(BaTiO 3，BTO)、氧化鋇鋯(BaZrO)、氧化鉿鑭(HfLaO)、氧化鑭矽(LaSiO)、氧化鋁矽(AlSiO)、氧化鋁(Al 2O 3)、氮化矽(Si 3N 4)、氮氧化矽(SiON)及其組合。
功函數金屬層224可包含用以提供用於高介電常數/金屬閘極結構220之合適的功函數的功函數金屬。對於n型鰭式場效電晶體，功函數金屬層224可包含一或多個n型功函數金屬(N金屬)。n型功函數金屬可示範性地包含但不限於：鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、碳氮化鉭(TaCN)、鉿(Hf)、鋯(Zr)、鈦(Ti)、鉭(Ta)、鋁(Al)、金屬碳化物(例如，碳化鉿(HfC)、碳化鋯(ZrC)、碳化鈦(TiC)、碳化鋁(AlC))、鋁化物及/或其他合適的材料。另一方面，對於p型鰭式場效電晶體，功函數金屬層134可包含一或多個p型功函數金屬(P金屬)。p型功函數金屬可示範性地包含但不限於：氮化鈦(TiN)、氮化鎢(WN)、鎢(W)、釕(Ru)、鈀(Pd)、鉑(Pt)、鈷(Co)、鎳(Ni)、導電金屬氧化物及/或其他合適的材料。
在一些實施例中，填充金屬226可示範性地包含但不限於：鎢、鋁、銅、鎳、鈷、鈦、鉭、氮化鈦、氮化鉭、矽化鎳、矽化鈷、碳化鈦(TaC)、矽氮化鉭(TaSiN)、碳氮化鉭、鈦鋁、氮化鈦鋁或其他合適的材料。
在第13圖中，視情況地，執行回蝕製程來回蝕替換閘極結構220，從而形成回蝕的閘極結構220上之凹部。在一些實施例中，因為替換閘極結構220之材料具有與閘極間隔物160不同的蝕刻選擇性，所以替換閘極結構220之頂表面高度可低於閘極間隔物160之頂表面高度。
介電質帽230可視情況地形成在回蝕的閘極結構220上。介電質帽層230包含氮化矽(SiN x)、氧化鋁(Al xO y)、氮氧化鋁(AlON)、碳氧化矽(SiO xC y)、碳氮化矽(SiC xN y)、其組合或類似者，且係藉由諸如化學氣相沉積、電漿增強化學氣相沉積 (plasma-enhanced CVD，PECVD)、原子層沈積、遠端電漿原子層沈積 (remote plasma 原子層沈積，RPALD)、電漿增強原子層沈積 (plasma - enhanced ALD，PEALD)、其組合或類似者之合適的沈積技術形成。然後執行化學機械平坦化製程來移除凹部外側的帽層，從而留下凹部中之介電質帽層之部分以作為介電質帽230。
在第14圖中，形成源極/汲極觸點240，源極/汲極觸點240延伸貫穿層間介電質層210 (及觸點蝕刻終止層層，若存在)。舉例而言但不限制，源極/汲極觸點240之形成包含執行一或多個蝕刻製程以形成延伸貫穿層間介電質層210的觸點開口，以暴露源極/汲極磊晶結構180、沉積超填觸點開口的一或多個金屬材料，然後執行化學機械平坦化製程以移除觸點開口外側的過量金屬材料。在一些實施例中，一或多個蝕刻製程為選擇性蝕刻，該選擇性蝕刻以相較於蝕刻介電質帽230及閘極間隔物160的較快蝕刻速度蝕刻層間介電質層210。因此，選擇性蝕刻係使用介電質帽230及閘極間隔物160作為蝕刻遮罩來執行，使得在不使用額外光微影製程的情況下形成自我對準至源極/汲極磊晶結構180的觸點開口及源極/汲極觸點240。在那一狀況下，允許形成自我對準的源極/汲極觸點240的介電質帽230可稱為SAC帽230。
積體電路結構100包含基板110、以間隔開的方式一個在另一個上方地排列在基板110上的通道層124、包圍/包裹每一個通道層124的閘極結構220、連接至通道層124的源極/汲極磊晶結構180及介於源極/汲極磊晶結構180與基板110之間的底部介電質結構174。亦即，源極/汲極磊晶結構180藉由底部介電質結構174與基板110分離。底部介電質結構174分別位於源極/汲極磊晶結構180以下以防止源極/汲極磊晶結構180之電流洩漏至基板110中，然後洩漏至其他源極/汲極磊晶結構180。
在一些實施例中，底部介電質結構174嵌入基板110中且與基板110之凹部R1’之內表面共形。亦即，底部介電質結構174具有彎曲(凸形)底表面及彎曲(凹形)頂表面。底部介電質結構174之頂表面174a低於基板110之頂表面111。底部介電質結構174之最大厚度H2在自約1 奈米至約500 奈米之範圍內。若厚度H2大於約500 奈米，則源極/汲極磊晶結構180可能不容易沉積在底部介電質結構174上；若厚度H2小於約1 奈米，則源極/汲極磊晶結構180可能具有電流漏泄問題。
在一些實施例中，積體電路結構100更包含介於閘極結構220與源極/汲極磊晶結構180之間的內介電質間隔物172。如第7圖至第8圖中所描述，因為內介電質間隔物172及底部介電質結構174係在相同製程中形成，所以內介電質間隔物172及底部介電質結構174具有相同材料。
第15圖為根據本揭示案之一些實施例之積體電路結構(或半導體裝置) 100a的橫截面圖。第15圖中之積體電路結構100a與第14圖中之積體電路結構100之間的差異是關於源極/汲極磊晶結構180之形狀。在第15圖中，至少一個孔隙(或氣隙) 182形成在源極/汲極磊晶結構180與底部介電質結構174之間。孔隙182可形成於第9A圖中所描述之磊晶生長製程中。磊晶生長製程可為選擇性磊晶生長(selectively epitaxial growth，SEG)製程，相較於在介電質材料上(例如，底部介電質結構174及內介電質間隔物172)，該選擇性磊晶生長製程具有在半導體材料(例如，通道層124)上較高的生長速度。因而，源極/汲極磊晶結構180之至少一部分可懸掛在底部介電質結構174上且在源極/汲極磊晶結構180下方形成孔隙。在一些實施例中，可藉由調諧磊晶生長製程之配方來調整源極/汲極磊晶結構180之形狀。積體電路結構100a之其他相關結構及製造細節與第14圖之積體電路結構100實質上相同或類似，且因此，在下文中將不重複在此方面之描述。
第16圖及第17圖為根據本揭示案之一些實施例之積體電路結構(或半導體裝置) 100b及100c的橫截面圖。第16圖中之積體電路結構100b、第17圖中之積體電路結構100c及第14圖中之積體電路結構100之間的差異是關於底部介電質結構174之形狀。在第16圖中，底部介電質結構174具有實質上平坦的頂表面，且在第17圖中，底部介電質結構174具有凸形頂表面。亦即，底部介電質結構174之頂表面174a與第16圖中之基板110之頂表面111實質上齊平，且底部介電質結構174之頂表面174a高於第17圖中之基板110之頂表面111。在一些實施例中，藉由調諧凹部R1’之深度來調整底部介電質結構174之形狀。例如，第16圖及第17圖中之凹部R1’之深度Hb及Hc比第5B圖中之凹部R1’之深度H1淺。因此，間隔物材料層170’(參見第7圖)較容易填充第16圖及第17圖中之凹部R1’。因而，在第8圖中所示之非等向性蝕刻製程ET1之後，更多間隔物材料層170’留在第16圖及第17圖之凹部R1’中。替代地或另外，可添加更多氟在用於蝕刻間隔物材料層170’的電漿中以形成第16圖及第17圖中所示之底部介電質結構174。積體電路結構100b及100c之其他相關結構及製造細節與第14圖之積體電路結構100實質上相同或類似，且因此，在下文中將不重複在此方面之描述。
第18圖為根據本揭示案之一些實施例之積體電路結構(或半導體裝置) 100d的橫截面圖。第18圖中之積體電路結構100d及第14圖中之積體電路結構100之間的差異是關於底部介電質結構174之形狀。在第18圖中，底部介電質結構174形成於凹部R1’之底部中且暴露凹部R1’之內表面之部分。在一些實施例中，藉由調諧凹部R1’之深度來調整底部介電質結構174之形狀。例如，第18圖中之凹部R1’之深度Hd比第5B圖中之凹部R1’之深度H1深。因此，間隔物材料層170’(參見第7圖)可形成在第18圖中之凹部R1’之底部處。因而，在第8圖中所示之非等向性蝕刻製程ET1之後，較少間隔物材料層170’留在第18圖之凹部R1’中。替代地或另外，添加較少氟在用於蝕刻間隔物材料層170’的電漿中以形成第18圖中所示之底部介電質結構174。在此組態的情況下，源極/汲極磊晶結構180可填充凹部R1’之剩餘部分。亦即，源極/汲極磊晶結構180與基板110接觸；如此，第18圖中之底部介電質結構174亦改善源極/汲極磊晶結構180之電流漏泄問題。積體電路結構100d之其他相關結構及製造細節與第14圖之積體電路結構100實質上相同或類似，且因此，在下文中將不重複在此方面之描述。
在一些實施例中，內介電質間隔物172及底部介電質結構174可包含不同的材料。因而，內介電質間隔物172及底部介電質結構174係在不同的製程中形成。第19圖至第22圖例示根據本揭示案之一些其他實施例之用於製造積體電路結構(或半導體裝置) 100e之各種階段的示範性橫截面圖。應理解，可在第19圖至第22圖所示的製程之前、期間及之後提供額外的操作，且對於方法之額外實施例，可替換或消除以下描述的一些操作。操作/製程之順序可為可互換的。與在第1圖至第14圖的情況下描述的相同或類似的組態、材料、製程及/或操作可使用在以下實施例中，且可省略詳細解釋。
在如第7圖中所示之結構形成之後，執行非等向性蝕刻製程ET1’來修整如第19圖中所示之沉積的間隔物材料層170’，留下填充凹部R2的沉積的間隔物材料層170’之部分，其中凹部R2是在側向蝕刻磊晶層122後留下的，且移除沉積在凹部R1’之底部中的沉積的間隔物材料層170’之另一部分，其中凹部R1’是在蝕刻鰭片結構130後留下的。為簡單起見，在修整製程之後，將沉積的間隔物材料之剩餘部分指示為凹部R2中之內介電質間隔物172。在此非等向性蝕刻製程ET1’期間，在電漿蝕刻製程中使用較少的氟，使得凹部R1’中之間隔物材料層170’之部分可被移除。
在第20圖中，形成間隔物材料層190’以填充凹部R1’。間隔物材料層190’可為低介電常數介電質材料，諸如氧化矽、氮化矽、碳化矽、氮氧化矽、探氧化矽或碳氮氧化矽，且可藉由諸如原子層沈積的合適的沈積方法形成。間隔物材料層190’可使用包含低壓化學氣相沉積及電漿加強化學氣相沉積的化學氣相沉積、物理氣相沉積、原子層沈積或其他合適的製程形成。間隔物材料層190’及間隔物材料層170’係由不同材料製成。
參考第21圖，在間隔物材料層190’之沈積之後，可執行另一非等向性蝕刻製程ET2來修整沉積的間隔物材料層190’，留下沉積在凹部R1’之底部中的沉積的間隔物材料層190’之部分，其中凹部R1’是在蝕刻鰭片結構130後留下的。在修整製程之後，為簡單起見，將沉積的間隔物材料之剩餘部分指示為凹部R1’中之底部介電質結構192。
在一些實施例中，非等向性蝕刻製程ET2為電漿蝕刻。具有第20圖中所例示之結構的基板110可裝載至電漿工具中，且暴露於在諸如三氟甲烷、四氟甲烷、八氟環丁烷、八氟環戊烯、六氟丁二烯或類似物種的含氟氣體、諸如氬或氦的惰性氣體之氣體混合物中藉由射頻或微波功率產生的電漿環境，持續足以蝕刻凹部R1’外側的間隔物材料層190’之部分的持續時間。在包含三氟甲烷、四氟甲烷及氬的氣體混合物中產生的電漿可用來調諧底部介電質結構192之形狀。在較多氟的情況下，電漿蝕刻之側向蝕刻速度增加，且剩下較多的底部介電質結構192。電漿藉由具有大於0且等於或小於約30 伏特之偏壓之射頻功率產生。若偏壓大於約30 伏特，則底部介電質結構192可能會被完全移除；若偏壓不存在，則內介電質間隔物172可能會被蝕刻。
參考第22圖，在第21圖中之蝕刻製程ET2完成之後，第21圖之結構經歷類似於第9A圖至第14圖的製程。亦即，源極/汲極磊晶結構180形成在半導體鰭片130之源極/汲極區域S/D及底部介電質結構192上。層間介電質層210形成於基板110上。以閘極結構220替換虛擬閘極結構150。介電質帽230視情況地形成在回蝕的閘極結構220上。形成源極/汲極觸點240，源極/汲極觸點240延伸貫穿層間介電質層210 (及觸點蝕刻終止層層，若存在)。關於前面提到的製程/元件的材料及製造製程細節類似於第9A圖至第14圖中所示之那些，且因而為簡潔起見在本文中不重複該等材料及製造製程細節。
如以上提到的，底部介電質結構192可由不同於內介電質間隔物172之材料的材料製成。在一些實施例中，內介電質間隔物172及底部介電質結構192具有蝕刻選擇性，使得第21圖中之非等向性蝕刻製程ET2不損壞內介電質間隔物172。替代地或另外，內介電質間隔物172包含高介電常數介電質材料，且底部介電質結構192包含低介電常數介電質材料。例如，內介電質間隔物172包含碳氮氧化矽、氮化矽、其組合或類似者，且底部介電質結構192包含氧化矽、碳化矽、其組合或類似者。因為底部介電質結構192為低介電常數介電質材料，所以可降低積體電路結構100e之寄生電容。積體電路結構100e之其他相關結構及製造細節與第14圖之積體電路結構100實質上相同或類似，且因此，在下文中將不重複在此方面之描述。
基於以上論述，可看出本揭示案提供優點。然而，應理解，其他實施例可提供額外優點，且並非所有優點在本文中必定予以揭示，且無特定優點為所有實施例需要的。其中一個優點在於底部介電質結構改善貫穿基板的源極/汲極磊晶結構之間的電流漏泄問題，藉此亦改善積體電路結構之汲極引發能障降低(drain induced barrier lowering，DIBL)問題。另一個優點在於底部介電質結構之材料可經選擇以降低積體電路結構之寄生電容。
根據一些實施例，半導體裝置包含基板、通道層、閘極結構、源極/汲極磊晶結構及底部介電質結構。通道層在基板上。閘極結構在基板上且包圍通道層。源極/汲極磊晶結構在基板上且連接至通道層。底部介電質結構介於源極/汲極磊晶結構與基板之間。
根據一些實施例，半導體裝置包含複數個通道層、閘極結構、源極/汲極磊晶結構、內介電質間隔物及底部介電質結構。通道層以間隔開的方式一個在另一個上方地排列在基板上。閘極結構包圍複數個通道層中之每一個。源極/汲極磊晶結構連接至通道層。內介電質間隔物介於源極/汲極磊晶結構與閘極結構之間。底部介電質結構在源極/汲極磊晶結構以下。
根據一些實施例，製造半導體裝置的方法包含形成鰭片結構，鰭片結構包含複數個第一半導體層及複數個第二半導體層，複數個第一半導體層及複數個第二半導體層交替地堆疊在基板上。虛擬閘極結構橫跨鰭片結構形成，使得虛擬閘極結構覆蓋鰭片結構之第一部分，而鰭片結構之第二部分暴露。移除鰭片結構之暴露的第二部分。移除鰭片結構之暴露的第二部分下方的基板之一部分以在基板中形成凹部。底部介電質結構形成在基板之凹部中。在形成底部介電質結構之後，源極/汲極磊晶結構形成於鰭片結構之第一部分中的第二半導體層之相反末端表面上。移除虛擬閘極結構以暴露鰭片結構之第一部分。移除鰭片結構之暴露的第一部分中之第一半導體層，而留下鰭片結構之暴露的第一部分中之第二半導體層，第二半導體層懸掛基板上。閘極結構形成以包圍懸掛的第二半導體層中之每一個。
先前內容概括若干實施例之特徵，使得熟習此項技術者可更好地理解本揭示案之態樣。熟習此項技術者應瞭解，他們可容易地將本揭示案用作用於設計或修改用於執行相同目的及/或達成本文引入之實施例之相同優點的其他製程及結構之基礎。熟習此項技術者亦應意識到，此類等效構造不脫離本揭示案之精神及範疇，且他們可在不脫離本揭示案之精神及範疇的情況下在本文中做出各種變化、置換，及變更。
100:積體電路結構 100a:積體電路結構 100b:積體電路結構 100c:積體電路結構 100d:積體電路結構 100e:積體電路結構 102:溝槽 110:基板 111:頂表面 112:基板部分 120:磊晶堆疊 122:磊晶層 124:磊晶層/通道層 130:半導體鰭片/鰭片結構 140:隔離區域 150:虛擬閘極結構 152:虛擬閘極介電質層 154:虛擬閘極電極層 156:層 158:層 160:間隔物/間隔物材料層 162:第一間隔物層 164:第二間隔物層 170’:間隔物材料層 172:內介電質間隔物 174:底部介電質結構 174a:頂表面 175:孔隙 180:源極/汲極磊晶結構 182:孔隙 190’:間隔物材料層 192:底部介電質結構 210:層間介電質層 220:閘極結構 222:閘極介電質層 224:功函數金屬層 226:填充金屬 230:介電質帽 240:源極/汲極觸點 910:硬遮罩層 912:氧化物層 914:氮化物層 A:區域 ET1:非等向性蝕刻製程 ET1’:非等向性蝕刻製程 ET2:非等向性蝕刻製程 GT1:閘極溝槽 H1:深度 H2:厚度 Hb:深度 Hc:深度 Hd:深度 O1:開口 X-X:切割線 Y-Y:切割線 R1:凹部 R1’:凹部 R2:側向凹部 S/D:源極/汲極區域 W1:寬度
本揭示案之態樣當與隨附圖式一起閱讀時，自以下詳細描述更好地理解。應注意，根據工業中之標準實習，各種特徵未按比例描繪。實際上，各種特徵之尺寸可出於論述之清晰性而任意地增加或減小。 第1圖至第14圖例示根據本揭示案之一些實施例的積體電路結構之形成中之中間階段的立體圖及橫截面圖。 第15圖為根據本揭示案之一些實施例的積體電路結構的橫截面圖。 第16圖及第17圖為根據本揭示案之一些實施例的積體電路結構的橫截面圖。 第18圖為根據本揭示案之一些實施例的積體電路結構的橫截面圖。 第19圖至第22圖例示根據本揭示案之一些其他實施例的用於製造積體電路結構之各種階段的示範性橫截面圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
100:積體電路結構
110:基板
111:頂表面
112:基板部分
124:磊晶層
160:間隔物/間隔物材料層
162:第一間隔物層
164:第二間隔物層
172:內介電質間隔物
174:底部介電質結構
174a:頂表面
180:源極/汲極磊晶結構
220:閘極結構
222:閘極介電質層
224:功函數金屬層
226:填充金屬
230:介電質帽
240:源極/汲極觸點
R1’:凹部
S/D:源極/汲極區域
H2:厚度

Claims (20)

  1. 一種半導體裝置，包含： 一基板； 一通道層，該通道層在該基板上； 一閘極結構，該閘極結構在該基板上且包圍該通道層； 一源極/汲極磊晶結構，該源極/汲極磊晶結構在該基板上且連接至該通道層；以及 一底部介電質結構，該底部介電質結構介於該源極/汲極磊晶結構與該基板之間。
  2. 如請求項1所述之半導體裝置，其中該底部介電質結構嵌入該基板中。
  3. 如請求項1所述之半導體裝置，其中該底部介電質結構之一頂表面低於該基板之一頂表面。
  4. 如請求項1所述之半導體裝置，其中該底部介電質結構之一頂表面高於該基板之一頂表面。
  5. 如請求項1所述之半導體裝置，其中該源極/汲極磊晶結構與該基板間隔開。
  6. 如請求項1所述之半導體裝置，其中該源極/汲極磊晶結構及該底部介電質結構一起定義在源極/汲極磊晶結構及該底部介電質結構之間之一孔隙。
  7. 一種半導體裝置，包含： 複數個通道層，該些通道層以一個置於另一個上方，且間隔開的方式排列在一基板上； 一閘極結構，該閘極結構包圍該些通道層中之每一個； 一源極/汲極磊晶結構，該源極/汲極磊晶結構連接至該些通道層； 一內介電質間隔物，該內介電質間隔物介於該源極/汲極磊晶結構與該閘極結構之間；以及 一底部介電質結構，該底部介電質結構在該源極/汲極磊晶結構以下。
  8. 如請求項7所述之半導體裝置，其中該內介電質間隔物及該底部介電質結構係由不同的材料製成。
  9. 如請求項7所述之半導體裝置，其中該底部介電質結構之一介電常數低於該內介電質間隔物之一介電常數。
  10. 如請求項7所述之半導體裝置，其中該源極/汲極磊晶結構及該內介電質間隔物定義在該源極/汲極磊晶結構及該內介電質間隔物之間之一孔隙。
  11. 一種製造半導體裝置的方法，包含： 形成一鰭片結構，該鰭片結構包含複數個第一半導體層及複數個第二半導體層，該些第一半導體層及該些第二半導體層交替地堆疊在一基板上； 形成橫跨該鰭片結構的一虛擬閘極結構，使得該虛擬閘極結構覆蓋該鰭片結構之一第一部分，且暴露該鰭片結構之複數個第二部分； 移除該鰭片結構之該些暴露的第二部分； 移除該鰭片結構之該些暴露的第二部分下方的該基板之一部分以在該基板中形成一凹部； 形成一底部介電質結構在該基板之該凹部中； 在形成該底部介電質結構之後，形成一源極/汲極磊晶結構在該鰭片結構之該第一部分中的該些第二半導體層之複數個相對末端表面上； 移除該虛擬閘極結構以暴露該鰭片結構之該第一部分； 移除該鰭片結構之該暴露的第一部分中之該些第一半導體層，而留下該鰭片結構之該暴露的第一部分中之該些第二半導體層，該些第二半導體層懸掛該基板上；以及 形成一閘極結構以包圍該些懸掛的第二半導體層中之每一個。
  12. 如請求項11所述之方法，其中形成該底部介電質結構包含： 形成一介電質層於該凹部中及該些第二半導體層之該些末端表面上；以及 蝕刻該介電質層以形成該底部介電質結構。
  13. 如請求項11所述之方法，其中蝕刻該介電質層係以一電漿蝕刻製程執行，且該電漿蝕刻製程係在具有大於0且等於或小於約30 伏特之一偏壓的一射頻功率下執行。
  14. 如請求項11所述之方法，其中蝕刻該介電質層係以一電漿蝕刻製程執行，且該電漿蝕刻製程之一電漿係自包含三氟甲烷、四氟甲烷及氬的一氣體混合物產生。
  15. 如請求項11所述之方法，更包含： 在移除該基板之該部分之後，側向地凹入該第一半導體層；以及 形成一內介電質間隔物在該些側向地凹入的第一半導體層之複數個末端表面上。
  16. 如請求項15所述之方法，其中形成該底部介電質結構在該基板中及形成該內介電質間隔物在該些側向地凹入的第一半導體層之該些末端表面上係同時執行。
  17. 如請求項15所述之方法，其中形成該內介電質間隔物在該些側向地凹入的第一半導體層之該些末端表面上係在形成該底部介電質結構在該基板中之前執行。
  18. 如請求項15所述之方法，其中該底部介電質結構之一介電常數低於該內介電質間隔物之一介電常數。
  19. 如請求項11所述之方法，其中在該基板中形成該凹部係在具有溴化氫及氦之一氣體混合物的情況下藉由一非等向性蝕刻製程執行，且溴化氫: 氦在自約1:1至約1:8之一範圍內。
  20. 如請求項11所述之方法，其中在該基板中形成該凹部使該凹部具有在自約1.3至約15之一範圍內之一深寬比。
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