CN114883422A - Heterojunction battery and preparation method thereof - Google Patents

Heterojunction battery and preparation method thereof Download PDF

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Publication number
CN114883422A
CN114883422A CN202210529216.1A CN202210529216A CN114883422A CN 114883422 A CN114883422 A CN 114883422A CN 202210529216 A CN202210529216 A CN 202210529216A CN 114883422 A CN114883422 A CN 114883422A
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silicon layer
layer
amorphous silicon
metal electrode
type doped
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毛卫平
郧树琛
王进
任明冲
张杜超
蔡涔
杨伯川
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Risen Energy Co Ltd
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Risen Energy Co Ltd
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Abstract

The invention discloses a heterojunction battery and a preparation method thereof, belonging to the field of heterojunction batteries and comprising a crystalline silicon layer, wherein the front surface of the crystalline silicon layer is sequentially provided with a first intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conducting layer and a first metal electrode from inside to outside, the back surface of the crystalline silicon layer is sequentially provided with a second intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a second transparent conducting layer and a second metal electrode from inside to outside, and the surface of the first metal electrode and/or the second metal electrode is/are provided with an insulating slurry protective layer. The invention has the beneficial effects that: the insulating slurry protective layers are arranged on the surfaces of the front and back copper-containing metal electrodes, so that the copper-containing metal electrodes can be effectively prevented from being oxidized or corroded by trace oxygen, water vapor and organic acid (such as acetic acid) in the atmospheric environment or the assembly, the efficiency attenuation or reliability reduction of a battery is avoided, and the service life of a photovoltaic device is prolonged; the method is favorable for application and popularization of the copper-containing low-temperature slurry in the heterojunction battery.

Description

Heterojunction battery and preparation method thereof
Technical Field
The invention relates to the field of heterojunction batteries, in particular to a heterojunction battery and a preparation method thereof.
Background
The monocrystalline silicon heterojunction solar cell has high conversion efficiency and is recognized as one of the key technologies of the next-generation large-scale industrialization by the photovoltaic industry.
The silicon-based heterojunction solar cell is generally manufactured by adopting an N-type monocrystalline silicon wafer with a double-sided pyramid textured structure, an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer are deposited on the front side of the silicon wafer, the intrinsic amorphous silicon layer and the p-type doped amorphous silicon layer are deposited on the back side of the silicon wafer, and then a transparent conductive film and a metal electrode are respectively formed on the two sides of the silicon wafer.
In the prior art, high consumption and high cost of low-temperature silver paste are main obstacles for restricting large-scale application of heterojunction batteries, and the replacement of conventional low-temperature silver paste by copper paste or silver-clad copper paste is one of important means for reducing the cost of the heterojunction batteries; however, since copper in the copper-containing paste electrode is easily oxidized or corroded by oxygen, moisture, organic acids (such as acetic acid) in an atmospheric environment or in a slight amount in a component, the efficiency of a battery is deteriorated or a reliability problem is caused, and in a serious case, a device is failed.
Disclosure of Invention
In order to solve the problem that copper in a copper-containing slurry electrode in the prior art is easily oxidized or corroded by trace oxygen, water vapor and organic acid (such as acetic acid) in an atmospheric environment or a component to cause the efficiency attenuation or reliability of a battery, the invention provides a heterojunction battery which comprises a crystalline silicon layer, wherein a first intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conducting layer and a first metal electrode are sequentially arranged on the front surface of the crystalline silicon layer from inside to outside, a second intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a second transparent conducting layer and a second metal electrode are sequentially arranged on the back surface of the crystalline silicon layer from inside to outside, and an insulating slurry protective layer is arranged on the surface of the first metal electrode and/or the second metal electrode.
The insulating slurry protective layers are arranged on the surfaces of the front and back copper-containing metal electrodes, so that the copper-containing metal electrodes can be effectively prevented from being oxidized or corroded by trace oxygen, water vapor and organic acid (such as acetic acid) in the atmospheric environment or components, and the efficiency attenuation or reliability reduction of the battery is avoided.
Preferably, the first metal electrode and/or the second metal electrode is a low-temperature copper-containing metal paste electrode, and the insulating paste protection layer is arranged on the surface of the low-temperature copper-containing metal paste electrode.
Preferably, the copper-containing metal paste is one of copper paste, silver-clad copper paste or nickel-clad copper paste.
Preferably, the thickness of the first metal electrode and/or the second metal electrode is 10-50um, and the width is 5-50 um.
Preferably, the insulation paste protective layer is prepared from the following components in percentage by mass: 80-90% of insulating oxide powder, 6-7.5% of resin, 0-1.5% of diluent, 2-3% of curing agent and 0.4-0.6% of dispersing agent.
Preferably, the insulation paste protective layer is prepared from the following components in percentage by mass: 90% of insulating oxide powder, 6% of resin, 1.5% of diluent, 2.0% of curing agent and 0.5% of dispersing agent.
Preferably, the insulating oxide powder is at least one of SiO2, Al2O3, and TiO2 powder.
Preferably, the crystalline silicon layer is N-type doped monocrystalline silicon, P-type doped monocrystalline silicon, or P-type doped monocrystalline silicon.
Preferably, the first transparent conductive layer and/or the second transparent conductive layer is/are a composite film layer formed by overlapping one or more of doped indium oxide, zinc oxide and tin oxide.
Preferably, the resin is one or a mixture of two of saturated polyester resin and acrylic resin with a hydroxyl value of less than 50 mgKOH/g.
Preferably, the diluent is one or a mixture of two of diethylene glycol ethyl ether acetate and dibasic ester which are high-boiling organic solvents.
Preferably, the curing agent is a blocked isocyanate curing agent.
Preferably, the dispersant is a polyurethane or acrylic dispersant.
The invention also provides a preparation method of the heterojunction battery, which comprises the following steps:
step one, providing a crystalline silicon layer;
step two, etching and cleaning;
depositing a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer on the front surface of the crystalline silicon layer in sequence; depositing a second intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on the back of the crystalline silicon layer in sequence;
depositing a first transparent conducting layer on the N-type doped amorphous silicon layer in the step three, and depositing a second transparent conducting layer on the P-type doped amorphous silicon layer;
fifthly, forming a first metal electrode on the first transparent conductive layer by utilizing screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing;
and sixthly, printing insulating slurry on the surfaces of the first metal electrode and the second metal electrode, and drying and curing to form an insulating slurry protective layer.
Has the advantages that:
the technical scheme of the invention has the following beneficial effects:
the insulating slurry protective layers are arranged on the surfaces of the front and back copper-containing metal electrodes, so that the copper-containing metal electrodes can be effectively prevented from being oxidized or corroded by trace oxygen, water vapor and organic acid (such as acetic acid) in the atmospheric environment or the assembly, the efficiency attenuation or reliability reduction of a battery is avoided, and the service life of a photovoltaic device is prolonged; the method is favorable for application and popularization of the copper-containing low-temperature slurry in the heterojunction battery.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a diagram of a preferred battery layer structure according to the present invention;
figure 2 is a flow chart of a preferred heterojunction cell fabrication process of the present invention.
In the figure, 1, a first metal electrode; 2. a second metal electrode; 3. an insulating paste protective layer;
4. a crystalline silicon layer; 5. a first intrinsic amorphous silicon layer; 6. an N-type doped amorphous silicon layer;
7. a first transparent conductive layer; 8. a second intrinsic amorphous silicon layer; 9. a P-type doped amorphous silicon layer;
10. a second transparent conductive layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
According to the embodiment, the insulating slurry protective layers are arranged on the surfaces of the front and back copper-containing metal electrodes, so that the copper-containing metal electrodes can be effectively prevented from being oxidized or corroded by trace oxygen, water vapor and organic acid (such as acetic acid) in the atmospheric environment or in the assembly, the efficiency attenuation or reliability reduction of a battery is avoided, and the service life of a photovoltaic device is prolonged; the method is favorable for application and popularization of the copper-containing low-temperature slurry in the heterojunction battery. The specific implementation mode is as follows:
as shown in fig. 1, the heterojunction cell comprises a crystalline silicon layer 4, wherein a first intrinsic amorphous silicon layer 5, an N-type doped amorphous silicon layer 6, a first transparent conductive layer 7 and a first metal electrode 1 are sequentially arranged on the front surface of the crystalline silicon layer 4 from inside to outside, a second intrinsic amorphous silicon layer 8, a P-type doped amorphous silicon layer 9, a second transparent conductive layer 10 and a second metal electrode 2 are sequentially arranged on the back surface from inside to outside, and a layer of insulating paste protective layer 3 is arranged on the surface of the first metal electrode 1 and/or the second metal electrode 2.
In a preferred embodiment, the first metal electrode 1 and/or the second metal electrode 2 are low-temperature copper-containing metal paste electrodes, and the insulating paste protection layer is disposed on the surface of the low-temperature copper-containing metal paste electrodes.
In a preferred embodiment, the copper-containing metal paste is one of copper paste, silver-clad copper paste or nickel-clad copper paste.
In a preferred embodiment, the thickness of the first metal electrode and/or the second metal electrode is 10-50um, and the width is 5-50 um.
As a preferred embodiment, the insulation paste protective layer is prepared from the following components in percentage by mass: 80-90% of insulating oxide powder, 6-7.5% of resin, 0-1.5% of diluent, 2-3% of curing agent and 0.4-0.6% of dispersing agent.
As a preferred embodiment, the insulation paste protective layer is prepared from the following components in percentage by mass: 90% of insulating oxide powder, 6% of resin, 1.5% of diluent, 2.0% of curing agent and 0.5% of dispersing agent.
In a preferred embodiment, the insulating oxide powder is at least one of SiO2, Al2O3, and TiO2 powder.
In a preferred embodiment, the crystalline silicon layer is N-doped, P-doped, or P-doped monocrystalline silicon and has a thickness of 50-250 um.
In a preferred embodiment, the first intrinsic amorphous silicon layer is a composite film layer formed by laminating one or more of undoped amorphous silicon, amorphous silicon oxide and amorphous silicon carbide semiconductor films, and the thickness of the composite film layer is 2-8 nm.
In a preferred embodiment, the second intrinsic amorphous silicon layer is a composite film layer formed by laminating one or more of undoped amorphous silicon, amorphous silicon oxide and amorphous silicon carbide semiconductor films, and the thickness of the composite film layer is 2-8 nm.
In a preferred embodiment, the N-type doped amorphous silicon layer is a composite film layer formed by stacking one or more of N-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor films, and the thickness of the composite film layer is 4-30 nm.
In a preferred embodiment, the P-type doped amorphous silicon layer is a composite film layer formed by stacking one or more P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor films, and the thickness of the composite film layer is 4-30 nm.
As a preferred embodiment, the first transparent conductive layer and/or the second transparent conductive layer is a composite thin film layer formed by stacking one or more of doped indium oxide, zinc oxide, and tin oxide. And the thickness thereof is 70-120 nm.
As a preferred embodiment, the resin is one or a mixture of two of saturated polyester resin and acrylic resin with a hydroxyl value of less than 50 mgKOH/g.
In a preferred embodiment, the diluent is one or a mixture of two of diethylene glycol ethyl ether acetate and dibasic ester which are high-boiling organic solvents.
As a preferred embodiment, the curing agent is a blocked isocyanate curing agent.
As a preferred embodiment, the dispersant is a polyurethane or acrylic dispersant.
The embodiment also provides a preparation method of the heterojunction battery, which comprises the following steps:
step S101, providing a crystalline silicon layer; adopting an N-type Czochralski monocrystalline silicon wafer, wherein the thickness of the N-type Czochralski monocrystalline silicon wafer is 50-250um, the resistivity is 3 omega-cm, and the minority carrier lifetime is 2000 mu s;
step S102, texturing and cleaning; and (3) carrying out silicon wafer texturing by using a mixed solution of NaOH and a texturing additive with the mass percentage of 2%. And then, cleaning the surface of the silicon wafer by adopting an RCA standard cleaning method to remove surface pollution impurities. Next, a hydrofluoric acid solution with a mass percentage of 2% was used to remove the surface oxide layer.
Step S103, depositing a first intrinsic amorphous silicon layer with the thickness of 2-8nm on the front surface of the crystalline silicon layer by adopting a PECVD process, wherein the reaction gases are SiH4 and H2, and the flow ratio of H2 to SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm2, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; then depositing an N-type doped amorphous silicon layer with the thickness of 4-30nm on the surface of the first intrinsic amorphous silicon layer; the reaction gases were SiH4, H2, and PH3, the flow ratio of H2 to SiH4 was 5, and the flow ratio of PH3 to SiH4 was 0.02. The power density of a power supply of the PECVD equipment is 15mW/cm2, the pressure is 80Pa, and the substrate temperature is 200 ℃.
And depositing a second intrinsic amorphous silicon layer with the thickness of 2-8nm on the front surface of the crystalline silicon layer by adopting a PECVD (plasma enhanced chemical vapor deposition) process, wherein the reaction gases are SiH4 and H2, and the flow ratio of H2 to SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm2, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; and depositing a P-type doped amorphous silicon layer with the thickness of 4-30nm on the surface of the second intrinsic amorphous silicon layer, wherein the reaction gases are SiH4, B2H6 and H2, the flow ratio of H2 to SiH4 is 4, and the flow ratio of B2H6 to SiH4 is 0.04. The power density of a power supply of the PECVD equipment is 15mW/cm2, the pressure is 60Pa, and the temperature of the substrate is 200 ℃.
Step S104, depositing a first transparent conducting layer with the thickness of 70-120nm on the N-type doped amorphous silicon layer by adopting a PVD method, and depositing a second transparent conducting layer with the thickness of 70-120nm on the P-type doped amorphous silicon layer; the first transparent conducting layer and the second transparent conducting layer are both ITO transparent conducting films, the mass percent of indium elements in the ITO is 90%, and the mass percent of tin elements is 10%. Ar and O2 are filled in the PVD equipment, the flow ratio of O2 to Ar is 0.025, the pressure is 0.5Pa, and the temperature of the substrate is room temperature.
Step S105, forming a first metal electrode on the first transparent conductive layer by utilizing screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing;
and S106, printing insulating slurry on the surfaces of the first metal electrode and the second metal electrode, and drying and curing to form an insulating slurry protective layer.
The advantageous effects of the protective layer using the insulating paste in this embodiment are further reviewed by examples and comparative examples below.
The first embodiment is as follows:
a method of making a heterojunction cell, comprising the steps of:
providing a crystalline silicon layer, wherein an N-type Czochralski monocrystalline silicon wafer is adopted, the thickness of the crystalline silicon layer is 150um, the resistivity of the crystalline silicon layer is 3 omega cm, and the minority carrier lifetime of the crystalline silicon layer is 2000 mu s;
step two, etching and cleaning; and (3) carrying out silicon wafer texturing by using a mixed solution of NaOH and a texturing additive with the mass percentage of 2%. And then, cleaning the surface of the silicon wafer by adopting an RCA standard cleaning method to remove surface pollution impurities. Next, a hydrofluoric acid solution with a mass percentage of 2% was used to remove the surface oxide layer.
And thirdly, depositing first intrinsic amorphous silicon with the thickness of 6nm on the front surface of the crystalline silicon layer by adopting a PECVD process, wherein the reaction gases are SiH4 and H2, and the flow ratio of H2 to SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm2, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; then depositing an N-type doped amorphous silicon layer with the thickness of 10nm on the first intrinsic amorphous silicon; the reaction gases were SiH4, H2, and PH3, the flow ratio of H2 to SiH4 was 5, and the flow ratio of PH3 to SiH4 was 0.02. The power density of a power supply of the PECVD equipment is 15mW/cm2, the pressure is 80Pa, and the substrate temperature is 200 ℃.
And depositing second intrinsic amorphous silicon with the thickness of 6nm on the front surface of the crystalline silicon layer by adopting a PECVD process, wherein the reaction gases are SiH4 and H2, and the flow ratio of H2 to SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm2, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; and depositing a 10 nm-thick P-type doped amorphous silicon layer on the second intrinsic amorphous silicon, wherein the reaction gases are SiH4, B2H6 and H2, the flow ratio of H2 to SiH4 is 4, and the flow ratio of B2H6 to SiH4 is 0.04. The power density of a power supply of the PECVD equipment is 15mW/cm2, the pressure is 60Pa, and the temperature of the substrate is 200 ℃.
Depositing a first transparent conducting layer with the thickness of 80nm on the N-type doped amorphous silicon layer by adopting a PVD method, and depositing a second transparent conducting layer with the thickness of 80nm on the P-type doped amorphous silicon layer; the first transparent conducting layer and the second transparent conducting layer are both ITO transparent conducting films, the mass percent of indium elements in the ITO is 90%, and the mass percent of tin elements is 10%. Ar and O2 are filled in the PVD equipment, the flow ratio of O2 to Ar is 0.025, the pressure is 0.5Pa, and the temperature of the substrate is room temperature.
Fifthly, forming a first metal electrode on the first transparent conductive layer by utilizing screen printing low-temperature silver-coated copper paste; forming a second metal electrode on the second transparent conductive layer by utilizing screen printing low-temperature copper paste;
and sixthly, printing insulating slurry on the surfaces of the first metal electrode and the second metal electrode, and drying and curing to form an insulating slurry protective layer.
The insulating slurry protective layer is prepared from the following components in percentage by mass: 90.0 percent of SiO2 powder, 6.0 percent of saturated polyester resin, 1.5 percent of high-boiling-point organic solvent diethylene glycol ethyl ether acetate, 2.0 percent of closed isocyanate curing agent and 0.5 percent of polyurethane dispersant.
Comparative example one:
a method of making a heterojunction cell, comprising the steps of:
providing a crystalline silicon layer, wherein an N-type Czochralski monocrystalline silicon wafer is adopted, the thickness of the crystalline silicon layer is 150um, the resistivity of the crystalline silicon layer is 3 omega cm, and the minority carrier lifetime of the crystalline silicon layer is 2000 mu s;
step two, etching and cleaning; and (3) carrying out silicon wafer texturing by using a mixed solution of NaOH and a texturing additive with the mass percentage of 2%. And then, cleaning the surface of the silicon wafer by adopting an RCA standard cleaning method to remove surface pollution impurities. Next, a hydrofluoric acid solution with a mass percentage of 2% was used to remove the surface oxide layer.
And thirdly, depositing first intrinsic amorphous silicon with the thickness of 6nm on the front surface of the crystalline silicon layer by adopting a PECVD process, wherein the reaction gases are SiH4 and H2, and the flow ratio of H2 to SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm2, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; then depositing an N-type doped amorphous silicon layer with the thickness of 10nm on the first intrinsic amorphous silicon; the reaction gases were SiH4, H2, and PH3, the flow ratio of H2 to SiH4 was 5, and the flow ratio of PH3 to SiH4 was 0.02. The power density of a power supply of the PECVD equipment is 15mW/cm2, the pressure is 80Pa, and the substrate temperature is 200 ℃.
And depositing second intrinsic amorphous silicon with the thickness of 6nm on the front surface of the crystalline silicon layer by adopting a PECVD process, wherein the reaction gases are SiH4 and H2, and the flow ratio of H2 to SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm2, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; and depositing a 10 nm-thick P-type doped amorphous silicon layer on the second intrinsic amorphous silicon, wherein the reaction gases are SiH4, B2H6 and H2, the flow ratio of H2 to SiH4 is 4, and the flow ratio of B2H6 to SiH4 is 0.04. The power density of a power supply of the PECVD equipment is 15mW/cm2, the pressure is 60Pa, and the temperature of the substrate is 200 ℃.
Depositing a first transparent conducting layer with the thickness of 80nm on the N-type doped amorphous silicon layer by adopting a PVD method, and depositing a second transparent conducting layer with the thickness of 80nm on the P-type doped amorphous silicon layer; the first transparent conducting layer and the second transparent conducting layer are both ITO transparent conducting films, the mass percent of indium elements in the ITO is 90%, and the mass percent of tin elements is 10%. Ar and O2 are filled in the PVD equipment, the flow ratio of O2 to Ar is 0.025, the pressure is 0.5Pa, and the temperature of the substrate is room temperature.
Fifthly, forming a first metal electrode on the first transparent conductive layer by utilizing screen printing low-temperature silver-coated copper paste; and forming a second metal electrode on the second transparent conductive layer by utilizing screen printing low-temperature copper paste.
The batteries of the examples and the comparative examples are respectively packaged into 4x4 small components, the small components are sent into an environment test box to be subjected to a damp-heat test (the temperature is 85 ℃, the relative humidity is 85 percent, and the time is 1000 hours), the IV performance of the small components before and after the test is tested, the IV performance of the batteries is calculated according to the area of the batteries, and the battery performance is shown in table 1.
TABLE 1 comparison of Battery Performance before and after aging
Figure BDA0003645517820000111
As can be seen from table 1, compared with the comparative examples, the examples can effectively prevent the oxidation or corrosion of trace amounts of oxygen, water vapor and organic acid (such as acetic acid) to the copper-containing metal electrode in the damp-heat aging test by arranging the insulating slurry protective layer on the surface of the front and back copper-containing metal electrodes, avoid the efficiency attenuation or reliability reduction of the cell, and improve the aging resistance of the photovoltaic module.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A heterojunction battery is characterized by comprising a crystalline silicon layer, wherein the front surface of the crystalline silicon layer is sequentially provided with a first intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conducting layer and a first metal electrode from inside to outside, the back surface of the crystalline silicon layer is sequentially provided with a second intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a second transparent conducting layer and a second metal electrode from inside to outside, and the surface of the first metal electrode and/or the second metal electrode is/are provided with an insulating slurry protective layer.
2. A heterojunction battery according to claim 1, wherein said first metal electrode and/or said second metal electrode is a low temperature copper-containing metal paste electrode, and said insulating paste protection layer is disposed on the surface of said low temperature copper-containing metal paste electrode.
3. A heterojunction battery according to claim 2, wherein said copper-containing metal paste is one of copper paste, silver-clad copper paste or nickel-clad copper paste.
4. A heterojunction cell according to claim 1, wherein said first metal electrode and/or said second metal electrode has a thickness of 10-50um and a width of 5-50 um.
5. A heterojunction battery according to claim 1, wherein said insulating paste protection layer is made of, in mass percent: 80-90% of insulating oxide powder, 6-7.5% of resin, 0-1.5% of diluent, 2-3% of curing agent and 0.4-0.6% of dispersing agent.
6. A heterojunction battery according to claim 5, wherein the insulating paste protection layer is made of, in mass percent: 90% of insulating oxide powder, 6% of resin, 1.5% of diluent, 2.0% of curing agent and 0.5% of dispersing agent.
7. A heterojunction battery according to claim 5, wherein said insulating oxide powder is at least one of SiO2, Al2O3 and TiO2 powder.
8. A heterojunction cell according to claim 1, wherein said crystalline silicon layer is N-doped monocrystalline silicon, N-doped monocrystalline-like silicon, P-doped monocrystalline silicon or P-doped monocrystalline-like silicon.
9. A heterojunction cell according to claim 1, wherein said first transparent conductive layer and/or said second transparent conductive layer is a composite thin film layer formed by stacking one or more of doped indium oxide, zinc oxide and tin oxide.
10. A method for preparing a heterojunction battery is characterized by comprising the following steps:
step one, providing a crystalline silicon layer;
step two, etching and cleaning;
depositing a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer on the front surface of the crystalline silicon layer in sequence; depositing a second intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on the back of the crystalline silicon layer in sequence;
depositing a first transparent conducting layer on the N-type doped amorphous silicon layer in the step three, and depositing a second transparent conducting layer on the P-type doped amorphous silicon layer;
fifthly, forming a first metal electrode on the first transparent conductive layer by utilizing screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing;
and sixthly, printing insulating slurry on the surfaces of the first metal electrode and the second metal electrode, and drying and curing to form an insulating slurry protective layer.
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