CN114883380A - Insulated gate semiconductor device and preparation method thereof - Google Patents
Insulated gate semiconductor device and preparation method thereof Download PDFInfo
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- CN114883380A CN114883380A CN202110649855.7A CN202110649855A CN114883380A CN 114883380 A CN114883380 A CN 114883380A CN 202110649855 A CN202110649855 A CN 202110649855A CN 114883380 A CN114883380 A CN 114883380A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 238000002955 isolation Methods 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000015556 catabolic process Effects 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 235000012239 silicon dioxide Nutrition 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- -1 boron ions Chemical class 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000002994 raw material Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims 1
- 239000000243 solution Substances 0.000 description 11
- 230000008859 change Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000004134 energy conservation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000011056 performance test Methods 0.000 description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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- 238000012423 maintenance Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention relates to the technical field of semiconductors, in particular to an insulated gate semiconductor device and a preparation method thereof. The utility model provides an insulated gate semiconductor device, includes collector layer, substrate layer, N + type buffer layer, the first drift layer of N-type, N type epitaxial layer, P type doping layer, the P + type doping layer that is located P type doping layer both sides, the inside N + type doping layer that is located P + type doping layer, run through N + type doping layer, doping layer and stretch into the slot of second drift layer, be located the first insulating isolation layer of slot lateral wall and bottom, be located the second insulating isolation layer above the slot, be located the emitter layer of second insulating isolation layer both sides from bottom to top in proper order, the height of emitter layer is less than the height of second insulating isolation layer, the lateral doping concentration of P type doping layer is the gradient and changes. In the technical scheme, the inventor can reduce the on-state voltage of the capacitance between the emitter and the collector by optimizing the structure of the trench semiconductor, so that the semiconductor module has excellent performances of low on-state voltage, low power loss and high breakdown voltage resistance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an insulated gate semiconductor device and a preparation method thereof.
Background
The IGBT is a short for insulated gate bipolar transistor, is a composite fully-controlled voltage-driven power semiconductor device consisting of a BJT (bipolar junction transistor) and an MOS (insulated gate field effect transistor), and has the advantages of high input impedance of the MOS and low conduction voltage drop of the GTR. The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is large; the MOS has small driving power, high switching speed, large conduction voltage drop and low current-carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. The method is very suitable for being applied to the fields of current transformation systems with direct-current voltage of 600V or more, such as alternating-current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like. The IGBT module has the characteristics of energy conservation, convenience in installation and maintenance, stable heat dissipation and the like; most of the current market products are such modular products, generally, the IGBT is also referred to as IGBT module; with the promotion of concepts of energy conservation, environmental protection and the like, the products are more and more seen in the market.
Since the invention of the IGBT, efforts have been made to improve the performance of the IGBT. Through decades of development, various IGBT device structures are proposed in succession, so that the performance of the device is stably improved. An example of a product that can be cited is an IEGT (enhanced injection insulated gate bipolar transistor) that reduces the on-state voltage drop of the module by increasing the conductivity modulation of the N-drift region; CSTBT (Carrier storage Trench Gate Bipolar transistor) reduces the turn-on voltage by increasing the conductivity modulation of the N-drift region; trenchtop IGBT (trench field stop insulated gate bipolar transistor) reduces the thickness of the whole component by field stop back doping technology, reduces the conducting voltage and reduces the low injection efficiency; DG-TIGBT (double gate trench insulated gate bipolar transistor) effectively blocks holes by the PNP transistor with low current gain when the device is turned on, thereby increasing the carrier density and conductivity modulation near the emitter terminal in the N-drift region and reducing the on-state voltage drop. The adoption of the trench gate electrode can cause the capacitance of an emitter and a collector to be large, however, the switching process of the IGBT device is the process of charging and discharging the capacitance of the emitter, the larger the capacitance of the emitter is, the longer the charging and discharging time is, the larger the capacitance of the emitter is, the switching speed of the device is reduced, the switching loss of the device is increased, and the compromise characteristic of the forward conduction voltage drop and the switching loss of the device is influenced.
There is a need for an insulated gate semiconductor device that has both a low turn-on voltage and low power consumption when turned off.
Disclosure of Invention
In order to solve the above problems, the present invention provides an insulated gate semiconductor device, which sequentially includes, from bottom to top, a collector layer, a substrate layer, an N + -type buffer layer, an N-type first drift layer, an N-type epitaxial layer, a P-type doping layer, P + -type doping layers located at two sides of the P-type doping layer, an N + -type doping layer located inside the P + -type doping layer, a trench penetrating through the N + -type doping layer and the doping layer and extending into the second drift layer, a first insulating isolation layer located at a sidewall and a bottom of the trench, a second insulating isolation layer located above the trench, and emitter layers located at two sides of the second insulating isolation layer, wherein the height of the emitter layer is smaller than that of the second insulating isolation layer, and the lateral doping concentration of the P-type doping layer is changed in a gradient manner.
Preferably, the concentration of the N + type buffer layer is 5e 16 ～5e 18 cm -3 。
Preferably, the concentration of the N-type first drift layer is 5e 13 ～3e 14 cm -3 。
Preferably, the concentration of the N-type epitaxial layer is 5e 15 ～5e 16 cm -3 。
Preferably, the doping concentration of the P-type doping layer below the P + -type doping layer is greater than the doping concentration of the P-type doping layer below the N + -type doping layer.
Preferably, the doping concentration of the P-type doping layer is 8.5e 12 ～3e 14 cm -2
Preferably, the breakdown voltage resistance of the insulated gate semiconductor device is larger than or equal to 1200V.
Preferably, the turn-on voltage of the insulated gate semiconductor device is less than 1.3V.
Preferably, the turn-off time of the insulated gate semiconductor device is <2 μ S.
Preferably, the substrate layer is a P-type silicon substrate layer.
Preferably, the material of the first insulating isolation layer is silicon dioxide.
Preferably, the material of the second insulating isolation layer is silicon dioxide.
The second aspect of the present invention provides a method for manufacturing an insulated gate semiconductor device, comprising at least the following steps:
(1) preparing a substrate layer, forming an N + type buffer layer on the substrate layer, forming an N-type first drift layer on the N + type buffer layer, forming an N-type epitaxial layer on the N-type first drift layer, and forming an N-type second drift layer on the N-type epitaxial layer;
(2) injecting boron ions into the N-type second drift layer to form a P-type doping layer, wherein the lateral doping concentration of the P-type doping layer is changed in a gradient manner;
(3) oxidizing the P-type doped layer to form an oxidation isolation layer, and implanting arsenic ions in the middle of the oxidation isolation layer to form an N + type doped layer;
(4) oxidizing the N + type doping layer to form an oxidation isolation layer, and implanting boron ions at two sides of the N + type doping layer to form a P + type doping layer;
(3) etching the middle part of the N + type doping layer to form a groove, wherein the groove penetrates through the thickness of the whole N + type doping layer and the whole P type doping layer, and the bottom of the groove extends into the N type epitaxial layer;
(4) arranging a first insulating isolation layer on the bottom and the side wall of the groove, wherein the first insulating isolation layer is made of silicon dioxide;
(5) embedding a grid electrode in the groove, and arranging a second insulating isolation layer on the grid electrode, wherein the second insulating isolation layer extends to two sides of the groove, is made of silicon dioxide and respectively extends into the N + type doping layers on two sides of the groove;
(6) and finally, covering an emitter on the P + type doping layer, the N + type doping layer and the second insulation isolation layer, and covering a collector on the lower part of the P type silicon substrate layer to obtain the insulated gate semiconductor device with low on-state voltage and high breakdown voltage resistance.
Preferably, the doping method of the P-type doped layer in the step (2) is to dope the P-type doped layer by using a graded mask during doping.
Preferably, the lateral doping concentration of the P-type doping layer is changed in a gradient manner, and the gradient change comprises a linear change, an upper parabolic change and a lower parabolic change.
Preferably, the gradient doping is according to the equation: n (x) ═ N 2 -N 1 )(1-x/L)+N 1 (ii) a The basis equation for the upper parabolic change is:
the following equation for the lower parabolic change is:
wherein N (x) is the doping concentration of the x-axis, L is the length, N 1 Is the base concentration, N 2 The peak concentration, x-axis length distance, y-axis doping concentration, and W open pitch.
Has the advantages that: in the technical scheme, the inventor can reduce the capacitance and the on-state voltage between the emitter and the collector by optimizing the structure of the trench semiconductor, so that the semiconductor module has excellent performances of low on-state voltage, low power loss and high breakdown voltage resistance. The inventor enables the semiconductor module to have excellent performances of low on-voltage, low power loss and high breakdown voltage resistance by enabling the doping concentration in the P-type doping layer to be changed in a gradient manner.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a structural view of an insulated gate semiconductor device in step (1) of the manufacturing method in example 1.
Fig. 2 is a structural diagram of the insulated gate semiconductor device in step (2) of the manufacturing method in example 1.
Fig. 3 is a structural view of the insulated gate semiconductor device at the completion of step (2) of the manufacturing method in example 1.
Fig. 4 is a structural diagram of the insulated gate semiconductor device at the completion of step (4) of the manufacturing method in example 1.
Fig. 5 is a complete structural view of the insulated gate semiconductor device in embodiment 1.
Fig. 6 is a performance test chart of the on-voltage of the insulated gate semiconductor device in example 1.
Fig. 7 is a performance test chart of the off time of the insulated gate semiconductor device in example 1.
The epitaxial structure comprises a 1-N-type second drift layer, a 2-N-type epitaxial layer, a 3-N-type first drift layer, a 4-N + type buffer layer, a 5-P + type silicon substrate layer, a 6-gradient photomask, a 7-P type doped layer, an 8-P + type doped layer, a 9-N + type doped layer, a 10-first insulating isolation layer, an 11-groove, a 12-second insulating isolation layer, a 13-emitter layer and a 14-collector layer.
Detailed Description
The disclosure may be understood more readily by reference to the following detailed description of preferred embodiments of the invention and the examples included therein. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In case of conflict, the present specification, including definitions, will control.
The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. "optional" or "any" means that the subsequently described event or events may or may not occur, and that the description includes instances where the event occurs and instances where it does not.
In addition, the indefinite articles "a" and "an" preceding an element or component of the invention are not intended to limit the number requirement (i.e., the number of occurrences) of the element or component. Thus, "a" or "an" should be read to include one or at least one, and the singular form of an element or component also includes the plural unless the number clearly indicates the singular.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Furthermore, the terms "horizontal", "vertical", "overhang" and the like do not imply that the components are required to be absolutely horizontal or overhang, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In order to solve the above problems, the present invention provides an insulated gate semiconductor device, which sequentially includes, from bottom to top, a collector layer, a substrate layer, an N + -type buffer layer, an N-type first drift layer, an N-type epitaxial layer, a P-type doping layer, P + -type doping layers located at two sides of the P-type doping layer, an N + -type doping layer located inside the P + -type doping layer, a trench penetrating through the N + -type doping layer and the doping layer and extending into the second drift layer, a first insulating isolation layer located at a sidewall and a bottom of the trench, a second insulating isolation layer located above the trench, and emitter layers located at two sides of the second insulating isolation layer, wherein the height of the emitter layer is smaller than that of the second insulating isolation layer, and the lateral doping concentration of the P-type doping layer is changed in a gradient manner.
As a preferable technical solution, the concentration of the N + -type buffer layer is 5e 16 ～5e 18 cm -3 。
As a preferable embodiment, the concentration of the N-type first drift layer is 5e 13 ～3e 14 cm -3 。
As a preferable technical scheme, the concentration of the N-type epitaxial layer is 5e 15 ～5e 16 cm -3 。
As a preferable technical solution, the doping concentration of the P-type doping layer below the P + -type doping layer is greater than the doping concentration of the P-type doping layer below the N + -type doping layer.
As a preferable technical solution, the doping concentration of the P-type doping layer is 8.5e 12 ～3e 14 cm -2
As a preferable technical scheme, the breakdown voltage resistance of the insulated gate semiconductor device is more than or equal to 1200V.
As a preferable technical scheme, the turn-on voltage of the insulated gate semiconductor device is less than 1.3V.
As a preferred solution, the turn-off time of the insulated gate semiconductor device is <2 μ S.
In the technical scheme, the doping concentration of the P-type doping layer is controlled to be in a gradient relation, so that the breakdown voltage resistance and the switching speed of the whole semiconductor device are improved, the conduction voltage and the switching loss are reduced, and the use performance of the semiconductor device is optimized.
As a preferable technical scheme, the breakdown voltage resistance of the insulated gate semiconductor device is more than or equal to 1200V.
As a preferable technical scheme, the turn-on voltage of the insulated gate semiconductor device is less than 1.3V.
As a preferred solution, the turn-off time of the insulated gate semiconductor device is <2 μ S.
As a preferable technical scheme, the substrate layer is a P-type silicon substrate layer.
As a preferred technical solution, the raw material of the first insulating isolation layer is silicon dioxide.
As a preferred technical solution, the raw material of the second insulating isolation layer is silicon dioxide.
The second aspect of the present invention provides a method for manufacturing an insulated gate semiconductor device, comprising at least the following steps:
(1) preparing a substrate layer, forming an N + type buffer layer on the substrate layer, forming an N-type first drift layer on the N + type buffer layer, forming an N-type epitaxial layer on the N-type first drift layer, and forming an N-type second drift layer on the N-type epitaxial layer;
(2) injecting boron ions into the N-type second drift layer to form a P-type doping layer, wherein the lateral doping concentration of the P-type doping layer is changed in a gradient manner;
(3) oxidizing the P-type doped layer to form an oxidation isolation layer, and implanting arsenic ions in the middle of the oxidation isolation layer to form an N + type doped layer;
(4) oxidizing the N + type doping layer to form an oxidation isolation layer, and implanting boron ions at two sides of the N + type doping layer to form a P + type doping layer;
(3) etching the middle part of the N + type doping layer to form a groove, wherein the groove penetrates through the thickness of the whole N + type doping layer and the whole P type doping layer, and the bottom of the groove extends into the N type epitaxial layer;
(4) arranging a first insulating isolation layer on the bottom and the side wall of the groove, wherein the first insulating isolation layer is made of silicon dioxide;
(5) embedding a grid electrode in the groove, and arranging a second insulating isolation layer on the grid electrode, wherein the second insulating isolation layer extends to two sides of the groove, is made of silicon dioxide and respectively extends into the N + type doping layers on two sides of the groove;
(6) and finally, covering an emitter on the P + type doping layer, the N + type doping layer and the second insulation isolation layer, and covering a collector on the lower part of the P type silicon substrate layer to obtain the insulated gate semiconductor device with low on-state voltage and high breakdown voltage resistance.
As a preferable technical solution, the doping method of the P-type doped layer in the step (2) is to dope by using a graded mask during doping.
As a preferred technical solution, the lateral doping concentration of the P-type doping layer varies in a gradient manner, and the gradient variation includes a linear variation, an upper parabolic variation and a lower parabolic variation.
As a preferred technical solution, the gradient doping is based on the following equation: n (x) ═ N 2 -N 1 )(1-x/L)+N 1 (ii) a The basis equation for the upper parabolic change is:
the following equation for the lower parabolic change is:
wherein N (x) is the doping concentration of the x-axis, L is the length, N 1 As base concentration, N 2 The peak concentration, x-axis length distance, y-axis doping concentration, and W open pitch.
Examples
The present invention will be specifically described below by way of examples. It should be noted that the following examples are only for illustrating the present invention and should not be construed as limiting the scope of the present invention, and that the insubstantial modifications and adaptations of the present invention by those skilled in the art based on the above disclosure are still within the scope of the present invention.
Example 1
The insulated gate semiconductor device in the embodiment sequentially comprises a collector layer 14, a P + -type silicon substrate layer 5, an N + -type buffer layer 4, an N-type first drift layer 3, an N-type epitaxial layer 2, a P-type doping layer 7, P + -type doping layers 8 positioned on two sides of the P-type doping layer 7, an N + -type doping layer 9 positioned inside the P + -type doping layer 8, a trench 11 penetrating through the N + -type doping layer 9 and the P-type doping layer 7 and extending into the N-type second drift layer 1, a first insulating isolation layer 10 positioned on the side wall and the bottom of the trench 11, a second insulating isolation layer 12 positioned above the trench 11, and emitter layers 13 positioned on two sides of the second insulating isolation layer 12 from bottom to top, wherein the height of the emitter layer 13 is smaller than that of the second insulating isolation layer 12, the lateral doping concentration of the P-type doping layers is changed in a gradient manner, and the doping concentration of the P-type doping layers is low when the P-type doping layers are close to the trench 11, the doping concentration on both sides is high.
The method for manufacturing the insulated gate semiconductor device in the embodiment includes the following steps:
(1) as shown in fig. 1, preparing a P + type silicon substrate layer 5, forming an N + type buffer layer 4 on the P + type silicon substrate layer 5, forming an N-type first drift layer 3 on the N + type buffer layer 4, forming an N-type epitaxial layer 2 on the N-type first drift layer 3, and forming an N-type second drift layer 1 on the N-type epitaxial layer 2;
(2) as shown in fig. 2 and 3, boron ion implantation is performed on the N-type second drift layer 1 to form a P-type doped layer 7, and a graded mask 6 is used for processing the P-type doped layer 7, wherein the P-type doped layer 7 is processed by increasing the amount of P-type dopant according to the graded mask under the manufacturing condition without mask, because some of the P-type dopant is blocked, the concentration balance of the originally designed device can be maintained, the breakdown voltage can be maintained, the turn-on voltage can be reduced, and the short-circuit time can be reduced, as shown in fig. 2, ion implantation is performed at the gaps W1, Wi, and Wn, to form a graded doping concentration, the graded doping concentration includes a linear variation, an upper parabolic variation, and a lower parabolic variation, and the linear doping is according to the equation: n (x) ═ N 2 -N 1 )(1-x/L)+N 1 (ii) a The basis equation for the upper parabolic change is:
the following equation for the lower parabolic change is:
wherein N (x) is the doping concentration of the x-axis, L is the length, N 1 Is the base concentration, N 2 The peak concentration, x-axis length distance, y-axis doping concentration, and W open pitch. (ii) a
(3) Oxidizing the P-type doped layer 7 to form an oxidation isolation layer, and implanting arsenic ions in the middle to form an N + type doped layer 9;
(4) oxidizing the N + type doping layer 9 to form an oxidation isolation layer, and implanting boron ions at two sides of the N + type doping layer 9 to form a P + type doping layer 8;
(3) etching the middle part of the N + type doping layer 9 to form a groove 11, wherein the groove 11 penetrates through the whole thickness of the N + type doping layer 9 and the P type doping layer 7, and the bottom of the groove extends into the N type epitaxial layer 2;
(4) as shown in fig. 4, a first insulating isolation layer 10 is disposed on the bottom and the sidewall of the trench 11, and the material of the first insulating isolation layer 10 is silicon dioxide;
(5) embedding a gate electrode in the trench 11, and disposing a second insulating isolation layer 12 on the gate electrode, wherein the second insulating isolation layer 12 extends to two sides of the trench 11, and the second insulating isolation layer 12 is made of silicon dioxide and extends into the N + -type doped layers 9 on two sides of the trench 11 respectively;
(6) as shown in fig. 5, finally, the emitter 13 is covered on the P + -type doped layer 8, the N + -type doped layer 9 and the second insulating isolation layer 12, and the collector 14 is covered on the lower portion of the P + -type silicon substrate layer 5, so that the insulated gate semiconductor device with low on-state voltage and high breakdown voltage is obtained. The concentration of the N + type buffer layer is 5e 18 cm -3 . The concentration of the N-type first drift layer is 3e 14 cm -3 . The concentration of the N-type epitaxial layer is 5e 16 cm -3 . The doping concentration of the P-type doping layer is 3e 14 cm -2
In the technical scheme, the breakdown voltage resistance of the insulated gate semiconductor device is larger than or equal to 1200V, the conduction voltage of the insulated gate semiconductor device is smaller than 1.3V, and the closing time of the insulated gate semiconductor device is smaller than 2 muS, as shown in fig. 6 and 7.
The foregoing examples are merely illustrative and serve to explain some of the features of the method of the present invention. The appended claims are intended to claim as broad a scope as is contemplated, and the examples presented herein are merely illustrative of selected implementations in accordance with all possible combinations of examples. Accordingly, it is applicants' intention that the appended claims are not to be limited by the choice of examples illustrating features of the invention. Also, where numerical ranges are used in the claims, subranges therein are included, and variations in these ranges are also to be construed as possible being covered by the appended claims.
Claims (10)
1. The insulated gate semiconductor device is characterized by comprising a collector layer, a substrate layer, an N + type buffer layer, an N-type first drift layer, an N-type epitaxial layer, a P-type doped layer, P + type doped layers positioned on two sides of the P-type doped layer, an N + type doped layer positioned inside the P + type doped layer, a groove penetrating through the N + type doped layer and the doped layer and extending into a second drift layer, a first insulating isolation layer positioned on the side wall and the bottom of the groove, a second insulating isolation layer positioned above the groove and emitter layers positioned on two sides of the second insulating isolation layer from bottom to top in sequence, wherein the height of the emitter layers is smaller than that of the second insulating isolation layer, and the lateral doping concentration of the P-type doped layers is changed in a gradient manner.
2. The insulated gate semiconductor device according to claim 1, wherein a doping concentration of the P-type doping layer below the P + -type doping layer is greater than a doping concentration of the P-type doping layer below the N + -type doping layer.
3. The insulated gate semiconductor device according to claim 1 or 2, wherein the breakdown voltage of the insulated gate semiconductor device is 1200V or more.
4. The insulated gate semiconductor device according to claim 3, wherein the turn-on voltage of the insulated gate semiconductor device is < 1.3V.
5. The insulated gate semiconductor device according to claim 3, characterized in that the off-time of the insulated gate semiconductor device is <2 μ S.
6. The insulated gate semiconductor device of claim 1, wherein the substrate layer is a P-type silicon substrate layer.
7. The insulated gate semiconductor device according to claim 1, wherein a raw material of the first insulating isolation layer is silicon dioxide.
8. The insulated gate semiconductor device according to claim 1, wherein a raw material of the second insulating spacer is silicon dioxide.
9. A method of manufacturing an insulated gate semiconductor device according to any of claims 1 to 8, comprising at least the steps of:
(1) preparing a substrate layer, forming an N + type buffer layer on the substrate layer, forming an N-type first drift layer on the N + type buffer layer, forming an N-type epitaxial layer on the N-type first drift layer, and forming an N-type second drift layer on the N-type epitaxial layer;
(2) injecting boron ions into the N-type second drift layer to form a P-type doping layer, wherein the lateral doping concentration of the P-type doping layer is changed in a gradient manner;
(3) oxidizing the P-type doped layer to form an oxidation isolation layer, and implanting arsenic ions in the middle of the oxidation isolation layer to form an N + type doped layer;
(4) oxidizing the N + type doping layer to form an oxidation isolation layer, and implanting boron ions at two sides of the N + type doping layer to form a P + type doping layer;
(3) etching the middle part of the N + type doping layer to form a groove, wherein the groove penetrates through the thickness of the whole N + type doping layer and the whole P type doping layer, and the bottom of the groove extends into the N type epitaxial layer;
(4) arranging a first insulating isolation layer on the bottom and the side wall of the groove, wherein the first insulating isolation layer is made of silicon dioxide;
(5) embedding a grid electrode in the groove, and arranging a second insulating isolation layer on the grid electrode, wherein the second insulating isolation layer extends to two sides of the groove, is made of silicon dioxide and respectively extends into the N + type doping layers on two sides of the groove;
(6) and finally, covering an emitter on the P + type doping layer, the N + type doping layer and the second insulation isolation layer, and covering a collector on the lower part of the P type silicon substrate layer to obtain the insulated gate semiconductor device with low on-state voltage and high breakdown voltage resistance.
10. The method for manufacturing an insulated gate semiconductor device according to claim 9, wherein the doping method of the P-type doping layer in step (2) is doping using a graded mask during doping.
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