CN114867207A - Circuit board back drilling stub control method and circuit board - Google Patents
Circuit board back drilling stub control method and circuit board Download PDFInfo
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- CN114867207A CN114867207A CN202210491705.2A CN202210491705A CN114867207A CN 114867207 A CN114867207 A CN 114867207A CN 202210491705 A CN202210491705 A CN 202210491705A CN 114867207 A CN114867207 A CN 114867207A
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- 238000005553 drilling Methods 0.000 title claims abstract description 148
- 238000000034 method Methods 0.000 title claims abstract description 40
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052802 copper Inorganic materials 0.000 claims abstract description 33
- 239000010949 copper Substances 0.000 claims abstract description 33
- 238000007747 plating Methods 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000009713 electroplating Methods 0.000 claims abstract description 11
- 230000000149 penetrating effect Effects 0.000 claims abstract description 8
- 238000003825 pressing Methods 0.000 claims abstract description 6
- 230000002093 peripheral effect Effects 0.000 claims abstract description 5
- 238000005406 washing Methods 0.000 claims abstract description 5
- 238000012360 testing method Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 10
- 238000007639 printing Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 4
- 238000004458 analytical method Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 abstract description 5
- 230000008054 signal transmission Effects 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- 230000006698 induction Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
- H05K3/424—Plated through-holes or plated via connections characterised by electroplating method by direct electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0207—Partly drilling through substrate until a controlled depth, e.g. with end-point detection
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to the technical field of circuit boards, and discloses a circuit board back drilling stub control method and a circuit board. The control method comprises the following steps: providing a plurality of core panels, the plurality of core panels comprising at least one indicia core panel; manufacturing anti-plating ink at a target position of the marking core plate, wherein the target position is located at a junction position of a back drilling penetrating layer of the back drilling to be drilled and a back drilling non-drilling penetrating layer, and the anti-plating ink at least covers a peripheral area of the back drilling to be drilled; after the plating-resistant ink is manufactured, sequentially pressing the multiple core plates, drilling through holes at the position to be back-drilled, depositing copper, washing off the plating-resistant ink and electroplating; and back drilling is carried out at the position to be back drilled, and the back drilling depth is smaller than that of the target position. The invention can reduce the influence of the back drilling depth precision on the back drilling processing, in particular to the back drilling processing containing an ultrathin core plate, avoids drilling through a signal layer and can reduce the influence of a back drilling stub on signal transmission to the maximum extent.
Description
Technical Field
The invention relates to the technical field of circuit boards, in particular to a circuit board back drilling stub control method and a circuit board.
Background
Currently, the back drilling depth is mainly controlled by two ways: one is to control depth by current induction and the other is to control depth by pressure induction. However, the back drilling error of the two control modes is larger than 50 μm, and even more, the error reaches more than 100 μm.
With the development of light weight, thinness, short size and small size of electronic products, the requirements for the mainboard of the electronic product are continuously increased. The back drilling machining precision of the position containing the ultrathin core plate is greatly influenced by the plate thickness tolerance, the uniformity of the plate thickness tolerance, the back drilling equipment tolerance and the like, the back drilling needs to drill through a target layer and cannot drill through a signal layer, and the realization difficulty is very high when the requirement that Stub length is smaller is met.
Disclosure of Invention
The invention aims to provide a circuit board back drilling stub control method and a circuit board, so as to overcome the defects of the ultra-thin core board back drilling processing yield and the product quality in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a circuit board back drilling stub control method comprises the following steps:
providing a plurality of core panels, the plurality of core panels comprising at least one indicia core panel;
manufacturing anti-plating ink at a target position of the marking core plate, wherein the target position is located at a junction position of a back drilling penetrating layer of the back drilling to be drilled and a back drilling non-drilling penetrating layer, and the anti-plating ink at least covers a peripheral area of the back drilling to be drilled;
after the plating-resistant ink is manufactured, sequentially pressing the multiple core plates, drilling through holes at the position to be back-drilled, depositing copper, washing off the plating-resistant ink and electroplating;
and back drilling is carried out at the position to be back drilled, and the back drilling depth is smaller than that of the target position.
Optionally, back drilling is performed at the position to be back drilled, and the back drilling method specifically includes:
determining a theoretical depth value D of a backdrill 0 And depth standard compensation value Delta D 0 ；
Compensating for a value Δ D according to the depth criterion 0 Determining a plurality of depth compensation values DeltaD at different gradients n ；
According to each depth compensation value DeltaD n Determining a plurality of depth values D of the backdrilling under different gradients n ＝△D n +D 0 And according to a plurality of back drilling depth values D n Manufacturing a plurality of first back drilling test holes on the process edge;
the plurality of first back drilling test holes are subjected to slicing analysis, the first back drilling test holes with the highest back drilling stub precision are screened out, and depth compensation values delta D corresponding to the screened first back drilling test holes n As actual backdrilling compensation value;
and performing compensation back drilling at the position of the back drilling to be planned according to the actual back drilling compensation value.
Optionally, determining the depth standard compensation value DeltaD of the back drill 0 The method of (1), comprising:
according to the theoretical depth value D 0 Manufacturing a second back drilling test hole on the process edge, and measuring the actual depth value of the second back drilling test hole;
according to the theoretical depth value D 0 And calculating the actual depth value of the second back drilling test hole to obtain a first compensation factor f 1 ；
Calculating to obtain a second compensation factor f according to the actual thickness value and the theoretical thickness value of the circuit board at the corresponding position of the second back drilling test hole 2 ；
According to the first compensation factor f 1 And said second compensation factor f 2 Determining a depth standard compensation value DeltaD of the first back drilling test hole 0 。
Optionally, the depth compensation value Δ D n ＝λ△D 0 Wherein λ is 0.8, 1.0 or 1.2.
Optionally, the thickness of the dielectric layer of the label core board is less than or equal to 0.102 mm.
Optionally, the thickness of the dielectric layer of the mark core plate is 0.076 mm.
Optionally, the plating-resistant ink is manufactured at the target position of the marking core plate by adopting a digital jet printing technology.
Optionally, the mark core board includes a substrate and a copper layer covering at least one side surface of the substrate, and a position of the back-drill drilled-through layer, which is located at a boundary with the back-drill non-drilled-through layer, is located on a surface of the copper layer.
A circuit board is manufactured by adopting the circuit board back drilling stub control method.
Compared with the prior art, the invention has the beneficial effects that:
according to the embodiment of the invention, plating-resistant ink is arranged at the target position in the hole wall of the back drill to form the isolating ring for isolating the back drill penetrating layer of the back drill to be subjected to back drilling and the back drill non-penetrating layer, so that the accurate separation of hole copper at the position to be subjected to back drilling is realized, most of invalid hole copper is removed by back drilling after electroplating, and the stub length of the back drill is effectively controlled. Compared with the traditional back drilling method, the embodiment of the invention can avoid the influence of back drilling depth precision and hole site precision on back drilling processing, particularly the back drilling processing in an ultrathin core plate layer, and on the premise of not drilling through a signal layer, the influence of back drilling stub on signal transmission is reduced to the maximum extent, the product yield is improved, and the product quality and the production efficiency are greatly improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a stub control method for back drilling of a circuit board according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of the labeled core board in step S1 according to the embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a marking core containing plating-resistant ink in step S1 according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of the circuit board body after being pressed in step S2 according to the embodiment of the present invention;
fig. 5 is a schematic structural diagram of the circuit board body after the through hole is drilled in step S2 according to the embodiment of the present invention;
fig. 6 is a schematic structural diagram of the circuit board body after copper deposition in step S2 according to the embodiment of the present invention;
fig. 7 is a schematic structural diagram of the circuit board body after being washed away in step S2 according to the embodiment of the present invention;
FIG. 8 is a schematic structural diagram of the circuit board semi-finished product after electroplating in step S2 according to the embodiment of the invention;
fig. 9 is a schematic structural diagram of the circuit board semi-finished product after backdrilling in step S2 according to the embodiment of the present invention;
fig. 10 is a flowchart illustrating the back drilling method of step S3 according to the embodiment of the present invention.
Reference numerals:
10-initial label core;
10 a-inner layer circuit pattern;
20-marking core containing plating resistant ink;
20 a-plating resistant ink;
30-circuit board body after pressing;
40-circuit board body after drilling;
40 a-drilled through hole to be backdrilled;
50-circuit board body after copper deposition;
50 a-copper deposition metallized through hole of back drilling;
60-circuit board body after being faded;
60 a-metallized through holes to be back-drilled after the step of removing;
70-circuit board body after electroplating;
70 a-metallized via to be backdrilled;
80-circuit board body after back drilling;
80 a-Back-drilled hole;
80 b-Back-drill through target layer;
80 c-Back-drilling the non-drilled through signal layer.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Referring to fig. 1, a method for controlling stub of back drilling of a circuit board according to an embodiment of the present invention includes the following steps:
step S1: providing a plurality of core plates required by the circuit board, wherein at least one mark core plate is included, and manufacturing the plating-resistant ink at the target position of the mark core plate.
According to the different depth of the pseudo-back drilling, the marked core plate can be the core plate which is drilled through the top layer of the core plate and is not drilled through the bottom layer of the core plate in the pseudo-back drilling operation, or the core plate which is closest to the back drilling drilled layer and is not drilled through the top layer of the core plate in the pseudo-back drilling operation.
Illustratively, there is provided 7 core boards for manufacturing a 16-layer circuit board, the 7 core boards specifically including: 5 normal core boards, and 1 marking core board 10 (shown in fig. 2) with inner layer circuits 10 a. The marker core boards 10 each include a substrate, a copper layer overlying an upper surface of the substrate (which may be considered a top layer of the core board), and a copper layer overlying a lower surface of the substrate (which may be considered a bottom layer of the core board).
In this embodiment, the marking core board 10 is a core board that should be drilled through the top layer of the core board and not drilled through the bottom layer of the core board in the back drilling operation, and at this time, the boundary position of the back drilling through layer and the back drilling non-drilling through layer of the back drilling to be drilled through is located at the original copper layer on the upper surface of the marking core board substrate.
Illustratively, two different core boards, IT-968core 0.076mm H/H and core 0.102mm H/H, can be used to laminate the high-speed material. I.e. the dielectric layer thickness of the label core 10 is 0.076 mm.
And spraying and printing anti-plating ink at a target position of the mark core plate, wherein the target position is located at a junction position of a back-drilling through target layer and a back-drilling non-through signal layer, the back-drilling through target layer is located at a copper layer on the surface of one side, close to the dielectric layer, of the mark core plate, the junction position is located on the surface of one side of the mark core plate substrate, and the anti-plating ink completely covers a position to be back-drilled.
For clearly explaining the principle of the scheme, the position of the back drill is L1-4/5, the length of the stub of the back drill is required to be less than 0.125mm, and the marking core plate 10 is L4/5.
Drilling, namely pre-expanding and expanding shrinkage according to material test data; and (6) pasting a dry film, and exposing by an LDI machine to finish the manufacture of the inner layer circuit.
In this embodiment, the target position of the plating resist ink 20a, that is, the position of the copper layer on the upper surface of the marking core board 10 is prepared. For this purpose, it is necessary to etch away the designated area of the copper layer on the upper surface, and then spray-print the plating resist ink 20a in the designated area, the plating resist ink 20a is directly spray-printed on the substrate by a digital ink-jet printer using a digital spray-printing technology to obtain a plating resist pattern, and after UV light curing, the finally obtained marking core 20 containing the plating resist ink 20a is shown in fig. 3.
In this embodiment, the plating resist ink 20a of the digital jet printing is a material that cannot or is difficult to deposit copper, and in the subsequent through hole drilling process, the plating resist ink 20a will be drilled through to form an isolation ring, and the isolation ring cannot achieve good copper deposition due to its material characteristics, and can be removed easily in the subsequent process. The plating resist ink 20a may be circular in shape, i.e., covering the entire back-drilling position and its peripheral area; or the shape is circular ring, namely only covering the edge area of the position to be backdrilled and the peripheral area thereof; in this embodiment, the plating resist ink 20a is circular in shape, and in this case, the diameter d of the plating resist ink 20a and the diameter d of the through hole are the same 0 The relationship of (1) is: d ═ d 0 +0.20mm＝0.20mm+0.20mm＝0.40mm。
Step S2: the pressed circuit board body 30 is prepared through browning and pressing; drilling a through hole to obtain a circuit board body 40 after the through hole is drilled; obtaining a circuit board body 50 after copper deposition through copper deposition; after the circuit board is washed, a circuit board body 60 after washing is obtained; and electroplating to obtain the electroplated circuit board body 70. See fig. 4-8.
The step of browning and pressing: and (4) brown oxidizing at the brown oxidizing speed according to the thickness of the bottom copper, and overlapping the outer layer copper foil, the prepreg, the common core board and the marking core board according to the design requirement. And selecting proper laminating conditions for lamination according to the characteristics of the plate materials to form the production plate. And (3) performing a thermal stress test after lamination, wherein the thermal stress test is performed for 288 ℃ 10s 5 times, the phenomenon of layering and plate explosion does not occur, the thickness of the plate and the thickness of each dielectric layer are detected, and the thickness of the laminated dielectric layer between the two core plates is 0.213 mm.
Drilling: drilling the production board by using the drilling data, wherein the drilled through holes comprise drilled through holes 40a needing back drilling, and the hole diameter of the drilled through holes is 0.20 mm; adopts a high-density backing plate and a brand-new drill bit. After drilling, the target position of the plating-resistant ink 20a is arranged on the wall of the through hole, so that an isolation ring is formed, and the back drill drilling target layer of the intended back drill is isolated from the back drill non-drilling signal layer.
Copper deposition: according to the material characteristics, plasma degumming treatment is carried out before copper deposition. And then copper is deposited to metalize the through holes on the circuit board, and the backlight test is carried out for 10 grades. In this process, due to the property of the isolation ring that copper cannot be deposited or is difficult to deposit, the copper deposition layer cannot be formed at the inner wall of the isolation ring where the through hole 40a is drilled.
And (3) fading and washing: and (3) completely removing the isolating ring on the inner wall of the drilled through hole 40a by adopting an alkaline chemical removing agent to form a cavity, wherein the cavity cannot be plated to form hole copper subsequently due to non-metallization.
Electroplating: and electroplating the whole board to obtain a metalized through hole to be back-drilled. In the process, the cavity position of the inner wall of the drilled through hole 40a can not form a copper plating layer, so that after electroplating, the hole copper can be accurately separated at the cavity position, thereby avoiding the reflection and interference of the redundant hole copper to signals in the high-speed signal transmission process and ensuring the integrity of signal transmission.
And S3, performing back drilling at the position to be back drilled, wherein the back drilling depth is less than the depth of the target position.
Specifically, as shown in fig. 10, step S3 further includes:
s31 determining theoretical depth value D of back drill 0 And depth standard compensation value Delta D 0 。
S32, compensating value Delta D according to the depth standard 0 Determining a plurality of depth compensation values DeltaD at different gradients n 。
Exemplary, depth compensation value Δ D n ＝λ△D 0 Wherein λ is 0.8, 1.0 or 1.2.
S33, compensating value DeltaD according to each depth n Determining multiple back-drilling depth values D at different gradients n ＝△D n +D 0 And according to a plurality of back drilling depth values D n And manufacturing a plurality of first back drilling test holes on the process edge.
S34, carrying out slicing analysis on the plurality of first back drilling test holes, screening out the first back drilling test hole with the highest back drilling stub precision, and selecting the depth compensation value delta D corresponding to the screened first back drilling test hole n As the actual back-drilling compensation value.
And S35, performing compensation back drilling at the position to be back drilled according to the actual back drilling compensation value to obtain the circuit board body 80, and referring to fig. 9.
In the back drilling method, the value Delta D is compensated according to the optimal depth n Carry out compensation back drilling, can effectively shorten the length of back drilling stub, improve the back drilling precision.
Exemplary, depth standard compensation Δ D for backdrilling is determined in S31 0 The method of (1), further comprising:
according to the theoretical depth value D 0 Manufacturing a second back drilling test hole on the process edge, and measuring the actual depth value of the second back drilling test hole;
according to the theoretical depth value D 0 And calculating the actual depth value of the second back drilling test hole to obtain a first compensation factor f 1 (ii) a Calculating to obtain a second compensation factor f according to the actual thickness value and the theoretical thickness value of the circuit board at the corresponding position of the second back drilling test hole 2 ；
According to a first compensation factor f 1 And a second compensation factorf 2 Determining a depth standard compensation value Delta D of a first back-drilled test hole 0 。
It should be noted that, in the back drilling process of the conventional technology, in the target position of the core board marked, the back drill is required to drill through the top layer of the core board and not to drill through the bottom layer of the core board (corresponding to the back drill non-drilling signal layer in the present invention), since the core board dielectric layer is 0.076mm, the process difficulty is large, the quality is low, and the yield is low.
The back-drilled hole copper is accurately separated at the cavity position after electroplating. At mark core target location, the back drill bores the top layer that the target layer kept away from mark core, can avoid the production board because of receiving the influence that production board warp, equipment back drill machining precision, still can avoid leading to appearing the quality that the non-signal layer of boring of back drill was bored and is bored the quality anomaly, and back drill stub length is the dielectric layer thickness of core behind the pressfitting, can effective control back drill stub length.
Example two
The embodiment of the invention provides a circuit board which is processed and prepared by the circuit board back drilling stub control method.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (9)
1. A circuit board back drilling stub control method is characterized by comprising the following steps:
providing a plurality of core panels, the plurality of core panels comprising at least one indicia core panel;
manufacturing anti-plating ink at a target position of the marking core plate, wherein the target position is located at a junction position of a back drilling penetrating layer of the back drilling to be drilled and a back drilling non-drilling penetrating layer, and the anti-plating ink at least covers a peripheral area of the back drilling to be drilled;
after the plating-resistant ink is manufactured, sequentially pressing the multiple core plates, drilling through holes at the position to be back-drilled, depositing copper, washing off the plating-resistant ink and electroplating;
and back drilling is carried out at the position to be back drilled, and the back drilling depth is smaller than that of the target position.
2. The method for controlling stub of circuit board back drilling according to claim 1, wherein back drilling is performed at the position to be back drilled, and specifically comprises:
determining a theoretical depth value D of a backdrill 0 And depth standard compensation value Delta D 0 ；
Compensating for a value Δ D according to the depth criterion 0 Determining a plurality of depth compensation values DeltaD at different gradients n ；
According to each depth compensation value DeltaD n Determining a plurality of depth values D of the backdrilling under different gradients n ＝△D n +D 0 And according to a plurality of back drilling depth values D n Manufacturing a plurality of first back drilling test holes on the process edge;
the plurality of first back drilling test holes are subjected to slicing analysis, the first back drilling test holes with the highest back drilling stub precision are screened out, and depth compensation values delta D corresponding to the screened first back drilling test holes n As actual backdrilling compensation value;
and performing compensation back drilling at the position of the back drilling to be planned according to the actual back drilling compensation value.
3. The method for controlling stub of circuit board back drilling according to claim 2, wherein the depth standard compensation value Δ D of back drilling is determined 0 The method of (1), comprising:
according to the theoretical depth value D 0 Manufacturing a second back drilling test hole on the process edge, and measuring the actual depth value of the second back drilling test hole;
according to the theoretical depth value D 0 And calculating the actual depth value of the second back drilling test hole to obtain a first compensation factor f 1 ；
Calculating to obtain a second compensation factor f according to the actual thickness value and the theoretical thickness value of the circuit board at the corresponding position of the second back drilling test hole 2 ；
According to the first compensation factor f 1 And said second compensation factor f 2 Determining a depth standard compensation value DeltaD of the first back drilling test hole 0 。
4. The method for controlling stub of circuit board back drilling according to claim 2, wherein the depth compensation value Δ D n ＝λ△D 0 Wherein λ is 0.8, 1.0 or 1.2.
5. The method for controlling stub of circuit board back drilling according to claim 1, wherein the thickness of the dielectric layer of the marking core board is less than or equal to 0.102 mm.
6. The method for controlling the back drilling stub of the circuit board according to claim 5, wherein the thickness of the dielectric layer of the marking core board is 0.076 mm.
7. The method for controlling stub of circuit board back drilling according to claim 1, wherein a digital jet printing technology is used to make plating-resistant ink at a target position of the marking core board.
8. The method for controlling stub of circuit board back-drilling according to claim 1, wherein the marking core board comprises a substrate and a copper layer covering at least one side surface of the substrate, and the position of the back-drilling through layer interfacing with the back-drilling non-drilling through layer is located on the surface of the copper layer.
9. A wiring board characterized in that the wiring board is manufactured by the wiring board back drilling stub control method as set forth in any one of claims 1 to 8.
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| CN202210491705.2A CN114867207A (en) | 2022-04-29 | 2022-04-29 | Circuit board back drilling stub control method and circuit board |
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| CN202210491705.2A CN114867207A (en) | 2022-04-29 | 2022-04-29 | Circuit board back drilling stub control method and circuit board |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117279224A (en) * | 2023-11-17 | 2023-12-22 | 深圳市大族数控科技股份有限公司 | Circuit board back drilling method and circuit board back drilling device |
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| CN117279224B (en) * | 2023-11-17 | 2024-01-26 | 深圳市大族数控科技股份有限公司 | Circuit board back drilling method and circuit board back drilling device |
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