CN114859207A - Reliability detection device and reliability detection method - Google Patents

Reliability detection device and reliability detection method Download PDF

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CN114859207A
CN114859207A CN202110166616.6A CN202110166616A CN114859207A CN 114859207 A CN114859207 A CN 114859207A CN 202110166616 A CN202110166616 A CN 202110166616A CN 114859207 A CN114859207 A CN 114859207A
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CN114859207B (en
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许文轩
郭俊仪
陈莹晏
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Realtek Semiconductor Corp
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Abstract

The reliability detection apparatus includes a control circuit, a plurality of oscillator circuits, and an output circuit. The control circuit is used for generating a plurality of enable signals according to the mode signal. The oscillator circuits are used for outputting oscillation signals. Each of the oscillator circuits is configured to generate a corresponding oscillation signal of the plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, and generate a corresponding oscillation signal according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value. The switching signal is associated with the functional circuit. The output circuit is used for outputting a detection signal according to the oscillation signals when the mode signal has a second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.

Description

可靠度检测装置与可靠度检测方法Reliability detection device and reliability detection method

技术领域technical field

本案是关于电路的可靠度检测装置,尤其是关于具有振荡器电路的可靠度检测装置与可靠度检测方法。This case is about a reliability detection device of a circuit, especially a reliability detection device and a reliability detection method with an oscillator circuit.

背景技术Background technique

随着运行时间变长,集成电路可能会因为一些非理想因素产生衰退。例如,负偏压温度不稳定性(negative-bias temperature instability)会使P型晶体管的临界电压逐渐变高。若P型晶体管的临界电压逐渐变高,可能会使集成电路的原有操作出现错误,或使集成电路的效能下降。在一些相关技术中,振荡器电路可被用来检测集成电路的效能,以确认集成电路中的组件可靠度是否在正常范围。然而,在上述技术中,振荡器电路可能会因为省电机制被关闭,或是被设定为过度切换,导致检测结果不准确。Integrated circuits may degrade due to some non-ideal factors as the run time becomes longer. For example, negative-bias temperature instability can gradually increase the threshold voltage of a P-type transistor. If the threshold voltage of the P-type transistor gradually increases, it may cause errors in the original operation of the integrated circuit, or reduce the performance of the integrated circuit. In some related art, an oscillator circuit can be used to detect the performance of the integrated circuit to confirm whether the reliability of the components in the integrated circuit is within a normal range. However, in the above technique, the oscillator circuit may be turned off due to the power saving mechanism or set to over-switch, resulting in inaccurate detection results.

发明内容SUMMARY OF THE INVENTION

在一些实施例中,可靠度检测装置包括控制电路、多个振荡器电路以及输出电路。控制电路用以根据模式信号产生多个使能信号。多个振荡器电路用以输出多个振荡信号。该多个振荡器电路中的每一者用以在该模式信号具有第一逻辑值时根据切换信号产生该多个振荡信号中的对应振荡信号,并在该模式信号具有第二逻辑值时根据该多个使能信号中的对应使能信号产生该对应振荡信号。该切换信号与功能性电路相关联。输出电路用以在该模式信号具有该第二逻辑值时根据该多个振荡信号输出检测信号,其中该检测信号用以反映该功能性电路的可靠度。In some embodiments, the reliability detection apparatus includes a control circuit, a plurality of oscillator circuits, and an output circuit. The control circuit is used for generating a plurality of enable signals according to the mode signal. A plurality of oscillator circuits are used for outputting a plurality of oscillating signals. Each of the plurality of oscillator circuits is configured to generate a corresponding oscillating signal of the plurality of oscillating signals according to a switching signal when the mode signal has a first logic value, and according to a switching signal when the mode signal has a second logic value A corresponding enable signal among the plurality of enable signals generates the corresponding oscillation signal. The switching signal is associated with a functional circuit. The output circuit is used for outputting a detection signal according to the plurality of oscillating signals when the mode signal has the second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.

在一些实施例中,可靠度检测方法包括下列操作:根据模式信号产生多个使能信号;在该模式信号具有第一逻辑值时根据切换信号产生多个振荡信号,其中该切换信号与功能性电路相关联;在该模式信号具有第二逻辑值时根据该多个使能信号中的对应使能信号产生该多个振荡信号中的对应振荡信号;以及在该模式信号具有该第二逻辑值时根据该多个振荡信号输出检测信号,其中该检测信号用以反映该功能性电路的可靠度。In some embodiments, the reliability detection method includes the following operations: generating a plurality of enable signals according to a mode signal; generating a plurality of oscillating signals according to a switching signal when the mode signal has a first logic value, wherein the switching signal is related to the functionality a circuit is associated; when the mode signal has a second logic value, a corresponding oscillating signal of the plurality of oscillating signals is generated according to a corresponding enable signal of the plurality of enable signals; and when the mode signal has the second logic value and outputting a detection signal according to the plurality of oscillating signals, wherein the detection signal is used to reflect the reliability of the functional circuit.

有关本案的特征、实作与功效,现在配合图式作较佳实施例详细说明如下。With regard to the features, implementations and effects of this case, a preferred embodiment is now described in detail as follows in conjunction with the drawings.

附图说明Description of drawings

图1为根据本案一些实施例绘制一种可靠度检测装置的示意图;FIG. 1 is a schematic diagram of drawing a reliability detection device according to some embodiments of the present application;

图2为根据本案一些实施例绘制图1的多个振荡器电路以及输出电路的示意图;FIG. 2 is a schematic diagram illustrating a plurality of oscillator circuits and output circuits of FIG. 1 according to some embodiments of the present application;

图3为根据本案一些实施例绘制图1的控制电路的示意图;以及FIG. 3 is a schematic diagram illustrating the control circuit of FIG. 1 according to some embodiments of the present invention; and

图4为根据本案一些实施例绘制一种可靠度检测方法的流程图。FIG. 4 is a flowchart illustrating a reliability detection method according to some embodiments of the present application.

具体实施方式Detailed ways

本文所使用的所有词汇具有其通常的含义。上述词汇在普遍常用字典中的定义,在本案的内容中包括任一于此讨论的词汇的使用例子仅为示例,不应限制本案的范围与含义。同样地,本案亦不仅以于此说明书所示出的各种实施例为限。All terms used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, the use of any of the words discussed herein in the content of this case is only an example, and should not limit the scope and meaning of this case. Likewise, the present application is not limited to the various embodiments shown in this specification.

关于本文中所使用的“耦接”或“连接”,均可指两个或多个组件相互直接作实体或电性接触,或是相互间接作实体或电性接触,亦可指两个或多个组件相互操作或动作。如本文所用,用语“电路系统(circuitry)”可为由至少一个电路(circuit)所形成的单一系统,且用语“电路”可为由至少一个晶体管与/或至少一个主被动组件按一定方式连接以处理信号的装置。As used herein, "coupling" or "connection" may refer to two or more components in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or two or more components in physical or electrical contact with each other. Multiple components interact or act on each other. As used herein, the term "circuitry" can be a single system formed by at least one circuit, and the term "circuit" can be connected in a manner by at least one transistor and/or at least one active and passive component A device for processing signals.

如本文所用,用语“和/或”包括了列出的关联项目中的一个或多个的任何组合。在本文中,使用第一、第二与第三等词汇,是用于描述并辨别各个组件。因此,在本文中的第一组件也可被称为第二组件,而不脱离本案的本意。为易于理解,各图式中的类似组件将被指定为相同标号。As used herein, the term "and/or" includes any combination of one or more of the associated listed items. In this document, the terms first, second and third are used to describe and identify each component. Therefore, the first component may also be referred to as the second component herein without departing from the original intent of the present case. For ease of understanding, similar components in the various figures will be designated by the same reference numerals.

图1为根据本案一些实施例绘制一种可靠度检测装置100的示意图。在一些实施例中,功能性电路101可为(但不限于)数字信号处理电路、特殊应用集成电路等等。于实际应用中,功能性电路101可能会因为操作时间变长产生衰退。在一些实施例中,可靠度检测装置100可与功能性电路101整合为单一系统,并可用于检测功能性电路101的衰退(aging)程度。FIG. 1 is a schematic diagram illustrating a reliability detection apparatus 100 according to some embodiments of the present application. In some embodiments, the functional circuit 101 may be, but is not limited to, a digital signal processing circuit, an application specific integrated circuit, or the like. In practical applications, the functional circuit 101 may degrade due to the prolonged operation time. In some embodiments, the reliability detection device 100 can be integrated with the functional circuit 101 into a single system, and can be used to detect the aging degree of the functional circuit 101 .

可靠度检测装置100包括控制电路110、多个振荡器电路120[0]~120[4]以及输出电路130。控制电路110用以根据模式信号AG产生多个使能信号EN[0]~EN[4]。例如,当模式信号AG具有第一逻辑值(例如为逻辑值1)时,所有使能信号EN[0]~EN[4]具有第二逻辑值(例如为逻辑值0),其中第一逻辑值相反于第二逻辑值(例如,在逻辑值非0即1的状况下)。或者,当模式信号AG具有第二逻辑值时,这些使能信号EN[0]~EN[4]中的一者可具有第一逻辑值。但根据模式信号AG产生多个使能信号EN[0]~EN[4]的组合不以此为限。The reliability detection device 100 includes a control circuit 110 , a plurality of oscillator circuits 120 [ 0 ] to 120 [ 4 ], and an output circuit 130 . The control circuit 110 is used for generating a plurality of enable signals EN[0]˜EN[4] according to the mode signal AG. For example, when the mode signal AG has a first logic value (eg, logic value 1), all enable signals EN[0]˜EN[4] have a second logic value (eg, logic value 0), wherein the first logic value The value is the opposite of the second logical value (eg, in the case where the logical value is either 0 or 1). Alternatively, when the mode signal AG has the second logic value, one of the enable signals EN[0]˜EN[4] may have the first logic value. However, the combination of generating a plurality of enable signals EN[0]˜EN[4] according to the mode signal AG is not limited to this.

多个振荡器电路120[0]~120[4]用以输出多个振荡信号SC[0]~SC[4]。在模式信号AG具有第一逻辑值(例如为逻辑值1)时,多个振荡器电路120[0]~120[4]中的每一者用以根据切换信号TG产生多个振荡信号SC[0]~SC[4]中的对应振荡信号。在一些实施例中,切换信号TG与功能性电路101相关联。例如,切换信号TG可为来自功能性电路的输出信号,或可为功能性电路101的内部信号,或是基于来自功能性电路101的信号所产生的信号。在一些实施例中,切换信号TG可用以反映功能性电路101的平均切换频率(toggle rate)。藉由上述操作,当模式信号AG具有第一逻辑值时,多个振荡器电路120[0]~120[4]可随着功能性电路101一起切换。如此一来,多个振荡器电路120[0]~120[4]的衰退程度可相近于功能性电路101的衰退程度,以产生更为准确的检测结果。The plurality of oscillator circuits 120[0]-120[4] are used for outputting a plurality of oscillation signals SC[0]-SC[4]. When the mode signal AG has a first logic value (eg, logic value 1), each of the plurality of oscillator circuits 120[0]˜120[4] is used to generate a plurality of oscillating signals SC[ according to the switching signal TG 0] to the corresponding oscillation signal in SC[4]. In some embodiments, switching signal TG is associated with functional circuit 101 . For example, the switching signal TG may be an output signal from the functional circuit, or may be an internal signal of the functional circuit 101, or a signal generated based on a signal from the functional circuit 101. In some embodiments, the switching signal TG may be used to reflect the average switching rate of the functional circuit 101 . Through the above operations, when the mode signal AG has the first logic value, the plurality of oscillator circuits 120[0]˜120[4] can be switched together with the functional circuit 101 . In this way, the degradation degrees of the plurality of oscillator circuits 120[0]-120[4] can be similar to the degradation degrees of the functional circuit 101, so as to generate more accurate detection results.

或者,在模式信号AG具有第二逻辑值(例如为逻辑值0)时,多个振荡器电路120[0]~120[4]中的每一者用以根据多个使能信号EN[0]~EN[4]中的对应使能信号产生多个振荡信号SC[0]~SC[4]中的对应振荡信号。换言之,在模式信号AG具有第二逻辑值时,各个振荡器电路120[0]~120[4]不响应于切换信号TG产生对应的振荡信号。藉由上述操作,在模式信号AG具有第二逻辑值时,多个振荡器电路120[0]~120[4]中的每一者可根据对应的使能信号操作为自由运行(free running)振荡器电路,以产生对应的振荡信号。于此条件下,多个振荡信号SC[0]~SC[4]可用来反映功能性电路101的衰退程度。Alternatively, when the mode signal AG has the second logic value (eg, logic value 0), each of the plurality of oscillator circuits 120[0]˜120[4] is used for the plurality of enable signals EN[0 The corresponding enable signals in ]˜EN[4] generate corresponding oscillating signals in the plurality of oscillating signals SC[0]˜SC[4]. In other words, when the mode signal AG has the second logic value, the respective oscillator circuits 120[0]˜120[4] do not generate the corresponding oscillation signal in response to the switching signal TG. Through the above operations, when the mode signal AG has the second logic value, each of the plurality of oscillator circuits 120[0]˜120[4] may operate free running according to the corresponding enable signal Oscillator circuit to generate the corresponding oscillating signal. Under this condition, a plurality of oscillating signals SC[0]-SC[4] can be used to reflect the degradation degree of the functional circuit 101.

输出电路130用以在模式信号AG具有第二逻辑值时根据多个振荡信号SC[0]~SC[4]输出检测信号SD。在一些实施例中,检测信号SD可用来反映功能性电路101的可靠度。在一些实施例中,在模式信号AG具有第一逻辑值时,输出电路130停止输出检测信号SD。换言之,输出电路130在模式信号AG具有第一逻辑值时可以停止切换。如此,可降低功率消耗并避免输出电路130衰退,以提升检测准确度。The output circuit 130 is used for outputting the detection signal SD according to the plurality of oscillation signals SC[0]-SC[4] when the mode signal AG has the second logic value. In some embodiments, the detection signal SD can be used to reflect the reliability of the functional circuit 101 . In some embodiments, when the mode signal AG has the first logic value, the output circuit 130 stops outputting the detection signal SD. In other words, the output circuit 130 may stop switching when the mode signal AG has the first logic value. In this way, the power consumption can be reduced and the degradation of the output circuit 130 can be avoided, so as to improve the detection accuracy.

在一些实施例中,可靠度检测装置100还可以包括处理电路(未示出)。在可靠度检测装置100第一次开机时,模式信号AG被设置为具有第二逻辑值。响应于此模式信号AG,多个振荡器电路120[0]~120[4]可响应于多个使能信号EN[0]~EN[4]依序产生多个振荡信号SC[0]~SC[4]。例如,当使能信号EN[0]具有第二逻辑值时,剩余的使能信号EN[1]~EN[4]具有第一逻辑值。于此条件下,振荡器电路120[0]可产生对应的振荡信号SC[0],且多个振荡器电路120[1]~120[4]不产生多个振荡信号SC[1]~SC[4]。输出电路130可基于振荡信号SC[0]输出对应的检测信号SD。接着,处理电路可根据此检测信号SD进行计数,以产生对应于振荡器电路120[0]的默认值,并储存该默认值于缓存器电路(未示出)。依此类推,在可靠度检测装置100第一次开机时,处理电路可储存分别对应于多个振荡器电路120[0]~120[4]的多个默认值。In some embodiments, the reliability detection apparatus 100 may further include a processing circuit (not shown). When the reliability detection apparatus 100 is turned on for the first time, the mode signal AG is set to have the second logic value. In response to the mode signal AG, the plurality of oscillator circuits 120[0]-120[4] may sequentially generate a plurality of oscillation signals SC[0]-120[4] in response to the plurality of enable signals EN[0]-EN[4] SC[4]. For example, when the enable signal EN[0] has the second logic value, the remaining enable signals EN[1]˜EN[4] have the first logic value. Under this condition, the oscillator circuit 120[0] can generate the corresponding oscillation signal SC[0], and the oscillator circuits 120[1]-120[4] do not generate the oscillation signals SC[1]-SC [4]. The output circuit 130 may output the corresponding detection signal SD based on the oscillation signal SC[0]. Then, the processing circuit can count according to the detection signal SD to generate a default value corresponding to the oscillator circuit 120[0], and store the default value in a register circuit (not shown). By analogy, when the reliability detection apparatus 100 is powered on for the first time, the processing circuit can store a plurality of default values corresponding to the plurality of oscillator circuits 120[0]-120[4] respectively.

在后续的检测操作中,处理电路可根据检测信号SD产生新的计数值,并比较该计数值与对应的默认值以确认功能性电路101的可靠度。例如,由于电路衰退,多个振荡信号SC[0]~SC[4]的频率越来越慢,使得新的计数值变小。若该计数值小于对应的默认值,代表功能性电路101的效能有衰退。在一些实施例中,处理电路可将计数值与临界值进行比较,并在该计数值小于临界值时发出警告信息。此警告信息可用于通知用户或其他校正电路功能性电路101的效能过低,以进行后续更换或校正。在一些实施例中,上述的处理电路可由处理器电路实施。例如,上述多个操作可由该处理器电路执行软件来实施,但本案并不以此为限。In subsequent detection operations, the processing circuit can generate a new count value according to the detection signal SD, and compare the count value with the corresponding default value to confirm the reliability of the functional circuit 101 . For example, due to circuit degradation, the frequencies of the plurality of oscillating signals SC[0]-SC[4] become slower and slower, so that the new count value becomes smaller. If the count value is smaller than the corresponding default value, it means that the performance of the functional circuit 101 is degraded. In some embodiments, the processing circuit may compare the count value with a threshold value and issue a warning message when the count value is less than the threshold value. This warning message can be used to inform the user or other correction circuit functional circuit 101 that the performance of the circuit 101 is too low for subsequent replacement or correction. In some embodiments, the processing circuit described above may be implemented by a processor circuit. For example, the above multiple operations can be implemented by the processor circuit executing software, but the present application is not limited thereto.

在一些相关技术中,为了节省功率消耗,在功能性电路执行一般操作时振荡器电路会被关闭。如此一来,振荡器电路的衰退程度将不同于功能性电路的衰退程度,而无法反映出准确的检测结果。或者,在一些相关技术中,振荡器电路被设置为持续切换。若振荡器电路被过度切换,振荡器电路的衰退程度可能大于功能性电路的衰退程度,而无法反映出准确的检测结果。In some related art, in order to save power consumption, the oscillator circuit is turned off while the functional circuit is performing normal operation. As a result, the degradation of the oscillator circuit will be different from the degradation of the functional circuit, and will not reflect the accurate detection results. Alternatively, in some related art, the oscillator circuit is arranged to switch continuously. If the oscillator circuit is over-switched, the degree of degradation of the oscillator circuit may be greater than that of the functional circuit, thus failing to reflect accurate detection results.

相较于上述相关技术,在本案一些实施例中,当模式信号AG具有第一逻辑值时,多个振荡器电路120[0]~120[4]可随着来自功能性电路101的切换信号TG进行切换。如此,可确保多个振荡器电路120[0]~120[4]的衰退程度接近于功能性电路101的衰退程度。再者,如先前所述,输出电路130在模式信号AG具有第一逻辑值时可以被关闭,以确保输出电路130不会被多个振荡器电路120[0]~120[4]切换,以提高检测准确度。Compared with the above-mentioned related art, in some embodiments of the present application, when the mode signal AG has the first logic value, the plurality of oscillator circuits 120 [ 0 ] ˜ 120 [ 4 ] can follow the switching signal from the functional circuit 101 TG to switch. In this way, it can be ensured that the degradation degree of the plurality of oscillator circuits 120 [ 0 ] to 120 [ 4 ] is close to that of the functional circuit 101 . Furthermore, as previously described, the output circuit 130 can be turned off when the mode signal AG has the first logic value to ensure that the output circuit 130 is not switched by the plurality of oscillator circuits 120[0]˜120[4] to Improve detection accuracy.

图2为根据本案一些实施例绘制图1的多个振荡器电路120[0]~120[4]以及输出电路130的示意图。多个振荡器电路120[0]~120[4]中的每一者具有相同电路结构。以图2的振荡器电路120[0]的详细结构为例,振荡器电路120[0]包括逻辑门电路222、多工器电路224、逻辑门电路226以及多个数字电路228。逻辑门电路222根据模式信号AG以及切换信号TG产生信号S1。当模式信号AG具有第一逻辑值时,逻辑门电路222将切换信号TG输出为信号S1。或者,当模式信号AG具有第二逻辑值时,逻辑门电路222输出具有固定电平(例如为低电平)的信号S1。于此例中,逻辑门电路222可为(但不限于)与门电路。多工器电路224用以根据模式信号AG将信号S1或信号S2输出为信号S3。例如,若模式信号AG具有第一逻辑值,多工器电路224将信号S1输出为信号S3。或者,若模式信号AG具有第二逻辑值,多工器电路224将信号S2输出为信号S3。FIG. 2 is a schematic diagram illustrating a plurality of oscillator circuits 120 [ 0 ] to 120 [ 4 ] and the output circuit 130 of FIG. 1 according to some embodiments of the present application. Each of the plurality of oscillator circuits 120[0]˜120[4] has the same circuit structure. Taking the detailed structure of the oscillator circuit 120 [ 0 ] of FIG. 2 as an example, the oscillator circuit 120 [ 0 ] includes a logic gate circuit 222 , a multiplexer circuit 224 , a logic gate circuit 226 and a plurality of digital circuits 228 . The logic gate circuit 222 generates the signal S1 according to the mode signal AG and the switching signal TG. When the mode signal AG has the first logic value, the logic gate circuit 222 outputs the switching signal TG as the signal S1. Alternatively, when the mode signal AG has the second logic value, the logic gate circuit 222 outputs the signal S1 having a fixed level (eg, a low level). In this example, the logic gate 222 can be, but is not limited to, an AND gate. The multiplexer circuit 224 is used for outputting the signal S1 or the signal S2 as the signal S3 according to the mode signal AG. For example, if the mode signal AG has the first logic value, the multiplexer circuit 224 outputs the signal S1 as the signal S3. Alternatively, if the mode signal AG has the second logic value, the multiplexer circuit 224 outputs the signal S2 as the signal S3.

逻辑门电路226用以根据对应的使能信号EN[0]以及信号S3产生对应的振荡信号SC[0]。例如,逻辑门电路226可为(但不限于)或非(NOR)门电路。多个数字电路228用以输出信号S2并接收信号S3。详细而言,多个数字电路228经由多工器电路224与逻辑门电路226串联耦接,以操作为环形振荡器电路。详细而言,当使能信号EN[0]具有第二逻辑值时,上述的环形振荡器电路可基于信号S2产生振荡信号SC[0]。例如,当使能信号EN[0]具有第二逻辑值时,环形振荡器电路可操作为自由运行的振荡器电路,其可基于信号S2开始切换而产生振荡信号SC[0]。或者,当使能信号EN[0]具有第一逻辑值时,逻辑门电路226的输出端将具有固定电平(例如为低电平)。等效地,环形振荡器电路响应于具有第一逻辑值的使能信号EN[0]停止产生振荡信号SC[0]。如此,可避免输出电路130被多个振荡器电路120[0]~120[4]切换,以减少输出电路130的衰退。The logic gate circuit 226 is used for generating the corresponding oscillation signal SC[0] according to the corresponding enable signal EN[0] and the signal S3. For example, logic gate 226 may be, but is not limited to, a NOR (NOR) gate. A plurality of digital circuits 228 are used to output the signal S2 and receive the signal S3. In detail, a plurality of digital circuits 228 are coupled in series with the logic gate circuit 226 via the multiplexer circuit 224 to operate as a ring oscillator circuit. In detail, when the enable signal EN[0] has the second logic value, the above-mentioned ring oscillator circuit can generate the oscillation signal SC[0] based on the signal S2. For example, when the enable signal EN[0] has the second logic value, the ring oscillator circuit may operate as a free-running oscillator circuit that may start switching based on the signal S2 to generate the oscillating signal SC[0]. Alternatively, when the enable signal EN[0] has the first logic value, the output terminal of the logic gate circuit 226 will have a fixed level (eg, a low level). Equivalently, the ring oscillator circuit stops generating the oscillation signal SC[0] in response to the enable signal EN[0] having the first logic value. In this way, the output circuit 130 can be prevented from being switched by the plurality of oscillator circuits 120 [ 0 ] to 120 [ 4 ], so as to reduce the degradation of the output circuit 130 .

如先前所述,多个振荡器电路120[0]~120[4]中的每一者具有相同电路结构。例如,在振荡器电路120[1]中,逻辑门电路226接收使能信号EN[1]并产生对应的振荡信号SC[1]。依此类推,应可理解多个振荡器电路120[0]~120[4]中的每一者的设置方式。As previously described, each of the plurality of oscillator circuits 120[0]-120[4] has the same circuit structure. For example, in the oscillator circuit 120[1], the logic gate circuit 226 receives the enable signal EN[1] and generates the corresponding oscillation signal SC[1]. By analogy, the arrangement of each of the plurality of oscillator circuits 120[0]-120[4] should be understood.

在图2的例子中,多个数字电路228为反相器电路,但本案并不以此为限。在一些实施例中,多个数字电路228的设置方式可基于功能性电路101而定。例如,若功能性电路101包括与门电路、或门电路、反相器电路以及与非门电路,多个数字电路228可使用相同的与门电路、或门电路、反相器电路以及与非门电路的组合实施。如此一来,可以得到更准确的可靠度检测结果。上述关于功能性电路101中所包括的电路种类用于示例,且本案并不以此为限。In the example of FIG. 2 , the plurality of digital circuits 228 are inverter circuits, but the present application is not limited to this. In some embodiments, the arrangement of the plurality of digital circuits 228 may be based on the functional circuit 101 . For example, if functional circuit 101 includes AND gates, OR gates, inverter circuits, and NAND gates, multiple digital circuits 228 may use the same AND gates, OR gates, inverter circuits, and NAND gates Combination implementation of gate circuits. In this way, more accurate reliability detection results can be obtained. The types of circuits included in the functional circuit 101 described above are used as examples, and the present application is not limited thereto.

在一些实施例中,信号S2经多个数字电路228以及逻辑门电路226反相处理的次数可设定为奇数,以确保多个振荡器电路120[0]~120[4]能够正确起振。换言之,在一些实施例中,在每一个振荡器电路120[0]~120[4]中,多个数字电路228以及逻辑门电路226的个数可为奇数。以图2的例子而言,振荡器电路120[0]包括4个数字电路228以及1个逻辑门电路226。如此,信号S2可经过5次的反相处理,以产生振荡信号SC[0]。或者,在另一些实施例中,振荡器电路120[0]包括50个数字电路228以及1个逻辑门电路226。如此,信号S2可经过51次的反相处理,以产生振荡信号SC[0]。上述关于多个数字电路228以及逻辑门电路226的数量用于示例,且本案并不以此为限。In some embodiments, the number of times the signal S2 is inverted by the plurality of digital circuits 228 and the logic gate circuit 226 may be set to an odd number to ensure that the plurality of oscillator circuits 120[0]˜120[4] can start up correctly . In other words, in some embodiments, in each of the oscillator circuits 120[0]˜120[4], the number of the plurality of digital circuits 228 and the logic gate circuits 226 may be an odd number. In the example of FIG. 2 , the oscillator circuit 120 [ 0 ] includes four digital circuits 228 and one logic gate circuit 226 . In this way, the signal S2 can be inverted for five times to generate the oscillating signal SC[0]. Alternatively, in other embodiments, the oscillator circuit 120 [ 0 ] includes 50 digital circuits 228 and one logic gate circuit 226 . In this way, the signal S2 can be inverted for 51 times to generate the oscillating signal SC[0]. The above-mentioned numbers of the plurality of digital circuits 228 and the logic gate circuits 226 are used as examples, and the present application is not limited thereto.

输出电路130包括逻辑门电路232以及逻辑门电路234。逻辑门电路232耦接至多个振荡器电路120[0]~120[4]以接收多个振荡信号SC[0]~SC[4]。逻辑门电路232用以根据多个振荡信号SC[0]~SC[4]产生信号S4。如先前所述,当多个使能信号EN[0]~EN[4]中的对应使能信号具有第二逻辑值时,多个使能信号EN[0]~EN[4]中的剩余使能信号皆具有第一逻辑值。于此条件下,逻辑门电路232可将多个振荡信号SC[0]~SC[4]中的对应振荡信号输出为信号S4。The output circuit 130 includes a logic gate circuit 232 and a logic gate circuit 234 . The logic gate circuit 232 is coupled to the plurality of oscillator circuits 120[0]-120[4] to receive the plurality of oscillation signals SC[0]-SC[4]. The logic gate circuit 232 is used for generating the signal S4 according to the plurality of oscillating signals SC[0]-SC[4]. As previously described, when the corresponding enable signal of the plurality of enable signals EN[0]˜EN[4] has the second logic value, the remaining ones of the plurality of enable signals EN[0]˜EN[4] The enable signals all have the first logic value. Under this condition, the logic gate circuit 232 can output the corresponding oscillating signal among the plurality of oscillating signals SC[0]-SC[4] as the signal S4.

例如,当使能信号EN[0]具有第二逻辑值时,剩余的使能信号EN[1]~EN[4]皆具有第一逻辑值。于此条件下,振荡器电路120[0]基于信号S2开始切换而产生振荡信号SC[0],且剩余振荡器电路120[1]~120[4]输出具有固定电平(例如为低电平)的多个振荡信号SC[1]~SC[4]。因此,逻辑门电路232可将振荡信号SC[0]输出为信号S4。于此例中,逻辑门电路232可为(但不限于)或门电路。For example, when the enable signal EN[0] has the second logic value, the remaining enable signals EN[1]-EN[4] all have the first logic value. Under this condition, the oscillator circuit 120[0] starts to switch based on the signal S2 to generate the oscillating signal SC[0], and the outputs of the remaining oscillator circuits 120[1]-120[4] have a fixed level (eg, a low power level). A plurality of oscillating signals SC[1] to SC[4]. Therefore, the logic gate circuit 232 can output the oscillation signal SC[0] as the signal S4. In this example, the logic gate 232 may be, but is not limited to, an OR gate.

逻辑门电路234耦接至逻辑门电路232以接收信号S4。在模式信号AG具有第二逻辑值时,逻辑门电路234根据信号S4输出检测信号SD。在模式信号AG具有第一逻辑值时,逻辑门电路234停止输出检测信号SD。例如,逻辑门电路234可为(但不限于)或非门电路。当模式信号AG具有第一逻辑值时,逻辑门电路234的输出端将被固定于低电平。等效地,逻辑门电路234响应于具有第一逻辑值的模式信号AG停止输出检测信号SD。如此,输出电路130可不被多个振荡器电路120[0]~120[4]切换。The logic gate 234 is coupled to the logic gate 232 to receive the signal S4. When the mode signal AG has the second logic value, the logic gate circuit 234 outputs the detection signal SD according to the signal S4. When the mode signal AG has the first logic value, the logic gate circuit 234 stops outputting the detection signal SD. For example, logic gate 234 may be, but is not limited to, a NOR gate. When the mode signal AG has the first logic value, the output terminal of the logic gate circuit 234 will be fixed at a low level. Equivalently, the logic gate circuit 234 stops outputting the detection signal SD in response to the mode signal AG having the first logic value. As such, the output circuit 130 may not be switched by the plurality of oscillator circuits 120[0]˜120[4].

图3为根据本案一些实施例绘制图1的控制电路110的示意图。在一些实施例中,控制电路110包括编码器电路310以及多个逻辑门电路320[0]~320[4]。编码器电路310用以根据选择信号SEL产生多个控制信号C[0]~C[4],其中选择信号SEL用以选择多个振荡电路120[0]~120[4]中的一者来检测功能性电路101的可靠度。多个逻辑门电路320[0]~320[4]分别接收多个控制信号C[0]~C[4],并接收模式信号AG。多个逻辑门电路320[0]~320[4]用以根据多个控制信号C[0]~C[4]以及模式信号AG产生多个使能信号EN[0]~EN[4]。例如,逻辑门电路320[0]根据控制信号C[0]以及模式信号AG产生使能信号EN[0]。依此类推,应可理解其他逻辑门电路320[1]~320[4]、多个控制信号C[1]~C[4]以及多个使能信号EN[1]~EN[4]之间的对应关系。FIG. 3 is a schematic diagram illustrating the control circuit 110 of FIG. 1 according to some embodiments of the present application. In some embodiments, the control circuit 110 includes an encoder circuit 310 and a plurality of logic gate circuits 320[0]˜320[4]. The encoder circuit 310 is used for generating a plurality of control signals C[0]-C[4] according to the selection signal SEL, wherein the selection signal SEL is used for selecting one of the plurality of oscillator circuits 120[0]-120[4] to The reliability of the functional circuit 101 is checked. The plurality of logic gate circuits 320[0] to 320[4] respectively receive the plurality of control signals C[0] to C[4] and receive the mode signal AG. The plurality of logic gate circuits 320[0]-320[4] are used to generate a plurality of enable signals EN[0]-EN[4] according to the plurality of control signals C[0]-C[4] and the mode signal AG. For example, the logic gate circuit 320[0] generates the enable signal EN[0] according to the control signal C[0] and the mode signal AG. By analogy, it should be understood that other logic gate circuits 320[1]-320[4], multiple control signals C[1]-C[4] and multiple enable signals EN[1]-EN[4] Correspondence between.

当模式信号AG具有第一逻辑值时,多个逻辑门电路320[0]~320[4]输出具有第二逻辑值的多个使能信号EN[0]~EN[4]。当模式信号AG具有第二逻辑值时,多个逻辑门电路320[0]~320[4]可分别将多个控制信号C[0]~C[4]输出为多个使能信号EN[0]~EN[4]。例如,多个逻辑门电路320[0]~320[4]中的每一者可为具有反相输入端的与门电路,且该反相输入端用以接收模式信号AG。When the mode signal AG has the first logic value, the plurality of logic gate circuits 320[0]˜320[4] output the plurality of enable signals EN[0]˜EN[4] having the second logic value. When the mode signal AG has the second logic value, the multiple logic gate circuits 320[0]˜320[4] can respectively output multiple control signals C[0]˜C[4] as multiple enable signals EN[ 0] to EN[4]. For example, each of the plurality of logic gates 320[0]-320[4] may be an AND gate having an inverting input to receive the mode signal AG.

应当理解,图1、图2以及图3的电路数量以及相关设置方式用于示例,且本案并不以此为限。例如,在其他的实施例中,可靠度检测装置100可包括不同数量的振荡器电路。It should be understood that the number of circuits and related arrangements in FIG. 1 , FIG. 2 and FIG. 3 are used as examples, and the present application is not limited thereto. For example, in other embodiments, the reliability detection apparatus 100 may include different numbers of oscillator circuits.

图4为根据本案一些实施例绘制一种可靠度检测方法400的流程图。在一些实施例中,可靠度检测方法400可由(但不限于)图1的可靠度检测装置100执行。FIG. 4 is a flowchart of a reliability detection method 400 according to some embodiments of the present application. In some embodiments, the reliability detection method 400 may be performed by (but not limited to) the reliability detection apparatus 100 of FIG. 1 .

在操作S410中,根据模式信号(例如为图1的模式信号AG)产生多个使能信号(例如为图1的多个使能信号EN[0]~EN[4])。在操作S420中,在模式信号具有第一逻辑值(例如为逻辑值1)时根据切换信号(例如为图1的切换信号TG)产生多个振荡信号(例如为图1的多个振荡信号SC[0]~SC[4]),其中切换信号与功能性电路(例如为图1的功能性电路101)相关联。在操作S430中,在模式信号具有第二逻辑值时根据该多个使能信号中的对应使能信号产生该多个振荡信号中的对应振荡信号。在操作S440中,在模式信号具有第二逻辑值时根据该多个振荡信号输出检测信号(例如为图1的检测信号SD),其中检测信号用以反映功能性电路的可靠度。In operation S410, multiple enable signals (eg, multiple enable signals EN[0]˜EN[4] of FIG. 1 ) are generated according to the mode signal (eg, the mode signal AG of FIG. 1 ). In operation S420 , when the mode signal has a first logic value (eg, logic value 1), a plurality of oscillating signals (eg, multiple oscillating signals SC of FIG. 1 ) are generated according to a switching signal (eg, switching signal TG of FIG. 1 ) [0] to SC[4]), wherein the switching signal is associated with a functional circuit (eg, the functional circuit 101 of FIG. 1 ). In operation S430, a corresponding oscillating signal of the plurality of oscillating signals is generated according to a corresponding enabling signal of the plurality of enabling signals when the mode signal has the second logic value. In operation S440 , when the mode signal has the second logic value, a detection signal (eg, the detection signal SD in FIG. 1 ) is output according to the plurality of oscillation signals, wherein the detection signal is used to reflect the reliability of the functional circuit.

上述多个操作的说明可参照前述各个实施例,故不重复赘述。上述可靠度检测方法400的多个操作仅为示例,并非限定需依照此示例中的顺序执行。在不违背本案的各实施例的操作方式与范围下,在可靠度检测方法400下的各种操作当可适当地增加、替换、省略或以不同顺序执行(例如可以是同时执行或是部分同时执行)。For the description of the above-mentioned operations, reference may be made to the foregoing embodiments, and thus will not be repeated. The operations of the reliability detection method 400 described above are only examples, and are not limited to be performed in the order in this example. Without departing from the operation mode and scope of the various embodiments of the present application, various operations under the reliability detection method 400 may be appropriately added, replaced, omitted or performed in a different order (for example, they may be performed simultaneously or partially simultaneously). implement).

综上所述,本案一些实施例中的可靠度检测装置与可靠度检测方法可以让振荡器电路的衰退相近于功能性电路的衰退,并降低其他控制电路的衰退。如此一来,可得到更准确的可靠度检测结果。To sum up, the reliability detection device and reliability detection method in some embodiments of the present application can make the degradation of the oscillator circuit similar to the degradation of the functional circuit, and reduce the degradation of other control circuits. In this way, more accurate reliability detection results can be obtained.

虽然本案的实施例如上所述,然而这些实施例并非用来限定本案,本技术领域具有通常知识者可依据本案的明示或隐含的内容对本案的技术特征施以变化,凡此种种变化均可能属于本案所寻求的专利保护范畴,换言之,本案之专利保护范围须视本说明书的申请专利范围所界定者为准。Although the embodiments of the present case are as described above, these embodiments are not intended to limit the present case. Those with ordinary knowledge in the technical field can make changes to the technical features of the present case according to the explicit or implicit content of the present case. It may belong to the scope of patent protection sought in this case. In other words, the scope of patent protection in this case must be determined by the scope of the patent application in this specification.

附图标记说明:Description of reference numbers:

100:可靠度检测装置100: Reliability testing device

101:功能性电路101: Functional Circuits

110:控制电路110: Control circuit

120[0]~120[4]:振荡器电路120[0]~120[4]: Oscillator circuit

130:输出电路130: Output circuit

222、226、228、232、234:逻辑门电路222, 226, 228, 232, 234: logic gate circuits

224:多工器电路224: Multiplexer circuit

310:编码器电路310: Encoder circuit

320[0]~320[4]:与门电路320[0]~320[4]: AND gate circuit

400:可靠度方法400: Reliability Methods

AG:模式信号AG: mode signal

C[0]~C[4]:控制信号C[0]~C[4]: Control signal

EN[0]~EN[4]:使能信号EN[0]~EN[4]: Enable signal

S1、S2、S3、S4:信号S1, S2, S3, S4: Signals

S410、S420、S430、S440:操作S410, S420, S430, S440: Operation

SC[0]~SC[4]:振荡信号SC[0]~SC[4]: Oscillation signal

SD:检测信号SD: Heartbeat

SEL:选择信号SEL: select signal

TG:切换信号TG: toggle signal

Claims (10)

1. A reliability detection apparatus comprising:
the control circuit is used for generating a plurality of enable signals according to the mode signal;
a plurality of oscillator circuits configured to output a plurality of oscillation signals, wherein each of the plurality of oscillator circuits is configured to generate a corresponding oscillation signal of the plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, and generate the corresponding oscillation signal according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value, and the switching signal is associated with a functional circuit; and
an output circuit for outputting a detection signal according to the plurality of oscillation signals when the mode signal has the second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.
2. The reliability detection apparatus of claim 1, wherein each of the plurality of oscillator circuits is configured to operate as a free-running oscillator circuit according to the corresponding enable signal to generate the corresponding oscillation signal when the mode signal has the second logic value.
3. The reliability detection apparatus of claim 1, wherein each of the plurality of oscillator circuits does not generate the corresponding oscillation signal in response to the switching signal when the mode signal has the second logic value.
4. The reliability detection apparatus of claim 1, wherein the output circuit is further configured to stop outputting the detection signal when the mode signal has the first logic value.
5. The reliability detection apparatus of claim 1, wherein each of the plurality of oscillator circuits comprises:
a first logic gate circuit for generating a first signal according to the mode signal and the switching signal;
a multiplexer circuit for outputting the first signal or the second signal as a third signal according to the mode signal;
a second logic gate circuit for generating the corresponding oscillation signal according to the corresponding enable signal and the third signal; and
a plurality of digital circuits for outputting the second signal and receiving the third signal, wherein the plurality of digital circuits are coupled in series with the second logic gate circuit via the multiplexer circuit to operate as a ring oscillator circuit.
6. The reliability detection apparatus of claim 5, wherein the ring oscillator circuit generates the corresponding oscillation signal based on the second signal when the corresponding enable signal has the second logic value.
7. The reliability detection apparatus according to claim 1, wherein the control circuit comprises:
the encoder circuit is used for generating a plurality of control signals according to the selection signal; and
and a plurality of logic gate circuits for generating the plurality of enable signals according to the plurality of control signals and the mode signal, wherein the plurality of enable signals all have the second logic value when the mode signal has the first logic value.
8. The reliability detection apparatus of claim 7, wherein each of the plurality of logic gate circuits is an AND gate circuit having an inverting input terminal for receiving the mode signal.
9. The reliability detection apparatus according to claim 1, wherein the output circuit includes:
a first logic gate circuit for generating signals according to the oscillation signals; and
and a second logic gate circuit for outputting the detection signal according to the mode signal when the mode signal has the second logic value, and stopping outputting the detection signal when the mode signal has the first logic value.
10. A reliability detection method, comprising:
generating a plurality of enable signals according to the mode signal;
generating a plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, wherein the switching signal is associated with a functional circuit;
generating a corresponding oscillation signal of the plurality of oscillation signals according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value; and
outputting a detection signal according to the plurality of oscillation signals when the mode signal has the second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.
CN202110166616.6A 2021-02-04 2021-02-04 Reliability detection device and reliability detection method Active CN114859207B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6157267A (en) * 1998-01-20 2000-12-05 Fujitsu Limited Variable frequency multiple loop ring oscillator
US20050134394A1 (en) * 2003-12-23 2005-06-23 Liu Jonathan H. On-chip transistor degradation monitoring
JP2006217455A (en) * 2005-02-07 2006-08-17 Kawasaki Microelectronics Kk Ring oscillator circuit
TW201541103A (en) * 2014-04-18 2015-11-01 Global Unichip Corp Aging detection circuit and method thereof
JP2019075782A (en) * 2017-10-13 2019-05-16 三星電子株式会社Samsung Electronics Co.,Ltd. Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6157267A (en) * 1998-01-20 2000-12-05 Fujitsu Limited Variable frequency multiple loop ring oscillator
US20050134394A1 (en) * 2003-12-23 2005-06-23 Liu Jonathan H. On-chip transistor degradation monitoring
JP2006217455A (en) * 2005-02-07 2006-08-17 Kawasaki Microelectronics Kk Ring oscillator circuit
TW201541103A (en) * 2014-04-18 2015-11-01 Global Unichip Corp Aging detection circuit and method thereof
JP2019075782A (en) * 2017-10-13 2019-05-16 三星電子株式会社Samsung Electronics Co.,Ltd. Semiconductor device

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