CN114859207A - Reliability detection device and reliability detection method - Google Patents

Abstract

The reliability detection apparatus includes a control circuit, a plurality of oscillator circuits, and an output circuit. The control circuit is used for generating a plurality of enable signals according to the mode signal. The oscillator circuits are used for outputting oscillation signals. Each of the oscillator circuits is configured to generate a corresponding oscillation signal of the plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, and generate a corresponding oscillation signal according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value. The switching signal is associated with the functional circuit. The output circuit is used for outputting a detection signal according to the oscillation signals when the mode signal has a second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.

Description

Reliability detection device and reliability detection method

technical field

This case is about a reliability detection device of a circuit, especially a reliability detection device and a reliability detection method with an oscillator circuit.

Background technique

Integrated circuits may degrade due to some non-ideal factors as the run time becomes longer. For example, negative-bias temperature instability can gradually increase the threshold voltage of a P-type transistor. If the threshold voltage of the P-type transistor gradually increases, it may cause errors in the original operation of the integrated circuit, or reduce the performance of the integrated circuit. In some related art, an oscillator circuit can be used to detect the performance of the integrated circuit to confirm whether the reliability of the components in the integrated circuit is within a normal range. However, in the above technique, the oscillator circuit may be turned off due to the power saving mechanism or set to over-switch, resulting in inaccurate detection results.

SUMMARY OF THE INVENTION

In some embodiments, the reliability detection apparatus includes a control circuit, a plurality of oscillator circuits, and an output circuit. The control circuit is used for generating a plurality of enable signals according to the mode signal. A plurality of oscillator circuits are used for outputting a plurality of oscillating signals. Each of the plurality of oscillator circuits is configured to generate a corresponding oscillating signal of the plurality of oscillating signals according to a switching signal when the mode signal has a first logic value, and according to a switching signal when the mode signal has a second logic value A corresponding enable signal among the plurality of enable signals generates the corresponding oscillation signal. The switching signal is associated with a functional circuit. The output circuit is used for outputting a detection signal according to the plurality of oscillating signals when the mode signal has the second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.

In some embodiments, the reliability detection method includes the following operations: generating a plurality of enable signals according to a mode signal; generating a plurality of oscillating signals according to a switching signal when the mode signal has a first logic value, wherein the switching signal is related to the functionality a circuit is associated; when the mode signal has a second logic value, a corresponding oscillating signal of the plurality of oscillating signals is generated according to a corresponding enable signal of the plurality of enable signals; and when the mode signal has the second logic value and outputting a detection signal according to the plurality of oscillating signals, wherein the detection signal is used to reflect the reliability of the functional circuit.

With regard to the features, implementations and effects of this case, a preferred embodiment is now described in detail as follows in conjunction with the drawings.

Description of drawings

FIG. 1 is a schematic diagram of drawing a reliability detection device according to some embodiments of the present application;

FIG. 2 is a schematic diagram illustrating a plurality of oscillator circuits and output circuits of FIG. 1 according to some embodiments of the present application;

FIG. 3 is a schematic diagram illustrating the control circuit of FIG. 1 according to some embodiments of the present invention; and

FIG. 4 is a flowchart illustrating a reliability detection method according to some embodiments of the present application.

Detailed ways

All terms used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, the use of any of the words discussed herein in the content of this case is only an example, and should not limit the scope and meaning of this case. Likewise, the present application is not limited to the various embodiments shown in this specification.

As used herein, "coupling" or "connection" may refer to two or more components in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or two or more components in physical or electrical contact with each other. Multiple components interact or act on each other. As used herein, the term "circuitry" can be a single system formed by at least one circuit, and the term "circuit" can be connected in a manner by at least one transistor and/or at least one active and passive component A device for processing signals.

As used herein, the term "and/or" includes any combination of one or more of the associated listed items. In this document, the terms first, second and third are used to describe and identify each component. Therefore, the first component may also be referred to as the second component herein without departing from the original intent of the present case. For ease of understanding, similar components in the various figures will be designated by the same reference numerals.

FIG. 1 is a schematic diagram illustrating a reliability detection apparatus 100 according to some embodiments of the present application. In some embodiments, the functional circuit 101 may be, but is not limited to, a digital signal processing circuit, an application specific integrated circuit, or the like. In practical applications, the functional circuit 101 may degrade due to the prolonged operation time. In some embodiments, the reliability detection device 100 can be integrated with the functional circuit 101 into a single system, and can be used to detect the aging degree of the functional circuit 101 .

The reliability detection device 100 includes a control circuit 110 , a plurality of oscillator circuits 120 [ 0 ] to 120 [ 4 ], and an output circuit 130 . The control circuit 110 is used for generating a plurality of enable signals EN[0]˜EN[4] according to the mode signal AG. For example, when the mode signal AG has a first logic value (eg, logic value 1), all enable signals EN[0]˜EN[4] have a second logic value (eg, logic value 0), wherein the first logic value The value is the opposite of the second logical value (eg, in the case where the logical value is either 0 or 1). Alternatively, when the mode signal AG has the second logic value, one of the enable signals EN[0]˜EN[4] may have the first logic value. However, the combination of generating a plurality of enable signals EN[0]˜EN[4] according to the mode signal AG is not limited to this.

The plurality of oscillator circuits 120[0]-120[4] are used for outputting a plurality of oscillation signals SC[0]-SC[4]. When the mode signal AG has a first logic value (eg, logic value 1), each of the plurality of oscillator circuits 120[0]˜120[4] is used to generate a plurality of oscillating signals SC[ according to the switching signal TG 0] to the corresponding oscillation signal in SC[4]. In some embodiments, switching signal TG is associated with functional circuit 101 . For example, the switching signal TG may be an output signal from the functional circuit, or may be an internal signal of the functional circuit 101, or a signal generated based on a signal from the functional circuit 101. In some embodiments, the switching signal TG may be used to reflect the average switching rate of the functional circuit 101 . Through the above operations, when the mode signal AG has the first logic value, the plurality of oscillator circuits 120[0]˜120[4] can be switched together with the functional circuit 101 . In this way, the degradation degrees of the plurality of oscillator circuits 120[0]-120[4] can be similar to the degradation degrees of the functional circuit 101, so as to generate more accurate detection results.

Alternatively, when the mode signal AG has the second logic value (eg, logic value 0), each of the plurality of oscillator circuits 120[0]˜120[4] is used for the plurality of enable signals EN[0 The corresponding enable signals in ]˜EN[4] generate corresponding oscillating signals in the plurality of oscillating signals SC[0]˜SC[4]. In other words, when the mode signal AG has the second logic value, the respective oscillator circuits 120[0]˜120[4] do not generate the corresponding oscillation signal in response to the switching signal TG. Through the above operations, when the mode signal AG has the second logic value, each of the plurality of oscillator circuits 120[0]˜120[4] may operate free running according to the corresponding enable signal Oscillator circuit to generate the corresponding oscillating signal. Under this condition, a plurality of oscillating signals SC[0]-SC[4] can be used to reflect the degradation degree of the functional circuit 101.

The output circuit 130 is used for outputting the detection signal SD according to the plurality of oscillation signals SC[0]-SC[4] when the mode signal AG has the second logic value. In some embodiments, the detection signal SD can be used to reflect the reliability of the functional circuit 101 . In some embodiments, when the mode signal AG has the first logic value, the output circuit 130 stops outputting the detection signal SD. In other words, the output circuit 130 may stop switching when the mode signal AG has the first logic value. In this way, the power consumption can be reduced and the degradation of the output circuit 130 can be avoided, so as to improve the detection accuracy.

In some embodiments, the reliability detection apparatus 100 may further include a processing circuit (not shown). When the reliability detection apparatus 100 is turned on for the first time, the mode signal AG is set to have the second logic value. In response to the mode signal AG, the plurality of oscillator circuits 120[0]-120[4] may sequentially generate a plurality of oscillation signals SC[0]-120[4] in response to the plurality of enable signals EN[0]-EN[4] SC[4]. For example, when the enable signal EN[0] has the second logic value, the remaining enable signals EN[1]˜EN[4] have the first logic value. Under this condition, the oscillator circuit 120[0] can generate the corresponding oscillation signal SC[0], and the oscillator circuits 120[1]-120[4] do not generate the oscillation signals SC[1]-SC [4]. The output circuit 130 may output the corresponding detection signal SD based on the oscillation signal SC[0]. Then, the processing circuit can count according to the detection signal SD to generate a default value corresponding to the oscillator circuit 120[0], and store the default value in a register circuit (not shown). By analogy, when the reliability detection apparatus 100 is powered on for the first time, the processing circuit can store a plurality of default values corresponding to the plurality of oscillator circuits 120[0]-120[4] respectively.

In subsequent detection operations, the processing circuit can generate a new count value according to the detection signal SD, and compare the count value with the corresponding default value to confirm the reliability of the functional circuit 101 . For example, due to circuit degradation, the frequencies of the plurality of oscillating signals SC[0]-SC[4] become slower and slower, so that the new count value becomes smaller. If the count value is smaller than the corresponding default value, it means that the performance of the functional circuit 101 is degraded. In some embodiments, the processing circuit may compare the count value with a threshold value and issue a warning message when the count value is less than the threshold value. This warning message can be used to inform the user or other correction circuit functional circuit 101 that the performance of the circuit 101 is too low for subsequent replacement or correction. In some embodiments, the processing circuit described above may be implemented by a processor circuit. For example, the above multiple operations can be implemented by the processor circuit executing software, but the present application is not limited thereto.

In some related art, in order to save power consumption, the oscillator circuit is turned off while the functional circuit is performing normal operation. As a result, the degradation of the oscillator circuit will be different from the degradation of the functional circuit, and will not reflect the accurate detection results. Alternatively, in some related art, the oscillator circuit is arranged to switch continuously. If the oscillator circuit is over-switched, the degree of degradation of the oscillator circuit may be greater than that of the functional circuit, thus failing to reflect accurate detection results.

Compared with the above-mentioned related art, in some embodiments of the present application, when the mode signal AG has the first logic value, the plurality of oscillator circuits 120 [ 0 ] ˜ 120 [ 4 ] can follow the switching signal from the functional circuit 101 TG to switch. In this way, it can be ensured that the degradation degree of the plurality of oscillator circuits 120 [ 0 ] to 120 [ 4 ] is close to that of the functional circuit 101 . Furthermore, as previously described, the output circuit 130 can be turned off when the mode signal AG has the first logic value to ensure that the output circuit 130 is not switched by the plurality of oscillator circuits 120[0]˜120[4] to Improve detection accuracy.

FIG. 2 is a schematic diagram illustrating a plurality of oscillator circuits 120 [ 0 ] to 120 [ 4 ] and the output circuit 130 of FIG. 1 according to some embodiments of the present application. Each of the plurality of oscillator circuits 120[0]˜120[4] has the same circuit structure. Taking the detailed structure of the oscillator circuit 120 [ 0 ] of FIG. 2 as an example, the oscillator circuit 120 [ 0 ] includes a logic gate circuit 222 , a multiplexer circuit 224 , a logic gate circuit 226 and a plurality of digital circuits 228 . The logic gate circuit 222 generates the signal S1 according to the mode signal AG and the switching signal TG. When the mode signal AG has the first logic value, the logic gate circuit 222 outputs the switching signal TG as the signal S1. Alternatively, when the mode signal AG has the second logic value, the logic gate circuit 222 outputs the signal S1 having a fixed level (eg, a low level). In this example, the logic gate 222 can be, but is not limited to, an AND gate. The multiplexer circuit 224 is used for outputting the signal S1 or the signal S2 as the signal S3 according to the mode signal AG. For example, if the mode signal AG has the first logic value, the multiplexer circuit 224 outputs the signal S1 as the signal S3. Alternatively, if the mode signal AG has the second logic value, the multiplexer circuit 224 outputs the signal S2 as the signal S3.

The logic gate circuit 226 is used for generating the corresponding oscillation signal SC[0] according to the corresponding enable signal EN[0] and the signal S3. For example, logic gate 226 may be, but is not limited to, a NOR (NOR) gate. A plurality of digital circuits 228 are used to output the signal S2 and receive the signal S3. In detail, a plurality of digital circuits 228 are coupled in series with the logic gate circuit 226 via the multiplexer circuit 224 to operate as a ring oscillator circuit. In detail, when the enable signal EN[0] has the second logic value, the above-mentioned ring oscillator circuit can generate the oscillation signal SC[0] based on the signal S2. For example, when the enable signal EN[0] has the second logic value, the ring oscillator circuit may operate as a free-running oscillator circuit that may start switching based on the signal S2 to generate the oscillating signal SC[0]. Alternatively, when the enable signal EN[0] has the first logic value, the output terminal of the logic gate circuit 226 will have a fixed level (eg, a low level). Equivalently, the ring oscillator circuit stops generating the oscillation signal SC[0] in response to the enable signal EN[0] having the first logic value. In this way, the output circuit 130 can be prevented from being switched by the plurality of oscillator circuits 120 [ 0 ] to 120 [ 4 ], so as to reduce the degradation of the output circuit 130 .

As previously described, each of the plurality of oscillator circuits 120[0]-120[4] has the same circuit structure. For example, in the oscillator circuit 120[1], the logic gate circuit 226 receives the enable signal EN[1] and generates the corresponding oscillation signal SC[1]. By analogy, the arrangement of each of the plurality of oscillator circuits 120[0]-120[4] should be understood.

In the example of FIG. 2 , the plurality of digital circuits 228 are inverter circuits, but the present application is not limited to this. In some embodiments, the arrangement of the plurality of digital circuits 228 may be based on the functional circuit 101 . For example, if functional circuit 101 includes AND gates, OR gates, inverter circuits, and NAND gates, multiple digital circuits 228 may use the same AND gates, OR gates, inverter circuits, and NAND gates Combination implementation of gate circuits. In this way, more accurate reliability detection results can be obtained. The types of circuits included in the functional circuit 101 described above are used as examples, and the present application is not limited thereto.

In some embodiments, the number of times the signal S2 is inverted by the plurality of digital circuits 228 and the logic gate circuit 226 may be set to an odd number to ensure that the plurality of oscillator circuits 120[0]˜120[4] can start up correctly . In other words, in some embodiments, in each of the oscillator circuits 120[0]˜120[4], the number of the plurality of digital circuits 228 and the logic gate circuits 226 may be an odd number. In the example of FIG. 2 , the oscillator circuit 120 [ 0 ] includes four digital circuits 228 and one logic gate circuit 226 . In this way, the signal S2 can be inverted for five times to generate the oscillating signal SC[0]. Alternatively, in other embodiments, the oscillator circuit 120 [ 0 ] includes 50 digital circuits 228 and one logic gate circuit 226 . In this way, the signal S2 can be inverted for 51 times to generate the oscillating signal SC[0]. The above-mentioned numbers of the plurality of digital circuits 228 and the logic gate circuits 226 are used as examples, and the present application is not limited thereto.

The output circuit 130 includes a logic gate circuit 232 and a logic gate circuit 234 . The logic gate circuit 232 is coupled to the plurality of oscillator circuits 120[0]-120[4] to receive the plurality of oscillation signals SC[0]-SC[4]. The logic gate circuit 232 is used for generating the signal S4 according to the plurality of oscillating signals SC[0]-SC[4]. As previously described, when the corresponding enable signal of the plurality of enable signals EN[0]˜EN[4] has the second logic value, the remaining ones of the plurality of enable signals EN[0]˜EN[4] The enable signals all have the first logic value. Under this condition, the logic gate circuit 232 can output the corresponding oscillating signal among the plurality of oscillating signals SC[0]-SC[4] as the signal S4.

For example, when the enable signal EN[0] has the second logic value, the remaining enable signals EN[1]-EN[4] all have the first logic value. Under this condition, the oscillator circuit 120[0] starts to switch based on the signal S2 to generate the oscillating signal SC[0], and the outputs of the remaining oscillator circuits 120[1]-120[4] have a fixed level (eg, a low power level). A plurality of oscillating signals SC[1] to SC[4]. Therefore, the logic gate circuit 232 can output the oscillation signal SC[0] as the signal S4. In this example, the logic gate 232 may be, but is not limited to, an OR gate.

The logic gate 234 is coupled to the logic gate 232 to receive the signal S4. When the mode signal AG has the second logic value, the logic gate circuit 234 outputs the detection signal SD according to the signal S4. When the mode signal AG has the first logic value, the logic gate circuit 234 stops outputting the detection signal SD. For example, logic gate 234 may be, but is not limited to, a NOR gate. When the mode signal AG has the first logic value, the output terminal of the logic gate circuit 234 will be fixed at a low level. Equivalently, the logic gate circuit 234 stops outputting the detection signal SD in response to the mode signal AG having the first logic value. As such, the output circuit 130 may not be switched by the plurality of oscillator circuits 120[0]˜120[4].

FIG. 3 is a schematic diagram illustrating the control circuit 110 of FIG. 1 according to some embodiments of the present application. In some embodiments, the control circuit 110 includes an encoder circuit 310 and a plurality of logic gate circuits 320[0]˜320[4]. The encoder circuit 310 is used for generating a plurality of control signals C[0]-C[4] according to the selection signal SEL, wherein the selection signal SEL is used for selecting one of the plurality of oscillator circuits 120[0]-120[4] to The reliability of the functional circuit 101 is checked. The plurality of logic gate circuits 320[0] to 320[4] respectively receive the plurality of control signals C[0] to C[4] and receive the mode signal AG. The plurality of logic gate circuits 320[0]-320[4] are used to generate a plurality of enable signals EN[0]-EN[4] according to the plurality of control signals C[0]-C[4] and the mode signal AG. For example, the logic gate circuit 320[0] generates the enable signal EN[0] according to the control signal C[0] and the mode signal AG. By analogy, it should be understood that other logic gate circuits 320[1]-320[4], multiple control signals C[1]-C[4] and multiple enable signals EN[1]-EN[4] Correspondence between.

When the mode signal AG has the first logic value, the plurality of logic gate circuits 320[0]˜320[4] output the plurality of enable signals EN[0]˜EN[4] having the second logic value. When the mode signal AG has the second logic value, the multiple logic gate circuits 320[0]˜320[4] can respectively output multiple control signals C[0]˜C[4] as multiple enable signals EN[ 0] to EN[4]. For example, each of the plurality of logic gates 320[0]-320[4] may be an AND gate having an inverting input to receive the mode signal AG.

It should be understood that the number of circuits and related arrangements in FIG. 1 , FIG. 2 and FIG. 3 are used as examples, and the present application is not limited thereto. For example, in other embodiments, the reliability detection apparatus 100 may include different numbers of oscillator circuits.

FIG. 4 is a flowchart of a reliability detection method 400 according to some embodiments of the present application. In some embodiments, the reliability detection method 400 may be performed by (but not limited to) the reliability detection apparatus 100 of FIG. 1 .

In operation S410, multiple enable signals (eg, multiple enable signals EN[0]˜EN[4] of FIG. 1 ) are generated according to the mode signal (eg, the mode signal AG of FIG. 1 ). In operation S420 , when the mode signal has a first logic value (eg, logic value 1), a plurality of oscillating signals (eg, multiple oscillating signals SC of FIG. 1 ) are generated according to a switching signal (eg, switching signal TG of FIG. 1 ) [0] to SC[4]), wherein the switching signal is associated with a functional circuit (eg, the functional circuit 101 of FIG. 1 ). In operation S430, a corresponding oscillating signal of the plurality of oscillating signals is generated according to a corresponding enabling signal of the plurality of enabling signals when the mode signal has the second logic value. In operation S440 , when the mode signal has the second logic value, a detection signal (eg, the detection signal SD in FIG. 1 ) is output according to the plurality of oscillation signals, wherein the detection signal is used to reflect the reliability of the functional circuit.

For the description of the above-mentioned operations, reference may be made to the foregoing embodiments, and thus will not be repeated. The operations of the reliability detection method 400 described above are only examples, and are not limited to be performed in the order in this example. Without departing from the operation mode and scope of the various embodiments of the present application, various operations under the reliability detection method 400 may be appropriately added, replaced, omitted or performed in a different order (for example, they may be performed simultaneously or partially simultaneously). implement).

To sum up, the reliability detection device and reliability detection method in some embodiments of the present application can make the degradation of the oscillator circuit similar to the degradation of the functional circuit, and reduce the degradation of other control circuits. In this way, more accurate reliability detection results can be obtained.

Although the embodiments of the present case are as described above, these embodiments are not intended to limit the present case. Those with ordinary knowledge in the technical field can make changes to the technical features of the present case according to the explicit or implicit content of the present case. It may belong to the scope of patent protection sought in this case. In other words, the scope of patent protection in this case must be determined by the scope of the patent application in this specification.

Description of reference numbers:

100: Reliability testing device

101: Functional Circuits

110: Control circuit

120[0]～120[4]: Oscillator circuit

130: Output circuit

222, 226, 228, 232, 234: logic gate circuits

224: Multiplexer circuit

310: Encoder circuit

320[0]～320[4]: AND gate circuit

400: Reliability Methods

AG: mode signal

C[0]～C[4]: Control signal

EN[0]～EN[4]: Enable signal

S1, S2, S3, S4: Signals

S410, S420, S430, S440: Operation

SC[0]～SC[4]: Oscillation signal

SD: Heartbeat

SEL: select signal

TG: toggle signal

Claims (10)

1. A reliability detection apparatus comprising:

the control circuit is used for generating a plurality of enable signals according to the mode signal;

a plurality of oscillator circuits configured to output a plurality of oscillation signals, wherein each of the plurality of oscillator circuits is configured to generate a corresponding oscillation signal of the plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, and generate the corresponding oscillation signal according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value, and the switching signal is associated with a functional circuit; and

an output circuit for outputting a detection signal according to the plurality of oscillation signals when the mode signal has the second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.

2. The reliability detection apparatus of claim 1, wherein each of the plurality of oscillator circuits is configured to operate as a free-running oscillator circuit according to the corresponding enable signal to generate the corresponding oscillation signal when the mode signal has the second logic value.

3. The reliability detection apparatus of claim 1, wherein each of the plurality of oscillator circuits does not generate the corresponding oscillation signal in response to the switching signal when the mode signal has the second logic value.

4. The reliability detection apparatus of claim 1, wherein the output circuit is further configured to stop outputting the detection signal when the mode signal has the first logic value.

5. The reliability detection apparatus of claim 1, wherein each of the plurality of oscillator circuits comprises:

a first logic gate circuit for generating a first signal according to the mode signal and the switching signal;

a multiplexer circuit for outputting the first signal or the second signal as a third signal according to the mode signal;

a second logic gate circuit for generating the corresponding oscillation signal according to the corresponding enable signal and the third signal; and

a plurality of digital circuits for outputting the second signal and receiving the third signal, wherein the plurality of digital circuits are coupled in series with the second logic gate circuit via the multiplexer circuit to operate as a ring oscillator circuit.

6. The reliability detection apparatus of claim 5, wherein the ring oscillator circuit generates the corresponding oscillation signal based on the second signal when the corresponding enable signal has the second logic value.

7. The reliability detection apparatus according to claim 1, wherein the control circuit comprises:

the encoder circuit is used for generating a plurality of control signals according to the selection signal; and

and a plurality of logic gate circuits for generating the plurality of enable signals according to the plurality of control signals and the mode signal, wherein the plurality of enable signals all have the second logic value when the mode signal has the first logic value.

8. The reliability detection apparatus of claim 7, wherein each of the plurality of logic gate circuits is an AND gate circuit having an inverting input terminal for receiving the mode signal.

9. The reliability detection apparatus according to claim 1, wherein the output circuit includes:

a first logic gate circuit for generating signals according to the oscillation signals; and

and a second logic gate circuit for outputting the detection signal according to the mode signal when the mode signal has the second logic value, and stopping outputting the detection signal when the mode signal has the first logic value.

10. A reliability detection method, comprising:

generating a plurality of enable signals according to the mode signal;

generating a plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, wherein the switching signal is associated with a functional circuit;

generating a corresponding oscillation signal of the plurality of oscillation signals according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value; and

outputting a detection signal according to the plurality of oscillation signals when the mode signal has the second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.

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