CN114859207A

CN114859207A - Reliability detection device and reliability detection method

Info

Publication number: CN114859207A
Application number: CN202110166616.6A
Authority: CN
Inventors: 许文轩; 郭俊仪; 陈莹晏
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-02-04
Filing date: 2021-02-04
Publication date: 2022-08-05

Abstract

The reliability detection apparatus includes a control circuit, a plurality of oscillator circuits, and an output circuit. The control circuit is used for generating a plurality of enable signals according to the mode signal. The oscillator circuits are used for outputting oscillation signals. Each of the oscillator circuits is configured to generate a corresponding oscillation signal of the plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, and generate a corresponding oscillation signal according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value. The switching signal is associated with the functional circuit. The output circuit is used for outputting a detection signal according to the oscillation signals when the mode signal has a second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.

Description

Reliability detection device and reliability detection method

Technical Field

The present disclosure relates to a reliability detection device for a circuit, and more particularly, to a reliability detection device having an oscillator circuit and a reliability detection method.

Background

As the operating time becomes longer, the integrated circuit may degrade due to some non-ideal factors. For example, negative-bias temperature instability (negative-bias temperature instability) can cause the threshold voltage of a P-type transistor to become gradually higher. If the threshold voltage of the P-type transistor is gradually increased, the original operation of the integrated circuit may be faulty or the performance of the integrated circuit may be degraded. In some related art, oscillator circuits may be used to detect the performance of an integrated circuit to determine whether the reliability of components in the integrated circuit is within a normal range. However, in the above-mentioned techniques, the oscillator circuit may be turned off or set to be switched excessively, which may cause the detection result to be inaccurate.

Disclosure of Invention

In some embodiments, the reliability detection apparatus includes a control circuit, a plurality of oscillator circuits, and an output circuit. The control circuit is used for generating a plurality of enable signals according to the mode signal. The oscillator circuits are used for outputting oscillation signals. Each of the plurality of oscillator circuits is configured to generate a corresponding oscillation signal of the plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, and to generate the corresponding oscillation signal according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value. The switching signal is associated with a functional circuit. The output circuit is configured to output a detection signal according to the plurality of oscillation signals when the mode signal has the second logic value, wherein the detection signal is configured to reflect a reliability of the functional circuit.

In some embodiments, the reliability detection method includes the following operations: generating a plurality of enable signals according to the mode signal; generating a plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, wherein the switching signal is associated with a functional circuit; generating a corresponding oscillation signal of the plurality of oscillation signals according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value; and outputting a detection signal according to the plurality of oscillation signals when the mode signal has the second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.

The features, implementations and functions of the present invention will now be described in detail with reference to the drawings.

Drawings

FIG. 1 is a schematic diagram of a reliability detection apparatus according to some embodiments of the disclosure;

FIG. 2 is a schematic diagram of the multiple oscillator circuits and output circuits of FIG. 1 according to some embodiments of the disclosure;

FIG. 3 is a schematic diagram of the control circuit of FIG. 1 according to some embodiments of the disclosure; and

fig. 4 is a flow chart illustrating a reliability detection method according to some embodiments of the present disclosure.

Detailed Description

All words used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries are provided, and any use of the words discussed herein in this document is by way of illustration only and should not be construed as limiting the scope and meaning of the present disclosure. Likewise, the disclosure is not limited to the various embodiments shown in this specification.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or the two or more elements operating or acting together. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuitry" may be a device connected by at least one transistor and/or at least one active and passive component in a manner to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like are used herein to describe and distinguish between various components. Thus, a first component may also be referred to herein as a second component without departing from the spirit of the disclosure. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.

Fig. 1 is a schematic diagram illustrating a reliability detection apparatus 100 according to some embodiments of the disclosure. In some embodiments, the functional circuit 101 may be, but is not limited to, a digital signal processing circuit, an application specific integrated circuit, or the like. In practical applications, the functional circuit 101 may be degraded due to the long operation time. In some embodiments, the reliability detection apparatus 100 may be integrated with the functional circuit 101 into a single system, and may be used to detect a fading (aging) level of the functional circuit 101.

The reliability detection device 100 includes a control circuit 110, a plurality of oscillator circuits 120[0] to 120[4], and an output circuit 130. The control circuit 110 is used for generating a plurality of enable signals EN [0] EN [4] according to the mode signal AG. For example, when the mode signal AG has a first logic value (e.g., logic value 1), all of the enable signals EN [0] EN [4] have a second logic value (e.g., logic value 0), wherein the first logic value is opposite to the second logic value (e.g., in the case of logic value other than 0, i.e., 1). Alternatively, one of the enable signals EN [0] EN [4] may have a first logic value when the mode signal AG has a second logic value. However, the combination of generating the plurality of enable signals EN [0] to EN [4] according to the mode signal AG is not limited to this.

The plurality of oscillator circuits 120[0] to 120[4] output a plurality of oscillation signals SC [0] to SC [4 ]. Each of the plurality of oscillator circuits 120[0] to 120[4] is configured to generate a corresponding oscillation signal of the plurality of oscillation signals SC [0] to SC [4] according to the switching signal TG when the mode signal AG has a first logic value (e.g., logic value 1). In some embodiments, the switching signal TG is associated with the functional circuit 101. For example, the switching signal TG may be an output signal from the functional circuit, or may be an internal signal of the functional circuit 101, or a signal generated based on a signal from the functional circuit 101. In some embodiments, the switching signal TG may be used to reflect an average switching frequency (toggle rate) of the functional circuit 101. By the above operation, the plurality of oscillator circuits 120[0] to 120[4] can be switched together with the functional circuit 101 when the mode signal AG has the first logic value. Thus, the degradation of the oscillator circuits 120[0] to 120[4] can be similar to the degradation of the functional circuit 101, so as to generate a more accurate detection result.

Alternatively, each of the plurality of oscillator circuits 120[0] to 120[4] is configured to generate a corresponding one of the plurality of oscillation signals SC [0] to SC [4] based on a corresponding one of the plurality of enable signals EN [0] to EN [4] when the mode signal AG has a second logic value (e.g., logic value 0). In other words, when the mode signal AG has the second logic value, each of the oscillator circuits 120[0] to 120[4] does not generate a corresponding oscillation signal in response to the switching signal TG. By the above operation, each of the plurality of oscillator circuits 120[0] 120[4] can operate as a free running (free running) oscillator circuit according to the corresponding enable signal to generate the corresponding oscillation signal when the mode signal AG has the second logic value. Under this condition, the oscillation signals SC [0] -SC [4] can be used to reflect the degradation degree of the functional circuit 101.

The output circuit 130 outputs the detection signal SD based on the oscillation signals SC [0] to SC [4] when the mode signal AG has a second logic value. In some embodiments, the detection signal SD may be used to reflect the reliability of the functional circuit 101. In some embodiments, the output circuit 130 stops outputting the detection signal SD when the mode signal AG has the first logic value. In other words, the output circuit 130 may stop switching when the mode signal AG has the first logic value. Thus, power consumption can be reduced and the output circuit 130 can be prevented from fading, so as to improve the detection accuracy.

In some embodiments, the reliability detection apparatus 100 may further include a processing circuit (not shown). The mode signal AG is set to have a second logic value when the reliability detection apparatus 100 is powered on for the first time. In response to the mode signal AG, the plurality of oscillator circuits 120[0] to 120[4] may sequentially generate a plurality of oscillation signals SC [0] to SC [4] in response to a plurality of enable signals EN [0] to EN [4 ]. For example, when the enable signal EN [0] has a second logic value, the remaining enable signals EN [1] -EN [4] have a first logic value. Under this condition, the oscillator circuit 120[0] can generate the corresponding oscillation signal SC [0], and the plurality of oscillator circuits 120[1] to 120[4] do not generate the plurality of oscillation signals SC [1] to SC [4 ]. The output circuit 130 may output a corresponding detection signal SD based on the oscillation signal SC [0 ]. The processing circuit then counts according to the detection signal SD to generate a default value corresponding to the oscillator circuit 120[0], and stores the default value in a buffer circuit (not shown). By analogy, the processing circuit may store a plurality of default values corresponding to the plurality of oscillator circuits 120[0] to 120[4], respectively, when the reliability detection apparatus 100 is first powered on.

In the subsequent detection operation, the processing circuit may generate a new count value according to the detection signal SD, and compare the count value with a corresponding default value to confirm the reliability of the functional circuit 101. For example, due to circuit degradation, the frequency of the plurality of oscillation signals SC [0] SC [4] becomes slower and slower, so that the new count value becomes smaller. If the count value is less than the corresponding default value, it indicates that the performance of the functional circuit 101 is degraded. In some embodiments, the processing circuit may compare the count value with a threshold value and issue a warning message when the count value is less than the threshold value. This warning message can be used to notify the user or other correction circuitry that the functional circuitry 101 is under-performing for subsequent replacement or correction. In some embodiments, the processing circuit described above may be implemented by a processor circuit. For example, the operations may be implemented by the processor circuit executing software, but the present invention is not limited thereto.

In some related art, in order to save power consumption, the oscillator circuit is turned off while the functional circuit performs a general operation. Therefore, the degradation degree of the oscillator circuit is different from that of the functional circuit, and the accurate detection result cannot be reflected. Alternatively, in some related art, the oscillator circuit is set to be continuously switched. If the oscillator circuit is switched excessively, the degradation degree of the oscillator circuit may be greater than that of the functional circuit, and an accurate detection result may not be reflected.

In contrast to the related art, in some embodiments, the oscillator circuits 120[0] to 120[4] are switched according to the switching signal TG from the functional circuit 101 when the mode signal AG has the first logic value. Thus, the degradation degree of the plurality of oscillator circuits 120[0] to 120[4] can be ensured to be close to the degradation degree of the functional circuit 101. Furthermore, as mentioned above, the output circuit 130 can be turned off when the mode signal AG has the first logic value to ensure that the output circuit 130 is not switched by the plurality of oscillator circuits 120[0] to 120[4] to improve the detection accuracy.

FIG. 2 is a schematic diagram of the plurality of oscillator circuits 120[0] to 120[4] and the output circuit 130 of FIG. 1 according to some embodiments of the disclosure. Each of the plurality of oscillator circuits 120[0] to 120[4] has the same circuit structure. Taking the detailed structure of the oscillator circuit 120[0] of FIG. 2 as an example, the oscillator circuit 120[0] includes a logic gate 222, a multiplexer circuit 224, a logic gate 226, and a plurality of digital circuits 228. The logic gate 222 generates a signal S1 according to the mode signal AG and the switching signal TG. When the mode signal AG has the first logic value, the logic gate circuit 222 outputs the switching signal TG as the signal S1. Alternatively, when the mode signal AG has the second logic value, the logic gate circuit 222 outputs the signal S1 having a fixed level (e.g., low level). In this example, the logic gate circuit 222 may be, but is not limited to, an AND gate circuit. The multiplexer circuit 224 outputs the signal S1 or the signal S2 as the signal S3 according to the mode signal AG. For example, if the mode signal AG has the first logic value, the multiplexer circuit 224 outputs the signal S1 as the signal S3. Alternatively, if the mode signal AG has the second logic value, the multiplexer circuit 224 outputs the signal S2 as the signal S3.

The logic gate 226 is used for generating a corresponding oscillation signal SC [0] according to the corresponding enable signal EN [0] and the signal S3. For example, the logic gate 226 may be, but is not limited to, a NOR (NOR) gate. The digital circuits 228 are used for outputting the signal S2 and receiving the signal S3. In detail, a plurality of digital circuits 228 are coupled in series with the logic gates 226 via the multiplexer circuit 224 to operate as a ring oscillator circuit. In detail, the ring oscillator circuit can generate the oscillation signal SC [0] based on the signal S2 when the enable signal EN [0] has a second logic value. For example, when the enable signal EN [0] has a second logic value, the ring oscillator circuit may operate as a free-running oscillator circuit that may generate the oscillation signal SC [0] based on the signal S2 beginning to switch. Alternatively, when the enable signal EN [0] has a first logic value, the output of the logic gate 226 will have a fixed level (e.g., low). Equivalently, the ring oscillator circuit stops generating the oscillation signal SC [0] in response to the enable signal EN [0] having the first logic value. Thus, the output circuit 130 is prevented from being switched by the oscillator circuits 120[0] to 120[4], thereby reducing the degradation of the output circuit 130.

As previously described, each of the plurality of oscillator circuits 120[0] -120 [4] has the same circuit structure. For example, in oscillator circuit 120[1], logic gate 226 receives enable signal EN [1] and generates a corresponding oscillation signal SC [1 ]. By analogy, the manner in which each of the plurality of oscillator circuits 120[0] 120[4] are disposed can be understood.

In the example of fig. 2, the digital circuits 228 are inverter circuits, but the disclosure is not limited thereto. In some embodiments, the plurality of digital circuits 228 may be arranged based on the functional circuit 101. For example, if the functional circuit 101 includes an and circuit, an or circuit, an inverter circuit, and a nand circuit, the plurality of digital circuits 228 may be implemented using the same and circuit, or circuit, inverter circuit, and nand circuit in combination. Therefore, a more accurate reliability detection result can be obtained. The above description of the types of circuits included in the functional circuit 101 is for illustration and the present disclosure is not limited thereto.

In some embodiments, the number of times the signal S2 is inverted by the plurality of digital circuits 228 and the logic gate 226 may be set to an odd number to ensure that the plurality of oscillator circuits 120[0] 120[4] can start oscillating correctly. In other words, in some embodiments, the number of digital circuits 228 and logic gates 226 may be odd for each of oscillator circuits 120[0] -120 [4 ]. For the example of FIG. 2, oscillator circuit 120[0] includes 4

digital circuits

228 and 1 logic gate 226. Thus, the signal S2 can be inverted 5 times to generate the oscillation signal SC [0 ]. Alternatively, in other embodiments, oscillator circuit 120[0] includes 50

digital circuits

228 and 1 logic gate 226. Thus, the signal S2 can be inverted 51 times to generate the oscillation signal SC [0 ]. The above-mentioned numbers of the plurality of digital circuits 228 and the logic gates 226 are used for illustration, and the disclosure is not limited thereto.

Output circuit 130 includes a logic gate circuit 232 and a logic gate circuit 234. The logic gate circuit 232 is coupled to the plurality of oscillator circuits 120[0] to 120[4] to receive a plurality of oscillation signals SC [0] to SC [4 ]. The logic gate 232 generates a signal S4 according to the oscillation signals SC [0] SC [4 ]. As previously described, when a corresponding enable signal of the plurality of enable signals EN [0] EN [4] has a second logic value, the remaining enable signals of the plurality of enable signals EN [0] EN [4] all have a first logic value. Under this condition, the logic gate circuit 232 can output a corresponding oscillation signal among the plurality of oscillation signals SC [0] to SC [4] as the signal S4.

For example, when the enable signal EN [0] has the second logic value, the remaining enable signals EN [1] -EN [4] all have the first logic value. Under this condition, the oscillator circuit 120[0] starts switching based on the signal S2 to generate the oscillation signal SC [0], and the remaining oscillator circuits 120[1] to 120[4] output a plurality of oscillation signals SC [1] to SC [4] having a fixed level (for example, a low level). Thus, logic gate 232 may output oscillation signal SC [0] as signal S4. In this example, the logic gate 232 may be, but is not limited to, an OR gate.

Logic gate 234 is coupled to logic gate 232 to receive signal S4. When the mode signal AG has the second logic value, the logic gate circuit 234 outputs the detection signal SD according to the signal S4. When the mode signal AG has the first logic value, the logic gate circuit 234 stops outputting the detection signal SD. For example, the logic gate circuit 234 may be, but is not limited to, a nor gate circuit. When the mode signal AG has a first logic value, the output of the logic gate circuit 234 will be fixed at a low level. Equivalently, the logic gate circuit 234 stops outputting the detection signal SD in response to the mode signal AG having the first logic value. Thus, the output circuit 130 is not switched by the plurality of oscillator circuits 120[0] to 120[4 ].

Fig. 3 is a schematic diagram illustrating the control circuit 110 of fig. 1 according to some embodiments of the disclosure. In some embodiments, control circuit 110 includes an encoder circuit 310 and a plurality of logic gate circuits 320[0] 320[4 ]. The encoder circuit 310 is used for generating a plurality of control signals C [0] C [4] according to a selection signal SEL, wherein the selection signal SEL is used for selecting one of the plurality of oscillation circuits 120[0] 120[4] to detect the reliability of the functional circuit 101. Each of the plurality of logic gate circuits 320[0] -320 [4] receives a plurality of control signals C [0] -C [4], and receives a mode signal AG. The plurality of logic gate circuits 320[0] to 320[4] are configured to generate a plurality of enable signals EN [0] to EN [4] according to a plurality of control signals C [0] to C [4] and a mode signal AG. For example, logic gate 320[0] generates enable signal EN [0] based on control signal C [0] and mode signal AG. By analogy, it should be understood that the corresponding relationships among the other logic gate circuits 320[1] -320 [4], the plurality of control signals C [1] -C [4], and the plurality of enable signals EN [1] -EN [4 ].

The plurality of logic gate circuits 320[0] to 320[4] output a plurality of enable signals EN [0] to EN [4] having a second logic value when the mode signal AG has a first logic value. When the mode signal AG has a second logic value, the plurality of logic gate circuits 320[0] to 320[4] can output the plurality of control signals C [0] to C [4] as a plurality of enable signals EN [0] to EN [4], respectively. For example, each of the plurality of logic gates 320[0] -320 [4] may be an AND gate having an inverting input for receiving the mode signal AG.

It should be understood that the number of circuits and the related arrangement of fig. 1, 2 and 3 are for illustration purposes and the present disclosure is not limited thereto. For example, in other embodiments, the reliability detection apparatus 100 may include a different number of oscillator circuits.

Fig. 4 is a flow chart illustrating a reliability detection method 400 according to some embodiments of the present disclosure. In some embodiments, the reliability detection method 400 may be performed by (but is not limited to) the reliability detection apparatus 100 of fig. 1.

In operation S410, a plurality of enable signals (e.g., a plurality of enable signals EN [0] EN [4] of FIG. 1) are generated according to a mode signal (e.g., the mode signal AG of FIG. 1). In operation S420, a plurality of oscillation signals (e.g., a plurality of oscillation signals SC [0] SC [4] of fig. 1) are generated according to a switching signal (e.g., the switching signal TG of fig. 1) when the mode signal has a first logic value (e.g., logic value 1), wherein the switching signal is associated with a functional circuit (e.g., the functional circuit 101 of fig. 1). In operation S430, a corresponding oscillation signal of the plurality of oscillation signals is generated according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value. In operation S440, a detection signal (e.g., the detection signal SD of fig. 1) is output according to the oscillation signals when the mode signal has the second logic value, wherein the detection signal reflects the reliability of the functional circuit.

The above description of the operations can refer to the above embodiments, and thus will not be repeated. The operations of the reliability detection method 400 are merely examples, and are not limited to being performed in the order of the examples. The various operations of the reliability detection method 400 may be added, substituted, omitted, or performed in a different order (e.g., simultaneously or partially simultaneously) as appropriate without departing from the scope and manner of operation of various embodiments of the disclosure.

In summary, the reliability detection apparatus and the reliability detection method in some embodiments of the present disclosure can make the degradation of the oscillator circuit similar to the degradation of the functional circuit, and reduce the degradation of other control circuits. Therefore, a more accurate reliability detection result can be obtained.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply variations to the technical features of the present invention according to the contents of the present invention, which may fall within the scope of the patent protection sought by the present invention.

Description of the reference numerals:

100: reliability detection device

101: functional circuit

110: control circuit

120[0] to 120[4 ]: oscillator circuit

130: output circuit

222. 226, 228, 232, 234: logic gate circuit

224: multiplexer circuit

310: encoder circuit

320[0] to 320[4 ]: AND gate circuit

400: reliability method

AG: mode signal

C [0] to C [4 ]: control signal

EN [0] to EN [4 ]: enable signal

S1, S2, S3, S4: signal

S410, S420, S430, S440: operation of

SC [0] to SC [4 ]: oscillating signal

SD: detecting the signal

SEL: selection signal

TG: switching signal

Claims

1. A reliability detection apparatus comprising:

the control circuit is used for generating a plurality of enable signals according to the mode signal;

a plurality of oscillator circuits configured to output a plurality of oscillation signals, wherein each of the plurality of oscillator circuits is configured to generate a corresponding oscillation signal of the plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, and generate the corresponding oscillation signal according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value, and the switching signal is associated with a functional circuit; and

an output circuit for outputting a detection signal according to the plurality of oscillation signals when the mode signal has the second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.

2. The reliability detection apparatus of claim 1, wherein each of the plurality of oscillator circuits is configured to operate as a free-running oscillator circuit according to the corresponding enable signal to generate the corresponding oscillation signal when the mode signal has the second logic value.

3. The reliability detection apparatus of claim 1, wherein each of the plurality of oscillator circuits does not generate the corresponding oscillation signal in response to the switching signal when the mode signal has the second logic value.

4. The reliability detection apparatus of claim 1, wherein the output circuit is further configured to stop outputting the detection signal when the mode signal has the first logic value.

5. The reliability detection apparatus of claim 1, wherein each of the plurality of oscillator circuits comprises:

a first logic gate circuit for generating a first signal according to the mode signal and the switching signal;

a multiplexer circuit for outputting the first signal or the second signal as a third signal according to the mode signal;

a second logic gate circuit for generating the corresponding oscillation signal according to the corresponding enable signal and the third signal; and

a plurality of digital circuits for outputting the second signal and receiving the third signal, wherein the plurality of digital circuits are coupled in series with the second logic gate circuit via the multiplexer circuit to operate as a ring oscillator circuit.

6. The reliability detection apparatus of claim 5, wherein the ring oscillator circuit generates the corresponding oscillation signal based on the second signal when the corresponding enable signal has the second logic value.

7. The reliability detection apparatus according to claim 1, wherein the control circuit comprises:

the encoder circuit is used for generating a plurality of control signals according to the selection signal; and

and a plurality of logic gate circuits for generating the plurality of enable signals according to the plurality of control signals and the mode signal, wherein the plurality of enable signals all have the second logic value when the mode signal has the first logic value.

8. The reliability detection apparatus of claim 7, wherein each of the plurality of logic gate circuits is an AND gate circuit having an inverting input terminal for receiving the mode signal.

9. The reliability detection apparatus according to claim 1, wherein the output circuit includes:

a first logic gate circuit for generating signals according to the oscillation signals; and

and a second logic gate circuit for outputting the detection signal according to the mode signal when the mode signal has the second logic value, and stopping outputting the detection signal when the mode signal has the first logic value.

10. A reliability detection method, comprising:

generating a plurality of enable signals according to the mode signal;

generating a plurality of oscillation signals according to a switching signal when the mode signal has a first logic value, wherein the switching signal is associated with a functional circuit;

generating a corresponding oscillation signal of the plurality of oscillation signals according to a corresponding enable signal of the plurality of enable signals when the mode signal has a second logic value; and

outputting a detection signal according to the plurality of oscillation signals when the mode signal has the second logic value, wherein the detection signal is used for reflecting the reliability of the functional circuit.