1297431 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種重設信號產生電路，且特別是有 關於一種電源啟動重設信號產生電路。 【先前技術】 為了使各電子元件有一個固定的初始值以免操作發生 錯誤，大部分的電子裝置中都會有一個在電源開啟時提供 φ 初始化條件的電路。此種電路由於是利用提供一個重設信 號給各電子元件以使各電子元件能進行初始化，因此一般 被稱為電源啟動重設信號（Power On Reset Signal)產生電 路。 請參見圖1，其為習知技術所使用之電源啟動重設信號 產生電路的電路圖。在此電源啟動重設信號產生電路1〇 中，工作電位VCC初始時的電源上升速度影響了控制電路 100所輸出之控制信號CTL的上升速度，而控制信號ctl • 的上升速度則影響到對A點進行放電之電流n的變化速BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset signal generating circuit, and more particularly to a power-on reset signal generating circuit. [Prior Art] In order to make each electronic component have a fixed initial value to avoid an operation error, most electronic devices have a circuit that supplies a φ initialization condition when the power is turned on. Such a circuit is generally referred to as a Power On Reset Signal generating circuit because it provides a reset signal to each electronic component to enable initialization of each electronic component. Please refer to FIG. 1, which is a circuit diagram of a power-on reset signal generating circuit used in the prior art. In this power-on reset signal generating circuit 1 ,, the power-up speed at the initial state of the operating potential VCC affects the rising speed of the control signal CTL outputted by the control circuit 100, and the rising speed of the control signal ctl • affects the pair A. The rate of change of the current n at which the discharge is performed
度。由於A點的電位是由充電電流12與放電電流^所共同 影響而得，因此依照前述的推論，A點輸出之信號从 化將會文到工作電位vcc之變化速度的影響。從另一個二 面來看，右將信號SA的高低切換點對應至工作電位 的-個臨界電位，則此臨界電位將會隨著卫作電 C 變化速度而有相應的變化。 之 再者’位準偏移單元丨2 Q是根據信號s A來 體M5的開關，而電晶體M5的開關則直接影響到重設^ 1297431 RESET、的位準變化。因此，在此電路中，假若工作電位 的上升速度過快，則信號SA的脈衝寬度將會_非常小， Ϊ = 導信號臓丁無法產生在邏輯上被視為 有,’&換句話說，在工作電位vcc上升速度過快的 時候’有可此發生無法正常輸出纽信號reset的情況。 此外為了達到低消耗電流的目的，電阻R0就必須要 #常的大（約需大於1百萬歐姆）。然而大電阻不但將使 用較多的電路空間，而且由於電阻太大，所以也將同時導 致重设位號RESET的驅動能力降低以及反應速度過慢，同 樣可能造成重設信號出上的問題。 【發明内容】 有鑑於此，本發明的目的就是在提供一種電源啟動重 設信號產生電路，其可在降低整體電路所需耗費的佈線空 間的同時，解決無法正常輸出重設信號的問題，降低靜態 消耗電流及提高重設信號的驅動力與反應速度。 為達前述及其他目的，本發明提出一種電源啟動重設 信號產生電路。此電源啟動重設信號產生電路包括第一/第 二電晶體，一個二極體，一個上升信號產生單元，以及第 //第二位準偏移單元。其中，第一電晶體之控制端接收控 制信號，二極體的陽極接收工作電位，而第二電晶體之兩 信號進出端分別電性耦接至二極體之陰極與第一電晶體的 ，個信號進出端。上升信號產生單元根據工作電位變化， 產生上升緣部分較工作電位上升速度為缓的脈衝信號，且 將此脈衝信號提供至第二電晶體之控制端。第一位準偏移 1297431 單元以第二電晶體及第一電晶體相電性耦接處所產生之中 繼信號為輸入，並將此中繼信號經位準偏移處理後輸出為 偏移中繼信號。第二位準偏移單元則根據中繼信號與偏移 中繼信號以產生重設信號。 在本發明的一個實施例中，前述上升信號產生單元包 括第一/第二P型電晶體、第一/第二N型電晶體、電容與反 相器組。第一 P型電晶體的閘極接地，源極接收工作電位， 汲極產生第一信號；第二P型電晶體的閘極接收第一信號， _ 源極接收工作電位，汲極產生第二信號。電容的一端電性 耦接第一 P型電晶體之汲極，另一端接地。第一 N型電晶 體的閘極接收第一信號，汲極電性耦接第二P型電晶體之 汲極；第二N型電晶體的閘極接收工作電位，汲極電性耦 接第一 N型電晶體之源極，源極接地。反相器組則具備偶 數個串連之反相器，並以第二信號為輸入以輸出前述的脈 衝信號。 在本發明的一個實施例中，前述第一位準偏移單元包 * 括第一/第二P型電晶體，一個N型電晶體與一個反相器 組。第一 P型電晶體的源極接收前述之工作電位且其閘極 ，接地。第二P型電晶體之源極耦接第一 P型電晶體之汲極， 閘極接收前述之中繼信號，而汲極則產生一個反相偏移中 繼信號。N型電晶體之汲極耦接第二P型電晶體之汲極， 閘極接收前述之中繼信號，源極則接地。反相器組具備奇 數個串連之反相器，並以反相偏移中繼信號為輸入以輸出 前述之偏移中繼信號。 1297431 . * 在本發明的一個實施例中，前述之第二位準偏移單元 包括一個第三電晶體與一個第四電晶體。其中，第三電晶 體包括控制端與兩個信號進出端，控制端接收前述的偏移 中繼信號，一個信號進出端接收前述的工作電位而另一個 信號進出端則產生前述的重設信號。第四電晶體同樣包括 控制端與兩信號進出端，控制端接收前述的中繼信號，一 信號進出端接地，另一信號進出端與第三電晶體產生前述 重設信號之信號進出端相電性耦接。 > 本發明因不於電路中使用大電阻，因此能有效的降低 整體電路所需耗費的佈線空間。此外，上升信號產生單元 所產生之脈衝信號因為有著較緩的上升緣上升速度，因此 將可解決無法正常輸出重設信號的問題。而第二位準偏移 單元中的第三電晶體開啟時的電阻極低，因此能提高對重 設信號的驅動能力與反應速度。再者，因其靜態消耗電流 為〇，因此還可以降低靜態消耗電流。 > 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 請參照圖2,其為根據本發明一實施例之電源啟動重設 信號產生電路的電路方塊圖。在本實施例中，電源啟動重 設信號產生電路20包括上升信號產生單元200，兩個P型 電晶體210、212，一個N型電晶體214，第一位準偏移單 元220以及第二位準偏移單元230。其中，上升信號產生單 1297431 凡2〇〇根據工作電位vcc的變化，產生上升緣部分較工作 電位VCC上升速度為緩的脈衝信號PWD，且將脈衝信號 PWD提供至P型電晶體212之控制端。p型電晶體21〇以 一個信號進出端接收工作電位VCC，另一個信號進出端與 其控制端相電性連接而產生等同於二極體的效果（此二極 體之陽極接收工作電位VCC，而陰極則電性耦接至P型電 晶體212) 〇 再者’ P型電晶體212除了控制端接收脈衝信號pwd 之外’兩個信號進出端則分別電性耦接至p型電晶體21〇 與N型電晶體214的一個信號進出端，且P型電晶體212 與N型電晶體214相電性耦接處係用以提供中繼信號cs。 N型電晶體214的控制端接收控制信號CTL· (此控制信號 CTL可為圖}之控制電路ι〇〇所產生，在此不再資述）， 不與P型電晶體212相電性輕接的信號進出端則接地。第 一位準偏移單元220以中繼信號CS為輸入，並將中繼信號 cs經位準偏移處理後輸出為偏移中繼信號sw。第二位準 偏移單元230則根據中繼信號CS與偏移中繼信號sw以產 生重設信號RESET。 由於中繼信號CS的上升緣上升速度會影響到偏移中繼 L號SW與童设#號RESET的上升緣上升速度，而中繼信 號CS的變化除了受到p型電晶體212的控制端電位影響之 外，同時也受到P型電晶體212的控制端及其與p型電晶 體210相電性|馬接之#號進出端間之電位差異的影響。因 此，除了產生上升緣部分較工作電位VCC上升速度為缓的 1297431 脈衝信號PWD之外，也可以在工作電位Vcc到p型電曰曰 體212之間串接其他二極體元件，以藉由調整p型電晶: 212的控制端與信號進出端之間的電位差異來調整中=俨 號CS的變化速度。 、° 為§羊細說明本發明之技術，請進一步參照圖3，其為祀 據本發明一實施例之上升信號產生單元的電路圖。為使4 明更加清楚’以下的P型電晶體與N型電晶體將分別用： 代稱PMOS與NMOS，因此其控制端將稱之為閘極，而俨 號進出端則稱為源極或汲極。在本實施例中，上升俨號^ 生單元30包括了 P型電晶體3〇〇與3〇4、電容3〇2:=型 電晶體306與3〇8以及反相器組32〇。p型電晶體3⑻的閘 極接地，源極接收工作電位VCC，而其汲極則耦接至電容 302的一端並產生一個信號P1至p型電晶體3〇4與n型電 晶體306的閘極。再者，P型電晶體3〇4的源極接收工作電 位VCC，汲極耦接至N型電晶體306的汲極並產生信號 P2 ; N型電晶體306的源極電性耦接N型電晶體3〇8之汲 極，而N型電晶體308則以閘極接收工作電位VCc，並以 源極接地。最後，反相器組320則具備偶數個串連之反相 器322〜324 (在本實施例中為兩個反相器），並以信號？2 為輸入以輸出脈衝信號PWD。 在本實施例中，工作電位VCC的上升將使得電容3〇2 開始充電而導致信號P1開始產生上升緣，而信號卩丨又同 時提供了用以控制P型電晶體304與N型電晶體306之閘 極的電位，是以，隨著信號Pl之電位的上升，p型電晶體 1297431 304 ¥電的通道將會逐步縮減，因此信號p2受到μ電晶 =綱之流通電流以進行充電的速度將會逐漸減緩；相反 的，,Ν型電晶體3〇6導電的通道將會逐步加大，因此信號 、豕、二到：1電曰曰體3〇6 <流通電流而進行放電的速度將會 逐^ ,快。是以，信號P2的電位變化就會受到p型電晶體 304與N型電晶们06的影響，而藉由調整？型電晶體3〇4degree. Since the potential at point A is caused by the combination of the charging current 12 and the discharging current, the signal output from point A is affected by the rate of change of the operating potential vcc according to the above-mentioned inference. From the other side, the high-low switching point of the signal SA corresponds to the ----------------- Furthermore, the level shifting unit 丨2 Q is a switch of the body M5 according to the signal s A , and the switching of the transistor M5 directly affects the level change of the reset ^ 1297431 RESET. Therefore, in this circuit, if the rising speed of the operating potential is too fast, the pulse width of the signal SA will be _ very small, Ϊ = the guiding signal can not be logically regarded as having, '& in other words When the operating potential vcc rises too fast, there is a case where the new signal reset cannot be output normally. In addition, in order to achieve low current consumption, the resistor R0 must be a large (about 1 million ohms). However, the large resistor will not only use more circuit space, but also because the resistance is too large, it will also cause the drive capability of the reset bit number RESET to decrease and the reaction speed to be too slow, which may also cause problems in resetting the signal. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a power-on reset signal generating circuit that can solve the problem that the reset signal cannot be normally output and reduce the wiring space required for the overall circuit. Static current consumption and increase the driving force and reaction speed of the reset signal. To achieve the foregoing and other objects, the present invention provides a power-on reset signal generating circuit. The power-on reset signal generating circuit includes a first/second transistor, a diode, a rising signal generating unit, and a // second level shifting unit. Wherein, the control end of the first transistor receives the control signal, the anode of the diode receives the working potential, and the two signal input and output ends of the second transistor are electrically coupled to the cathode of the diode and the first transistor, respectively, Signals in and out. The rising signal generating unit generates a pulse signal whose rising edge portion is slower than the working potential rising speed according to the change of the operating potential, and supplies the pulse signal to the control terminal of the second transistor. The first quasi-offset 1294431 unit takes as input a relay signal generated by the second transistor and the first transistor, and outputs the relay signal as an offset after being subjected to level offset processing. Following the signal. The second level shifting unit generates a reset signal based on the relay signal and the offset relay signal. In one embodiment of the invention, the rising signal generating unit includes a first/second P-type transistor, a first/second N-type transistor, a capacitor and a phase inverter group. The gate of the first P-type transistor is grounded, the source receives the working potential, the drain generates the first signal; the gate of the second P-type transistor receives the first signal, the _ source receives the working potential, and the drain receives the second potential signal. One end of the capacitor is electrically coupled to the drain of the first P-type transistor, and the other end is grounded. The gate of the first N-type transistor receives the first signal, the gate of the second N-type transistor is electrically coupled to the drain of the second P-type transistor; the gate of the second N-type transistor receives the working potential, and the gate of the second N-type transistor is electrically coupled The source of an N-type transistor, the source is grounded. The inverter group has an even number of serially connected inverters and uses the second signal as an input to output the aforementioned pulse signal. In one embodiment of the invention, the first level offset unit includes a first/second P-type transistor, an N-type transistor and an inverter group. The source of the first P-type transistor receives the aforementioned operating potential and its gate is grounded. The source of the second P-type transistor is coupled to the drain of the first P-type transistor, the gate receives the aforementioned relay signal, and the drain generates an inverted offset relay signal. The drain of the N-type transistor is coupled to the drain of the second P-type transistor, the gate receives the aforementioned relay signal, and the source is grounded. The inverter group has an odd number of serially connected inverters and inputs an inverted offset relay signal to output the aforementioned offset relay signal. 1297431. * In one embodiment of the invention, the aforementioned second level shifting unit comprises a third transistor and a fourth transistor. The third transistor includes a control terminal and two signal input and output terminals, and the control terminal receives the offset relay signal, and a signal input and output terminal receives the aforementioned working potential, and another signal input and output terminal generates the foregoing reset signal. The fourth transistor also includes a control end and two signal input and output ends, the control end receives the aforementioned relay signal, one signal is grounded at the input and output end, and the other signal input and output end is electrically connected to the signal input and output end of the third transistor for generating the reset signal. Sexual coupling. > The present invention can effectively reduce the wiring space required for the entire circuit because it does not use a large resistor in the circuit. In addition, since the pulse signal generated by the rising signal generating unit has a slow rising edge rising speed, the problem that the reset signal cannot be normally output can be solved. When the third transistor in the second level shifting unit is turned on, the resistance is extremely low, so that the driving ability and the reaction speed for the reset signal can be improved. Furthermore, since the static current consumption is 〇, the static current consumption can also be reduced. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. [Embodiment] Please refer to FIG. 2, which is a circuit block diagram of a power-on reset signal generating circuit according to an embodiment of the present invention. In the present embodiment, the power-on reset signal generating circuit 20 includes a rising signal generating unit 200, two P-type transistors 210, 212, an N-type transistor 214, a first level shifting unit 220, and a second bit. Quasi-offset unit 230. Wherein, the rising signal generation unit 1297431, according to the change of the operating potential vcc, generates a pulse signal PWD whose rising edge portion is slower than the working potential VCC, and supplies the pulse signal PWD to the control terminal of the P-type transistor 212. . The p-type transistor 21 接收 receives the working potential VCC with one signal input and output end, and the other signal input and output end is electrically connected with the control end thereof to produce an effect equivalent to the diode (the anode of the diode receives the working potential VCC, and The cathode is electrically coupled to the P-type transistor 212). Further, the P-type transistor 212 is electrically coupled to the p-type transistor 21, respectively, except that the control terminal receives the pulse signal pwd. And a signal input and output end of the N-type transistor 214, and the P-type transistor 212 and the N-type transistor 214 are electrically coupled to provide a relay signal cs. The control terminal of the N-type transistor 214 receives the control signal CTL· (this control signal CTL can be generated by the control circuit ι of FIG. }, which is not described herein), and is not electrically lightly connected to the P-type transistor 212. The incoming and outgoing signals are grounded. The first quasi-offset unit 220 takes the relay signal CS as an input, and the relay signal cs is subjected to the level offset processing and then output as the offset relay signal sw. The second level shifting unit 230 generates a reset signal RESET based on the relay signal CS and the offset relay signal sw. Since the rising edge rising speed of the relay signal CS affects the rising edge rising speed of the offset relay L number SW and the child set # number RESET, the change of the relay signal CS is affected by the control terminal potential of the p-type transistor 212. In addition to the influence, it is also affected by the potential difference between the control terminal of the P-type transistor 212 and its phase-to-exit end with the p-type transistor 210. Therefore, in addition to the 1297431 pulse signal PWD whose rising edge portion is slower than the operating potential VCC rising speed, other diode elements may be connected in series between the working potential Vcc and the p-type electric body 212. Adjust the potential difference between the control terminal of the p-type transistor: 212 and the signal input and output terminals to adjust the rate of change of the medium = apostrophe CS. The technique of the present invention will be described in detail with reference to FIG. 3, which is a circuit diagram of a rising signal generating unit according to an embodiment of the present invention. In order to make the 4 clearer clear, the following P-type and N-type transistors will be used separately: PMOS and NMOS, so the control terminal will be called the gate, and the nickname is called the source or the 汲. pole. In the present embodiment, the rising symmetry unit 30 includes P-type transistors 3A and 3〇4, capacitors 3〇2:=-type transistors 306 and 3〇8, and an inverter group 32〇. The gate of the p-type transistor 3 (8) is grounded, the source receives the working potential VCC, and the drain is coupled to one end of the capacitor 302 and generates a signal P1 to the gate of the p-type transistor 3〇4 and the n-type transistor 306. pole. Furthermore, the source of the P-type transistor 3〇4 receives the working potential VCC, the drain is coupled to the drain of the N-type transistor 306 and generates the signal P2; the source of the N-type transistor 306 is electrically coupled to the N-type The anode of the transistor 3〇8, and the N-type transistor 308 receives the working potential VCc with the gate and is grounded with the source. Finally, the inverter group 320 has an even number of inverters 322 to 324 (in this embodiment, two inverters) connected in series, and signals? 2 is input to output pulse signal PWD. In this embodiment, the rise of the operating potential VCC will cause the capacitor 3〇2 to start charging, causing the signal P1 to begin to generate a rising edge, and the signal 卩丨 is simultaneously provided to control the P-type transistor 304 and the N-type transistor 306. The potential of the gate is such that, as the potential of the signal P1 rises, the channel of the p-type transistor 1297431 304 is gradually reduced, so the signal p2 is subjected to the current of the transistor. It will gradually slow down; on the contrary, the channel of the Ν-type transistor 3〇6 will gradually increase, so the signal, 豕, two to: 1 electric body 3〇6 < the speed of discharge current Will be ^, fast. Therefore, the potential change of the signal P2 is affected by the p-type transistor 304 and the N-type transistor 06, and is adjusted by ? Type transistor 3〇4
及N型電晶體306與308的尺寸，就能夠設計出:有適當 上升緣時間的信號P2,並進而透過反相器組32〇產生出一 個^有適當上升緣時間的信號PWD。而為了解決如圖、中 因4號SA上升緣時間不足而導致無法正常產生重設信號 的問題，在此處應將P型電晶體304及贝型電晶體3〇6與 3〇8設計成使其所產生之信號p2具備一個較緩上升緣之型 態為佳。 接下來清參照圖4 ’其為根據本發明一實施例之第^一位 準偏移單元之電路圖。此第一位準偏移單元40包括兩個P 型電晶體400與402、一個N型電晶體404以及一個反相器 組410。在本實施例中，p型電晶體402與N型電晶體404 的閘極都接收中繼信號CS，而P型電晶體400的閘極則接 地。此外，P型電晶體402的汲極與N型電晶體的汲極404 相電性耦接並產生信號S1，而此信號S1在經過具有奇數個 反相器（在本實施例中為一個反相器412)的反相器組410 之後即成為前述的偏移中繼信號SW。 接下來請參照圖5，其為根據本發明一實施例之第二位 準偏移單元之電路圖。此第二位準偏移單元50包括了一個 1297431 » p型電晶體502與一個N型電晶體504。P型電晶體502的 源極接到工作電位VCC，閘極接收偏移中繼信號SW，源極 則與N型電晶體504的源極相電性耦接，並產生重設信號 RESET。N型電晶體504的閘極接收中繼信號CS，源極則 接地。根據前述電路的耦接，中繼信號CS與偏移中繼信號 SW都具有坡度較緩，亦即，上升時間較長的上升緣，因此 當其分別用以控制N型電晶體504與P型電晶體502的時 候5也可以產生一個具有較長上升時間之上升緣的重設信 .號RESET。再者，由於在第二位準偏移單元50裡用來連接 工作電位VCC的元件是P型電晶體502而非如習知技術般 採用大電阻值的電阻，因此整體電路佔用面積得以縮減， 且當P型電晶體502關閉時，由於其靜態電流為零，因此 也可以降低功率的損耗。另一方面，當P型電晶體打開時， 由於其電阻值極小，因此可以提高對重設信號RESET的驅 動能力及反應速度。 綜上所述，本發明能有效的降低整體電路所需耗費的 > 佈線空間，且可以降低靜態消耗電流，並提高重設信號的 驅動力與反應速度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為習知技術所使用之電源啟動重設信號產生電路 -12- 1297431 的電路圖 電路^路為^^㈣―實施狀電源啟動重設信號產生And the size of the N-type transistors 306 and 308, it is possible to design a signal P2 having an appropriate rising edge time, and further, through the inverter group 32, to generate a signal PWD having an appropriate rising edge time. In order to solve the problem that the reset signal cannot be generated normally due to insufficient rising edge time of the No. 4 SA in the figure, the P-type transistor 304 and the shell-type transistors 3〇6 and 3〇8 should be designed here. It is preferable that the signal p2 generated by it has a gentle rising edge. Next, reference is made to Fig. 4' which is a circuit diagram of a first bit shifting unit according to an embodiment of the present invention. The first level shifting unit 40 includes two P-type transistors 400 and 402, an N-type transistor 404, and an inverter group 410. In the present embodiment, both the p-type transistor 402 and the gate of the N-type transistor 404 receive the relay signal CS, and the gate of the P-type transistor 400 is grounded. In addition, the drain of the P-type transistor 402 is electrically coupled to the drain 404 of the N-type transistor and generates a signal S1, and the signal S1 is passed through an odd number of inverters (in this embodiment, an inverse The inverter group 410 of the phaser 412) becomes the aforementioned offset relay signal SW. Next, please refer to FIG. 5, which is a circuit diagram of a second level shifting unit according to an embodiment of the invention. This second level shifting unit 50 includes a 1297431 » p-type transistor 502 and an N-type transistor 504. The source of the P-type transistor 502 is connected to the operating potential VCC, the gate receives the offset relay signal SW, and the source is electrically coupled to the source of the N-type transistor 504, and a reset signal RESET is generated. The gate of the N-type transistor 504 receives the relay signal CS, and the source is grounded. According to the coupling of the foregoing circuit, the relay signal CS and the offset relay signal SW both have a gentle slope, that is, a rising edge with a long rise time, so that they are used to control the N-type transistor 504 and the P-type, respectively. At time 5 of transistor 502, a reset signal RESET with a rising edge of a longer rise time can also be generated. Furthermore, since the element for connecting the working potential VCC in the second level shifting unit 50 is the P-type transistor 502 instead of using a large resistance value as in the prior art, the overall circuit footprint is reduced. And when the P-type transistor 502 is turned off, since the quiescent current is zero, the power loss can also be reduced. On the other hand, when the P-type transistor is turned on, since the resistance value thereof is extremely small, the driving ability and the reaction speed for the reset signal RESET can be improved. In summary, the present invention can effectively reduce the wiring space required for the overall circuit, and can reduce the static current consumption and improve the driving force and reaction speed of the reset signal. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a power-on reset signal generating circuit -12-1297431 used in the prior art. The circuit is a ^^(4)-implemented power-on reset signal generation
路圖 路圖 圖3為根據本發明—實施例之上升信 圖4為根據本發明一實施例之第 圖 路圖。 為根據本發明—實施例之第 號產生單元的電 位準偏移單元之電 ‘位準偏移單 元之電 【主要元件符號說明】 10、20 :電源啟動重設信號產生電路 30、200 :上升信號產生單元 40、220 :第一位準偏移單元 50、230 :第二位準偏移單元 1〇〇:控制電路 φ 120:位準偏移單元 M2、M7、M8 : P型電晶體 210、212、300、304、400、402、502 : P 型電曰曰體 M5、M6、M9 : N型電晶體 一 214、306、308、404、504 ·· N 型電晶體 R0 :電阻 302·•電容 320、410 ·•反相器組 322、324、412 :反相器 -13-Figure 3 is a riser diagram in accordance with an embodiment of the present invention. Figure 4 is a diagram of a first embodiment of the present invention. The electric component of the electric potential shifting unit of the potential generating unit of the first generation unit according to the present invention is the main component symbol description. 10, 20: power-on reset signal generating circuit 30, 200: rising Signal generating unit 40, 220: first level shifting unit 50, 230: second level shifting unit 1: control circuit φ 120: level shifting unit M2, M7, M8: P-type transistor 210 , 212, 300, 304, 400, 402, 502: P type electric body M5, M6, M9: N type transistor - 214, 306, 308, 404, 504 · N type transistor R0: resistance 302 · • Capacitors 320, 410 • Inverter banks 322, 324, 412: Inverter-13-