CN114823617A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN114823617A
CN114823617A CN202110563281.1A CN202110563281A CN114823617A CN 114823617 A CN114823617 A CN 114823617A CN 202110563281 A CN202110563281 A CN 202110563281A CN 114823617 A CN114823617 A CN 114823617A
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Prior art keywords
layer
tantalum
barrier
over
passivation
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CN202110563281.1A
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Inventor
邱雅琴
林明贤
许家栋
邱仑捷
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN114823617A publication Critical patent/CN114823617A/zh
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Abstract

半导体结构包括多层互连结构、钝化层、阻挡层和焊盘层。钝化层位于多层互连结构之上。阻挡层内衬钝化层的内侧壁、钝化层的顶面和多层互连结构的导线的顶面。阻挡层包括第一层、第二层、第三层和第四层。第一层是纳米晶相。第二层位于第一层之上并且是非晶相。第三层位于第二层之上并且是多晶相。第四层位于第三层之上并且是纳米晶相。焊盘层位于阻挡层之上。本申请的实施例还涉及用于制造半导体结构的方法。

Description

半导体结构及其制造方法
技术领域
本申请的实施例涉及半导体结构及其制造方法。
背景技术
半导体器件包括一个或多个用作金属互连件的导电金属层。导电金属层通过介电材料将各个器件组件彼此耦接。彼此堆叠形成位于各个器件层处的导电金属层。此外，半导体器件包括用作焊盘结构的一部分的最上部或顶部金属层。因此，顶部金属层可以电耦接焊料凸块或其它外部组件，以便能够电连接至半导体器件。
发明内容
本申请的一些实施例提供了一种半导体结构，包括：多层互连结构；钝化层，位于所述多层互连结构之上；阻挡层，内衬所述钝化层的内侧壁、所述钝化层的顶面和所述多层互连结构的导线的顶面，其中，所述阻挡层包括：第一层，是纳米晶相；第二层，位于所述第一层之上并且是非晶相；第三层，位于所述第二层之上并且是多晶相；以及第四层，位于所述第三层之上并且是纳米晶相；以及焊盘层，位于所述阻挡层之上。
本申请的另一些实施例提供了一种半导体结构，包括：多层互连结构；钝化层，位于所述多层互连结构之上；焊盘层，部分位于所述钝化层中并且位于所述多层互连结构之上；以及阻挡层，位于所述多层互连结构和所述焊盘层之间，其中，所述阻挡层包括：第一含钽层；第二含钽层，位于所述第一含钽层之上；以及第三含钽层，位于所述第二含钽层之上，其中，所述第一含钽层和所述第三含钽层具有比所述第二含钽层的氮浓度高的氮浓度，并且所述第二含钽层的厚度小于所述第三含钽层的厚度。
本申请的又一些实施例提供了一种用于制造半导体结构的方法，包括：在多层互连结构之上形成钝化层；在所述钝化层中形成开口以暴露所述多层互连结构；形成内衬所述钝化层中的所述开口的阻挡层，包括：形成是纳米晶相的第一层；在所述第一层之上形成是非晶相的第二层；在所述第二层之上形成是多晶相的第三层；以及在所述第三层之上形成是纳米晶相的第四层；在所述阻挡层上方形成导电材料；以及图案化所述阻挡层和所述导电材料。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图9B示出了根据本发明的一些实施例的用于在各个阶段制造半导体器件的方法。
图10是根据本发明的一些实施例的图9A中的区域B’的放大图。
图11是根据本发明的一些实施例的用于形成半导体结构的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
如本文所使用，“左右”、“约”、“大约”或“基本”通常是指给定值或范围的百分之20以内、百分之10以内或百分之5以内。本文给出的数值是近似的，意味着如果没有明确说明，则可以推断出术语“左右”、“约”、“大约”或“基本”。
本发明的一些实施例涉及具有多个阻挡层以防止金属扩散的半导体结构。利用这样的配置，导线的位于阻挡层下面的金属元素不容易穿过所有多个阻挡层，并且增强了阻挡层的性能。
图1至图9B示出了根据本发明的一些实施例的用于在各个阶段制造半导体器件的方法。在一些实施例中，图1至图9B所示的半导体器件可以是在处理集成电路(IC)或它的部分期间制造的中间器件，可以包括静态随机存取存储器(SRAM)、逻辑电路、无源组件(诸如电阻器、电容器和电感器)和/或有源组件(诸如p型场效应晶体管(PFET)、n型FET(NFET)、多栅极FET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其它存储器单元和它们的组合)。
参考图1。提供衬底110。在一些实施例中，衬底110可以包括硅(Si)。可选地，衬底110可以包括锗(Ge)、硅锗(SiGe)、砷化镓(GaAs)或其它适当的半导体材料。在一些实施例中，衬底110可以包括绝缘体上半导体(SOI)结构，诸如埋介电层。同样可选地，衬底110可以包括埋介电层，诸如埋氧(BOX)层，诸如通过称为注氧隔离(SIMOX)技术、晶圆接合、SEG或另一适当的方法形成的层。在各个实施例中，衬底110可以包括多种衬底结构和材料中的任何一种。
在一些实施例中，在衬底110中形成多个隔离部件120，诸如浅沟槽隔离(STI)部件或硅的局部氧化(LOCOS)部件。隔离部件120可以限定并且隔离用于各个微电子元件(诸如晶体管(金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管，双极结型晶体管(BJT)、高压晶体管、高频晶体管等)、电阻器、二极管、电容器和其它合适的元件)的有源区域。因此，实施各种工艺，诸如沉积、蚀刻、注入、光刻、退火和本领域普通技术人员可用于形成微电子元件的其它合适的工艺。微电子元件互连以形成集成电路，诸如逻辑器件、存储器器件(例如，SRAM)、RF器件、输入/输出(I/O)器件、片上系统(SoC)器件、它们的组合和本领域已知的其它合适类型的器件。
在包括微电子元件的衬底110上方形成层间电介质(ILD)130。ILD 130可以包括氧化硅、氮氧化硅或低k材料。ILD 130可以通过化学汽相沉积(CVD)、高密度等离子体CVD(HDP-CVD)、旋涂、物理汽相沉积(PVD或溅射)或其它合适的技术形成。应该指出，在形成ILD130之前，可以在衬底110上方形成诸如接触蚀刻停止层(CESL)的应力层。
在一些实施例中，在ILD 130中形成多个接触件140。接触件140可以通过图案化并且蚀刻ILD 130以形成沟槽来形成。沟槽可以通过沉积诸如TiN的金属阻挡层，以及然后在金属阻挡层上沉积诸如W的接触插塞层来填充。在一些实施例中，金属阻挡层可以包括用于W接触插塞的Ti/TiN。在一些其它实施例中，金属阻挡层可以包括用于Cu接触插塞的Ta/TaN。接触件140提供至形成在衬底110中的各个微电子元件的连接。
在ILD 130和接触件140之上形成多层互连结构150。多层互连结构150包括在各个微电子之间以及导电层自身之间提供互连(布线)的多个导电层150a-150g。应该理解，导电层的数量可以根据特定半导体器件的设计而变化。在图1中，导电层150a-150g包括具有最底部导电层150a(M1)、最顶部导电层150g(M7)以及最底部导电层150a和最顶部导电层150g之间的导电层150b-150f(M2-M6)的七个(7)导电层。导电层150a-150g(M1-M7)可以包括由诸如铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物或它们的组合的导电材料形成的线。可选地，导电层150a-150g可以包括由铜、铜合金、钛、氮化钛、钽、氮化钽、钨、多晶硅、金属硅化物或它们的组合形成的线。
导电层150a-150g(M1-M7)可以通过金属间介电(IMD)层160彼此绝缘。IMD层160可以包括低介电常数或低k值(低k)的材料。在一些实施例中，多层互连结构150的各个层处的IMD层160可以由不同的介电材料形成。已经观察到，具有低K(LK)、极低K(ELK)和/或超低K(XLK)材料的IMD层160可以增强电路性能。材料分类可以基于介电常数。例如，LK材料可以指具有小于大约3.5，并且优选小于大约3.0的k值的那些材料。ELK材料可以指具有小于大约2.9，并且优选小于大约2.6的k值的那些材料。XLK材料可以指通常具有小于大约2.4的k值的那些材料。应该理解，这些分类仅仅是实例，并且也可以利用基于材料的介电常数的其它分类。LK、ELK和/或XLK介电材料可以包括氮化硅、氮氧化硅、旋涂玻璃(SOG)、未掺杂的硅酸盐玻璃(USG)、氟化石英玻璃(FSG)、碳掺杂的氧化硅(例如，SiCOH)、含碳材料、Black
Figure BDA0003079892520000051
(加利福尼亚州圣克拉拉的应用材料)、Xerogel、Aerogel、非晶氟化碳、聚对二甲苯、BCB(双苯并环丁烯)、Flare、SiLK(密歇根州米德兰陶氏化学公司)、聚酰亚胺、其它合适的多孔聚合物材料、其它合适的介电材料和/或它们的组合。IMD层160可以通过包括旋涂、CVD、PVD或原子层沉积(ALD)的技术来形成。
导电层150a-150g和IMD层160可以在诸如镶嵌工艺或光刻/等离子体蚀刻工艺的集成工艺中形成。最底部导电层150a(M1)可以包括耦接至用于连接至形成在衬底110中的微电子元件的接触件140的导线152。多层互连结构150可以进一步包括设置在用于连接相邻导电层150a-150g的导线152的IMD层160内的各个金属通孔165。
参考图2。在导电层150a-150g(M1-M7)和IMD层160之上形成蚀刻停止层(ESL)210。在一些实施例中，ESL 210提供了当形成通孔和/或接触件时停止蚀刻工艺的机制。ESL 210由具有与相邻层(例如，下面的导电层150g)不同的蚀刻选择性的介电材料形成。在一些实施例中，ESL 210可以由通过CVD或PECVD技术沉积的SiNx、SiCN、SiO2、CN、AlOxNy、它们的组合等形成。
随后，在ESL 210之上形成第一钝化层220。第一钝化层220可以由选自未掺杂的硅酸盐玻璃(USG)、氮化硅、氮氧化硅、氧化硅和/或它们的多层的非有机材料制成。可选地，第一钝化层220可以由聚合物层制成，诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等，但是也可以使用其它相对软的、通常是有机的介电材料。在一些实施例中，第一钝化层220的厚度大于ESL 210的厚度。
在第一钝化层220之上形成具有开口312的第一光刻胶层310。第一光刻胶层310通过旋涂或其它合适的技术来形成。诸如烘烤的其它操作可以在涂覆第一光刻胶层310之后进行。在一些实施例中，开口312暴露第一钝化层220的在最顶部导电层150g(M7)中的导线152中的一个正上方的部分。
参考图3A和图3B，其中图3B是图3A中的区域B的放大图。在第一钝化层220和ESL210中形成开口222以暴露最顶部导电层150g(M7)中的导线152的部分。基于图案化的光刻胶层310(见图2)去除第一钝化层220和ESL 210的部分以形成开口222，并且在形成开口222之后去除图案化的光刻胶层310。在一些实施例中，开口222包括底部222b(即，对应导线152的顶面)和侧壁222s(即，第一钝化层220的内侧壁)。
参考图4。在图3A的结构之上共形地形成阻挡层230(见图5)。即，阻挡层230内衬第一钝化层220的内侧壁222s、第一钝化层220的顶面220t和导线152的顶面222b。阻挡层230可以起阻挡的作用，以防止导线152的金属元素扩散至随后形成的焊盘层240(见图7)和/或防止随后形成的焊盘层240的金属元素扩散至第一钝化层220中。具体地，沉积覆盖开口222的侧壁222s和底部222b的第一底部层232a。即，在开口222中共形地形成第一底部层232a。通过共形地形成第一底部层232a，第一底部层232a将沿开口222的侧壁222s以及也沿开口222的底部222b具有基本相等的厚度。第一底部层232a可以使用诸如化学汽相沉积(CVD)、物理汽相沉积(PVD)、等离子体增强CVD(PECVD)、等离子体增强物理汽相沉积(PEPVD)、原子层沉积(ALD)、这些的组合等的工艺形成。
在一些实施例中，第一底部层232a由钽、钛、它们的组合等制成。在一些实施例中，第一底部层232a是金属层。在一些其它实施例中，第一底部层232a是纯金属层或基本纯的金属层，例如，具有高于约百分之99的金属百分比。在一些实施例中，第一底部层232a是纳米晶相(非常小的晶体或晶粒，接近非晶)。在一些实施例中，第一底部层232a具有在约20埃至约30埃的范围内的厚度T1a。在一些实施例中，第一底部层232a通过使用在约475kW至约525kW的范围内的源DC功率的PVD技术来形成。
下一步，在第一底部层232a之上共形地形成第一中间层234a。通过共形地形成第一中间层234a，第一中间层234a将沿开口222的侧壁222s以及也沿开口222的底部222b具有基本相等的厚度。第一中间层234a可以使用将促进共形地形成的工艺来形成，诸如原子层沉积(ALD)。可以可选地使用诸如等离子体增强化学汽相沉积(PECVD)或等离子体增强物理汽相沉积(PEPVD)的其它工艺，其中将偏压施加至衬底110以减小第一中间层234a的厚度变化。在一些实施例中，第一中间层234a通过使用在约475kW至约525kW的范围内的源DC功率的PVD技术来形成。在一些实施例中，第一底部层232a和第一中间层234a利用基本相同的功率(例如，约500W)形成。
在一些实施例中，第一中间层234a由氮化钽、氮化钛、它们的组合等制成。在一些实施例中，第一中间层234a是氮化物层。在一些实施例中，第一中间层234a的金属百分比低于第一底部层232a的金属百分比。在一些实施例中，第一中间层234a是非晶相。在一些实施例中，第一中间层234a具有在约18埃至约22埃的范围内的厚度T2a。在一些实施例中，厚度T2a大于、小于或与第一底部层232a的厚度T1a基本相同。
随后，在第一中间层234a之上共形地形成第一顶部层236a。通过共形地形成第一顶部层236a，第一顶部层236a将沿开口222的侧壁222s以及也沿开口222的底部222b具有基本相等的厚度。第一顶部层236a可以使用将促进共形地形成的工艺来形成，诸如原子层沉积(ALD)。可以可选地使用诸如等离子体增强化学汽相沉积(PECVD)或等离子体增强物理汽相沉积(PEPVD)的其它工艺，其中将偏压施加至衬底以减小第一顶部层236a的厚度变化。在一些实施例中，第一顶部层236a通过使用在约5700kW至约6300kW的范围内的源DC功率的PVD技术来形成。在一些实施例中，第一顶部层236a利用比第一中间层234a的功率大约十倍的功率来形成。
在一些实施例中，第一顶部层236a由氮化钽、氮化钛、它们的组合等制成。在一些实施例中，第一顶部层236a是氮化物层。在一些实施例中，第一顶部层236a的金属百分比低于第一底部层232a的金属百分比。在一些实施例中，第一顶部层236a是多晶相。在一些实施例中，第一顶部层236a具有在约170埃至约190埃的范围内的厚度T3a。在一些实施例中，厚度T3a大于第一中间层234a的厚度T2a。在一些实施例中，第一顶部层236a的厚度T3a大于第一底部层232a的厚度T1a。在图4中，第一底部层232a、第一中间层234a和第一顶部层236a一起称为第一阻挡层230a。
参考图5。在第一阻挡层230a之上共形地形成阻挡层230的第二阻挡层230b。第二阻挡层230b包括第二底部层232b、第二中间层234b和第二顶部层236b。第二底部层232b的形成和材料与第一底部层232a的形成和材料类似或相同，并且因此，在下文中将不再重复这方面的描述。第二中间层234b的形成和材料与第一中间层234a的形成和材料类似或相同，并且因此，在下文中将不再重复这方面的描述。第二顶部层236b的形成和材料与第一顶部层236a的形成和材料类似或相同，并且因此，在下文中将不再重复这方面的描述。
随后，在第二阻挡层230b之上共形地形成阻挡层230的第三阻挡层230c。第三阻挡层230c包括第三底部层232c、第三中间层234c和第三顶部层236c。第三底部层232c的形成和材料与第一底部层232a的形成和材料类似或相同，并且因此，在下文中将不再重复这方面的描述。第三中间层234c的形成和材料与第一中间层234a的形成和材料类似或相同，并且因此，在下文中将不再重复这方面的描述。第三顶部层236c的形成和材料与第一顶部层236a的形成和材料类似或相同，并且因此，在下文中将不再重复这方面的描述。因此，第一阻挡层230a、第二阻挡层230b和第三阻挡层230c一起称为阻挡层230。
参考图6。下一步，在阻挡层230之上形成填充开口222的剩余间隔的导电材料240’。为了清楚起见，阻挡层230的子层(即，图5所示的层)或在图6中未示出。在一些实施例中，导电材料240’是金属层并且可以包括铝(Al)，但是它也可以由铜(Cu)、银(Ag)、金(Au)、镍(Ni)、钨(W)、合金或它们的任何组合。在一些其它实施例中，导电材料240’可以由铝铜(AlCu)制成。在一些实施例中，导电材料240’通过使用溅射、物理汽相沉积(PVD)、化学汽相沉积(CVD)、电化学镀铜(ECP)等来制成。
随后，在导电材料240’之上形成抗反射涂层245’。可以在导电材料240’上方形成抗反射涂层245’，以有助于随后光刻工艺来图案化上面的层。抗反射涂层245’在随后光刻工艺中防止辐射从下方的层反射并且干扰曝光工艺。这种干扰可以增大光刻工艺的临界尺寸。抗反射涂层245’可以包括SiON、聚合物等或它们的组合，并且可以通过CVD、旋涂工艺等或它们的组合来形成。在一些实施例中，抗反射涂层245’在例如大于约300摄氏度的高温下形成，并且阻挡层230可以在用于形成抗反射涂层245’的高温工艺期间防止导线中的金属元素穿过阻挡层230和导电材料240’。抗反射涂层245’具有基于材料和波长足以提供足够的抗反射质量的厚度。
在抗反射涂层245’之上形成第二光刻胶层320。第二光刻胶层320通过旋涂或其它合适的技术来形成。诸如烘烤的其它操作可以在涂覆第二光刻胶层320之后进行。在开口222正上方形成第二光刻胶层320，并且抗反射涂层245’的部分未被第二光刻胶层320覆盖。
参考图7。使用第二光刻胶层320(见图6)作为掩模图案化抗反射涂层245’、导电材料240’和阻挡层230，以在开口中并且在第一钝化层220之上形成抗反射涂层245、焊盘层240和阻挡层230，并且去除第二光刻胶层320。
参考图8。在图7中的结构之上形成第二钝化层250。第二钝化层250的形成和材料与第一钝化层220的形成和材料类似或相同，并且因此，在下文中将不再重复这方面的描述。随后，在第二钝化层250之上形成第三钝化层260。第三钝化层260的形成和材料与ESL210的形成和材料类似或相同，并且因此，在下文中将不再重复这方面的描述。
参考图9A和图9B，其中图9B是图9A中的区域B’的放大图。对第二钝化层250和第三钝化层260实施图案化工艺，从而使得在第二钝化层250和第三钝化层260中形成开口265以暴露抗反射涂层245的顶面。例如，在第三钝化层260之上形成另一图案化的光刻胶，并且实施蚀刻工艺以去除第二钝化层250和第三钝化层260的由图案化的光刻胶暴露的部分。然后在蚀刻工艺之后去除图案化的光刻胶。
图9A和图9B所示的半导体结构包括多层互连结构150、第一钝化层220、阻挡层230和焊盘层240。第一钝化层220位于多层互连结构150之上，并且暴露导线152的部分。在第一钝化层220和导线152之上共形地形成阻挡层230。焊盘层240位于阻挡层230之上，从而使得焊盘层240可以通过阻挡层230电连接至导线152。
阻挡层230包括第一阻挡层230a、第二阻挡层230b和第三阻挡层230c。第二阻挡层230b位于第一阻挡层230a之上，并且第三阻挡层230c位于第二阻挡层230b之上。即，第二阻挡层230b夹在第一阻挡层230a和第三阻挡层230c之间(并且与第一阻挡层230a和第三阻挡层230c直接接触)。第一阻挡层230a夹在导线152(或第一钝化层220)和第二阻挡层230b之间(并且与导线152(或第一钝化层220)和第二阻挡层230b直接接触)。第三阻挡层230c夹在第二阻挡层230b和焊盘层240之间(并且与第二阻挡层230b和焊盘层240直接接触)。
第一阻挡层230a包括第一底部层232a、第一中间层234a和第一顶部层236a。第二阻挡层230b包括第二底部层232b、第二中间层234b和第二顶部层236b。第三阻挡层230c包括第三底部层232c、第三中间层234c和第三顶部层236c。
在一些实施例中，第一底部层232a、第二底部层232b和第三底部层232c的每个由钽、钛、它们的组合等制成。在一些实施例中，第一底部层232a、第二底部层232b和第三底部层232c的每个是金属层并且不含氮。在一些其它实施例中，第一底部层232a、第二底部层232b和第三底部层232c的每个是纯金属层或基本纯的金属层，例如，具有高于约百分之99的金属百分比。在一些实施例中，第一底部层232a、第二底部层232b和第三底部层232c的每个是纳米晶相(非常小的晶体或晶粒，接近非晶)。在一些实施例中，第一底部层232a的厚度T1a、第二底部层232b的厚度T1b和第三底部层232c的厚度T1c的每个在约20埃至约30埃的范围内。在一些实施例中，厚度T1a大于、等于或小于厚度T1b(或T1c)。
在一些实施例中，第一中间层234a、第二中间层234b和第三中间层234c的每个由氮化钽、氮化钛、它们的组合等制成。在一些实施例中，第一中间层234a、第二中间层234b和第三中间层234c的每个是氮化物层，并且具有比第一底部层232a、第二底部层232b和第三底部层232c的每个的氮浓度高的氮浓度。在一些实施例中，第一中间层234a、第二中间层234b和第三中间层234c的每个的金属百分比低于第一底部层232a的金属百分比。在一些实施例中，第一中间层234a、第二中间层234b和第三中间层234c的每个是非晶相。在一些实施例中，第一中间层234a的厚度T2a、第二中间层234b的厚度T2b和第三中间层234c的厚度T2c的每个在约18埃至约22埃的范围内。在一些实施例中，厚度T2a大于、等于或小于厚度T2b(或T2c)。
在一些实施例中，第一顶部层236a、第二顶部层236b和第三顶部层236c的每个由氮化钽、氮化钛、它们的组合等制成。在一些实施例中，第一顶部层236a、第二顶部层236b和第三顶部层236c的每个是氮化物层，并且具有比第一底部层232a、第二底部层232b和第三底部层232c的每个的氮浓度高的氮浓度。在一些实施例中，第一顶部层236a、第二顶部层236b和第三顶部层236c的每个的金属百分比低于第一底部层232a的金属百分比。在一些实施例中，第一顶部层236a、第二顶部层236b和第三顶部层236c的每个是多晶相。在一些实施例中，第一顶部层236a的厚度T3a、第二顶部层236b的厚度T3b和第三顶部层236c的厚度T3c的每个在约170埃至约190埃的范围内。在一些实施例中，厚度T3a大于、等于或小于厚度T3b(或T3c)。
在一些实施例中，第一底部层232a、第一中间层234a和第一顶部层236a包括相同的金属(例如，钽)。在一些实施例中，第二底部层232b、第二中间层234b和第二顶部层236b包括相同的金属(例如，钽)。在一些实施例中，第三底部层232c、第三中间层234c和第三顶部层236c包括相同的金属(例如，钽)。在一些实施例中，阻挡层230具有在约624埃至约726埃的范围内的厚度T。如果厚度T大于约726埃，则阻挡层230可以具有高电阻；如果厚度T小于约624埃，则阻挡层230的电性能可能是不期望的。在一些实施例中，T2a:T3a的比率在约0.094至约0.129的范围内。如果T2a:T3a的比率超出该范围，则阻挡层230可能不满足半导体器件的期望电性能。在一些实施例中，厚度T1a、T2a和T3a的总和在约208埃至约242埃的范围内。如果厚度T1a、T2a和T3a的总和大于约242埃，则阻挡层230可以具有高电阻；如果厚度T1a、T2a和T3a的总和小于约208埃，则阻挡层230的电性能可能是不期望的。在一些实施例中，T1a:T2a:T3a的比率基本等于T1b:T2b:T3b的比率并且基本等于T1c:T2c:T3c的比率。因此，改善了焊盘层240的电性能。在一些实施例中，T1a:T2a:T3a的比率可以在约1.2:1:8.5至约1.3:1:9.5的范围内，例如，约1.25:1:9。如果T1a:T2a:T3a的比率超出该范围，则阻挡层230可能不满足半导体器件的期望电性能。
如图9B所示，因为第一顶部层236a、第二顶部层236b和第三顶部层236c是多晶相，所以可以在其中形成螺纹位错缺陷238。相反，螺纹位错缺陷可能不存在于第一底部层232a、第二底部层232b和第三底部层232c中，因为它们是纳米晶相。在图9B中，因为第一顶部层236a、第二顶部层236b和第三顶部层236c分别形成，并且第二底部层232b和第三底部层232c介于其间，所以第一顶部层236a、第二顶部层236b和第三顶部层236c中的螺纹位错缺陷238彼此未对准。
导线152中的金属元素在热工艺期间(例如，如图6所示的抗反射涂层245’的沉积工艺)可以穿过第一顶部层236a中的螺纹位错缺陷238。但是，金属元素可以被第二底部层232b和第二中间层234b阻挡，因为其中不存在螺纹位错缺陷238。即使稀少或一些金属元素仍然穿过第二底部层232b和第二中间层234b，第二顶部层236b中的螺纹位错缺陷238的未对准配置仍然有助于阻止金属元素的扩散。另外，第三底部层232c、第三中间层234c和第三顶部层236c具有与第二底部层232b、第二中间层234b和第二顶部层236b相同的功能。利用这样的配置，在一些实施例中，半导体结构的故障率(例如，导线152的扩散至焊盘层240的金属元素)减小至低于约1％。
在一些实施例中，半导体结构还包括第一钝化层220和最顶部导电层150g的导线152之间的ESL 210。ESL 210与阻挡层230的第一底部层232a直接接触。在一些实施例中，半导体结构还包括焊盘层240之上的抗反射涂层245。在一些实施例中，半导体结构还包括第二钝化层250和第三钝化层260。第二钝化层250位于第一钝化层220和焊盘层240之上，并且第三钝化层260位于第二钝化层250之上。
图10是根据本发明的一些实施例的图9A中的区域B’的放大图。图10和图9B中的结构之间的差异与阻挡层230中的层的厚度有关。在图10中，第一顶部层236a的厚度T3a大于第二顶部层236b的厚度T3b，并且第二顶部层236b的厚度T3b大于第三顶部层236c的厚度T3c。这可能是因为阻挡层230的沉积速率。例如，第一顶部层236a的沉积速率大于第二顶部层236b的沉积速率，并且第二顶部层236b的沉积速率大于第三顶部层236c的沉积速率。但是，T1a:T2a:T3a的比率基本等于T1b:T2b:T3b的比率，并且基本等于T1c:T2c:T3c的比率。图10中的阻挡层230的其它相关结构细节与图9B中的阻挡层230基本相同或类似，并且因此，在下文中将不再重复这方面的描述。
图11是根据本发明的一些实施例的用于形成半导体结构的方法M的流程图。虽然方法M示出和/或描述为一系列步骤或事件，但是应该理解，方法不限于示出的顺序或步骤。因此，在一些实施例中，步骤可以以与示出的顺序不同的顺序执行，和/或可以同时执行。此外，在一些实施例中，示出的步骤或事件可以细分为多个步骤或事件，这些步骤或事件可以在不同的时间或者与其它步骤或子步骤同时执行。在一些实施例中，可以省略一些示出的步骤或事件，并且可以包括其它未示出的步骤或事件。
在框S12处，在导线之上形成钝化层。图2示出了对应于框S12中的步骤的一些实施例的截面图。在框S14处，在钝化层中形成开口。图3A和图3B示出了对应于框S14中的步骤的一些实施例的截面图。在框S16处，在钝化层的开口中形成阻挡层的第一底部层、第一中间层和第一顶部层。图4示出了对应于框S16中的步骤的一些实施例的截面图。在框S18处，在第一顶部层之上形成阻挡层的第二底部层、第二中间层和第二顶部层。图5示出了对应于框S18中的步骤的一些实施例的截面图。在框S20处，在第二顶部层之上形成阻挡层的第三底部层、第三中间层和第三顶部层。图5示出了对应于框S20中的步骤的一些实施例的截面图。在框S22处，在阻挡层之上形成导电材料。图6示出了对应于框S22中的步骤的一些实施例的截面图。在框S24处，图案化阻挡层和导电材料。图7示出了对应于框S24中的步骤的一些实施例的截面图。
基于以上讨论，可以看出本发明提供了优势。但是，应该理解，其它实施例可以提供额外的优势，并且本文不必公开所有优势，并且没有特定的优势对于所有实施例都是需要的。一个优势是，阻挡层的第二底部层和/或第三底部层阻止导线的金属元素扩散至焊盘层。另一个优势是，阻挡层的第一顶部层、第二顶部层和第三顶部层具有未对准的螺纹位错缺陷，金属元素不容易穿过所有的第一顶部层、第二顶部层和第三顶部层。利用这样的配置，在一些实施例中，半导体结构的故障率(例如，导线的扩散至焊盘层的金属元素)减小至低于约1％。
根据一些实施例，半导体结构包括多层互连结构、钝化层、阻挡层和焊盘层。钝化层位于多层互连结构之上。阻挡层内衬钝化层的内侧壁、钝化层的顶面和多层互连结构的导线的顶面。阻挡层包括第一层、第二层、第三层和第四层。第一层是纳米晶相。第二层位于第一层之上并且是非晶相。第三层位于第二层之上并且是多晶相。第四层位于第三层之上并且是纳米晶相。焊盘层位于阻挡层之上。
在一些实施例中，所述第二层的材料与所述第三层的材料基本相同。在一些实施例中，所述第一层的材料与所述第四层的材料基本相同。在一些实施例中，所述第三层的厚度大于所述第四层的厚度。在一些实施例中，所述第一层、所述第二层和所述第三层的厚度的比率在约1.2:1:8.5至约1.3:1:9.5的范围内。在一些实施例中，所述第一层、所述第二层和所述第三层的厚度的总和在约208埃至约242埃的范围内。
根据一些实施例，半导体结构包括多层互连结构、钝化层、焊盘层和阻挡层。钝化层位于多层互连结构之上。焊盘层部分位于钝化层中并且位于多层互连结构之上。阻挡层位于多层互连结构和焊盘层之间。阻挡层包括第一含钽层、第二含钽层和第三含钽层。第二含钽层位于第一含钽层之上。第三含钽层位于第二含钽层之上。第一含钽层和第三含钽层具有比第二含钽层的氮浓度高的氮浓度，并且第二含钽层的厚度小于第三含钽层的厚度。
在一些实施例中，所述第二层的金属百分比高于所述第一层的金属百分比。在一些实施例中，所述第二层是基本纯的金属层。在一些实施例中，所述第二层不含氮。在一些实施例中，所述第二层是纳米晶相。在一些实施例中，所述第一层是多晶相。在一些实施例中，半导体结构还包括：第四含钽层，位于所述第二含钽层和所述第三含钽层之间，其中，所述第四含钽层的厚度与所述第三含钽层的厚度的比率在约0.094至约0.129的范围内。在一些实施例中，所述第一层与所述第二层接触。在一些实施例中，所述第一层中的螺纹位错缺陷与所述第三层的螺纹位错缺陷未对准。
根据一些实施例，用于制造半导体结构的方法包括在导线之上形成钝化层。在钝化层中形成开口以暴露导线。在钝化层的开口中形成阻挡层。形成阻挡层包括形成是纳米晶相的第一层。在第一层之上形成是非晶相的第二层。在第二层之上形成是多晶相的第三层。在第三层之上形成是纳米晶相的第四层。在阻挡层上方形成导电材料。图案化阻挡层和导电材料。
在一些实施例中，所述第二层的材料与所述第三层的材料基本相同。在一些实施例中，所述第一层的材料与所述第四层的材料基本相同。在一些实施例中，用于形成所述第三层的功率高于用于形成所述第四层的功率。在一些实施例中，所述第四层的金属百分比高于所述第三层的金属百分比。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
多层互连结构；
钝化层，位于所述多层互连结构之上；
阻挡层，内衬所述钝化层的内侧壁、所述钝化层的顶面和所述多层互连结构的导线的顶面，其中，所述阻挡层包括：
第一层，是纳米晶相；
第二层，位于所述第一层之上并且是非晶相；
第三层，位于所述第二层之上并且是多晶相；以及
第四层，位于所述第三层之上并且是纳米晶相；以及
焊盘层，位于所述阻挡层之上。
2.根据权利要求1所述的半导体结构，其中，所述第二层的材料与所述第三层的材料基本相同。
3.根据权利要求1所述的半导体结构，其中，所述第一层的材料与所述第四层的材料基本相同。
4.根据权利要求1所述的半导体结构，其中，所述第三层的厚度大于所述第四层的厚度。
5.根据权利要求1所述的半导体结构，其中，所述第一层、所述第二层和所述第三层的厚度的比率在约1.2:1:8.5至约1.3:1:9.5的范围内。
6.根据权利要求1所述的半导体结构，其中，所述第一层、所述第二层和所述第三层的厚度的总和在约208埃至约242埃的范围内。
7.一种半导体结构，包括：
多层互连结构；
钝化层，位于所述多层互连结构之上；
焊盘层，部分位于所述钝化层中并且位于所述多层互连结构之上；以及
阻挡层，位于所述多层互连结构和所述焊盘层之间，其中，所述阻挡层包括：
第一含钽层；
第二含钽层，位于所述第一含钽层之上；以及
第三含钽层，位于所述第二含钽层之上，其中，所述第一含钽层和所述第三含钽层具有比所述第二含钽层的氮浓度高的氮浓度，并且所述第二含钽层的厚度小于所述第三含钽层的厚度。
8.根据权利要求7所述的半导体结构，其中，所述第二层的金属百分比高于所述第一层的金属百分比。
9.根据权利要求7所述的半导体结构，其中，所述第二层是基本纯的金属层。
10.一种用于制造半导体结构的方法，包括：
在多层互连结构之上形成钝化层；
在所述钝化层中形成开口以暴露所述多层互连结构；
形成内衬所述钝化层中的所述开口的阻挡层，包括：
形成是纳米晶相的第一层；
在所述第一层之上形成是非晶相的第二层；
在所述第二层之上形成是多晶相的第三层；以及
在所述第三层之上形成是纳米晶相的第四层；
在所述阻挡层上方形成导电材料；以及
图案化所述阻挡层和所述导电材料。
CN202110563281.1A 2021-01-27 2021-05-24 半导体结构及其制造方法 Pending CN114823617A (zh)

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JP3625652B2 (ja) 1998-06-30 2005-03-02 シャープ株式会社 半導体装置の製造方法
US6187673B1 (en) * 1998-09-03 2001-02-13 Micron Technology, Inc. Small grain size, conformal aluminum interconnects and method for their formation
US6294836B1 (en) * 1998-12-22 2001-09-25 Cvc Products Inc. Semiconductor chip interconnect barrier material and fabrication method
US6140231A (en) * 1999-02-12 2000-10-31 Taiwan Semiconductor Manufacturing Company Robust diffusion barrier for Cu metallization
US7049702B2 (en) * 2003-08-14 2006-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Damascene structure at semiconductor substrate level
US7453149B2 (en) * 2004-08-04 2008-11-18 Taiwan Semiconductor Manufacturing Co., Ltd. Composite barrier layer
KR100642750B1 (ko) 2005-01-31 2006-11-10 삼성전자주식회사 반도체 소자 및 그 제조 방법
US7229918B2 (en) * 2005-02-14 2007-06-12 Infineon Technologies Ag Nitrogen rich barrier layers and methods of fabrication thereof
US7449409B2 (en) 2005-03-14 2008-11-11 Infineon Technologies Ag Barrier layer for conductive features
US9773732B2 (en) 2013-03-06 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for packaging pad structure
US20150001720A1 (en) 2013-06-27 2015-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect Structure and Method for Forming Interconnect Structure
US9418951B2 (en) * 2014-05-15 2016-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with composite barrier layer under redistribution layer and manufacturing method thereof
US10720581B2 (en) 2018-10-30 2020-07-21 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for resistive random access memory

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