CN114823555B - 封装结构及其制作方法 - Google Patents

封装结构及其制作方法 Download PDF

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Publication number
CN114823555B
CN114823555B CN202210232068.7A CN202210232068A CN114823555B CN 114823555 B CN114823555 B CN 114823555B CN 202210232068 A CN202210232068 A CN 202210232068A CN 114823555 B CN114823555 B CN 114823555B
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layer
flexible
area
fan
hard board
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CN114823555A (zh
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陈先明
徐小伟
黄高
黄本霞
林文健
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Zhuhai Yueya Semiconductor Co ltd
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Zhuhai Yueya Semiconductor Co ltd
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Priority to CN202210232068.7A priority Critical patent/CN114823555B/zh
Publication of CN114823555A publication Critical patent/CN114823555A/zh
Priority to US17/955,759 priority patent/US20230282565A1/en
Priority to KR1020220129833A priority patent/KR20230131084A/ko
Priority to TW111138870A priority patent/TW202349648A/zh
Priority to JP2022183955A priority patent/JP2023129238A/ja
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Abstract

本申请提供一种封装结构及其制作方法，所述封装结构包括多个封装单元，所述封装单元包括硬板区、绕折区和扇出区；在所述封装结构中，所述封装单元的所述硬板区堆叠设置，部分或全部所述扇出区封装有芯片，部分或全部封装有芯片的所述扇出区通过所述绕折区弯折后，与所述硬板区堆叠设置。如此设计，每个扇出区单独封装之后再彼此堆叠封装，实现芯片与芯片、芯片与基板之间的互联，且彼此封装单元之间不受干扰。

Description

封装结构及其制作方法
技术领域
本申请实施例涉及半导体封装技术领域，尤其涉及一种封装结构及其制作方法。
背景技术
电子产品微型化是当今的发展趋势，带给半导体行业的趋势是集成功能广泛、封装密度增加。在半导体封测领域，常规的封装方式是在基板XY方向设置多颗芯片或元器件来提高封装功能的集成化，此方式有其自身的缺陷，即增加了XY方向的封装面积，不利于产品的微型化。因此，采用更先进的封装方式减小封装面积是当下封装技术发展的方向。
现有封装技术中，MCP(Multiple Chip Package)多芯片封装和PoP(Package onPackage)叠层封装技术可实现在Z方向的堆叠，从而减小X、Y方向的封装面积。
MCP封装技术在一个塑封外壳内Z方向堆叠多颗芯片，实现封装集成化的同时同步获得XY方向的小型化。MCP封装芯片堆叠方式分为金字塔堆叠和悬空式堆叠，金字塔模式堆叠限定了堆叠芯片的尺寸大小及堆叠顺序，悬空式堆叠同样对芯片尺寸限制，同时由于芯片悬空，容易因应力问题导致芯片crack，特别是薄芯片，需要在悬空位置打线的产品则风险更高。
对于PoP封装而言，由于需要在两个封装体之间实现互联，通常为BGA(Ball GridArray，球栅阵列)互联，互联位置同时兼具电气导通与物理间接的功能，而往往封装体之间容易因为CTE(coefficient of thermal expansion，热膨胀系数)之间的差异等因素存在应力，应力存在导致封装体产生翘曲，进而封装体与封装体之间互联、低层封装体与母基板之间互联失效。
发明内容
有鉴于此，本申请实施例的目的在于提出一种封装结构及制作方法。
第一方面，本申请实施例提供一种封装结构，所述封装结构包括多个封装单元，所述封装单元包括硬板区、绕折区和扇出区；
在所述封装结构中，所述封装单元的所述硬板区堆叠设置，部分或全部所述扇出区封装有芯片，部分或全部封装有芯片的所述扇出区通过所述绕折区弯折后，与所述硬板区堆叠设置。
在一种可能的实施方式中，所述封装单元包括挠性介质层以及设置于所述挠性基板一侧的第一线路层，所述挠性介质层为采用挠性材料制成的挠性板。
在一种可能的实施方式中，所述封装单元包括挠性覆铜板，所述挠性覆铜板包括挠性介质层以及设置于所述挠性介质层一侧的铜箔层，所述挠性介质层为采用挠性材料制成的挠性板，所述第一线路层位于所述铜箔层。
在一种可能的实施方式中，所述封装单元在所述硬板区封装有单颗芯片或垂直堆叠多颗芯片。
在一种可能的实施方式中，所述封装单元在所述扇出区封装有单颗芯片或垂直堆叠多颗芯片。
在一种可能的实施方式中，在所述封装结构中，至少两个所述扇出区相对于所述硬板区的延伸方向不同。
在一种可能的实施方式中，所述封装结构在所述硬板区设置有沿堆叠方向延伸的铜柱，以及在所述硬板区的两侧设置有与所述铜柱连通的第二线路层。
在一种可能的实施方式中，所述第二线路层的外侧设置有阻焊层和表面处理层。
在一种可能的实施方式中，在所述绕折区和所述扇出区，所述挠性介质层在远离所述第一线路层的一侧设置有加强片。
在一种可能的实施方式中，在所述绕折区和所述扇出区，所述第一线路层在远离所述挠性介质层的一侧设置有用于绝缘的覆盖膜。
第二方面，本申请实施例提供了一种封装结构的制作方法，包括以下步骤：
A)提供多张挠性基板，挠性基板包括硬板区、绕折区和扇出区；
B)在挠性基板的一侧形成第一线路层；
C)对多张挠性基板在硬板区进行压合粘结，形成多层堆叠结构；
D)在多层堆叠结构的硬板区，制作用于层间连接的铜柱；
E)在多层堆叠结构的硬板区两侧，制作与铜柱连接的第二线路层；
F)将多层堆叠结构在绕折区和扇出区两侧的介质材料去除；
G)封装芯片，并将部分或全部扇出区通过绕折区弯折后，与硬板区堆叠设置。
在一种可能的实施方式中，所述步骤A和步骤B包括：
提供多张挠性覆铜板，挠性覆铜板包括挠性介质层和位于挠性介质层两侧的铜箔层；
对要制作第一线路层的一面贴覆感光抗蚀刻膜，另外一面不需贴膜；
对贴有感光抗蚀刻膜的挠性基板进行单面曝光；
通过显影将要蚀刻的铜箔层露出；
蚀刻挠性介质层两侧露出的铜箔层，形成第一线路层。
在一种可能的实施方式中，所述步骤B还包括：
在第一线路层远离挠性介质层的一侧整面压合用于绝缘的覆盖膜；
通过图形转移的方式在绕折区和扇出区保留覆盖膜。
在一种可能的实施方式中，所述步骤C包括：
依据堆叠顺序，在需要做粘结的线路面预贴粘结片；
在绕折区及扇出区预贴耐高温可剥离胶；
对挠性基板非粘结面压合绝缘介质层；
对多层挠性基板进行压合粘结，形成多层堆叠结构。
在一种可能的实施方式中，所述步骤D包括：
在多层堆叠结构的硬板区，进行机械钻孔形成层间导通的过孔；
在多层堆叠结构的表面制作种子层；
贴感光抗镀干膜，并通过图形转移的方式将需要电镀填孔的孔露出；
进行电镀填孔；
贴感光抗镀干膜，通过图形转移的方式将需要做铜柱位置露出；
电镀制作铜柱。
在一种可能的实施方式中，所述步骤E包括：
采用图形转移的方式制作第二线路层；
在第二线路层的外侧制作阻焊层和表面处理层。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请一个或多个实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a至1r为本申请实施例提供的一种封装结构在制作过程中的示意图；
图2为本申请实施例提供的一种封装结构的结构示意图；
图3为本申请实施例提供的另一种封装结构的结构示意图；
图4为本申请实施例提供的另一种封装结构的结构示意图；
图5为本申请实施例提供的另一种封装结构的结构示意图。
附图标记说明：
1-挠性覆铜板、2-挠性介质层、3-铜箔层、4-感光抗蚀刻干膜、5-第一线路层、6-覆盖膜、7-耐高温可剥离胶、8-粘结片、9-绝缘介质层、10-过孔、11-种子层、12-第一感光抗镀干膜、13-第二感光抗镀干膜、14-铜柱层、15-第二绝缘介质层、16-阻焊层、17-表面处理层、18-第二线路层、19-加强片、20、芯片。
100-硬板区、200-绕折区、300-扇出区。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1a-1r为本申请实施例提供的一种封装结构在制作过程中的示意图，如图1a-1r所示，该封装结构的制作方法包括以下步骤。
如图1a所示，提供多张挠性基板(步骤A)；
挠性基板为采用挠性材料制作的板状结构，能够实现挠性弯折，即能够在外力作用下进行弯折，且弯折后在无外力的作用下不会恢复至弯折前的状态。根据不同的设计要求，将挠性基板分为硬板区、绕折区和扇出区。
在一些实施方式中，挠性基板可以在挠性介质层单面或双面粘接有铜箔的挠性覆铜板(Flexible Copper Clad Laminate，FCCL)。优选地，本实施例中的挠性覆铜板1为双面均具有铜箔的结构，即包括挠性覆铜板包括挠性介质层2以及位于挠性介质层2两侧面的铜箔层3。
接着，如图1c所示，在挠性基板上的一侧形成第一线路层(步骤B)；
第一线路层通常通过图形转移的方式形成。例如，在可能的实施方式中，步骤B包括在挠性基板上施加种子层，在种子层上施加金属层，在金属层上施加光刻胶层，图形化光刻胶层以形成暴露出金属层的图案，蚀刻图案下方的金属层和种子层以形成线路层。
通过上述描述可知，在本实施例中挠性基板为双面均具有铜箔层的挠性覆铜板1，因此步骤B包括在挠性覆铜板1的一面形成第一线路层5，并将另外一面铜完全蚀刻以露出挠性介质层2，具体方法包括：
如图1b和图1c所示，仅对要制作第一线路层的一面贴覆感光抗蚀刻干膜4，另外一面不需贴膜；然后，对贴好感光抗蚀刻干膜4的挠性基板进行单面曝光，另外一面不曝光；通过显影将要蚀刻的铜露出来，并通过酸性蚀刻的方式将露出的铜蚀刻干净；褪膜后形成一面形成第一线路层，另一面直接露出挠性介质层的结构，如图1c所示。
在可能的实施方式中，步骤B还包括：
如图1d所示，在挠性基板的第一线路层5上压合覆盖膜6；
其中，挠性基板包括硬板区100、绕折区200和扇出区。覆盖膜6起到线路绝缘的作用，仅在绕折区200和扇出区300保留即可，具体方法包括：
在绕折区200及扇出区300整面压合一层感光型覆盖膜6，通过曝光显影的方式，在绕折区200和扇出区300选择性保留覆盖膜6，其它部分可以全部显影消除；也可使用非感光性覆盖膜6，在压合前通过激光切割或机械铣的方式除去覆盖膜6上不需要保留的部分。
接着，对多张挠性基板在硬板区进行压合粘结，形成多层堆叠结构(步骤C)；
在一个实施例中，如图1e至图1g所示，步骤C包括：
依据堆叠的上下顺序关系，在需要做粘结的线路面预贴粘结片8，粘结片8的主要作用是将多个挠性基板进行粘连结合成一体，形成多层堆叠结构。粘结片9可事先通过机械锣或激光切割的方式制作，对不需要粘结的部分切割去除，保留下需要起粘结作用的部分；
在绕折区及扇出区预贴耐高温可剥离胶7，设置耐高温可剥离胶7的目的是隔离两侧的介质层，通过剥离耐高温可剥离胶7可分离两侧的介质层；
依据多层挠性基板的压叠板顺序关系，对挠性基板非粘结面压合第一绝缘介质层9，第一绝缘介质层9可采用半固化片(PP)或ABF(Ajinomoto build-up film substrate)类材料。
然后，对多层挠性基板进行压合粘结，形成如图1g所示的多层堆叠结构。
接着，如图1o，在多层堆叠结构的硬板区，制作用于层间连接的铜柱(步骤D)；
如图1h至图1o所示，在可能的实施方式中，该方法包括：
在多层堆叠结构的硬板区，进行机械钻孔或激光钻“X”型孔形成层间导通的过孔10；完成过孔10后，在多层堆叠结构的表面制作一层薄金属，作为后续电镀的导通种子层11，种子层11的制作方法包括：
对过孔10之后的多层堆叠结构进行除胶渣处理；
对除胶渣之后的多层堆叠结构整板进行Sputter加工，溅射约1μm的金属Ti、0.8～4μm厚金属Cu；
对加工Sputter之后的多层挠性板进行PTH，沉积0.6～1μm左右的金属Cu。
完成种子层11的制作之后，对整板贴第一感光抗镀干膜12，并通过图形转移的方式将需要电镀填孔的孔露出；然后，通过电镀填孔，将孔填平；电镀填孔之后，在现有基础上贴第二感光抗镀干膜13，然后通过曝光，显影，将需要做铜柱位置露出；对上一步已显影的挠性基板进行等离子清洗之后做铜柱电镀，从而形成层间连接的铜柱层14。
然后，将第一感光抗镀干膜12和第二感光抗镀干膜13褪去，在整板蚀刻种子层，种子层可以包括钛、铜、钛铜或钛钨合金等，种子层可以通过沉积、化学镀或溅射的方式制作。
接着压合第二绝缘介质层15，将第二绝缘介质层15热固化之后，借助磨板或等离子蚀刻的方式减薄部分第二绝缘介质层15，以使铜柱层14露出，便于后续制作层间导通。
接着，如图1p所示，在多层堆叠结构的硬板区两侧，制作与铜柱连接的第二线路层(步骤E)；
第二线路层18可以采用图形转移的方式实现，例如，在一种实施方式中，包括制作种子层-贴膜-曝光-显影-电镀-褪膜-蚀刻种子层；
步骤E还可以包括制作阻焊层16和表面处理层17。其中，阻焊层16的制作方式为滚涂或丝印的方式；表面处理方式为电镀镍金、镍钯金或OSP(Organic SolderabilityPreservatives，有机保焊剂)。
接着，如图1q所示，将多层堆叠结构在绕折区和扇出区两侧的介质材料去除(步骤F)；
在步骤F中，通过机械控深锣的方式，锣至内层耐高温胶位置，并将需要移除的介质层随耐高温胶一并撕除。
如图1r所示，在可能的实施方式中，还可以在挠性介质层远离第一线路层叠一侧，对扇出区部分，根据实际需要可选择贴加强片19以增加刚性。
接着，封装芯片，并将部分或全部扇出区通过绕折区弯折后，与硬板区堆叠设置(步骤G)；请参考图2至图5。
本申请实施例提供了一种通过上述制作方法制作的封装结构，封装结构包括多个封装单元，封装单元包括硬板区、绕折区和扇出区；
在封装结构中，封装单元的硬板区堆叠设置，部分或全部扇出区封装有芯片，部分或全部封装有芯片的扇出区通过绕折区弯折后，与硬板区堆叠设置。
可选的，封装单元包括挠性介质层以及设置于挠性基板一侧的第一线路层，挠性介质层为采用挠性材料制成的挠性板。
可选的，封装单元包括挠性覆铜板，挠性覆铜板包括挠性介质层以及设置于挠性介质层一侧的铜箔层，挠性介质层为采用挠性材料制成的挠性板，第一线路层位于铜箔层。
可选的，封装单元在硬板区封装有单颗芯片或垂直堆叠多颗芯片。
可选的，封装单元在扇出区封装有单颗芯片或垂直堆叠多颗芯片。
可选的，在封装结构中，至少两个扇出区相对于硬板区的延伸方向不同。
可选的，封装结构在硬板区设置有沿堆叠方向延伸的铜柱，以及在硬板区的两侧设置有与铜柱连通的第二线路层。
可选的，第二线路层的外侧设置有阻焊层和表面处理层。
可选的，在绕折区和扇出区，挠性介质层在远离第一线路层的一侧设置有加强片。
可选的，在绕折区和扇出区，第一线路层在远离挠性介质层的一侧设置有用于绝缘的覆盖膜。
图2为本申请实施例提供的一种封装结构的结构示意图，如图2所示，在该封装结构中，部分扇出区300封装芯片(Die)20之后再通过绕折区200翻折与硬板区100堆叠，保留部分不需要做封装的扇出区300。
图3为本申请实施例提供的另一种封装结构的结构示意图，如图3所示，在该封装结构中，将所有扇出区300封装芯片20之后，选择性通过绕折区200翻折与硬板区100堆叠。
图4为本申请实施例提供的另一种封装结构的结构示意图，如图4所示，在该封装结构中，将所有扇出区300封装芯片20之后，均通过绕折区200翻折与硬板区100堆叠。且在硬板区100和扇出区200均封装有单颗芯片20。
图5为本申请实施例提供的另一种封装结构的结构示意图，如图5所示，在该封装结构中，将所有扇出区300封装芯片20之后，均通过绕折区200翻折与硬板区100堆叠。且在硬板区100和扇出区200均堆叠封装两颗芯片20。
但是本申请实施例提供的封装结构并不局限于此，例如，可以在封装位置封装多颗堆叠的芯片，还可以在硬板区的双边、三边、四边实施扇出封装。
在本申请实施例提供的封装机构及制作方法中，使用挠性材料特性，在挠性材料上制作多个X、Y平面扇出互联封装模块，每个模块单独封装之后再彼此堆叠封装，并通过在挠性基板内布线实现芯片与芯片、芯片与基板之间的互联，彼此封装体之间不受干扰。
对比常规PoP封装，规避了翘曲对电气互联的影响，对比常规MCP封装，封装芯片尺寸不受限定，芯片无悬空堆叠带来的可靠性风险。同时，可实现将部分扇出区域与硬板区域垂直堆叠的同时，还可根据具体需求保留部分扇出区域，封装形式更灵活多变。
另外，根据挠性材料特性可多个模块多角度、多方位、多功能自由弯折，实现更多芯片的封装集成，同时缩小了X、Y的占用面积。
在本申请实施例的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请实施例中的具体含义。
此外，上文所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
至此，已经结合附图所示的优选实施方式描述了本申请的技术方案，但是，本领域技术人员容易理解的是，本申请的保护范围显然不局限于这些具体实施方式。在不偏离本申请的原理的前提下，本领域技术人员可以对相关技术特征作出等同的更改或替换，这些更改或替换之后的技术方案都将落入本申请的保护范围之内。

Claims (15)

1.一种封装结构，其特征在于，所述封装结构包括多个封装单元，所述封装单元包括硬板区、绕折区和扇出区；
在所述封装结构中，所述封装单元的所述硬板区堆叠设置，部分或全部所述扇出区封装有芯片，部分或全部封装有芯片的所述扇出区通过所述绕折区弯折后，与所述硬板区堆叠设置；其中，所述封装单元包括挠性介质层以及设置于所述挠性介质层一侧的第一线路层，所述挠性介质层为采用挠性材料制成的挠性板；
所述封装结构在所述硬板区设置有沿堆叠方向延伸的铜柱。
2.根据权利要求1所述的封装结构，其特征在于，所述封装单元包括挠性覆铜板，所述挠性覆铜板包括挠性介质层以及设置于所述挠性介质层一侧的铜箔层，所述挠性介质层为采用挠性材料制成的挠性板，所述第一线路层位于所述铜箔层。
3.根据权利要求1或2所述的封装结构，其特征在于，所述封装单元在所述硬板区封装有单颗芯片或垂直堆叠多颗芯片。
4.根据权利要求3所述的封装结构，其特征在于，所述封装单元在所述扇出区封装有单颗芯片或垂直堆叠多颗芯片。
5.根据权利要求1所述的封装结构，其特征在于，在所述封装结构中，至少两个所述扇出区相对于所述硬板区的延伸方向不同。
6.根据权利要求1所述的封装结构，其特征在于，所述封装结构在所述硬板区的两侧设置有与所述铜柱连通的第二线路层。
7.根据权利要求6所述的封装结构，其特征在于，所述第二线路层的外侧设置有阻焊层和表面处理层。
8.根据权利要求2所述的封装结构，其特征在于，在所述绕折区和所述扇出区，所述挠性介质层在远离所述第一线路层的一侧设置有加强片。
9.根据权利要求2所述的封装结构，其特征在于，在所述绕折区和所述扇出区，所述第一线路层在远离所述挠性介质层的一侧设置有用于绝缘的覆盖膜。
10.一种封装结构的制作方法，其特征在于，包括以下步骤：
A)提供挠性基板，挠性基板包括硬板区、绕折区和扇出区；
B)在挠性基板的一侧形成第一线路层；
C)对多张挠性基板在硬板区进行压合粘结，形成多层堆叠结构；
D)在多层堆叠结构的硬板区，制作用于层间连接的铜柱；
E)在多层堆叠结构的硬板区两侧，制作与铜柱连接的第二线路层；
F)将多层堆叠结构在绕折区和扇出区两侧的介质材料去除；
G)封装芯片，并将部分或全部扇出区通过绕折区弯折后，与硬板区堆叠设置。
11.根据权利要求10所述的制作方法，其特征在于，所述步骤A和步骤B包括：
提供多张挠性覆铜板，挠性覆铜板包括挠性介质层和位于挠性介质层两侧的铜箔层；
对要制作第一线路层的一面贴覆感光抗蚀刻膜，另外一面不需贴膜；
对贴有感光抗蚀刻膜的挠性基板进行单面曝光；
通过显影将要蚀刻的铜箔层露出；
蚀刻挠性介质层两侧露出的铜箔层，形成第一线路层。
12.根据权利要求11所述的制作方法，其特征在于，所述步骤B还包括：
在第一线路层远离挠性介质层的一侧整面压合用于绝缘的覆盖膜；
通过图形转移的方式在绕折区和扇出区保留覆盖膜。
13.根据权利要求10所述的制作方法，其特征在于，所述步骤C包括：
依据堆叠顺序，在需要做粘结的线路面预贴粘结片；
在绕折区及扇出区预贴耐高温可剥离胶；
对挠性基板非粘结面压合绝缘介质层；
对多层挠性基板进行压合粘结，形成多层堆叠结构。
14.根据权利要求10所述的制作方法，其特征在于，所述步骤D包括：
在多层堆叠结构的硬板区，进行机械钻孔形成层间导通的过孔；
在多层堆叠结构的表面制作种子层；
贴感光抗镀干膜，并通过图形转移的方式将需要电镀填孔的孔露出；
进行电镀填孔；
贴感光抗镀干膜，通过图形转移的方式将需要做铜柱位置露出；
电镀制作铜柱。
15.根据权利要求10所述的制作方法，其特征在于，所述步骤E包括：
采用图形转移的方式制作第二线路层；
在第二线路层的外侧制作阻焊层和表面处理层。
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