CN114783879A - Device manufacturing method for improving radiation resistance of super-junction VDMOS device - Google Patents
Device manufacturing method for improving radiation resistance of super-junction VDMOS device Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention relates to a device manufacturing method for improving the radiation resistance of a super-junction VDMOS device, belonging to the field of semiconductor device manufacturing; the Schottky communicated with the source electrode is arranged in the JFET region of the plane gate super-junction VDMOS, and holes generated in the process of a heavy ion incidence device can be extracted quickly by arranging the Schottky structure, so that the number of the holes flowing through the P-type base region is reduced, the opening of a parasitic transistor is effectively inhibited, and the single-particle burnout resistance of the device is improved; the structure can effectively discharge holes generated in the incident process of heavy ions, reduce the accumulation condition of the holes under the gate oxide layer, improve the single particle resistance of the plane gate super junction device, and is compatible with the conventional super junction VDMOS processing technology and easy to process.
Description
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and relates to a device manufacturing method for improving the radiation resistance of a super-junction VDMOS device.
Background
The power VDMOS device is used as a multi-photon conductive unipolar device, has no minority carrier storage effect, and has the advantages of high working frequency, high switching speed, low switching loss and the like. Meanwhile, the power VDMOS is a voltage-controlled device, has high input impedance, needs small driving current when used as a power switch, has a simple driving circuit, has a negative temperature coefficient, does not have the secondary breakdown problem of a bipolar transistor, and has a large safe working area. VDMOS is therefore an ideal power device, both for switching and linear applications.
When the power VDMOS device is used as a switch, the power VDMOS device has high breakdown voltage and low on-resistance. However, the power VDMOS device has the problem of "silicon limit", and the breakdown voltage of the device is increased while the conduction loss of the device is correspondingly increased, so that the overall performance of the system is reduced, and the application of the power VDMOS device in the high-voltage and high-power field is limited. The super-junction VDMOS device breaks through the silicon limit in the traditional sense, namely the breakdown voltage of the device is improved while the on-resistance is greatly reduced, the relation between the breakdown voltage and the on-resistance is changed from the original proportional ratio of 2.5 th power to approximate linearity, and therefore the power loss of the device is greatly reduced. Due to the excellent electrical characteristics of the super junction device, the super junction device is gradually an irreplaceable component in a power electronic system in the high voltage field.
Electronic components which are not subjected to reinforcement design are very susceptible to the influence of radiation environment to generate single event effect when working in the field of aerospace, so that the electrical performance of the components is degraded and even loses efficacy, and even equipment such as a space vehicle and a satellite is abnormal or fails, thereby causing huge potential safety hazard.
In order to improve the radiation resistance of the conventional power VDMOS device, the method is mainly comprehensively carried out from multiple aspects of material selection, structure improvement, process optimization, packaging technology and the like. The material can be selected from SiC, GaN and other wide bandgap semiconductor materials, the structure can adopt deep P + injection, a buried oxide layer, a heavy doping buffer and the like, the process optimization mainly adopts reasonable annealing temperature and a gate-last process to improve the quality of a gate oxide layer so as to improve the total dose radiation resistance of the device, and the package can adopt metal, ceramic package or metal-based composite material and other sealing tube shells. However, the radiation-resistant reinforcing means for the super junction power VDMOS device does not form a unified theory.
Disclosure of Invention
The invention solves the technical problems that: the defects in the prior art are overcome, the device manufacturing method for improving the radiation resistance of the super-junction VDMOS device is provided, holes generated in the incident process of heavy ions can be effectively discharged, the gathering condition of the holes under a gate oxide layer is reduced, the single particle resistance of the plane gate super-junction device is improved, and meanwhile, the method is compatible with a conventional super-junction VDMOS processing technology and easy to process.
The technical scheme of the invention is as follows:
a device manufacturing method for improving radiation resistance of a super junction VDMOS device comprises the following steps:
selecting an N + type silicon substrate slice; sequentially growing 3 epitaxial layers on the upper surface of the N + type silicon substrate slice to obtain an epitaxial slice;
etching the upper surface of the epitaxial wafer to form a groove;
filling the groove in three layers through P-type silicon until the groove is filled;
carrying out grinding treatment on the upper surface of the epitaxial wafer filled with the P-type silicon to obtain a super junction structure; carrying out P-body mask photoetching on the upper surface of the epitaxial wafer, and forming a P-body region by boron implantation and diffusion junction-pushing processes;
carrying out N + mask photoetching on the upper surface of the epitaxial wafer, and forming an N + source region through phosphorus injection and diffusion junction pushing processes;
oxidizing the upper surface of the epitaxial wafer to generate a gate oxide layer, and depositing polycrystalline silicon on the upper surface of the gate oxide layer to form a gate electrode;
carrying out photoetching treatment on the upper surface of the gate electrode, and evaporating aluminum to form a Schottky groove;
depositing a silicon dioxide dielectric layer on the upper surface of the epitaxial wafer, and etching the upper surface of the silicon dioxide dielectric layer; carrying out metallization treatment to form source metal;
passivating and etching the PAD area on the upper surface of the source metal;
and carrying out metallization treatment on the lower surface of the N + type silicon substrate in the epitaxial wafer to form drain metal, thereby finishing the VDMOS manufacturing.
In the device manufacturing method for improving the radiation resistance of the super-junction VDMOS device, the doping concentration of the N + type silicon substrate is 1E20cm2。
In the device manufacturing method for improving the radiation resistance of the super-junction VDMOS device, the total thickness of the 3 epitaxial layers is 40-50 mu m; wherein the doping concentration of the epitaxial layer on the N + type silicon substrate slice is 0.5E 15cm2-1.5E 15cm2(ii) a The doping concentration of the topmost epitaxial layer is 2.5E 15cm2-3.5E 15cm2。
In the device manufacturing method for improving the radiation resistance of the super-junction VDMOS device, the upper surface of the epitaxial wafer is etched by adopting a dry etching process, the groove depth of the groove is 40-50 mu m, and the groove width is 6-8 mu m.
In the device manufacturing method for improving the radiation resistance of the super-junction VDMOS device, when the groove is filled, the doping concentration of the bottom layer P-type silicon is 0.5E 15cm2-1.5E 15cm2(ii) a The doping concentration of the top layer P-type silicon is 2.5E 15cm2-3.5E 15cm2。
In the method for manufacturing the device for improving the radiation resistance of the super-junction VDMOS device, the temperature of the oxidation gate oxide layer is 950-1050 ℃; the thickness of the gate oxide layer is
According to the device manufacturing method for improving the radiation resistance of the super-junction VDMOS device, when photoetching is carried out on the upper surface of the gate electrode, the gate oxide layer and the P-type silicon are etched in sequence.
In the device manufacturing method for improving the radiation resistance of the super-junction VDMOS device, the groove depth of the Schottky groove is 0.8-1.2 μm, and the groove width is 0.2-0.5 μm.
In the above method for manufacturing a device for improving the radiation resistance of a super junction VDMOS device, the step of metalizing the upper surface of the silicon dioxide dielectric layer specifically comprises:
and evaporating a layer of metal on the silicon dioxide dielectric layer after the etching treatment, wherein the layer of gold is contacted with the N + source region and the Schottky groove through the etched hole to form source metal.
In the above method for manufacturing a device for improving the radiation resistance of a super junction VDMOS device, the step of performing metallization on the lower surface of the N + type silicon substrate sheet specifically comprises:
and evaporating a layer of metal on the lower surface of the N < + > type silicon substrate slice to form drain metal.
Compared with the prior art, the invention has the beneficial effects that:
(1) the method is simple in process and compatible with a super junction VDMOS manufacturing process;
(2) according to the super-junction structure of the super-junction VDMOS device, the N column layer is formed through multi-step and multi-time epitaxy, the P column is formed through multi-step filling of groove etching, and the doping concentration is gradually increased from bottom to top. The upper layer of the N column is higher in doping concentration, and the holes are hindered when moving to the P-body and the grid electrode, and the high concentration layer of the N column can accelerate the recombination of the holes, so that the total amount of the holes is reduced. For the P column, the doping concentration of the upper layer is higher, and holes can be accelerated to move towards the upper source electrode after entering the P column. At the moment, holes passing through the P-body are greatly reduced, the opening of a parasitic transistor is effectively inhibited, and the possibility of single-particle burning is reduced;
(3) according to the invention, the Schottky communicated with the source electrode is arranged in the JFET region of the plane gate super-junction VDMOS, and holes generated in the process of a heavy ion incidence device can be rapidly extracted through arranging the Schottky structure, so that the number of the holes flowing through the P-type base region is reduced, the opening of a parasitic transistor is effectively inhibited, and the single-particle burnout resistance of the device is improved;
(4) the invention can be compatible with the existing super-junction VDMOS device manufacturing process, and by arranging the Schottky structure and the non-uniformly doped P/N column, holes are rarely gathered under the gate oxide layer, thereby effectively improving the single-particle gate penetration resistance of the device.
Drawings
FIG. 1 is a flow chart of the device fabrication of the present invention;
FIG. 2 is a schematic view of 3 epitaxial layers grown on an N + type silicon substrate according to the present invention;
FIG. 3 is a schematic view of a trench according to the present invention;
FIG. 4 is a schematic view of filling a trench according to the present invention;
FIG. 5 is a schematic view of the P-body region of the present invention;
FIG. 6 is a schematic diagram of an N + source region according to the present invention;
FIG. 7 is a schematic view of a gate oxide and gate electrode of the present invention;
FIG. 8 is a schematic view of a Schottky trench of the present invention;
FIG. 9 is a schematic diagram of a completed VDMOS of the invention.
Detailed Description
The invention is further illustrated by the following examples.
The invention provides a device manufacturing method for improving the radiation resistance of a super-junction VDMOS device, which is characterized in that a Schottky communicated with a source electrode is arranged in a JFET region of a planar gate super-junction VDMOS, and holes generated in the heavy ion incidence device process can be rapidly extracted by arranging a Schottky structure, so that the number of the holes flowing through a P-type base region is reduced, the opening of a parasitic transistor is effectively inhibited, and the single-particle burnout resistance of the device is improved.
As shown in fig. 1, the device manufacturing method for improving the radiation resistance of the super junction VDMOS device includes the specific steps of:
selecting an N + type silicon substrate slice 1; and sequentially growing 3 epitaxial layers 2 on the upper surface of the N + type silicon substrate slice 1 to obtain an epitaxial wafer, as shown in figure 2. The doping concentration of the N + type silicon substrate slice 1 is 1E20cm2. The total thickness of the 3 epitaxial layers 2 is 40-50 μm; wherein, the doping concentration of the epitaxial layer 2 on the N + type silicon substrate slice 1 is 0.5E 15cm2-1.5E 15cm2(ii) a The doping concentration of the topmost epitaxial layer 2 is 2.5E 15cm2-3.5E 15cm2。
The epitaxial wafer upper surface is etched to form trenches 3, as shown in fig. 3. And etching the upper surface of the epitaxial wafer by adopting a dry etching process, wherein the groove depth of the groove 3 is 40-50 mu m, and the groove width is 6-8 mu m.
The trench 3 is filled in three layers through the P-type silicon until the trench 3 is filled, as shown in fig. 4. When the groove 3 is filled, the doping concentration of the bottom layer P type silicon is 0.5E 15cm2-1.5E 15cm2(ii) a The doping concentration of the top layer P-type silicon is 2.5E 15cm2-3.5E 15cm2。
Carrying out grinding treatment on the upper surface of the epitaxial wafer filled with the P-type silicon to obtain a super junction structure; p-body mask lithography is performed on the epitaxial upper surface to form a P-body region 4 by boron implantation and diffusion push-to-connect process, as shown in fig. 5.
And carrying out N + mask photoetching on the upper surface of the epitaxial wafer, and forming an N + source region 5 through a phosphorus implantation and diffusion junction-pushing process, as shown in FIG. 6.
Oxidizing the upper surface of the epitaxial wafer to generate a gate oxide layer 6, and depositing polysilicon on the upper surface of the gate oxide layer 6 to form a gate electrode 7, as shown in fig. 7. The temperature of the oxidation gate oxide layer 6 is 950-1050 ℃; grid 0
The thickness of the oxide layer 6 was 800A.
The upper surface of the gate electrode 7 is subjected to a photolithography process and aluminum is evaporated to form a schottky trench 8, as shown in fig. 8. When the upper surface of the gate electrode 7 is subjected to photolithography processing, the gate electrode 7, the gate oxide layer 6, and the P-type silicon are etched in sequence. The depth of the Schottky groove 8 is 0.8-1.2 μm, and the width of the Schottky groove is 0.2-0.5 μm.
Depositing a silicon dioxide dielectric layer on the upper surface of the epitaxial wafer, and etching the upper surface of the silicon dioxide dielectric layer; carrying out metallization treatment to form a source metal 9; the metallization treatment of the upper surface of the silicon dioxide dielectric layer specifically comprises the following steps:
and evaporating a layer of metal on the silicon dioxide dielectric layer after etching treatment, wherein the layer of gold is contacted with the N + source region 5 and the Schottky groove 8 through the etched holes to form source metal 9.
And passivating and etching the PAD area on the upper surface of the source metal 9.
The lower surface of the N + type silicon substrate sheet 1 in the epitaxial wafer is metallized to form a drain metal 10, and the VDMOS fabrication is completed, as shown in fig. 9. The metallization treatment of the lower surface of the N + type silicon substrate slice 1 specifically comprises the following steps: a layer of metal is evaporated on the lower surface of the N + type silicon substrate sheet 1 to form a drain metal 10.
The super-junction P/N column of the device manufactured by the invention adopts non-uniform doping, the doping concentration is higher and higher from bottom to top, the upper layer with higher concentration of the N column can block a hole from moving to a P-body and a grid, the upper layer with higher concentration of the P column can accelerate the hole to move to a source electrode, the starting of a parasitic transistor is effectively inhibited, and the possibility of single-particle burnout is reduced. The Schottky structure and the non-uniformly doped P/N column are arranged, and holes are rarely gathered under the gate oxide layer, so that the single-particle gate penetration resistance of the device is effectively improved. The manufacturing method can effectively discharge holes generated in the incident process of heavy ions, and improve the single particle resistance of the plane gate super junction VDMOS device. Compared with the prior art, the super-junction VDMOS device can be compatible with the existing super-junction VDMOS process and the single particle resistance of the device can be effectively improved.
According to the super-junction VDMOS device, the manufacturing process is improved on the basis of the traditional super-junction VDMOS manufacturing process, the number of holes flowing through the P-type base region in the heavy ion incidence process of the super-junction VDMOS device is reduced, the opening of a parasitic transistor is effectively inhibited, the single-particle burnout resistance of the device is improved, fewer holes are gathered under a gate oxide layer, and the single-particle gate penetration resistance of the device is effectively improved. The specific principle is as follows: a Schottky communicated with a source electrode is arranged in a JFET area of the device, and holes generated in the process of heavy ion incidence on the device can be rapidly extracted through the arrangement of the Schottky structure, so that the number of the holes flowing through a P-type base region is reduced. The super-junction P/N column of the device is doped non-uniformly, the doping concentration is higher and higher from bottom to top, the upper layer with higher concentration of the N column can block the movement of holes to a P-body and a grid, the upper layer with higher concentration of the P column can accelerate the movement of the holes to a source, and the opening of a parasitic transistor is effectively inhibited. The Schottky structure and the non-uniform doped P/N column are arranged, and holes are rarely gathered under the gate oxide layer, so that the single-particle gate penetration resistance of the device is improved.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make possible variations and modifications of the present invention using the method and the technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention are all within the scope of the present invention.
Claims (10)
1. A device manufacturing method for improving the radiation resistance of a super junction VDMOS device is characterized in that: the method comprises the following steps:
selecting an N + type silicon substrate slice (1); sequentially growing 3 epitaxial layers (2) on the upper surface of the N + type silicon substrate slice (1) to obtain an epitaxial slice;
etching the upper surface of the epitaxial wafer to form a groove (3);
filling the groove (3) by P-type silicon in three layers until the groove (3) is filled;
carrying out grinding treatment on the upper surface of the epitaxial wafer filled with the P-type silicon to obtain a super junction structure; carrying out P-body mask photoetching on the upper surface of the epitaxial wafer, and forming a P-body region (4) by boron implantation and diffusion junction-pushing processes;
carrying out N + mask photoetching on the upper surface of the epitaxial wafer, and forming an N + source region (5) by phosphorus injection and diffusion junction-pushing processes;
oxidizing the upper surface of the epitaxial wafer to generate a gate oxide layer (6), and depositing polycrystalline silicon on the upper surface of the gate oxide layer (6) to form a gate electrode (7);
photoetching the upper surface of the gate electrode (7), and evaporating aluminum to form a Schottky groove (8);
depositing a silicon dioxide dielectric layer on the upper surface of the epitaxial wafer, and etching the upper surface of the silicon dioxide dielectric layer; carrying out metallization treatment to form a source metal (9);
passivating and etching the PAD area on the upper surface of the source metal (9);
and carrying out metallization treatment on the lower surface of the N + type silicon substrate slice (1) in the epitaxial slice to form drain metal (10), thus finishing the VDMOS manufacturing.
2. The device manufacturing method for improving the radiation resistance of the super junction VDMOS device according to claim 1, wherein: the doping concentration of the N + type silicon substrate slice (1) is 1E20cm2。
3. The device manufacturing method for improving the radiation resistance of the super junction VDMOS device according to claim 2, wherein: the total thickness of the 3 epitaxial layers (2) is 40-50 mu m; wherein the doping concentration of the epitaxial layer (2) on the N + type silicon substrate slice (1) is 0.5E 15cm2-1.5E 15cm2(ii) a The doping concentration of the topmost epitaxial layer (2) is 2.5E 15cm2-3.5E 15cm2。
4. The device manufacturing method for improving the radiation resistance of the super junction VDMOS device according to claim 3, wherein: and etching the upper surface of the epitaxial wafer by adopting a dry etching process, wherein the groove depth of the groove (3) is 40-50 mu m, and the groove width is 6-8 mu m.
5. The device manufacturing method for improving radiation resistance of the super-junction VDMOS device according to claim 1, wherein: when the groove (3) is filled, the doping concentration of the bottom layer P-type silicon is 0.5E 15cm2-1.5E 15cm2(ii) a The doping concentration of the top layer P-type silicon is 2.5E 15cm2-3.5E 15cm2。
6. The device manufacturing method for improving the radiation resistance of the super junction VDMOS device according to claim 1, wherein: the temperature of the oxidation gate oxide layer (6) is 950-; the thickness of the gate oxide layer (6) is
7. The device manufacturing method for improving the radiation resistance of the super junction VDMOS device according to claim 1, wherein: when the photoetching treatment is carried out on the upper surface of the gate electrode (7), the gate oxide layer (6) and the P-type silicon are etched in sequence.
8. The device manufacturing method for improving radiation resistance of the super-junction VDMOS device according to claim 1, wherein: the depth of the Schottky groove (8) is 0.8-1.2 μm, and the width of the Schottky groove is 0.2-0.5 μm.
9. The device manufacturing method for improving the radiation resistance of the super junction VDMOS device according to claim 1, wherein: the metallization treatment on the upper surface of the silicon dioxide dielectric layer specifically comprises the following steps:
and evaporating a layer of metal on the silicon dioxide dielectric layer after the etching treatment, wherein the layer of gold is in contact with the N + source region (5) and the Schottky groove (8) through the etched hole to form source metal (9).
10. The device manufacturing method for improving the radiation resistance of the super junction VDMOS device according to claim 1, wherein: the metallization treatment of the lower surface of the N + type silicon substrate slice (1) specifically comprises the following steps:
a layer of metal is evaporated on the lower surface of the N + type silicon substrate slice (1) to form drain metal (10).
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